JP4357539B2 - Turbo decoder - Google Patents

Description

The present invention relates to a turbo decoding device, and more particularly to a turbo decoding device that performs decoding using a decoding result of a received signal, and thereafter repeatedly outputs decoded data using sequentially obtained decoding results.
About.

The error correction code is used to correct errors contained in received information, reproduction information, and the like so that the original information can be correctly decoded, and is applied to various systems. For example, the present invention is applied to the case where data is transmitted without error during mobile communication, FAX, or other data communication, or when data is reproduced without error from a large-capacity storage medium such as a magnetic disk or CD.
Among error correction codes, turbo codes (see, for example, Non-Patent Document 1) have been decided to be adopted for standardization in next-generation mobile communications. FIG. 14 is a configuration diagram of a communication system including a turbo encoder and a turbo decoder. 11 is a turbo encoder provided on the data transmission side, 12 is a turbo decoder provided on the data reception side, and 13 is data. It is a communication channel. Further, u is information data of length N to be transmitted, xa, xb and xc are encoded data obtained by encoding the information data u by the turbo encoder 11, and ya, yb and yc are encoded data xa, xb and xc, respectively. A received signal propagating through the communication path 13 and affected by noise and fading, u ′ is a decoding result obtained by decoding the received data ya, yb, yc by the turbo decoder 12 and is expressed as follows. The decoded result u ′ includes “determination result” and “likelihood” of the decoded data.

Original data: u = [u1, u2, u3, .., uN]
Encoded data: xa = [xa1, xa2, xa3, ..., xak, ..., xaN]
: Xb = [xb1, xb2, xb3, ..., xbk, ..., xbN]
: Xc = [xc1, xc2, xc3, ..., xck, ..., xcN]
Received data: ya = [ya1, ya2, ya3, ..., yak, ..., yaN]
: Yb = [yb1, yb2, yb3, ..., ybk, ..., ybN]
: Yc = [yc1, yc2, yc3, ..., yck, ..., ycN]
The turbo encoder 11 encodes information data u having an information length N and outputs encoded data xa, xb, xc. The encoded data xa is the information data u itself, the encoded data xb is data obtained by convolutionally encoding the information data u with the encoder ENC1, and the encoded data xc is interleaved (π) with the information data u and is encoded with the encoder ENC2. This is convolutionally encoded data. That is, the turbo code is synthesized by using two convolutional codes. However, the interleave output xa ′ is not output because it is different in order from the encoded data xa.

  FIG. 15 is a detailed diagram of the turbo encoder 11, 11 a and 11 b are convolutional encoders (ENC 1 and ENC 2) having the same configuration, and 11 c is an interleave unit (π). The convolutional encoders 11a and 11b are configured to output a recursive systematic convolutional code, and are configured by connecting two flip-flops FF1 and FF2 and three exclusive OR circuits EXOR1 to EXOR3 as shown in the figure. Has been. The flip-flops FF1 and FF2 take four states (00), (01), (10), and (11). When 0 or 1 is input in each state, the state transitions as shown in FIG. And xa and xb are output. In FIG. 16, the left side is the state before receiving data, the right side is the state after input, the solid line is the state transition path when “0” is input, the dotted line is the state transition path when “1” is input, and 00, 11 on the path , 10, 01 indicate the values of the output signals xa, xb. For example, in state 0 (00), when “0” is input, the output is 00, the state is 0 (00), and when “1” is input, the output is 11, and the state is 1 (10).

FIG. 17 is a block diagram of the turbo decoder. In the turbo decoding, first of all, ya and yb among the received signals ya, yb and yc are decoded by the first element decoder (DEC1) 12a. The element decoder 12a is a soft output element decoder and outputs the likelihood of the decoding result. Next, similar decoding is performed by the second element decoder (DEC2) 12b using the likelihood and yc output from the first element decoder 12a. That is, the second element decoder 12b is also a soft output element decoder and outputs the likelihood of the decoding result. Since yc is a received signal corresponding to xc obtained by encoding the interleaved information data u, the likelihood output from the first element decoder 12a is the interleaving section ((2) before being input to the second element decoder DEC2. π) Interleave at 12c.
The likelihood output from the second element decoder 12b is deinterleaved by the deinterleave unit (π ⁻¹ ) 12d, and then fed back as an input to the first element decoder 12a. Further, u ′ is decoded data (decoded result) obtained by determining “0”, “1” as a result of deinterleaving of the second element decoder 12b. Thereafter, the error rate is reduced by repeating the above decoding operation a predetermined number of times.
U.S. Patent No. 5,446,747

In turbo decoding, the number of decoding result errors decreases each time the number of repetitions of decoding processing is repeated, but the number of times the decoding result error disappears varies depending on the state of the communication path. For this reason, when data is correctly decoded at a stage where the number of repetitions is small, the turbo decoder repeats unnecessary decoding operations until the set number of times thereafter.
In turbo decoding, errors in the decoding result decrease each time the decoding process is repeated. However, even if the decoding process is performed a set number of times, all errors may not be corrected and errors may remain. In such a case, errors may be considerably reduced, and if the decoding process is performed once again, there is a high possibility that all errors will be corrected. A conventional turbo decoder outputs a decoding result including an error as it is without considering this possibility if decoding is performed a set number of times.
In the conventional turbo decoder, the first and second element decoders 12a and 12b perform the first and second decoding processes on different combinations of received signals, but the decoding operation is exactly the same. Therefore, there is a possibility that one element decoder can be used for the first and second decoding processes. However, conventionally, since the first and second element decoders are used for the first and second decoding processes, the amount of hardware increases, and there is a problem in terms of power consumption.

Further, as shown in FIG. 17, the output of the turbo decoder is a result of deinterleaving the output of the second element decoder 12d. For this reason, when an error remains in the decoded data, the error is randomized by deinterleaving. As shown in FIG. 18A, the unit of the turbo code is often very long, and a plurality of information blocks are included in one turbo code unit. In such a case, when the error is randomized by deinterleaving, the error is distributed to a plurality of information blocks as shown in FIG. 18B, and the error rate in information block units is increased. When retransmission control is performed, there is a problem that causes an increase in retransmission.
In the next-generation mobile communication, information to be transmitted has various characteristics, and depending on the type of data to be transmitted, it is better that the error pattern of the decoded data is in a burst state. Sometimes it is better to be random. However, the conventional turbo decoder cannot make the error pattern included in the decoded data to be output burst or random as necessary.
Accordingly, an object of the present invention is to make an error occurrence pattern included in a decoding result (decoded data) into a burst form.
Another object of the present invention is to make the generation of an error pattern of decoded data burst or random depending on the type of data to be transmitted.

According to the present invention, the above problem is to repeat the first decoding process and the second decoding process based on the decoding result of the first decoding process in the order of the first decoding process and the second decoding process. When the turbo decoding device performs decoding processing on one turbo code unit composed of a plurality of information blocks, the second decoding processing is the first decoding. An output unit that is configured to use a result obtained by deinterleaving the decoding result obtained by the processing, and that can output the result of the second decoding process as a turbo decoding result without going through the interleaving process. This is achieved by a turbo decoding device characterized in that.
According to the present invention, there is provided a turbo decoding device that repeatedly performs a first decoding process and a second decoding process using an interleaved result of the first decoding process according to the data type. Switching means for switching the output of whether the result of the first decoding process is output without going through an interleaving process, or the result of the second decoding process is outputted through a deinterleaving process This is achieved by a turbo decoding device characterized by the following.

According to the present invention, since the result of the second decoding process is output as a turbo decoding result without going through the interleaving process, the error occurrence pattern included in the decoding result (decoded data) can be made into a burst form. .
According to the present invention, the result of the first decoding process is output without going through the interleaving process or the result of the second decoding process is outputted through the deinterleaving process depending on the data type. Since the output is switched, the generation of the error pattern of the decoded data can be made burst or random depending on the data type.

(A) Example 1
FIG. 1 is a block diagram of a turbo decoder according to a first embodiment of the present invention. Ya, yb, and yc are encoded data xa, xb, and xc output from a turbo encoder on the transmission side and propagate through a communication path. It is a signal received under the influence of noise and fading. The encoded data xa is the information data u itself, the encoded data xb is data obtained by convolutionally encoding the information data u, and the encoded data xc is data obtained by convolutionally encoding the information data u after interleaving.
The reception data memory 51 stores all reception signals ya, yb, yc in units of turbo codes, and the reading unit 52 reads the reception signals ya, yb, yc from the memory at an appropriate timing, and first and second element decoders. Input to (DEC1, DEC2) 53, 54. The first and second element decoders 53 and 54 perform a decoding process according to, for example, a well-known maximum a posteriori probability (MAP) decoding algorithm, and are soft decision input soft decision output decoders.

The first element decoder 53 performs a MAP decoding operation using the received signals ya and yb and outputs the likelihood of the decoding result (the first half of turbo decoding). Next, the second element decoder 54 performs a similar MAP decoding operation using the likelihood output from the first element decoder 53 and the received signal yc, and outputs the likelihood of the decoding result (the second half of turbo decoding). ). Since the reception signal yc is a reception signal corresponding to the encoded data xc obtained by encoding the interleaved information data u, the interleaving unit (π) 55 interleaves the likelihood output from the first element decoder 53 to obtain the first value. 2 to the second element decoder 54. The deinterleave unit (π ⁻¹ ) 56 deinterleaves the likelihood output from the second element decoder 54 and feeds it back to the first element decoder 53. Thus, one cycle of turbo decoding is completed, and thereafter, the error rate included in the decoding result is reduced by repeating the above decoding operation a predetermined number of times.

  The reading control unit 61 controls the reading unit 52 to read out the received signals ya, yb, yc from the memory 51, and inputs the signals to the first and second element decoders 53, 54 in accordance with the decoding processing timing. In addition, the read control unit 61 makes an error in the decoding result even when (1) the decoding operation of the set number of times is completed for the target received signal and (2) the number of repetitions is less than the set number of times. Is no longer included, the reading unit 52 performs reading control to start decoding of the next new received signal.

The iterative counter 62 counts up each time each of the element decoders 53 and 54 completes the first and second half decoding operations of turbo decoding, and inputs the respective count values to the iterative control unit 63.
The repetition control unit 63 causes each of the element decoders 53 and 54 to repeat the decoding operation. When the number of repetitions reaches the set number, the repetition control unit 63 notifies the read control unit 61 and the output control unit 66 (decoding operation end signal DED). Output). When the decoding result contains no error, the repetition control unit 63 stops the decoding operation by the signal ERZ output from the error detection circuit 64 and clears the count value of the repetition counter 62 to zero.
The error detection circuit 64 performs an error detection operation using the first decoding result output from the first element decoder 53 and the second decoding result output from the deinterleave 56. The decoded data having the information length N is composed of a large number of information blocks, and an error detection code such as a CRC code is added to each information block. Therefore, the error detection circuit 64 performs error detection using the error detection code, When no error is detected from all the information blocks, an error zero signal ERZ is output.

The decoded data memory 65 alternately stores the first decoding result output from the first element decoder 53 and the second decoding result output from the deinterleave 56, and the output control unit 66 receives a set number of times from the repetition control unit 63. When the signal DED indicating the end of the decoding operation is received, or when the error zero signal ERZ is received from the error detection circuit 64, the decoding result stored in the decoded data memory 65 is output.
As described above, in parallel with the decoding operation, an error in the decoding result is detected by the error detection circuit 64, and if the error remains even after the decoding operation, each element decoder 53, 54 performs the decoding operation for the set number of times, Thereafter, when the decoding operation end signal DED is generated, the output control unit 66 outputs the decoding result. However, if there is no error in the decoding result before the number of decoding times reaches the set number, the output control unit 66 outputs the decoding result by the error zero signal ERZ even during the decoding operation repetition, and iterative control. The unit 63 aborts the decoding operation. In this way, the decoding time can be shortened and the power consumption of the circuit can be reduced.

Modification of the first embodiment The turbo decoder of the first embodiment performs decoding for a set number of times if the error does not disappear, ends the decoding operation, and outputs the decoding result at that time. By the way, even if errors remain after the set number of decoding processes, the number of errors is small, and if the decoding process is performed once again, there is a high possibility that all errors will be corrected. In such a case, it is better to have the decoding operation performed once more and output the decoding result without error. For this reason, in the modification of FIG. 2, an error detection number counter 67 and a threshold determination unit 68 are provided in addition to the configuration of the first embodiment. Since the error detection circuit 64 outputs an error detection signal ERR every time an error is detected, the error detection number counter 67 counts the signal ERR and monitors the error detection number of the set number of decoding results. The threshold determination unit 68 compares the number of error detections included in the decoding result of the set number of times with a threshold value, and if not more than the threshold value, notifies the control unit 63 repeatedly.

If the number of error detections is larger than the threshold value, the repetition control unit 63 ends the decoding operation and outputs a decoding operation end signal DED to the read control unit 61 and the output control unit 66. As a result, the output control unit 66 outputs the decoding result, and the read control unit 61 starts control for reading the next new received signal.
On the other hand, if the number of detected errors is smaller than the threshold value, the repetition control unit 63 does not end the decoding operation, and does not output the decoding operation end signal DED to the read control unit 61 and the output control unit 66. As a result, the decoding operation is performed once more. Thereafter, the iterative control unit 63 outputs the decoding operation end signal DED to the read control unit 61 and the output control unit 66 regardless of whether the number of error detections is larger or smaller than the threshold value. As a result, the output control unit 66 outputs the decoding result, and the read control unit 61 controls reading of the next new received signal.
As described above, when the number of decoding processes is performed a set number of times and the number of errors remains, the number of errors is small. If the decoding process is performed once again, there is a high possibility that all errors will be corrected. By performing the sign operation, the decoding result can be output with all errors corrected.
(B) Example 2

FIG. 3 shows an embodiment of a turbo decoder with one element decoder.
The element decoder 21 1) receives the received signals ya and yb and the second half decoding result (first half decoding process) performed by the first element decoder 53 in FIG. 1 and 2) the received signal yc and the first half. And the decoding process using the decoding result (second half decoding process) are performed in a time-sharing manner. That is, the timing of the decoding operation is divided into a first timing for performing the first (first half) decoding process and a second timing for performing the second (second half) decoding process, and the first half decoding process is performed at the first timing. The second half of the decoding process is performed at the second timing.
The selection circuit 22 selects the received signal yb at the first timing for performing the first half decoding process and inputs it to the element decoder 21, and selects the received signal yc at the second timing for performing the second half decoding process to perform element decoding. To the device 21. The interleaver 23 interleaves the first half decoding result and feeds it back to the input side of the element decoder 21. The deinterleaving 24 deinterleaves the second half decoding result and feeds it back to the input side of the element decoder 21. The switches 25 and 26 perform switching so that the first half and second half decoding results are input to the interleave unit 23 and the deinterleave unit 24, respectively, and fed back to the input side of the element decoder 21.

To explain the overall operation, the selection circuit 22 inputs the received signal ya to the element decoder 21 at the first timing, and the switches 25 and 26 are switched to the solid line state shown in the figure. The element decoder 21 performs a MAP decoding operation using the received signals ya and yb and outputs the likelihood of the decoding result (the first half of turbo decoding). The interleave unit 23 interleaves the likelihood output from the element decoder 21 and feeds it back to the input of the element decoder 21. Next, at the second timing, the selection circuit 22 inputs the received signal yc to the element decoder 21, and the switches 25 and 26 are switched to the dotted line state shown in the figure.
The element decoder 21 performs a MAP decoding operation using the first half decoding result (likelihood) and the received signal yc, and outputs the likelihood of the decoding result (second half of turbo decoding). The deinterleave unit (π ⁻¹ ) 24 deinterleaves the likelihood output from the element decoder 21 and feeds back the likelihood to the element decoder 21.
Thus, one cycle of turbo decoding is completed, and thereafter, the error rate included in the decoding result is reduced by repeating the above decoding operation a predetermined number of times. Then, after performing the decoding operation a predetermined number of times, the output of the deinterleave 24 is output as the decoding result u ′ at the second timing.
If configured as described above, the number of element decoders can be reduced to one and the amount of hardware can be reduced.
(C) Example 3

Conventionally, as shown in FIG. 18 (b), errors are dispersed in a plurality of information blocks, the error rate in information blocks increases, and retransmission control is performed in information blocks. Yes. For this reason, when performing retransmission control, it is more advantageous to concentrate errors than to distribute them. In the convolutional code, the error pattern of the decoding result of the element decoder has a property of being burst. Using this property, the decoding result can be directly output from the element decoder without interleaving or deinterleaving.
FIG. 4 is a block diagram of a third embodiment of the present invention in which the error occurrence pattern included in the decoding result (decoded data) is made bursty.
The interleaving unit 30 interleaves the received signal ya and inputs it to the first element decoder 31. The first element decoder 31 performs a MAP decoding operation on the received signals ya and yc and outputs the likelihood of the decoding result. The deinterleaving unit 32 deinterleaves the likelihood output from the element decoder 31 and inputs it to the second element decoder 33. The second element decoder 33 performs a MAP decoding operation using the deinterleaved decoding result (likelihood) and the received signal yb, outputs a decoding result (likelihood) u ′, and inputs it to the interleave 30.

  In the third embodiment, the received signals ya and yc are input to the first element decoder 31, and the received signal yb is input to the second element decoder 33, so that the latter half of the decoding process in the conventional turbo decoding is performed. First, the first half of the decoding process is performed in the second half. As a result, the output of the second element decoder 33 can be output as it is as the decoding result u ′. In the convolutional code, the error pattern included in the decoding result of the element decoder is in a burst shape as described above. Therefore, according to the third embodiment, errors are concentrated as shown in FIG. The error rate can be reduced and the number of retransmissions can be reduced.

Modified example of the third embodiment In the third embodiment of FIG. 4, the first and second element decoders are used to make the error occurrence pattern included in the decoding result into a burst shape. Even when the first and second decoding processes performed by the second element decoder are performed by one element decoder, the error occurrence pattern included in the decoding result can be made into a burst. FIG. 6 shows a modification of the third embodiment, and the same reference numerals are given to the same parts as those of the second embodiment of FIG.
3 differs from the second embodiment of FIG. 3 in that (1) an interleaving unit 27 is provided and the received signal ya is interleaved and input to the element decoder 21, and (2) the selecting unit 22 is the first half of the first half. The reception signal yc is input to the element decoder 21 at the timing, and the reception signal yb is input to the element decoder 21 at the second timing of the latter half. (3) The switches 25 and 26 are element decoded at the first timing. The output of the decoder 21 is input to the deinterleave 24, the deinterleave result is fed back to the input side of the element decoder 21, the output of the element decoder 21 is input to the interleave 23 at the second timing, and the interleave result is element decoded. (4) The decoding result u ′ is directly extracted from the output of the element decoder 21, not after the deinterleave unit 24.

To explain the overall operation, the selection circuit 22 inputs the received signal yc to the element decoder 21 at the first timing, and the switches 25 and 26 are switched to the solid line state shown in the figure. The element decoder 21 performs a MAP decoding operation using the received signals ya and yc and outputs the likelihood of the decoding result. The deinterleaver 24 deinterleaves the likelihood output from the element decoder 21 and feeds it back to the input of the element decoder 21. Next, at the second timing, the selection circuit 22 inputs the received signal yb to the element decoder 21, and the switches 25 and 26 are switched to the dotted line state shown in the figure.
The element decoder 21 performs a MAP decoding operation using the previous decoding result (likelihood) and the received signal yb, and outputs the likelihood of the decoding result. The interleaving unit 23 interleaves the likelihood output from the element decoder 21 and feeds it back to the element decoder 21.
As described above, even in the case of one element decoder, the second half decoding process in the conventional turbo decoding is performed first and the first half decoding process is performed in the second half as in the third embodiment. The output of the element decoder 21 can be output as it is as the decoding result u ′, and the error pattern of the decoding result can be made into a burst form. The decoding result is output as u ′ at the second timing.
Further, in the modified example of FIG. 6, the amount of hardware can be reduced, and the error rate for each information block can be reduced, and the number of retransmissions can be reduced.
(D) Example 4

If one of the first and second decoding results output from the first and second element decoders constituting the turbo decoder can be selected and output, the error pattern of the decoded data can be changed as necessary. Generation can be burst or random. For example, when there is an error correction circuit in the subsequent stage, the error pattern of the decoded data can be generated in a random manner and the error correction can be performed by the correction circuit. Further, when there is an error generation block retransmission function, the number of reproductions can be reduced by generating an error pattern of decoded data in a burst form.
FIG. 7 is a block diagram of a fourth embodiment in which the generation of an error pattern of decoded data is made burst or random, and has the same configuration as a conventional turbo decoder except for the selection circuit. In turbo decoding, first of all, ya and yb of received signals ya, yb, and yc are decoded by a first element decoder (DEC1) 53. The element decoder 53 is a soft output element decoder and outputs a decoding result (likelihood). Next, similar decoding is performed by the second element decoder 54 using the likelihood output from the first element decoder 53 and the received signal yc. That is, the second element decoder 54 is also a soft output element decoder and outputs a decoding result (likelihood). Since the received signal yc is a received signal corresponding to xc obtained by encoding the interleaved information data u, the likelihood output from the first element decoder 53 is not input to the second element decoder 54. Interleaving is performed by an interleaving unit (π) 55.

The likelihood output from the second element decoder 54 is deinterleaved by the deinterleave unit (π ⁻¹ ) 56 and then fed back as an input to the first element decoder 53. The selection circuit 57 selects and outputs one of the first decoding result A output from the first element decoder 53 and the second decoding result B output from the deinterleave 56. Since the first decoding result A is not subjected to interleaving / deinterleaving, the error occurrence pattern is in a burst form as shown in FIG. On the other hand, since the second decoding result B is interleaved / deinterleaved on the decoding result of the element decoder 54, the error occurrence pattern is random as shown in FIG. 8B. Therefore, by selecting and outputting one of the first and second decoding results A and B, the generation of the error pattern of the decoded data can be made burst or random as necessary.
Since the first and second element decoders 53 and 54 perform interleaving, the order of data output from the second element decoder 54 is different from that of the original information data. For this reason, the decoding result output from the second element decoder 54 is deinterleaved and returned to the original order and output. On the other hand, since the decoding result of the first element decoder 53 has the same order as the original information data, it can be output as it is without changing the order.

As described above, the quality of data transmission is improved by selecting whether to output the first decoding result A or the second decoding result B as the decoded data u ′ depending on the nature of the data to be transmitted. Can do.
For example, as shown in FIG. 9, when further error correction is performed on the turbo decoding result of the turbo decoder 100 by another error correction decoder 200, a decoding result B in which the error occurrence pattern is random is output. In this way, as shown in FIG. 9A, error bits included in the decoding result output from the turbo decoder 100 are dispersed and can be corrected by the error correction decoder 200. After correction (b) As shown in FIG. 5, the error correction efficiency can be increased. It is also suitable to output the decoding result B even when the data to be transmitted allows a certain amount of random errors such as voice.

Also, as shown in FIG. 10, a plurality of information blocks are included in the turbo code unit, and there is no error for each information block from the information blocks (a) and (b) output from the two turbo decoders. When an information block is selected and the selection combination result (c) is output, the decoding result A is output. FIG. 11 shows an example of selective combining. 101 is a turbo decoder provided in the first base station, 102 is a second turbo decoder provided in another base station, 103 is a mobile device, and 104 is mobile. This is a selective synthesizer provided in the switching station or base station controller, and the selective synthesizer 104 has a site diversity function for selecting a good information block. When the mobile device 103 is located near the zone boundary of the adjacent base station, the first and second base stations receive the signal from the mobile device 103, and perform turbo decoding and input to the mobile switching center. As shown in FIG. 10, the selection synthesizer 104 of the mobile switching center selects a block having no error for each information block, and processes based on the result of selection combination.
The selection synthesizer 104 includes memories 104a and 104b that store the decoding results input from the first and second turbo decoders 101 and 102, error detection circuits 104c and 104d that detect errors in the decoding results, and based on the error detection results. And a selection unit 104e that selects and outputs an error-free information block.

Modification of Fourth Embodiment FIG. 12 shows a first modification of the fourth embodiment. The received signals yb and yc input to the first and second element decoders 53 and 54 by the signal selection circuit 71 are shown in FIG. The order is variable. In the figure, π is an interleave unit, π ⁻¹ is a deinterleave unit, and SW is a switch.
In the modification of FIG. 12, in order to obtain the same effect as the fourth embodiment, whether the decoding result is output directly from the element decoder 54 depending on the nature of the decoding result to be output (the error occurrence pattern is burst or random). (Burst), Deinterleaving and then outputting (Random) are switched with a switch.
When deinterleaving and outputting the decoding result, all the switches SW are switched to the upper side (solid line position). In addition, the signal selection circuit 71 inputs the reception signal yb to the first element decoder 53 and inputs the reception signal yc to the second element decoder 54. In this state, since deinterleaving is performed last, if errors remain in the decoded data, the errors are scattered and output as random errors.

  On the other hand, when outputting the output of the element decoder 54 as it is, all the switches SW are switched to the lower side (dotted line position). Further, the signal selection circuit 71 inputs the received signal yc to the first element decoder 53 and inputs the received signal yb to the second element decoder 54. Further, the first element decoder 53 receives an interleaved received signal ya. In such a state, since the data is deinterleaved and rearranged in the original order before the input to the second element decoder 54, the output of the second element decoder 54 can be directly output as u ′. As a result, if an error remains in the decoded data, the error becomes a burst error.

Another Modification of the Fourth Embodiment FIG. 13 is another modification of the fourth embodiment, and the same parts as those in FIGS. 3 and 6 are denoted by the same reference numerals. In this modification, the first and second decoding processes performed by the first and second element decoders are performed by one element decoder 21, and the configuration shown in FIGS. And the order of the received signals yb and yc input to the element decoder 21 is made variable so that the error occurrence pattern included in the decoding result is appropriately burst or random. .

The data initially input from the selection circuit 22 to the element decoder 21 may be the reception signal yb or the reception signal yc. However, in the case of the received signal yb, the switch SW1 when inputting the received signal ya is switched to the upper side, and when the received signal yc is input, it is switched to the lower side. Each time decoding is repeated, the selection circuit 22 alternately switches the input to the element decoder 21 between the reception signal yb and the reception signal yc. Further, when the received signal yb is input to the element decoder 21, the output is switched back by interleaving by switching SW2 to the upper side. On the other hand, the output when the received signal yc is input to the element decoder 21 is output by switching SW2 to the lower side, deinterleaving.
The switch SW3 is switched as follows. If the input to the element decoder 21 is the received signal yb, the switch SW3 is switched to the lower side and output. At this time, if an error remains in the decoding result u ′, a burst error occurs. If the input to the element decoder 21 is the received signal yc, the switch SW3 is switched to the upper side and output. At this time, if an error remains in the decoding result u ′, a random error occurs.

The overall operation will be described below.
In order to make the error occurrence pattern of the decoding result into a burst shape, each switch is set to the solid line position state shown in FIG. 3 (the state shown in FIG. 3). In this state, the selection circuit 22 inputs the received signal yb to the element decoder 21 at the first timing. The element decoder 21 performs a MAP decoding operation using the received signals ya and yb and outputs the likelihood of the decoding result. The interleave unit 23 interleaves the likelihood output from the element decoder 21 and feeds it back to the input of the element decoder 21. Next, at the second timing, the selection circuit 22 inputs the received signal yc to the element decoder 21, and the switches 25 and 26 are switched to the dotted line state shown in the figure. The element decoder 21 performs a MAP decoding operation using the first half decoding result (likelihood) and the received signal yc, and outputs the likelihood of the decoding result. The deinterleave unit 24 deinterleaves the likelihood output from the element decoder 21 and feeds back the likelihood to the element decoder 2. If the decoding result is extracted from the element decoder 21 and output at the first timing, the error occurrence pattern of the decoding result becomes a burst.

When the error occurrence pattern of the decoding result is random, each switch is set to the dotted line position state (the state shown in FIG. 6). In this state, the selection circuit 22 inputs the received signal yc to the element decoder 21 at the first timing. The element decoder 21 performs a MAP decoding operation using the interleaved received signal ya and received signal yc, and outputs the likelihood of the decoding result. The deinterleave unit 24 deinterleaves the likelihood output from the element decoder 21 and feeds back the likelihood to the input of the element decoder 21. Next, at the second timing, the selection circuit 22 inputs the received signal yb to the element decoder 21, and the switches 25 and 26 are switched to the solid line state shown in the figure.
The element decoder 21 performs a MAP decoding operation using the previous decoding result (likelihood) and the received signal yb, and outputs the likelihood of the decoding result. The interleaving unit 23 interleaves the likelihood output from the element decoder 21 and feeds it back to the element decoder 21. If the decoding result is extracted and output from the deinterleave 24 at the first timing, the error occurrence pattern of the decoding result becomes random.
As described above, even in the case of a turbo decoder having one element decoder, it is possible to generate an error pattern of decoded data in a burst or random manner. In this case, since the conventional two element decoders are shared by one element decoder, the circuit scale can be reduced.

It is a block diagram of the turbo decoder of 1st Example of this invention. It is a modification of the turbo decoder of 1st Example of this invention. It is a block diagram of the 2nd turbo decoder of this invention which shared the element decoder. It is a block diagram (it makes an error generation into a burst form) of the turbo decoder of 3rd Example of this invention. It is effect explanatory drawing of 3rd Example. It is another block diagram of the turbo decoder of 3rd Example of this invention. It is a block diagram (decoding result selection system) of the turbo decoder of 4th Example of this invention. It is an error occurrence pattern explanatory diagram. It is explanatory drawing in case an error is better random. FIG. 10 is an explanatory diagram of selective synthesis of information blocks. This is an application example of selective synthesis. This is a modification of the fourth embodiment of the present invention (a configuration in which the order of yb and yc input to DEC1 and DEC2 is made variable). It is another modification (structure which shared the element decoder) of 4th Example of this invention. 1 is a schematic diagram of a communication system. It is a block diagram of a turbo encoder. It is a state transition diagram of a convolutional encoder. It is a block diagram of a turbo decoder. It is explanatory drawing of the error pattern contained in the decoding result of a turbo code unit and the conventional turbo decoder.

Explanation of symbols

30 interleaving section 31 first element decoder 32 deinterleaving section 33 second element decoders 53 and 54 first and second element decoders 55 interleaving section 56 deinterleaving section 57 selection circuit

Claims (2)

In a turbo decoding device that repeatedly performs a first decoding process and a second decoding process based on a decoding result of the first decoding process in the order of the first decoding process and the second decoding process.
When the turbo decoding device performs a decoding process on one turbo code unit composed of a plurality of information blocks, the second decoding process is a decoding result obtained by the first decoding process. Is set to use a deinterleaved version of
An output unit capable of outputting the result of the second decoding process as a turbo decoding result without interleaving;
A turbo decoding device comprising: In a turbo decoding device that repeatedly performs a first decoding process and a second decoding process using an interleaved result of the first decoding process,
Switching means for switching the output of whether the result of the first decoding process is output without going through the interleaving process, or the result of the second decoding process is outputted through the deinterleaving process, depending on the data type ,
A turbo decoding device comprising:

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