JP4356165B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit equipped with a cache function.
[0002]
[Prior art]
A computer system such as a microprocessor is provided with a cache memory that functions as a high-speed buffer memory by storing a part of the program and data in the main memory between the central processing unit and the main memory for high-speed operation. It has been.
[0003]
Further, since a virtual address is used as the address of the recent central processing unit, it is necessary to convert the address between the real address of the cache memory and the main memory. For this reason, the conversion table becomes larger as the address space becomes larger, and the table is usually hierarchized. Since it takes time to extract a real address by referring to a hierarchical table, a table having an associative function called a translation lookaside buffer (hereinafter referred to as TLB) is provided in parallel with the hierarchical table. And pulling out real addresses at high speed. As described above, the TLB is required to perform address translation at high speed and to perform address translation with a high probability using a small-scale circuit.
[0004]
In TLB, two associative methods called a full associative method and a set associative method are used. The former method is a method in which the input address and all the stored data in the TLB are checked for coincidence, and if there is matching stored data, a signal indicating the presence and the stored data are output. In the latter set associative method, candidates that are expected to match are selected, a match / mismatch is checked for the addresses of those candidates, and if there is matching data, a signal indicating the presence and a real address corresponding to the matching address are output. It is a method.
[0005]
Conventionally, in order to realize TLB address conversion and cache memory operation in one cycle operation, there is a method of reducing wiring delay by arranging the TLB and the cache tag comparator as close as possible. FIG. 6 is a conventional example in which a 4-way set associative cache and a TLB are physically arranged. 1 is a data portion of the cache memory, 2 is a tag portion of the cache memory, 3 is a TLB, and is converted by the TLB. The physical address thus entered is input to the comparator 5 in the tag portion of the cache through the address line 4. The comparator 5 in the tag portion of each way compares the physical address with the data in each tag portion, and outputs a hit signal via the buffer 6 if it matches any of the data. If a hit signal is output from any of the four ways, data in the data portion of the cache of that way is output to the data bus by the tri-state buffer 7 and finally to the outside of the cache by the buffer 8. Is output.
[0006]
[Problems to be solved by the invention]
In the configuration described in the prior art, even if the wiring width, wiring interval, wiring length, and wiring film thickness all decrease with the miniaturization of the semiconductor integrated circuit, the wiring is assumed to be of the same material and scaled. If the ratio of S is S, the wiring resistance R will be S times, the wiring capacity will be 1 / S times, the delay product of the RC will not change, and the output from the cache data part will not be able to be further increased. It was. The wiring delay at the output of the tri-state buffer 7 is R (Cb + 2 * Cs), where Cs is the capacitance between the lower layers of the wiring and Cs is the capacitance between the Cb wirings and R is the wiring resistance. However, if the output of the adjacent signal and the main output change in opposite directions, the side capacitance Cs appears to be double, so the maximum delay is R (Cb + 2 * 2 * Cs), which is the standard There was a problem of being slower than the state of. In addition, when the delay time is reduced by increasing the instantaneous current of the transistor by increasing the driver, there is a problem that when all the data buses change, a power supply voltage drop occurs and the delay value increases. . Further, when the signal in the lower layer and upper layer wiring of the data bus transitions in the bus hold state, there is a problem that the output value is inverted because the hold resistance cannot be suppressed.
[0007]
[Means for Solving the Problems]
In the set associative cache constituted by a plurality of ways, the present invention arranges a first power supply line and a second power supply line below the output signal line connected to the output of the data portion of the cache way, The first power supply line and the second power supply line intersect perpendicularly with the output signal line, and the first power supply line and the second power supply line are alternately and repeatedly arranged to reduce substrate noise. A configuration that is difficult to receive is possible.
[0008]
The first power supply line and the second power supply line are disposed above the output signal line, and the first power supply line and the second power supply line intersect each other perpendicularly and alternately with the output signal line. Thus, a configuration that is not easily affected by other signals is possible.
[0009]
A power supply potential is supplied to the first power supply line, a ground potential is supplied to the second power supply line, a P-channel MOS transistor is disposed below the first power supply line, and a gate of the P-channel MOS transistor is The P channel MOS transistor is connected to the second power supply line, the drain and source of the P channel MOS transistor are connected to the first power supply line, an N channel MOS transistor is disposed below the second power supply line, and the N channel MOS transistor The gate of the transistor is connected to the first power supply line, the drain and source of the N channel MOS transistor are connected to the second power supply line, and the P channel MOS transistor is directly below the first power supply line. There is arranged, by the N-channel MOS transistor directly under the second power supply line is arranged to receive the substrate noise Pile configuration is possible.
[0010]
Since the first power supply line and the second power supply line are branched and connected from a power supply source to the cache from the outside of the cache, a configuration that is not easily affected by fluctuations in the power supply potential is possible.
[0011]
By not arranging other signal lines in parallel with all or part of the output signal lines in the lower layer, upper layer, and adjacent to the output signal lines, a configuration that is not easily affected by other signals can be realized.
[0012]
By arranging the first power supply line or the second power supply line in parallel with all or part of the output signal line between the output signal line and another signal line, the influence of other signals The structure which is hard to receive becomes possible.
[0013]
In the configuration having a plurality of pairs of positive and negative pairs as outputs of the data portion of the way, the output signal lines connected to the pairs of positive and negative pairs are connected to the first power supply line for each pair. By disposing the second power supply line between the second power supply line and the second power supply line, a configuration that is hardly affected by other signals is possible.
[0014]
By outputting from the output signal line to the outside of the cache by the first sense amplifier, the output to the outside of the cache can be speeded up.
[0015]
By outputting the output of the data portion of the way to the output signal line by the second sense amplifier, the output to the outside of the cache can be made faster.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention, and shows a physical arrangement of a 4-way set associative cache and a TLB.
[0017]
1 is a data part of the cache memory, 2 is a tag part of the cache memory, one set is arranged in each way, and there are four sets. Reference numeral 3 denotes a TLB, the TLB 3 is arranged in the center, and the data input / output units of the data unit 1 and tag unit 2 of each cache memory are arranged adjacent to each other or face each other. And is isolated from external signals, and the data bus wiring length between each way is shortened.
[0018]
The physical address converted by the TLB 3 passes through the address line 4 and is input to the comparator 5 in the tag portion of each way. The comparator 5 compares the physical address with the data in each TLB for each way, and outputs a hit signal if it matches any data. For example, when there is a match in way0, a hit signal is output via the buffer 6. On the other hand, the signal of the memory cell 11 in the data portion 1 of the matched cache is amplified by the sense amplifier 10. The signals Bit and / Bit of the memory cell 11 are opposite signals, and are output to the data bus 20 through the N-channel MOS transistors 12 and 13 which are turned on by the hit signal output from the buffer 6. Amplified by the sense amplifier 21 activated by the logical sum signal wayhit0123 of the hit signal of way0 or way1, way2, or way3 via the N-channel MOS transistors 14 and 15 that are turned on by the logical sum signal wayhit01 of the hit signal of way0 or way1 Finally, the data is output outside the cache by the buffer 8.
[0019]
As shown in FIG. 5, it is possible to output with a sense amplifier instead of the buffer 8, or it is possible to reduce the number of sense amplifiers in the data section 1 and output with only the sense amplifier 21. Further, by inputting the positive signal of the output of the sense amplifier 21 to the set input of the RS flip-flop and inputting the opposite signal of the output of the sense amplifier 21 to the reset input of the RS flip-flop, erroneous data due to the malfunction of the sense amplifier is externally input. It is also possible to prevent the output to.
[0020]
FIG. 2 is a timing chart when the comparison result signal of the comparator 5 is activated after the physical address output from the TLB 3 matches the data in the tag unit 2. The horizontal axis is the transition time, and the vertical axis is the voltage, showing the transition of each signal line. When the data coincides with any data of the way, the output signal Bit of the way0 and the signal / Bit in the opposite phase change. When the hit signal of the comparator 5 of the tag unit 2 becomes High, the N-channel MOS transistors 12 and 13 connected to the output of the comparator 5 become conductive, and the output signal of the sense amplifier 10 is transmitted to the data bus 20. Since the data bus is pulled up to VDD, if the output signal of the sense amplifier is high, the amplitude decreases to VDD, and if the output signal is low, the amplitude decreases to the VSS side by about 100 mV. The N-channel MOS transistors 14 and 15 are turned on by the logical sum signal wayhit01 of the hit signals of way0 and way1 and transmitted to the sense amplifier 21. The sense amplifier 21 of the data bus is operated by the logical sum signal wayhit0123 of the hit signals of way0 or way1, way2, and way3, and the amplitude is sufficient to drive the buffer 8, and the buffer 8 outputs data.
[0021]
By adopting the configuration as described above, the signal on the data bus 20 may have a low amplitude, and a tri-state buffer is not required, so that the signal is transmitted at high speed. Further, since the adjacent bus is only a signal that is fixed at VDD or transits to the VSS side at the time of signal transmission, there is no amplitude that swings in the opposite direction, so the inter-wiring capacity does not increase and the delay time decreases.
[0022]
A detailed view of the data bus of FIG. 1 is shown in FIG. The data output wirings 103 and 104 of the cache memory are the signal lines 102 and 105 connected to the power supply line 100 and the ground line 101 of the lower layer of the wiring via the contacts 110 and 111, and the data output wirings 103 and 105 of the opposite pair. The noise from the other signals to the data output wiring is reduced by sandwiching 104, and the power output line 100 and the ground line 101 are arranged so that the data output wiring lower layer intersects the data output wirings 103 and 104 vertically. By alternately wiring, the influence of noise on the data output wiring from the lower layer can be reduced. FIG. 4 shows a detailed view below the wiring as a method for further strengthening the shield. The drain 112 and the source 113 of the P-channel MOS transistor are each connected to the power supply line 100 via a contact 110, and the gate 111 is connected to the ground line 101 via a contact 120. The N-channel MOS transistor has a configuration in which the drain and source are connected to the ground line via a contact, and the gate is connected to the power line via the contact. The potential of the power line and the ground line is stabilized by the gate capacitance of the MOS transistor. We are strengthening. With the above configuration, the mesh-like power supply wiring and ground wiring can be configured, and the influence of noise from the lower layer wiring can be reduced to the minimum. Moreover, the voltage drop is reduced by alternately placing the power source and the ground line.
[0023]
【The invention's effect】
As described above, according to the present invention, in the set associative cache of a plurality of ways, the board noise to the data bus and the noise from other signal lines can be reduced to the minimum. By alternately placing the, it is possible to reduce the voltage drop. Further, since the output of the cache is performed by the sense amplifier and the buffer is not used, the data output can be speeded up.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention. 4 is a physical layout diagram of a data bus of a semiconductor integrated circuit according to the embodiment. FIG. 4 is a lower layer wiring diagram of a physical layout of the data bus of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a block diagram of a semiconductor integrated circuit according to another embodiment. FIG. 6 is a block diagram of a conventional semiconductor integrated circuit.
1 Data part of cache memory 2 Tag part of cache memory 3 TLB
5 Comparator 6 Buffer 7 Tristate buffer 8 Buffer

Claims (5)

In a set associative cache composed of a plurality of ways, a first power supply line and a second power supply line are arranged below an output signal line connected to the output of the data portion of the cache way, The power supply line and the second power supply line intersect perpendicularly with the output signal line, and the first power supply line and the second power supply line are alternately and repeatedly arranged ,
A power supply potential is supplied to the first power supply line, a ground potential is supplied to the second power supply line, a P-channel MOS transistor is disposed below the first power supply line, and a gate of the P-channel MOS transistor is The P channel MOS transistor is connected to the second power supply line, the drain and source of the P channel MOS transistor are connected to the first power supply line, an N channel MOS transistor is disposed below the second power supply line, and the N channel MOS transistor A gate of the transistor is connected to the first power supply line, and a drain and a source of the N-channel MOS transistor are connected to the second power supply line;
A semiconductor integrated circuit , wherein the P-channel MOS transistor is disposed immediately below the first power supply line, and the N-channel MOS transistor is disposed immediately below the second power supply line .   The first power supply line and the second power supply line are disposed above the output signal line, and the first power supply line and the second power supply line intersect each other perpendicularly and alternately with the output signal line. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed. 3. The semiconductor integrated circuit according to claim 1, wherein the first power supply line and the second power supply line are branched and connected from a power supply source to the cache from the outside of the cache. Lower layer of the output signal lines, the upper layer and adjacent to the semiconductor integrated circuit of claims 1 to 3, wherein a is not disposed in parallel with other signal lines with all or a portion of the output signal line. Claim 1, wherein placing the first power supply line or the second power supply line between the output signal lines and other signal lines in parallel with all or part of the output signal line 5. The semiconductor integrated circuit according to 4 .

Images