JP4354759B2 - Method for forming buried electrode and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a forming method of an embedded electrode with which the embedded electrode such as a through electrode can be formed without contaminating an element and wiring, and to provide a manufacturing method of a semiconductor device. <P>SOLUTION: When the embedded electrode is formed in such a way that it is embedded in a semiconductor substrate 11, a resist mask 14 having an opening part 14a in a previously decided position where the buried electrode is to be formed is formed on a face where an interlayer insulating film 12 and signal wiring 13 of the semiconductor substrate 11 are formed. The interlayer insulating film 12 and the semiconductor substrate 11 are etched and deep holes 15 are formed. Intra-hole insulating films 16 and conductive plugs 17 are formed in the deep holes 15 in a state where the resist mask 14 is left, and the resist mask 14 is removed. Thus, the embedded electrode constituted of the conductive plug 17 can be formed without contaminating the semiconductor element and signal wiring 13, which are used when the intra-hole insulating films 16 and the conductive plugs 17 are formed in the deep holes 15. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a method of forming a buried electrode provided for drawing out an electrode or wiring formed on one surface side of a substrate such as a semiconductor substrate to the other surface side of the substrate, and manufacturing a semiconductor device having the buried electrode. Regarding the method.

  Portable electronic devices such as mobile phones and portable information devices have been reduced in size and weight in order to pursue convenience in usage. For this purpose, miniaturization and higher density of semiconductor devices themselves mounted on portable electronic devices are being promoted. As a semiconductor device, a semiconductor device in which a plurality of semiconductor chips formed by integrating electronic circuits composed of a large number of elements on one semiconductor substrate or in a substrate are connected to each other is widely used. In order to increase the functionality and speed of operation, it is necessary to shorten the connection wiring between semiconductor substrates as much as possible.

In response to such demands on semiconductor devices, large scale integrated circuits (Large Scale)
Integration; abbreviation: LSI) A semiconductor device having a stacked structure in which chips are stacked vertically has been proposed (for example, see Patent Document 1). FIG. 27 is a cross-sectional view schematically showing the structure of the semiconductor device 100 having a stacked structure. As shown in FIG. 27, in the semiconductor device 100 having a laminated structure, in order to realize the laminated structure, the semiconductor chips 120a, 120b, and 120c stacked on the lowermost circuit board 121 on which an electronic circuit (not shown) is formed are formed. Each semiconductor substrate 101 is provided with a through-electrode 109 that penetrates the substrate in the thickness direction, and a structure in which the wiring 104 a formed on one surface side of the semiconductor substrate 101 is drawn to the other surface side by the through-electrode 109 is used. Yes.

  By stacking the semiconductor chips 120a, 120b, and 120c on which the through electrodes 109 are formed on the circuit board 121 in the vertical direction toward the paper surface via the surface wiring 110 and the protruding electrodes 111 as shown in FIG. Three-dimensional mounting can be performed. That is, by stacking as shown in FIG. 27, the wiring 104a connected to the element (not shown) provided in each semiconductor chip 120a, 120b, 120c is electrically connected via the surface wiring 110, the through electrode 109, and the protruding electrode 111. Therefore, electrical signals can be transmitted between the semiconductor chips 120a, 120b, 120c and the circuit board 121.

  As described above, by mounting the semiconductor chips 120a, 120b, and 120c on the circuit board 121 three-dimensionally, the mounting form can be improved as compared with the case of mounting the semiconductor chips 120a, 120b, and 120c on the circuit board 121 in a planar manner. It can be downsized. In addition, the length of the wiring can be shortened. Note that the through electrode 109 is insulated from the semiconductor substrate 101 by the insulating film 107.

  Hereinafter, a method for forming the through electrode 109 according to the prior art will be described. 28 to 37 are cross-sectional views schematically showing the state of each step in the formation of the through electrode 109 according to the prior art.

  FIG. 28 is a view showing a state in which the connection hole 103 is formed in the interlayer insulating film 102 provided on the semiconductor substrate 101. In the conventional method for forming the through electrode 109, first, elements (not shown) are integrated and formed on the semiconductor substrate 101, and then the interlayer insulating film 102 is formed on the surface of the semiconductor substrate 101 where the elements are formed. Next, a connection hole 103 is formed in the interlayer insulating film 102.

  FIG. 29 is a diagram showing a state in which the conductive film 104 is formed. Next, the semiconductor substrate 101 is filled with a conductive film 104 made of a conductive material such as an aluminum (element symbol: Al) -copper (element symbol: Cu) alloy by sputtering, for example, so as to fill the inside of the connection hole 103. The interlayer insulating film 102 is formed over the entire surface.

  FIG. 30 is a view showing a state in which a resist mask 105 is formed on the conductive film 104. As shown in FIG. 30, a resist mask 105 having an opening at a predetermined position is formed on the surface of the conductive film 104.

  FIG. 31 shows a state where the conductive film 104 is etched. By etching the conductive film 104 with the resist mask 105 formed on the surface, an opening is formed at a predetermined position of the conductive film 104 as shown in FIG. As a result, the opening shape of the resist mask 105 is transferred to the conductive film 104.

  FIG. 32 is a view showing a state where the resist mask 105 is removed. When the resist mask 105 shown in FIG. 31 is removed by ashing using oxygen plasma, the state shown in FIG. 32 is obtained.

  FIG. 33 is a view showing a state in which the deep hole 106 is formed. The interlayer insulating film 102 and the semiconductor substrate 101 are dry-etched using the conductive film 104 in which the opening is formed as a mask pattern to form a deep hole 106.

FIG. 34 is a diagram showing a state in which the wiring 104a is formed. 33, the conductive film 104 outside the connection hole 103 is chemically mechanically polished (Chemical Mechanical Polishing).
Polishing (abbreviation: CMP) is used to remove the wiring 104a.

  FIG. 35 is a diagram showing a state in which the insulating film 107 and the conductive film 108 are formed. An insulating film 107 is formed on the entire surface of the semiconductor substrate 101 where the wiring 104a is formed so as to cover the inner surface of the deep hole 106. Next, a conductive film 108 made of a conductive material is formed over the entire surface of the semiconductor substrate 101 where the wiring 104a is formed so as to fill the inside of the insulating film 107 formed in the deep hole 106.

  FIG. 36 is a diagram showing a state in which the conductive plug 108a is formed. Of the insulating film 107 and the conductive film 108 shown in FIG. 35, the unnecessary insulating film 107 and the conductive film 108 outside the deep hole 106 are removed by a CMP method. Thereby, the conductive plug 108a is formed.

  FIG. 37 is a diagram showing a state in which the through electrode 109 is formed. The surface of the semiconductor substrate 101 opposite to the surface on which the wiring 104a is formed is polished and retracted by CMP until the conductive plug 108a shown in FIG. 36 is exposed. As a result, the through electrode 109 made of the remaining portion of the conductive plug 108a is formed.

  The surface wiring 110 and the protruding electrode 111 shown in FIG. 27 described above are formed on the semiconductor substrate 101 on which the through electrode 109 has been formed as described above to obtain semiconductor chips 120a, 120b, and 120c.

JP-A-11-251316 (page 4-5, Fig. 1-2)

  In the technique described in Patent Document 1 described above, the wiring 104a is exposed when the insulating film 107 and the conductive film 108 are formed in the step shown in FIG. There is a problem in that the electrical characteristics deteriorate, such as the wiring 104a being contaminated with the material to be shorted, the wirings being short-circuited, and the insulation between the wirings being deteriorated. In order to meet the demand for finer wiring with higher density in recent years, it is very important to ensure the insulation between the wirings. May be.

Further, the through electrode is formed on one surface of the semiconductor substrate by a charge coupled device (Charge Coupled).
In a semiconductor device using a semiconductor chip provided with an image sensor such as Device (abbreviation: CCD) alone, an electrode for applying a voltage to the image sensor is drawn out to the other surface side of the semiconductor substrate, and the other surface Provided to place the power supply on the side. However, in this case, when the through electrode is formed by the method shown in FIGS. 28 to 37, the surface of the image sensor is contaminated, and there is a problem that it cannot be put to practical use.

  An object of the present invention is to provide an embedded electrode capable of forming a buried electrode such as a through electrode without contaminating elements and wiring, ensuring insulation at the wiring portion, and forming a highly reliable electric wiring. A forming method and a manufacturing method of a semiconductor device are provided.

The present invention is provided so as to be embedded in a position where the extraction electrode is formed on a substrate on which an element and an extraction electrode electrically connected to the element are formed, and is electrically connected to the extraction electrode. A method of forming a buried electrode comprising:
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
Forming a resist mask having an opening at a predetermined position for forming the embedded electrode on the surface of the substrate on which the extraction electrode is formed;
Etching the substrate on which the resist mask is formed to form a deep hole;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
And forming a surface wiring for electrically connecting the extraction electrode and the conductive layer.

Further, the present invention is provided so as to be embedded in a position where the extraction electrode is formed on a substrate on which an element and an extraction electrode electrically connected to the element are formed, and electrically connected to the extraction electrode A method for forming a buried electrode, comprising:
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
Forming a resist mask having an opening at a predetermined position for forming the embedded electrode on the surface of the substrate on which the extraction electrode is formed;
Etching the substrate on which the resist mask is formed to form a deep hole;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
And forming a surface wiring for electrically connecting the extraction electrode and the conductive layer.

Furthermore, the present invention provides a step of forming the surface wiring,
The method further includes the step of retracting the surface of the substrate opposite to the surface on which the surface wiring is formed until the conductive layer is exposed.

Furthermore, the present invention relates to the above-mentioned lead-out of a semiconductor substrate on which an element, an interlayer insulating film provided so as to cover the element, and a lead electrode provided on the interlayer insulating film and electrically connected to the element are formed. A method of forming a buried electrode provided to be buried at a position where an electrode is formed and electrically connected to the extraction electrode,
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
On the surface of the semiconductor substrate on which the interlayer insulating film and the extraction electrode are formed, a resist mask having an opening at a position where the extraction electrode is removed and at a predetermined position to form the embedded electrode Forming, and
Removing the interlayer insulating film in a portion corresponding to the opening of the resist mask;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Forming an in-hole insulating film in the deep hole while leaving the resist mask;
Filling the deep hole in which the in-hole insulating film is formed with a conductive material up to a height at which a resist mask is formed by a printing method, and forming a conductive layer;
Removing the resist mask;
And forming a surface wiring for electrically connecting the extraction electrode and the conductive layer.

Furthermore, the present invention provides an opening at a predetermined position for forming the embedded electrode, on the surface of the semiconductor substrate where the interlayer insulating film and the extraction electrode are formed, at a position where the extraction electrode is removed. In the step of forming a resist mask having
The resist mask is formed so that the extraction electrode is not exposed.

Furthermore, the present invention includes a step of forming a surface wiring that electrically connects the extraction electrode and the conductive layer,
The method further includes the step of retracting the surface of the semiconductor substrate opposite to the surface on which the surface wiring is formed until the conductive layer is exposed.

Furthermore, the present invention provides a step of removing the resist mask,
It is a step of removing the resist mask using a solvent.

Furthermore, in the present invention, the step of forming a conductive layer in the deep hole includes:
The deep hole includes a step of filling a conductive material to a height at which a resist mask is formed by a printing method and filling the deep hole with the conductive material.

Furthermore, in the present invention, the step of forming a conductive layer in the deep hole includes:
The method further includes the step of heating the conductive material after the step of filling the deep hole with the conductive material,
The conductive material includes conductive particles having a particle diameter of 1 nm to 10 nm.

  Furthermore, the present invention is characterized in that the conductive layer contains at least one of gold, silver, copper and nickel as a main component.

Furthermore, the present invention provides a semiconductor substrate, an element provided on the semiconductor substrate, a signal wiring provided on the semiconductor substrate and electrically connected to the element, and the signal provided to be embedded in the semiconductor substrate. A method of manufacturing a semiconductor device having a buried electrode electrically connected to a wiring,
Forming an element and a signal wiring electrically connected to the element on a semiconductor substrate;
Forming a resist mask having an opening at a predetermined position to form the embedded electrode on the surface of the semiconductor substrate on which the signal wiring is formed, so as to cover the signal wiring;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
Forming a surface wiring for electrically connecting the signal wiring and the conductive layer; and a method for manufacturing a semiconductor device.

Furthermore, the present invention provides a semiconductor substrate, an element provided on the semiconductor substrate, an extraction electrode provided on the semiconductor substrate and electrically connected to the element, and a position where the extraction electrode is formed on the semiconductor substrate. A method of manufacturing a semiconductor device having a buried electrode provided to be buried and electrically connected to the extraction electrode,
Forming an element and an extraction electrode electrically connected to the element on a semiconductor substrate;
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
Forming a resist mask having an opening at a predetermined position to form the buried electrode on the surface of the semiconductor substrate on which the extraction electrode is formed;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
And a step of forming a surface wiring for electrically connecting the extraction electrode and the conductive layer.

Furthermore, the present invention provides a step of forming the surface wiring,
The method further includes the step of retracting the surface of the semiconductor substrate opposite to the surface on which the surface wiring is formed until the conductive layer is exposed.

According to the present invention, the embedded electrode provided so as to be embedded in the substrate on which the element and the signal wiring are formed and electrically connected to the signal wiring is formed on the surface of the substrate on which the signal wiring is formed. A resist mask having an opening at a predetermined position to form a buried electrode is formed so as to cover the signal wiring, the substrate is etched to form a deep hole, and the resist mask is left in the deep hole, After forming the conductive layer by filling the conductive material to the height where the resist mask is formed by the printing method, removing the resist mask and forming the surface wiring that electrically connects the signal wiring and the conductive layer Formed by. When the conductive layer is formed in the deep hole, the surface of the substrate other than the surface facing the deep hole, and the surfaces of the element and the signal wiring are covered and protected by a resist mask. Therefore, of the conductive material used when forming the conductive layer, the surplus conductive material other than that filled in the deep hole is the surface of the substrate other than the surface facing the deep hole, and the surface of the element and signal wiring It adheres to the surface of the resist mask without adhering to the surface, and is simultaneously removed by lift-off when the resist mask is removed.
When the conductive layer is cured and contracted, the conductive layer can be prevented from being recessed from the surface of the substrate.

  This makes it possible to form an embedded electrode with a conductive material used for forming a conductive layer without contaminating the surface of the substrate other than the surface facing the deep hole, and the surface of the element and signal wiring. . Therefore, it is possible to reliably insulate the wiring portion and form a highly reliable electric wiring, and to prevent a short circuit between the wiring and a malfunction of the element. In particular, when an embedded electrode is formed after forming an imaging device such as a charge coupled device in which an electrode is exposed on one surface of the semiconductor substrate using a semiconductor substrate as a substrate, contamination of the imaging device surface can be prevented. Therefore, it is possible to prevent malfunction of the image sensor and reduce the defective product rate.

  In addition, when a conductive layer is formed in a deep hole, a resist mask can be used as a pattern mask. Therefore, the conductive layer can be formed only in the deep hole portion without using another mask.

According to the invention, the embedded electrode that is provided so as to be embedded in the position where the extraction electrode is formed on the substrate on which the element and the extraction electrode are formed, and is electrically connected to the extraction electrode is at least the embedded electrode The extraction electrode at a predetermined position is removed to form a resist mask having an opening at a predetermined position at which the extraction electrode is removed and a buried electrode is formed. Then, the substrate is etched to form a deep hole, and the conductive layer is filled with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask. After forming, the resist mask is removed, and a surface wiring that electrically connects the extraction electrode and the conductive layer is formed. When the conductive layer is formed in the deep hole, the surface of the substrate and the extraction electrode other than the surface facing the deep hole and the surface of the element are covered and protected by a resist mask. Therefore, of the conductive material used when forming the conductive layer, the surplus conductive material other than that filled in the deep hole is the surface of the substrate and the extraction electrode other than the surface facing the deep hole, and the surface of the element It adheres to the surface of the resist mask without adhering to the surface, and is simultaneously removed by lift-off when the resist mask is removed.
When the conductive layer is cured and contracted, the conductive layer can be prevented from being recessed from the surface of the substrate.

  This makes it possible to form a buried electrode without contaminating the substrate and the surface of the extraction electrode other than the surface facing the deep hole and the surface of the element with a conductive material used when forming the conductive layer. . Therefore, it is possible to reliably insulate the wiring portion and form a highly reliable electric wiring, and to prevent a short circuit between the wiring and a malfunction of the element. In particular, when an embedded electrode is formed after forming an imaging device such as a charge coupled device in which an electrode is exposed on one surface of the semiconductor substrate using a semiconductor substrate as a substrate, contamination of the imaging device surface can be prevented. Therefore, it is possible to prevent malfunction of the image sensor and reduce the defective product rate.

  In addition, when a conductive layer is formed in a deep hole, a resist mask can be used as a pattern mask. Therefore, the conductive layer can be formed only in the deep hole portion without using another mask.

  According to the invention, after the surface wiring is formed, the surface of the substrate opposite to the surface on which the surface wiring is formed is retracted until the conductive layer is exposed. As a result, a through electrode can be formed as an embedded electrode that can penetrate the substrate and lead out the signal wiring or the extraction electrode formed on one surface side of the substrate to the other surface side. Therefore, for example, when a semiconductor substrate provided with an image sensor on one surface side is used alone as a semiconductor device, the image sensor is electrically connected via an extraction electrode or an extraction electrode for applying a voltage to the image sensor. The signal wiring to be connected can be led out to the other surface side of the semiconductor substrate by the through electrode, and the power source can be provided on the other surface side. Therefore, compared with the case where the power source is provided on the surface side where the image sensor is provided. A semiconductor device including an imaging element can be reduced in size. In addition, by stacking a plurality of substrates through the through electrodes, three-dimensional mounting can be performed, so that the length of the wiring can be shortened as compared with the case where the plurality of substrates are mounted in a plane. it can. Further, the mounting form can be miniaturized, and the apparatus can be miniaturized and densified.

According to the invention, the embedded electrode is provided so as to be embedded in the position where the extraction electrode is formed on the semiconductor substrate on which the element, the interlayer insulating film, and the extraction electrode are formed, and is electrically connected to the extraction electrode. Removes at least a lead electrode at a predetermined position to form a buried electrode, and forms a resist mask having an opening at a predetermined position at which the lead electrode is removed at a predetermined position to form a buried electrode Formed on the surface on which the interlayer insulating film and the extraction electrode are formed, the interlayer insulating film corresponding to the opening of the resist mask is removed, the semiconductor substrate is etched to form a deep hole, and the resist mask is left. the state deep holes, holes are formed in the insulating film, the deep hole that is formed in the borehole insulating film, a conductive material to a height resist mask is formed by a printing method Hama and after forming the conductive layer, the resist mask is removed, it is formed by forming a surface wiring for electrically connecting the lead electrode and the conductive layer. When forming the in-hole insulating film and the conductive layer in the deep hole, the surfaces of the semiconductor substrate, the interlayer insulating film and the extraction electrode other than the surface facing the deep hole are covered and protected by a resist mask. Therefore, of the insulating material and conductive material used when forming the in-hole insulating film and the conductive layer, the surplus insulating material and conductive material other than those filled in the deep holes are surfaces facing the deep holes. It adheres to the surface of the resist mask without adhering to the surfaces of the other semiconductor substrate, interlayer insulating film and extraction electrode, and is simultaneously removed by lift-off when removing the resist mask.
When the conductive layer is cured and contracted, the conductive layer can be prevented from being recessed from the surface of the interlayer insulating film.

  By this, the insulating material and conductive material used when forming the in-hole insulating film and the conductive layer without contaminating the surface of the semiconductor substrate, the interlayer insulating film and the extraction electrode other than the surface facing the deep hole A buried electrode can be formed. Therefore, it is possible to reliably insulate the wiring portion and form a highly reliable electric wiring, and to prevent a short circuit between the wiring and a malfunction of the element. In particular, when an embedded electrode is formed after forming an imaging device such as a charge coupled device in which an electrode is exposed on one surface of a semiconductor substrate, the imaging device surface can be prevented from being contaminated. Functional failure can be prevented, and the defective product rate can be reduced.

  In addition, when forming the in-hole insulating film and the conductive layer in the deep hole, the resist mask can be used as a pattern mask. Therefore, the insulating film and the conductive layer are formed only in the deep hole portion without using another mask. Can be formed.

  According to the invention, the resist mask is formed so that the extraction electrode is not exposed. When a resist mask is formed so that a part of the extraction electrode, for example, the surface facing the deep hole of the extraction electrode is exposed, when the in-hole insulating film is formed in the deep hole, the extraction is performed beyond the depth of the deep hole. When the in-hole insulating film is formed to the height at which the electrode is formed, the in-hole insulating film is formed in contact with the extraction electrode, so that the surface area of the extraction electrode exposed after removing the resist mask is in contact with the in-hole insulating film. It becomes smaller by the area to be used. Accordingly, the contact area between the surface wiring formed after the resist mask is removed and the extraction electrode is also reduced.

  However, in the method of forming the buried electrode according to the present invention, as described above, the resist mask is formed so that the extraction electrode is not exposed. Therefore, when forming the in-hole insulating film in the deep hole, the depth of the deep hole is reduced. Even if the in-hole insulating film is formed up to the height where the extraction electrode is formed, the in-hole insulating film is formed in contact with the resist mask and is not formed in contact with the extraction electrode. Accordingly, since the surface area of the extraction electrode exposed after the removal of the resist mask can be increased as compared with the case where the resist mask is formed so that a part of the extraction electrode is exposed, the surface wiring formed after the removal of the resist mask can be increased. The contact area between the lead electrode and the lead electrode can be increased, and the electrical resistance of the connection portion between the lead electrode and the surface wiring can be reduced.

  According to the invention, after the surface wiring is formed, the surface of the semiconductor substrate opposite to the surface on which the surface wiring is formed is retracted until the conductive layer is exposed. As a result, it is possible to form a penetrating electrode that can penetrate the semiconductor substrate and lead out the lead electrode formed on one surface side of the semiconductor substrate to the other surface side as the embedded electrode. Therefore, for example, when a semiconductor substrate provided with an image sensor on one surface side is used alone as a semiconductor device, an extraction electrode for applying a voltage to the image sensor is used as a lead electrode on the other surface of the semiconductor substrate. Since the power supply can be provided on the other surface side, the semiconductor device including the image sensor can be downsized compared to the case where the power supply is provided on the surface side where the image sensor is provided. Further, by stacking a plurality of semiconductor substrates through the through electrodes, three-dimensional mounting can be performed, so that the length of the wiring is reduced as compared with the case where the plurality of semiconductor substrates are mounted in a plane. be able to. Further, the mounting form can be downsized, and the semiconductor device can be downsized and densified.

  According to the present invention, the resist mask is removed using a solvent. If there is an extraneous material such as an electrically conductive material or an insulating material on the surface of the resist mask, it is difficult to remove the resist mask located under the deposit by a dry-type removal method such as ashing. Since the solvent penetrates into the lower layer of the deposit, the resist mask located in the lower layer of the deposit can be easily peeled off by the solvent. Therefore, by removing the resist mask using a solvent as described above, the resist mask can be surely removed even when there is a deposit on the surface of the resist mask, so the resist mask is removed. After the process, a clean surface substrate and a layer provided on the substrate can be obtained.

According to the invention, the conductive layer provided in the deep hole is formed through a step of filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method. When filling the deep hole with the conductive material, the surface of the substrate other than the position where the deep hole is formed is covered with the resist mask, so the conductive material is filled up to the height where the resist mask is formed. can do. In other words, more conductive material can be supplied to the deep hole portion than when there is no resist mask. Therefore, for example, when a conductive paste is used as the conductive material, the paste is filled beyond the depth of the deep hole in anticipation of the cure shrinkage of the paste, and the surface of the conductive layer becomes the surface of the substrate due to the cure shrinkage of the paste. Therefore, it is possible to prevent a connection failure when the conductive layer and the signal wiring or the extraction electrode are connected by the surface wiring.

  According to the invention, the conductive layer provided in the deep hole is formed by filling the deep hole with a conductive material containing conductive particles having a particle diameter of 1 nm or more and 10 nm or less, and then heating the conductive material. It is formed. Very small conductive particles having a particle size of 1 nm or more and 10 nm or less are fused at a temperature considerably lower than the melting point of the bulk metal because the ratio of the surface area to the total volume when filled is higher than that of the bulk metal. The phenomenon occurs. Therefore, by using a conductive material including conductive particles having a particle diameter of 1 nm or more and 10 nm or less, the conductive particles can be fused at a considerably lower temperature than when bulk metal is used as the conductive material. The conductive layer can be formed as a conductive film having a conductivity equivalent to that of a bulk metal and having almost no pores called voids without causing thermal damage to the substrate or the like.

  According to the present invention, since the conductive layer contains at least one of gold, silver, copper, and nickel as a main component, a low-resistance buried electrode can be formed. By using such a buried electrode as a wiring, the operation of a device such as a semiconductor device can be speeded up.

According to the present invention, a semiconductor device having a buried electrode provided so as to be buried in a semiconductor substrate and electrically connected to a signal wiring includes a step of forming an element and a signal wiring on the semiconductor substrate, A step of forming a resist mask having an opening at a predetermined position to form a buried electrode on the surface on which the signal wiring is formed so as to cover the signal wiring, and etching the semiconductor substrate on which the resist mask is formed A step of forming a deep hole, a step of filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer; And a step of forming a surface wiring that electrically connects the signal wiring and the conductive layer. When the conductive layer is formed in the deep hole, the surface of the semiconductor substrate other than the surface facing the deep hole and the surfaces of the element and the signal wiring are covered and protected by a resist mask. Therefore, of the conductive material used when forming the conductive layer, the surplus conductive material other than that filled in the deep holes is the surface of the semiconductor substrate other than the surface facing the deep holes, and the elements and signal wirings. It adheres to the surface of the resist mask without adhering to the surface, and is simultaneously removed by lift-off when the resist mask is removed.
When the conductive layer is cured and contracted, the conductive layer can be prevented from being recessed from the surface of the substrate.

  As a result, the conductive material used when forming the conductive layer is used to form a semiconductor device having a buried electrode without contaminating the surface of the semiconductor substrate other than the surface facing the deep hole and the surface of the element and signal wiring. Can be manufactured. Therefore, it is possible to reliably insulate the wiring portion and form a highly reliable electric wiring, and to prevent a short circuit between the wiring and a malfunction of the element. In particular, when a semiconductor device is manufactured by forming an embedded electrode after forming an imaging device such as a charge coupled device with an electrode exposed on one surface of a semiconductor substrate, contamination of the imaging device surface can be prevented. It is possible to prevent malfunction of the image sensor and reduce the defective product rate.

  In addition, when a conductive layer is formed in a deep hole, a resist mask can be used as a pattern mask. Therefore, the conductive layer can be formed only in the deep hole portion without using another mask. Therefore, the manufacturing cost of the semiconductor device can be reduced compared to the case where the conductive layer is patterned using a photomask.

According to the present invention, a semiconductor device having a buried electrode provided so as to be buried at a position where a lead electrode is formed on a semiconductor substrate and electrically connected to the lead electrode is provided on the semiconductor substrate. Forming at least a predetermined position for forming the buried electrode, and removing the lead electrode on the surface where the lead electrode is formed on the surface of the semiconductor substrate. Forming a resist mask having an opening at a predetermined position to form an electrode; etching a semiconductor substrate on which the resist mask is formed; forming a deep hole; and leaving the resist mask in a deep state. the hole, forming a conductive layer by filling a conductive material to a height resist mask is formed by a printing method, a resist mask Removing, it is prepared a lead electrode and a conductive layer and a process of forming a surface wiring which electrically connects. When the conductive layer is formed in the deep hole, the surface of the semiconductor substrate and the extraction electrode other than the surface facing the deep hole and the surface of the element are covered and protected by a resist mask. Therefore, of the conductive material used when forming the conductive layer, the surplus conductive material other than that filled in the deep hole is the surface of the semiconductor substrate and the extraction electrode other than the surface facing the deep hole, and the element. It adheres to the surface of the resist mask without adhering to the surface, and is simultaneously removed by lift-off when the resist mask is removed .

  As a result, a semiconductor device having a buried electrode without contaminating the surface of the semiconductor substrate and the extraction electrode other than the surface facing the deep hole and the surface of the element with a conductive material used when forming the conductive layer. Can be manufactured. Therefore, it is possible to reliably insulate the wiring portion and form a highly reliable electric wiring, and to prevent a short circuit between the wiring and a malfunction of the element. In particular, when a semiconductor device is manufactured by forming an embedded electrode after forming an imaging device such as a charge coupled device with an electrode exposed on one surface of a semiconductor substrate, contamination of the imaging device surface can be prevented. It is possible to prevent malfunction of the image sensor and reduce the defective product rate.

  In addition, when a conductive layer is formed in a deep hole, a resist mask can be used as a pattern mask. Therefore, the conductive layer can be formed only in the deep hole portion without using another mask. Therefore, the manufacturing cost of the semiconductor device can be reduced compared to the case where the conductive layer is patterned using a photomask.

  According to the invention, after the surface wiring is formed, the surface of the semiconductor substrate opposite to the surface on which the surface wiring is formed is retracted until the conductive layer is exposed. As a result, it is possible to obtain a semiconductor device having a through electrode that can penetrate the semiconductor substrate as a buried electrode and can lead out a signal wiring or an extraction electrode formed on one surface side of the semiconductor substrate to the other surface side. it can. Therefore, for example, when a semiconductor substrate provided with an image sensor on one surface side is used alone as a semiconductor device, the image sensor is electrically connected via an extraction electrode or an extraction electrode for applying a voltage to the image sensor. The signal wiring to be connected can be led out to the other surface side of the semiconductor substrate by the through electrode, and the power source can be provided on the other surface side. A semiconductor device including an imaging element can be reduced in size. Also, by stacking a plurality of semiconductor substrates via through electrodes, a semiconductor device mounted three-dimensionally can be obtained, so that the wiring can be compared to a semiconductor device in which a plurality of semiconductor substrates are mounted in a plane. The length of the semiconductor device can be shortened, the operation of the semiconductor device can be speeded up, and the high-functionality and high-speed operation of the electronic device in which the semiconductor device is mounted can be realized. Further, the mounting form can be downsized, and the semiconductor device can be downsized and densified.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

  FIG. 1 is a schematic cross-sectional view schematically showing a configuration of a semiconductor device 1 having a through electrode 2. The semiconductor device 1 includes a circuit board 26 and semiconductor chips 25a, 25b, and 25c stacked on the circuit board 26. The semiconductor chips 25a, 25b, and 25c are electrically connected to the semiconductor substrate 11, the semiconductor element (not shown), the interlayer insulating film 12 provided so as to cover the semiconductor element, and the semiconductor element provided on the interlayer insulating film 12, respectively. Signal wiring 13, the through electrode 2 penetrating the semiconductor substrate 11 in the thickness direction, the in-hole insulating film 16 insulating the through electrode 2 and the semiconductor substrate 11, and the through electrode 2 provided on the interlayer insulating film 12. And a surface wiring 18 that electrically connects the signal wiring 13 to each other. The circuit board 26 is provided with an electronic circuit (not shown) composed of a semiconductor element or the like. The semiconductor substrates 11 of the semiconductor chips 25a, 25b, and 25c are stacked on the circuit board 26 in the vertical direction toward the paper surface through the through electrode 2, the surface wiring 18, and the protruding electrode 27.

  In this manner, the semiconductor devices mounted in a three-dimensional manner by stacking the semiconductor substrates 11 of the semiconductor chips 25a, 25b, and 25c on the circuit substrate 26 through the through electrode 2, the surface wiring 18, and the protruding electrodes 27. 1 can be obtained. Accordingly, the length of the wiring can be shortened as compared with the semiconductor device in which a plurality of semiconductor substrates are mounted on the circuit board 26 in a planar manner, the operation of the semiconductor device 1 is increased, and the semiconductor device 1 is mounted. High functionality and high speed operation of electronic equipment can be realized. Further, the mounting form can be downsized, and the semiconductor device 1 can be downsized and densified.

  The semiconductor device manufacturing method of the present invention for manufacturing the semiconductor device as shown in FIG. 1 uses the embedded electrode forming method of the present invention. First, the embedded electrode forming method of the present invention will be described below. Note that in this specification, an embedded electrode is an electrode provided so as to be embedded in a substrate or a layer such as a semiconductor substrate, and an electrode penetrating the substrate or layer like the through electrode 2 shown in FIG. , And any electrode that does not penetrate through the substrate or layer and reaches the inside of the substrate from one surface side of the substrate or layer.

  In the embedded electrode forming method according to the first embodiment of the present invention, a method of forming the through electrode 2 penetrating the substrate will be described. 2 to 11 are cross-sectional views schematically showing the state of each step in forming the through electrode 2. FIG. 2 is a diagram showing a state in which the interlayer insulating film 12 and the signal wiring 13 are formed on the semiconductor substrate 11. First, after forming a semiconductor element (not shown) on the semiconductor substrate 11, an interlayer insulating film 12 is formed on the surface of the semiconductor substrate 11 on which the semiconductor element is formed so as to cover the semiconductor element. Next, a signal wiring 13 that is electrically connected to the semiconductor element is formed at a predetermined position on the interlayer insulating film 12.

The semiconductor substrate 11 is a substrate made of a semiconductor material such as a silicon (chemical formula: Si) wafer. The interlayer insulating film 12 is a film made of an insulating material provided to insulate and protect the surface of the semiconductor element, and is typically made of silicon dioxide (chemical formula: SiO ₂ ). The signal wiring 13 is an electrical wiring provided for extracting a signal from the semiconductor element and transmitting it to an electronic circuit (not shown) or for electrically connecting the semiconductor element and a power source. The signal wiring 13 is made of a conductive material such as aluminum (element symbol: Al), and is formed by sputtering, for example.

  FIG. 3 is a view showing a state in which the resist mask 14 is formed. As shown in FIG. 3, on the surface of the semiconductor substrate 11 on which the interlayer insulating film 12 and the signal wiring 13 are formed, a predetermined position for forming the through electrode 2 (hereinafter, this position is also referred to as a formation planned position). A resist mask 14 having an opening 14 a is formed so as to cover the signal wiring 13. The resist mask 14 is formed by, for example, applying a resist on the surface of the semiconductor substrate 11 on which the interlayer insulating film 12 and the signal wiring 13 are formed by spin coating or the like and then selectively removing the resist mask 14 by photolithography. . Note that the type of material constituting the resist mask 14 and the resist exposure or development method are not particularly limited.

  In the present embodiment, since the resist mask 14 is used for the etching process not only in the step shown in FIG. 4 described later but also in the step shown in FIG. 14 is formed. By forming the resist mask 14 thick in this way, the resist mask 14 at positions other than the opening 14a is prevented from being removed and opened in the etching process shown in FIGS. It is possible to prevent the interlayer insulating film 12 and the signal wiring 13 at the position of.

FIG. 4 is a view showing a state in which the interlayer insulating film 12 is etched. The interlayer insulating film 12 is etched using the resist mask 14 as a pattern mask, and the portion of the interlayer insulating film 12 corresponding to the opening 14a of the resist mask 14 is removed. As a result, the interlayer insulating film 12 is opened corresponding to the pattern of the resist mask 14, and the semiconductor substrate 11 at the position where the through electrode 2 is to be formed is exposed. The interlayer insulating film 12 is etched by plasma etching using a fluorine-based gas such as carbon tetrafluoride (chemical formula: CF ₄ ), for example.

FIG. 5 is a view showing a state in which the deep hole 15 is formed. The semiconductor substrate 11 is etched using the resist mask 14 used in the previous step as a pattern mask, and penetrates the interlayer insulating film 12 from the surface of the interlayer insulating film 12 facing the resist mask 14 to a predetermined portion inside the semiconductor substrate 11. A deep hole 15 is formed. That is, the depth D1 of the deep hole 15 from the surface of the semiconductor substrate 11 facing the interlayer insulating film 12 is smaller than the thickness T1 of the semiconductor substrate 11 (D1 <T1). Etching of the semiconductor substrate 11 is performed by anisotropic etching such as reactive ion etching (abbreviation: RIE) using a fluorine-based gas such as sulfur hexafluoride (chemical formula: SF ₆ ). The deep hole 15 has, for example, an opening of about 70 μm square, that is, a length s11 in the left-right direction and a length s12 in the direction perpendicular to the paper surface of FIG. The depth D1 from the surface facing the film 12 is about 100 μm.

  FIG. 6 is a view showing a state in which the in-hole insulating film 16 is formed in the deep hole 15. Insulating the hole so as to cover the wall surface of the deep hole 15 as shown in FIG. 6 with the resist mask 14 used in the previous step left without being removed from the semiconductor substrate 11 in which the deep hole 15 is formed. A film 16 is formed. Here, the wall surface of the deep hole 15 refers to the semiconductor substrate 11 that is in the vertical direction toward the plane of FIG. 6 among the surface of the interlayer insulating film 12 facing the deep hole 15 and the surface of the semiconductor substrate 11 facing the deep hole 15. It is a surface substantially parallel to the thickness direction.

  The in-hole insulating film 16 is formed as follows, for example. FIG. 7 is a diagram schematically showing a method of forming the in-hole insulating film 16. As shown in FIG. 7A, a screen mask 19 having an opening corresponding to the deep hole 15 is used as a pattern mask, and a photosensitive insulating material 20 is selectively filled into the deep hole 15. As the photosensitive insulating material 20, for example, photosensitive polyimide, or photosensitive resin such as photosensitive epoxy resin, epoxy acrylate resin, or urethane acrylate resin used as a permanent resist is used.

  As a method of filling the deep hole 15 with the photosensitive insulating material 20, it is preferable to use a vacuum printing technique in order to sufficiently fill the photosensitive insulating material 20 to the bottom of the deep hole 15. When the vacuum printing technique is used, the entire semiconductor substrate 11 in which the deep holes 15 are formed is placed under a state where the pressure is lower than the atmospheric pressure, and under this state, photosensitive insulation is performed from the opening of the screen mask 19 by the squeegee 21. The material 20 is applied to the deep hole 15. At this time, the photosensitive insulating material 20 is applied so as to cover the top of the deep hole 15, and is not filled up to the bottom of the deep hole 15. Next, the pressure around the semiconductor substrate 11 is returned to atmospheric pressure. Thus, the space below the deep hole 15 not filled with the photosensitive insulating material 20 and the space outside the deep hole 15 where the photosensitive insulating material 20 filled above the deep hole 15 is exposed. A differential pressure is generated between Since the pressing force toward the lower portion of the deep hole 15 acts on the photosensitive insulating material 20 by this differential pressure, the photosensitive insulating material 20 can be filled to the bottom of the deep hole 15.

  After filling the deep hole 15 with the photosensitive insulating material 20 in this way, as shown in FIG. 7B, the photosensitive material is irradiated with light in the direction of the arrow 23 through the photomask 22. The insulating material 20 is selectively exposed. In the present embodiment, a photosensitive insulating material 20 is used that has a photosensitivity in which the exposed portion is soluble in the developer, and the photomask 22 is smaller than the opening size of the deep hole 15. What has an opening dimension is used. The opening shape of the photomask 22 is appropriately selected according to the photosensitivity of the photosensitive insulating material 20.

  Next, the exposed portion is removed with a developer, and an internal space 16a is formed in the photosensitive insulating material 20 filled in the deep hole 15 as shown in FIG. As a result, the in-hole insulating film 16 is formed on the wall surface of the deep hole 15 as shown in FIG.

  FIG. 8 is a view showing a state in which the conductive plug 17 is formed. With the resist mask 14 left, the photosensitive insulating material 20 shown in FIG. 7A is placed in the deep hole 15 in which the in-hole insulating film 16 is formed, that is, in the internal space 16a of the in-hole insulating film 16. In the same manner as the step of filling the deep holes 15, the conductive material is filled with a conductive material using a screen mask having an opening corresponding to the deep holes 15 as a pattern mask, and heated as necessary to form a conductive layer as a conductive layer. Plug 17 is formed. The conductive plug 17 is exposed at an inner end of the semiconductor substrate 11 in a process shown in FIG. 11 described later, and becomes a through electrode 2 penetrating the semiconductor substrate 11. In this specification, the conductive plug that is in a state of penetrating the semiconductor substrate is commonly referred to as a through electrode.

  Also when filling the deep hole 15 with the conductive material, it is preferable to use the above-described vacuum printing technique. By using the vacuum printing technique, the conductive material can be filled to the bottom of the deep hole 15. Further, when the vacuum printing technique is used, the gas component in the conductive material is reduced by being exposed to a vacuum state, so that generation of voids called voids when the deep hole 15 is filled with the conductive material is reduced. Is possible.

  The conductive material to be the conductive plug 17 is preferably mainly composed of at least one of gold, silver, copper and nickel. By using these as main components, the low-resistance through electrode 2 can be formed. By using such a through electrode 2 as a wiring, the operation of the semiconductor device 1 can be speeded up.

  As the conductive material, conductive particles themselves may be used, or a paste containing conductive particles may be used. As the paste containing conductive particles, a paste in which conductive particles are contained in a solid state in a solvent, for example, a paste in which conductive particles are dispersed in an organic solvent together with a thermosetting resin is used. Note that the conductive paste used as the conductive material is not limited to a paste containing conductive particles, but deposits fine metal particles as conductive particles, such as a metal dissolved in a solvent. It may be a paste-like product.

  The conductive particles preferably have a particle size of sub-micron to nano size, and particularly preferably include particles having a particle size of 1 nm to 10 nm. The extremely small conductive particles having such a particle diameter exhibit a behavior different from that of the bulk metal because the ratio of the surface area to the total volume occupied when filled is higher than that of the bulk metal. That is, the fusing phenomenon occurs at a temperature considerably lower than the melting point of the bulk metal. Therefore, by using a conductive material including conductive particles having such a particle size, the conductive particles can be fused at a temperature considerably lower than that when bulk metal is used as the conductive material. The conductive plug 17 can be formed as a conductive film having conductivity equivalent to that of a bulk metal and having almost no voids, without causing thermal damage to the semiconductor element 11 and the semiconductor element provided on the semiconductor substrate 11.

  When the deep hole 15 is filled with a conductive material, the surface of the interlayer insulating film 12 and the semiconductor substrate 11 other than the position where the deep hole 15 is formed is covered with a resist mask 14 as shown in FIG. Therefore, the conductive material can be filled up to the height at which the resist mask 14 is formed. That is, more conductive material can be supplied to the deep hole 15 than in the case without the resist mask 14. Therefore, for example, when a conductive paste is used as the conductive material, the depth E1 from the surface facing the resist mask 14 of the interlayer insulating film 12 in the deep hole 15, that is, the interlayer insulation, in anticipation of the curing shrinkage of the paste. The paste is filled to a sum (B1 + D1) or more of the thickness B1 of the film 12 and the depth D1 from the surface of the semiconductor substrate 11 facing the interlayer insulating film 12 of the deep hole 15, and the surface of the conductive plug 17 is caused by curing shrinkage of the paste. Can be prevented from being recessed from the surface of the interlayer insulating film 12, so that a connection failure when the conductive plug 17 and the signal wiring 13 are connected by the surface wiring 18 in the process shown in FIG. 10 to be described later is prevented. can do.

  FIG. 9 is a view showing a state where the resist mask 14 is removed. The resist mask 14 shown in FIG. 8 is removed. As a result, as shown in FIG. 9, the signal wiring 13 and the interlayer insulating film 12 covered with the resist mask 14 are exposed. As a method for removing the resist mask 14, a method of peeling using a solvent or a dry method of removing such as ashing is used. Among these, a method of peeling using a solvent is preferably used. As the solvent, a solvent in which the resist mask 14 is selectively dissolved as compared with the interlayer insulating film 12 and the in-hole insulating film 16 is used. By using such a solvent, it is possible to prevent the interlayer insulating film 12 and the in-hole insulating film 16 from being dissolved by the solvent when the resist mask 14 is peeled off.

  FIG. 10 is a diagram showing a state in which the surface wiring 18 is formed. A surface wiring 18 is formed on the surface of the interlayer insulating film 12 exposed by removing the resist mask 14 so as to connect the signal wiring 13 and the conductive plug 17 as shown in FIG. The surface wiring 18 is made of a conductive material, and can be formed by a simple method such as screen printing of a conductive paste.

  FIG. 11 is a diagram illustrating a state in which the through electrode 2 is formed. The surface of the semiconductor substrate 11 opposite to the surface on which the surface wiring 18 is formed is polished and retracted until the end of the conductive plug 17 shown in FIG. 10 on the inner side of the semiconductor substrate 11 is exposed. As a result, the conductive plug 17 is in a state of penetrating the semiconductor substrate 11 and becomes the through electrode 2 that can lead out the signal wiring 13 formed on one surface side of the semiconductor substrate 11 to the other surface side.

  In order to expose the conductive plug 17 in this way, when the surface of the semiconductor substrate 11 opposite to the surface on which the surface wiring 18 is formed is retracted to make the semiconductor substrate 11 thinner, the mechanical strength is weak. Therefore, there is a high risk of damage to the semiconductor substrate 11 during the process. Therefore, in order to avoid such a risk, a reinforcing plate made of smooth quartz glass or the like is attached to the surface of the semiconductor substrate 11 where the surface wiring 18 is formed with an adhesive or the like, and the semiconductor substrate 11 is reinforced in this state. It is preferable to perform mechanical polishing and chemical polishing together.

  As described above, in the method of forming the through electrode 2 according to the present embodiment, when forming the in-hole insulating film 16 and the conductive plug 17 in the deep hole 15 in the steps shown in FIGS. The surface of the interlayer insulating film 12 and the surface of the signal wiring 13 other than the surface facing the surface are covered and protected by a resist mask 14. Therefore, of the insulating material and the conductive material used when forming the in-hole insulating film 16 and the conductive plug 17, the surplus insulating material and conductive material other than the deep hole 15 filled are deep holes. Adhering to the surface of the resist mask 14 without adhering to the surface of the interlayer insulating film 12 other than the surface facing the surface 15 and the surface of the signal wiring 13, it is simultaneously removed by lift-off when removing the resist mask 14.

  Thus, the surface of the interlayer insulating film 12 and the surface of the signal wiring 13 other than the surface facing the deep hole 15 are made of the insulating material and the conductive material used when forming the in-hole insulating film 16 and the conductive plug 17. The through electrode 2 can be formed without contamination. That is, even when the through electrode 2 is formed after forming the signal wiring 13 as in the present embodiment, the signal wiring 13 forms the in-hole insulating film 16 and the conductive plug 17 in the deep hole 15. Therefore, it is possible to reliably insulate the wiring portion where the signal wiring 13 is provided, to form a highly reliable electric wiring, and to prevent a short circuit between the wirings. it can.

  In particular, when the through electrode 2 is formed after forming an imaging device such as a charge coupled device with an electrode exposed on one surface side of the semiconductor substrate 11 as a semiconductor device, contamination of the imaging device surface can be prevented. Therefore, it is possible to prevent malfunction of the image sensor and reduce the defective product rate. The semiconductor substrate 11 provided with the imaging element is used as the uppermost semiconductor chip 25a of the semiconductor device 1 shown in FIG. 1 or as a semiconductor device alone without being stacked with another semiconductor substrate 11. When the semiconductor substrate 11 provided with the imaging element is used alone as a semiconductor device, an electrode for applying a voltage to the imaging element by forming the through electrode 2 in the semiconductor substrate 11 as shown in FIG. The signal wiring 13 electrically connected to the semiconductor substrate 11 can be drawn out to the other surface side of the semiconductor substrate 11 and a power source can be provided on the other surface side. Therefore, the semiconductor device including the imaging element can be downsized as compared with the case where the power source is provided on the surface side where the imaging element is provided.

  As described above, in this embodiment, the screen mask 19 is used as a pattern mask in the step of filling the deep hole 15 shown in FIG. As described above, the resist mask 14 may be used as a pattern mask. Similarly, in the step of filling the deep hole 15 shown in FIG. 8 with a conductive material, the resist mask 14 may be used as a pattern mask. By using the resist mask 14 as a pattern mask in this way, the in-hole insulating film 16 and the conductive plug 17 can be formed only in the deep hole 15 without using another mask such as the screen mask 19. Therefore, for example, compared with the case where the conductive plug 17 is formed by forming a conductive layer on the entire surface of the semiconductor substrate 11 on which the signal wiring 13 is formed and then patterning the conductive layer using a photomask, the manufacturing cost of the semiconductor device is reduced. Can be suppressed.

  When the photosensitive insulating material 20 is filled using the resist mask 14 as a pattern mask in this way, as shown in FIG. 12, the photosensitive insulating material 20 used for forming the in-hole insulating film 16 is formed. Among these, the excess photosensitive insulating material 20 that is not applied to the deep holes 15 adheres to the surface of the resist mask 14. Similarly, surplus conductive material that is not applied to the deep hole 15 among the conductive materials used when forming the conductive plug 17 also adheres to the surface of the resist mask 14.

  In the case where there is an extraneous photosensitive insulating material 20 and a deposit 20a such as a conductive material on the surface of the resist mask 14, in the dry-type removal method using a plasma asher or the like, the resist located under the deposit 20a It is difficult to remove the mask 14. On the other hand, the method of removing the resist mask 14 using a solvent as described above has a higher effect of allowing the solvent to permeate the lower layer of the deposit 20a as compared with ashing, and is therefore positioned below the deposit 20a. The resist mask 14 can also be easily peeled off with a solvent, and the deposit 20a adhering to the surface of the resist mask 14 can be removed by lift-off at the same time as the resist mask 14 is peeled off. Therefore, by removing the resist mask 14 using a solvent, the resist mask 14 can be reliably removed even when the deposit 20a is present on the surface of the resist mask 14 as shown in FIG. After the step of removing the resist mask 14, the interlayer insulating film 12 and the signal wiring 13 having a clean surface can be obtained.

  Further, in this embodiment, the in-hole insulating film 16 is predetermined in order to form the internal space 16a by filling the deep hole 15 with the photosensitive insulating material 20 and then exposing the deep hole 15 as shown in FIG. Although it is formed by removing the photosensitive insulating material 20 of the portion, without being limited thereto, for example, after filling the deep hole 15 with an insulating material such as an insulating resin and curing, It may be formed by removing a predetermined portion of the insulating material to form the internal space 16a by a laser or the like. As the insulating material that is filled into the deep hole 15 and cured, a photocurable resin or a thermosetting resin used as a permanent resist is used.

  The in-hole insulating film 16 may be formed using a chemical vapor deposition (abbreviation: CVD) method. FIG. 13 is a cross-sectional view schematically showing the state of each step in the formation of the in-hole insulating film 16 by the CVD method. As shown in FIG. 13A, the surface of the deep hole 15, that is, the semiconductor substrate 11 facing the deep hole 15 and the interlayer insulating film 12 with respect to the semiconductor substrate 11 in which the deep hole 15 shown in FIG. An insulating film 24 made of an insulating material is formed so as to cover the surface. At this time, the insulating film 24 is formed not only on the position of the deep hole 15 but also on the entire surface of the semiconductor substrate 11 on which the resist mask 14 is formed.

  As shown in FIG. 13B, the screen mask or resist mask 14 is used as a pattern mask in the deep hole 15 in which the insulating film 24 is formed, as in the process of forming the conductive plug 17 shown in FIG. A conductive plug 17 is formed by filling a conductive material.

  Next, when the resist mask 14 is peeled off using a solvent, the state shown in FIG. At this time, the insulating film 24 formed on the surface of the resist mask 14 shown in FIG. 13B is also peeled off simultaneously with the resist mask 14 to form the in-hole insulating film 16. In this method, the in-hole insulating film 16 is formed not only on the wall surface of the deep hole 15 but also on the entire surface of the semiconductor substrate 11 facing the deep hole 15 including the bottom surface of the deep hole 15.

  According to this method, it is not necessary to form the internal space 16a for filling the conductive material by a photolithography process as in the process shown in FIG. 7, and therefore the in-hole insulating film 16 can be easily formed. . In addition, a film having a uniform thickness can be easily formed on the wall surface of the deep hole 15. Further, when it is desired to increase the film thickness of the in-hole insulating film 16 in order to improve the insulating properties with respect to the semiconductor substrate 11, it is only necessary to lengthen the processing time when forming the insulating film 24.

  The in-hole insulating film 16 may be formed using a spray method. Even when the in-hole insulating film 16 is formed by using the spray method, it is possible to obtain the same shape as that obtained by using the CVD method.

  The conductive plug 17 may also be formed by a CVD method or a spray method. However, when the CVD method or the spray method is used, it is difficult to fill the inner space 16a of the in-hole insulating film 16 without gaps with the conductive film formed by the CVD method or the spray method. The conductive plug 17 is preferably formed by filling the internal space 16a with a conductive material.

  A method for manufacturing a semiconductor device 1 according to another embodiment of the present invention includes the method for forming the through electrode 2 according to the present embodiment, and further includes the following steps. That is, the protruding electrode 27 made of a conductive material is provided on the semiconductor substrate 11 on which the through electrode 2 is formed in the step shown in FIG. 11 so that electrical connection can be obtained at a predetermined place as shown in FIG. The semiconductor chips 25a, 25b, and 25c are obtained by projecting. The obtained semiconductor chips 25a, 25b, and 25c are stacked on the circuit board 26 on which the electronic circuit is formed via the through electrode 2, the surface wiring 18, and the protruding electrode 27. The semiconductor device 1 can be manufactured as described above.

  FIG. 14 is a schematic cross-sectional view schematically showing the configuration of the semiconductor device 3 having the through electrode 4. The semiconductor device 3 includes a circuit board 41 and semiconductor chips 40 a and 40 b stacked on the circuit board 41. The semiconductor chips 40a and 40b are respectively provided on the semiconductor substrate 31, a semiconductor element (not shown), a passivation film 32 that is an interlayer insulating film provided so as to cover the semiconductor element, and electrically provided on the semiconductor element. A lead electrode 33 to be connected; a protective film 34 provided so as to cover a part of the lead electrode 33; a through electrode 4 provided at a position where the lead electrode 33 is formed and penetrating the semiconductor substrate 31 in the thickness direction; The in-hole insulating film 37 that insulates the through electrode 4 and the semiconductor substrate 31 and the conductive plug cap 39 that is a surface wiring that electrically connects the through electrode 4 and the extraction electrode 33 are configured. An insulating film 42 is formed on the surface of the semiconductor substrate 31 opposite to the surface on which the extraction electrode 33 is formed. The circuit board 41 is provided with an electronic circuit (not shown) composed of a semiconductor element or the like. Each semiconductor substrate 31 of the semiconductor chips 40a and 40b is stacked on the circuit board 41 in the vertical direction toward the paper surface through the through electrode 4, the conductive plug cap 39, the surface wiring 43, and the protruding electrode 44.

  Thus, by laminating each semiconductor substrate 31 of the semiconductor chips 40a and 40b on the circuit board 41 via the through electrode 4, the conductive plug cap 39, the surface wiring 43 and the protruding electrode 44, the first embodiment and Similarly, three-dimensional mounting can be performed. Accordingly, the length of the wiring can be reduced as compared with the case where a plurality of semiconductor substrates are mounted on the circuit board 41 in a planar manner. Further, the mounting form can be reduced in size, and the semiconductor device 3 can be reduced in size and density.

  As a method for forming a buried electrode according to the second embodiment of the present invention, a lead-through electrode 33 provided on one surface side of the semiconductor substrate 31 is penetrated to be provided on the other surface side of the semiconductor substrate 31. A method for forming the electrode 4 will be described. 15 to 25 are diagrams schematically showing the state of each step in the formation of the through electrode 4.

  FIG. 15A is a cross-sectional view showing a state where the passivation film 32 and the extraction electrode 33 are formed on the semiconductor substrate 31. FIG. 15 (b) is a plan view showing the semiconductor substrate 31 on which the passivation film 32 and the extraction electrode 33 shown in FIG. 15 (a) are formed as viewed from the direction of the arrow 50, and FIG. This corresponds to a cross-sectional view taken along section line II in FIG. First, after forming a semiconductor element (not shown) on the semiconductor substrate 31, a passivation film 32, which is an interlayer insulating film, is formed on the surface of the semiconductor substrate 31 on which the semiconductor element is formed so as to cover the semiconductor element. An extraction electrode 33 electrically connected to the semiconductor element and a signal wiring (not shown) electrically connected to the extraction electrode 33 are formed at predetermined positions on the passivation film 32. In the present embodiment, the extraction electrode 33 is formed in a rectangular shape.

The semiconductor substrate 31 is a substrate made of a semiconductor material such as a silicon (Si) wafer. The passivation film 32 is a film made of an insulating material provided to insulate and protect the surface of the semiconductor element, and is typically made of silicon dioxide (SiO ₂ ). The extraction electrode 33 is an electrode provided for extracting a signal from the semiconductor element or for applying a voltage from a power source to the semiconductor element. The signal wiring is an electrical wiring provided to transmit a signal extracted from the semiconductor element by the extraction electrode 33 to an electronic circuit (not shown) or to electrically connect the extraction electrode 33 and the power source. The extraction electrode 33 and the signal wiring are typically made of a conductive material such as aluminum (Al), and are formed by sputtering, for example.

  FIG. 16A is a cross-sectional view showing a state in which the protective film 34 is formed. 16B is a plan view showing the semiconductor substrate 31 on which the protective film 34 shown in FIG. 16A is formed as viewed from the direction of the arrow 50. FIG. 16A is a plan view of FIG. This corresponds to a cross-sectional view seen from the section line II of FIG. A protective film 34 is formed on the surface of the semiconductor substrate 31 on which the extraction electrode 33 is formed so that at least a part of the extraction electrode 33 is exposed. That is, the protective film 34 is formed so as to be opened so that at least a part of the extraction electrode 33 is exposed at the position where the extraction electrode 33 is formed, and has an opening 34a. The protective film 34 is provided to protect the semiconductor element, the extraction electrode 33 and the signal wiring, and is typically made of an insulating material such as silicon nitride (SiN).

  In the present embodiment, the protective film 34 is formed so as to cover the end portion of the extraction electrode 33 and the signal wiring. Therefore, the opening size of the opening 34 a of the protective film 34 is smaller than the size of the extraction electrode 33. That is, the opening 34a of the protective film 34 has a length b1 in the left-right direction shorter than the length a1 in the left-right direction of the extraction electrode 33 (b1 <a1) toward the paper surface of FIG. The length b2 is shorter than the length a2 in the vertical direction of the extraction electrode 33 (b2 <a2).

  FIG. 17A is a cross-sectional view showing a state where the opening 33 a is formed in the extraction electrode 33. 17B is a plan view showing the semiconductor substrate 31 in which the opening 33a is formed in the extraction electrode 33 shown in FIG. 17A when viewed from the direction of the arrow 50. FIG. This corresponds to a cross-sectional view taken along the section line II in FIG. Of the exposed extraction electrode 33, at least the extraction electrode 33 at the position where the through electrode 4 is to be formed is removed by, for example, etching, so that the underlying passivation film 32 is exposed. The extraction electrode 33 is etched by a method generally used for metal etching, for example, a method using a solvent containing phosphoric acid or acetic acid.

  In the present embodiment, the extraction electrode 33 is removed and opened at a position including the position where the through electrode 4 is to be formed, so that an opening 33 a having an opening size smaller than the opening 34 a of the protective film 34 is formed. . That is, the opening 33a of the extraction electrode 33 has a length t1 in the left-right direction shorter than the length b1 in the left-right direction of the opening 34a of the protective film 34 (t1 <b1). The vertical length t2 is shorter than the vertical length b2 of the opening 34a of the protective film 34 (t2 <b2).

  FIG. 18A is a cross-sectional view showing a state in which a resist mask 35 is formed. 18B is a plan view showing the semiconductor substrate 31 on which the resist mask 35 shown in FIG. 18A is formed as viewed from the direction of the arrow 50. FIG. 18A is a plan view of FIG. This corresponds to a cross-sectional view seen from the section line II of FIG. As shown in FIG. 18, in the same manner as the step of forming the resist mask 14 shown in FIG. 3 of the first embodiment on the surface of the semiconductor substrate 31 on which the passivation film 32, the extraction electrode 33 and the protective film 34 are formed. Then, a resist mask 35 having an opening 35a at the position where the through electrode 4 is to be formed, which is the position of the opening 33a of the extraction electrode 33, which is the position where the extraction electrode 33 has been removed, is formed. That is, the resist mask 35 is formed to be open so that the passivation film 32 is exposed at least at a position where the through electrode 4 is to be formed, of the position of the opening 33 a of the extraction electrode 33.

  In this embodiment, the resist mask 35 is formed so that the extraction electrode 33 is not exposed. Therefore, the opening size of the opening 35 a of the resist mask 35 is smaller than the opening size of the opening 33 a of the extraction electrode 33. That is, the opening 35a of the resist mask 35 has a length d1 in the left-right direction shorter than the length t1 in the left-right direction of the opening 33a of the extraction electrode 33 (d1 <t1). The vertical length d2 is shorter than the vertical length t2 of the opening 33a of the extraction electrode 33 (d2 <t2). Similarly to the first embodiment, the resist mask 35 has a film thickness C2 of, for example, 20 so that it will not be opened at a position other than the opening 35a by etching in the steps shown in FIGS. It is formed to a thickness of about 30 μm.

FIG. 19 is a cross-sectional view showing a state where the passivation film 32 is etched. The passivation film 32 is etched using the resist mask 35 as a pattern mask, and the portion of the passivation film 32 corresponding to the opening 35a of the resist mask 35 is removed. Thereby, the passivation film 32 is opened corresponding to the pattern of the resist mask 35, and the semiconductor substrate 31 at the position where the through electrode 4 is to be formed is exposed. Etching of the passivation film 32 is performed by plasma etching using a fluorine-based gas such as carbon tetrafluoride (CF ₄ ), for example.

FIG. 20A is a cross-sectional view showing a state in which the deep hole 36 is formed. 20B is a plan view showing the semiconductor substrate 31 in which the deep hole 36 shown in FIG. 20A is formed as viewed from the direction of the arrow 50, and FIG. 20A is a plan view of FIG. This corresponds to a cross-sectional view seen from the section line II of FIG. The semiconductor substrate 31 is etched using the resist mask 35 as a pattern mask, and a deep hole 36 that penetrates the passivation film 32 from the surface of the passivation film 32 facing the resist mask 35 and reaches a predetermined portion inside the semiconductor substrate 31 is formed. . In other words, the depth D2 of the deep hole 36 from the surface of the semiconductor substrate 31 facing the passivation film 32 is smaller than the thickness T2 of the semiconductor substrate 31 (D2 <T2). Etching of the semiconductor substrate 31 is performed by anisotropic etching such as RIE using a fluorine-based gas such as sulfur hexafluoride (SF ₆ ) as in the first embodiment.

  The deep hole 36 has, for example, an opening of about 70 μm square, that is, the length s21 in the left-right direction and the length s22 in the up-down direction are about 70 μm toward the paper surface of FIG. The depth D2 from the surface facing 32 is about 100 μm. The opening size of the deep hole 36 is substantially equal to the opening size of the opening 35 a of the resist mask 35. That is, the length s21 of the deep hole 36 is substantially equal to the length d1 of the opening 35a of the resist mask 35 in the left-right direction toward the paper surface of FIG. 18B, and the length s22 of the deep hole 36 is The length 35 of the opening 35a of the resist mask 35 is substantially equal to the length d2 in the vertical direction toward the paper surface of FIG. Therefore, when the deep hole 36 having an opening of about 70 μm square is formed as described above, the opening portion 35a of the resist mask 35 shown in FIG. 18B described above is provided with the length d1 and the length d2. May be formed to be about 70 μm.

  FIG. 21 is a cross-sectional view showing a state in which the in-hole insulating film 37 is formed in the deep hole 36. In the state where the resist mask 35 used in the previous step is left without being removed, an in-hole insulating film 37 is formed on the wall surface of the deep hole 36 in the same manner as in the first embodiment.

  FIG. 22 is a cross-sectional view showing a state in which the conductive plug 38 is formed. As in the first embodiment, the conductive material is filled with a conductive material in the deep hole 36 in which the in-hole insulating film 37 is formed, that is, the inner space 37a of the in-hole insulating film 37, and heated as necessary. A conductive plug 38 is formed.

  FIG. 23 is a cross-sectional view showing a state where the resist mask 35 is removed. In the same manner as in the first embodiment, the resist mask 35 shown in FIG. 22 is removed. As a result, as shown in FIG. 23, the extraction electrode 33, the protective film 34, and the passivation film 32 covered with the resist mask 35 are exposed.

  FIG. 24A is a cross-sectional view showing a state where the conductive plug cap 39 is formed. 24B is a plan view showing the semiconductor substrate 31 on which the conductive plug cap 39 shown in FIG. 24A is formed as viewed from the direction of the arrow 50. FIG. 24A is a plan view of FIG. Corresponds to a cross-sectional view taken along the section line II of FIG. As shown in FIG. 24, a conductive plug cap 39, which is a surface wiring made of a conductive material, is formed so as to fill the opening 33a of the extraction electrode 33 and the opening 34a of the protective film 34. As a result, the extraction electrode 33 and the conductive plug 38 are electrically connected by the conductive plug cap 39. The conductive plug cap 39 can be formed by a simple method such as screen printing of a conductive paste as in the step of forming the surface wiring 18 shown in FIG. 10 of the first embodiment.

  FIG. 25 is a cross-sectional view showing a state in which the through electrode 4 is formed. The surface of the semiconductor substrate 31 on the opposite side of the surface on which the conductive plug cap 39 is formed is similar to the first embodiment in that the end on the inner side of the semiconductor substrate 31 of the conductive plug 38 shown in FIG. Polish until exposed and then retract. As a result, the conductive plug 38 enters the semiconductor substrate 31 and becomes the through electrode 4 that can lead out the extraction electrode 33 formed on one surface side of the semiconductor substrate 31 to the other surface side.

  As described above, in the method of forming the through electrode 4 according to the present embodiment, in the process shown in FIGS. 21 and 22, the deep hole 36 is insulated in the hole in the same manner as the method of forming the through electrode 2 of the first embodiment. When the film 37 and the conductive plug 38 are formed, the surface of the passivation film 32 other than the surface facing the deep hole 36 and the surfaces of the extraction electrode 33 and the protective film 34 are covered and protected by the resist mask 35. Therefore, of the insulating material and the conductive material used when forming the in-hole insulating film 37 and the conductive plug 38, the surplus insulating material and conductive material other than the deep hole 36 filled are deep holes. Adhering to the surface of the resist mask 35 without adhering to the surface of the passivation film 32 other than the surface facing the surface 36 and the surfaces of the extraction electrode 33 and the protective film 34, and simultaneously removed by lift-off when removing the resist mask 35 The

  As a result, the surface of the passivation film 32 other than the surface facing the deep hole 36, the extraction electrode 33, and the protective film, which are insulating materials and conductive materials used when forming the in-hole insulating film 37 and the conductive plug 38. The through electrode 4 can be formed without contaminating the surface 34.

  In the present embodiment, as shown in FIG. 18, the resist mask 35 does not expose the extraction electrode 33, that is, the opening dimension of the opening 35a of the resist mask 35 is larger than the opening dimension of the opening 33a of the extraction electrode 33. However, a part of the extraction electrode 33, for example, the surface facing the deep hole 36 of the extraction electrode 33 as shown in FIG. 26A is exposed, that is, the opening of the resist mask 35. 35a and the opening 33a of the extraction electrode 33 may be formed to substantially coincide with each other. However, in this case, when the in-hole insulating film 37 is formed in the deep hole 36, the hole exceeds the depth E2 of the deep hole 36 to the height where the extraction electrode 33 is formed as shown in FIG. When the inner insulating film 37 is formed, the in-hole insulating film 37 is formed in contact with the extraction electrode 33. Therefore, the surface area of the extraction electrode 33 exposed after the removal of the resist mask 35 is an area in contact with the in-hole insulating film 37. It gets smaller by the minute. Therefore, as shown in FIG. 26B, the contact area between the conductive plug cap 39 and the extraction electrode 33 formed after the removal of the resist mask 35 is also reduced.

  On the other hand, in the present embodiment, as described above, the resist mask 35 is formed so that the extraction electrode 33 is not exposed. Therefore, when forming the in-hole insulating film 37 in the deep hole 36, as shown in FIG. Even if the in-hole insulating film 37 is formed to the height at which the extraction electrode 33 is formed beyond the depth E2 of the deep hole 36, the in-hole insulating film 37 is formed in contact with the resist mask 35, and the extraction electrode 33 It is not formed in contact with 33. Therefore, the surface area of the extraction electrode 33 exposed after the removal of the resist mask 35 can be increased compared to the case where the resist mask 35 is formed so that a part of the extraction electrode 33 is exposed as shown in FIG. As shown in FIG. 24, the contact area between the conductive plug cap 39 and the extraction electrode 33 formed after the removal of the resist mask 35 is increased, and the electrical resistance of the connection portion between the extraction electrode 33 and the conductive plug cap 39 is decreased. Can do.

  From the above, the resist mask 35 is preferably formed so that the extraction electrode 33 is not exposed as in the present embodiment.

The manufacturing method of the semiconductor device 3 which is still another embodiment of the present invention includes the method of forming the through electrode 4 of the present embodiment and further includes the following steps. That is, after the through electrode 4 is formed in the step shown in FIG. 25, an insulating film made of an insulating material as shown in FIG. 14 is formed on the surface of the semiconductor substrate 31 exposed by polishing when the through electrode 4 is formed. 42 is formed. The insulating film 42 is made of, for example, silicon dioxide (SiO ₂ ). Next, as shown in FIG. 14, the surface wiring 43 and the protruding electrode 44 made of a conductive material are formed so that electrical connection is obtained at a predetermined place, and the semiconductor chips 40a and 40b are obtained. The protruding electrode 44 is provided so as to protrude from the semiconductor substrate 31. The protruding electrode 44 and the through electrode 4 of the semiconductor chip 40 a are electrically connected by the surface wiring 43. The obtained semiconductor chips 40a and 40b are stacked on the circuit board 41 on which the electronic circuit is formed via the through electrode 4, the conductive plug cap 39, the surface wiring 43, and the protruding electrode 44. The semiconductor device 3 can be manufactured as described above.

  The method for forming the buried electrode according to the present invention is not limited to the case of forming the through electrodes 2 and 4 penetrating the semiconductor substrates 11 and 31 as in the first and second embodiments described above. Also, it can be used when forming an electrode that does not penetrate through the semiconductor substrates 11 and 31 and reaches the inside of the semiconductor substrates 11 and 31 from one surface side of the semiconductor substrates 11 and 31. Such a buried electrode that does not penetrate the semiconductor substrate is used as an electrode reaching the drain region or the source region formed inside the semiconductor substrate, or a capacitor. In the case where the buried electrode that does not penetrate the semiconductor substrates 11 and 31 is formed as described above, the step of retracting the surface of the semiconductor substrates 11 and 31 until the conductive plugs 17 and 38 shown in FIG. It is unnecessary.

  The method for forming a buried electrode according to the present invention is a method for forming a buried electrode reaching a semiconductor substrate or a lower interlayer insulating film from a lead electrode or signal wiring formed on the surface of the interlayer insulating film provided on the semiconductor substrate. Can also be used. In this case, a deep hole reaching the semiconductor substrate or the lower interlayer insulating film from the surface of the interlayer insulating film is formed in the same manner as the step of forming the deep hole shown in FIGS. 4 to 5 or 19 to 20. . According to the method for forming a buried electrode of the present invention, even if the buried electrode is formed after forming the lead electrode or the signal wiring on the surface of the interlayer insulating film, the lead electrode or the signal wiring on the surface of the interlayer insulating film is not a deep hole. In addition, since the conductive layer is not contaminated with the material used for forming the conductive layer, a highly reliable multilayer wiring without a short circuit between the wirings can be formed.

  In addition, the method of forming the buried electrode according to the present invention is not limited to the case of forming the buried electrode on the semiconductor substrate, but is buried in various substrates such as an insulating substrate made of an insulating material such as resin. It can also be used when forming an electrode.

1 is a schematic cross-sectional view schematically showing a configuration of a semiconductor device 1 having a through electrode 2. 2 is a view showing a state in which an interlayer insulating film 12 and a signal wiring 13 are formed on a semiconductor substrate 11. FIG. It is a figure which shows the state in which the resist mask 14 was formed. It is a figure which shows the state which etched the interlayer insulation film. It is a figure which shows the state in which the deep hole 15 was formed. It is a figure which shows the state which formed the in-hole insulating film 16 in the deep hole 15. FIG. It is a figure which shows typically the method of forming the insulating film 16 in a hole. It is a figure which shows the state in which the conductive plug 17 was formed. It is a figure which shows the state which removed the resist mask. It is a figure which shows the state in which the surface wiring 18 was formed. It is a figure which shows the state in which the penetration electrode 2 was formed. It is a figure which shows typically the method of filling the photosensitive insulating material 20 using the resist mask 14 as a pattern mask. It is sectional drawing which shows typically the state of each process in formation of the insulating film 16 in the hole by CVD method. 2 is a schematic cross-sectional view schematically showing a configuration of a semiconductor device 3 having a through electrode 4. FIG. FIG. 15A is a cross-sectional view showing a state where the passivation film 32 and the extraction electrode 33 are formed on the semiconductor substrate 31. FIG. 15B is a plan view showing the semiconductor substrate 31 on which the passivation film 32 and the extraction electrode 33 shown in FIG. FIG. 16A is a cross-sectional view showing a state in which the protective film 34 is formed. FIG. 16B is a plan view showing the semiconductor substrate 31 formed with the protective film 34 shown in FIG. FIG. 17A is a cross-sectional view showing a state where the opening 33 a is formed in the extraction electrode 33. FIG. 17B is a plan view showing the semiconductor substrate 31 in which the opening 33a is formed in the extraction electrode 33 shown in FIG. FIG. 18A is a cross-sectional view showing a state in which a resist mask 35 is formed. FIG. 18B is a plan view showing the semiconductor substrate 31 on which the resist mask 35 shown in FIG. It is sectional drawing which shows the state which etched the passivation film 32. FIG. FIG. 20A is a cross-sectional view showing a state in which the deep hole 36 is formed. FIG. 20B is a plan view showing the semiconductor substrate 31 formed with the deep hole 36 shown in FIG.

4 is a cross-sectional view showing a state in which an in-hole insulating film 37 is formed in the deep hole 36. FIG. It is sectional drawing which shows the state in which the conductive plug 38 was formed. It is sectional drawing which shows the state which removed the resist mask. FIG. 24A is a cross-sectional view showing a state where the conductive plug cap 39 is formed. FIG. 24B is a plan view showing the semiconductor substrate 31 formed with the conductive plug cap 39 shown in FIG. It is sectional drawing which shows the state in which the penetration electrode 4 was formed. FIG. 5 is a cross-sectional view showing a state in which an in-hole insulating film 37 and a conductive plug cap 39 are formed when the resist mask 35 is formed so that the surface facing the deep hole 36 of the extraction electrode 33 is exposed. It is sectional drawing which shows the structure of the semiconductor device 100 which has a laminated structure typically. 2 is a view showing a state in which a connection hole 103 is formed in an interlayer insulating film 102 provided on a semiconductor substrate 101. FIG. It is a figure which shows the state in which the electrically conductive film 104 was formed. FIG. 6 shows a state in which a resist mask 105 is formed on a conductive film 104. It is a figure which shows the state which etched the electrically conductive film. It is a figure which shows the state which removed the resist mask 105. FIG. It is a figure which shows the state which formed the deep hole. It is a figure which shows the state which formed the wiring 104a. It is a figure which shows the state in which the insulating film 107 and the electrically conductive film 108 were formed. It is a figure which shows the state in which the conductive plug 108a was formed. It is a figure which shows the state in which the penetration electrode 109 was formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,3 Semiconductor device 2,4 Through electrode 11,31 Semiconductor substrate 12 Interlayer insulating film 13 Signal wiring 14,35 Resist mask 14a, 35a Opening 15,36 Deep hole 16,37 In-hole insulating film 16a, 37a Internal space 17 , 38 Conductive plug 18, 43 Surface wiring 25a, 25b, 25c, 40a, 40b Semiconductor chip 26, 41 Circuit board 27, 44 Protruding electrode 32 Passivation film 33 Extraction electrode 33a Opening 34 Protective film 34a Opening 39 Conductive plug cap 42 Insulation film

Claims (13)

A method of forming a buried electrode provided to be embedded in a substrate on which an element and a signal wiring electrically connected to the element are formed, and electrically connected to the signal wiring,
Forming a resist mask having an opening at a predetermined position on the surface of the substrate on which the signal wiring is formed so as to form the embedded electrode so as to cover the signal wiring;
Etching the substrate on which the resist mask is formed to form a deep hole;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
And forming a surface wiring for electrically connecting the signal wiring and the conductive layer. An embedded electrode that is provided so as to be embedded in a position where the extraction electrode is formed on a substrate on which an element and an extraction electrode electrically connected to the element are formed, and is electrically connected to the extraction electrode A forming method comprising:
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
Forming a resist mask having an opening at a predetermined position for forming the embedded electrode on the surface of the substrate on which the extraction electrode is formed;
Etching the substrate on which the resist mask is formed to form a deep hole;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
Forming a buried surface electrode for electrically connecting the extraction electrode and the conductive layer. After the step of forming the surface wiring,
The surface opposite to the substrate of the surface wiring formed surface forming method according to claim 1 or 2, wherein the buried electrode, characterized in that it further comprises the step of retracting to said conductive layer is exposed. The extraction electrode of the semiconductor substrate in which an element, an interlayer insulating film provided so as to cover the element, and an extraction electrode provided on the interlayer insulating film and electrically connected to the element are formed. A method of forming a buried electrode provided to be buried in a position and electrically connected to the extraction electrode,
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
On the surface of the semiconductor substrate on which the interlayer insulating film and the extraction electrode are formed, a resist mask having an opening at a position where the extraction electrode is removed and at a predetermined position to form the embedded electrode Forming, and
Removing the interlayer insulating film in a portion corresponding to the opening of the resist mask;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Forming an in-hole insulating film in the deep hole while leaving the resist mask;
Filling the deep hole in which the in-hole insulating film is formed with a conductive material up to a height at which a resist mask is formed by a printing method, and forming a conductive layer;
Removing the resist mask;
Forming a buried surface electrode for electrically connecting the extraction electrode and the conductive layer. On the surface of the semiconductor substrate on which the interlayer insulating film and the extraction electrode are formed, a resist mask having an opening at a position where the extraction electrode is removed and at a predetermined position to form the embedded electrode In the process of forming,
5. The method of forming a buried electrode according to claim 4 , wherein the resist mask is formed so that the extraction electrode is not exposed. After the step of forming the surface wiring that electrically connects the extraction electrode and the conductive layer,
It said semiconductor substrate surface opposite to the surface wiring formed surface forming method according to claim 4 or 5, wherein the buried electrode, characterized in that it further comprises the step of retracting to said conductive layer is exposed. The step of removing the resist mask includes:
Method of forming a buried electrode according to any one of claims 1-6, characterized in that the step of removing the resist mask using a solvent. The step of forming a conductive layer in the deep hole includes:
Wherein the deep hole, any one of claims 1-7, characterized in that it comprises a step of filling a conductive material is filled with a conductive material to a height resist mask is formed by a printing method A method for forming a buried electrode according to claim 1. The step of forming a conductive layer in the deep hole includes:
The method further includes the step of heating the conductive material after the step of filling the deep hole with the conductive material,
The method for forming an embedded electrode according to claim 8 , wherein the conductive material includes conductive particles having a particle diameter of 1 nm to 10 nm. The conductive layer of gold, silver, the method of forming the buried electrode according to any one of claims 1-9, characterized in that the copper and based on at least one of nickel. A semiconductor substrate; an element provided on the semiconductor substrate; a signal wiring provided on the semiconductor substrate and electrically connected to the element; and embedded in the semiconductor substrate and electrically connected to the signal wiring. A method of manufacturing a semiconductor device having a buried electrode to be connected,
Forming an element and a signal wiring electrically connected to the element on a semiconductor substrate;
Forming a resist mask having an opening at a predetermined position to form the embedded electrode on the surface of the semiconductor substrate on which the signal wiring is formed, so as to cover the signal wiring;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
Forming a surface wiring for electrically connecting the signal wiring and the conductive layer. A semiconductor substrate, an element provided on the semiconductor substrate, an extraction electrode provided on the semiconductor substrate and electrically connected to the element, and embedded in a position where the extraction electrode is formed on the semiconductor substrate A method of manufacturing a semiconductor device having a buried electrode provided and electrically connected to the extraction electrode,
Forming an element and an extraction electrode electrically connected to the element on a semiconductor substrate;
Removing at least the extraction electrode at a predetermined position to form the embedded electrode;
Forming a resist mask having an opening at a predetermined position to form the buried electrode on the surface of the semiconductor substrate on which the extraction electrode is formed;
Etching the semiconductor substrate on which the resist mask is formed to form deep holes;
Filling the deep hole with a conductive material up to a height at which the resist mask is formed by a printing method while leaving the resist mask, and forming a conductive layer;
Removing the resist mask;
Forming a surface wiring for electrically connecting the extraction electrode and the conductive layer. A method for manufacturing a semiconductor device, comprising: After the step of forming the surface wiring,
It said semiconductor substrate surface opposite to the surface wiring formed surface, a method of manufacturing a semiconductor device according to claim 11 or 12, wherein said conductive layer is characterized in that it further comprises the step of retracting to expose.

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