JP4350810B2 - Discharge lamp device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a discharge lighting device for lighting a high-pressure discharge lamp, and is particularly suitable for application to a vehicle front illumination lamp device.
[0002]
[Prior art]
When a high-pressure discharge lamp (hereinafter referred to as a discharge lamp) is used for a vehicle lamp, the primary side battery voltage (DC power supply voltage) is converted to a high voltage via a transformer, and the discharge lamp arranged on the secondary side Lights up.
Further, the current flowing through the primary side of the transformer is controlled so that predetermined energy (electric power) is supplied to the secondary side discharge lamp when the discharge lamp is lit. Specifically, the primary current is controlled to be turned on and off by a MOS transistor serving as a switch, and the on / off timing (duty ratio) of the MOS transistor is adjusted by a PWM controller, whereby the primary current of the transformer is adjusted. Is controlling.
[0003]
Here, when using a transformer that stores energy on the primary side during the on-time of the MOS transistor and supplies energy stored during the off-time of the MOS transistor to the secondary side, use a transformer on the primary side. The PWM control device sets the ON time of the MOS transistor so that the ON / OFF timing is such that the MOS transistor is turned on until a predetermined energy is accumulated.
[0004]
That is, when the battery voltage decreases, the on-time of the MOS transistor is set to be long compared to when the battery voltage is sufficient, and thus the primary voltage of the flyback transformer is related to the level of the battery voltage. Instead, the same energy is stored.
[0005]
[Problems to be solved by the invention]
Here, FIGS. 25A and 25B show the current waveforms on the primary side when the battery voltage is sufficient and when the battery voltage decreases, respectively. However, in order to simplify the explanation, here, waveforms are shown when the secondary side of the transformer is not a winding.
[0006]
As shown in FIGS. 25A and 25B, during the on-time of the MOS transistor, the primary current I increases according to a predetermined time constant, and the predetermined energy is accumulated on the primary side of the flyback transformer. The Thereafter, the stored energy is supplied to the secondary side of the flyback transformer during the off-time of the MOS transistor.
At this time, when the battery voltage is sufficient, the off time of the MOS transistor is long, so the accumulated energy is sufficiently supplied to the secondary side of the flyback transformer. Since the off-time of the transistor is short, the on-time of the MOS transistor comes before all of the stored energy is supplied to the secondary side of the flyback transformer, and sufficient energy supply cannot be performed. is there.
[0007]
The present invention has been made in view of the above problems, and an object thereof is to sufficiently supply energy to the secondary side of a transformer even when the voltage of a DC power supply is lowered.
[0008]
[Means for Solving the Problems]
  In order to achieve the above object, the following technical means are adopted.
  In invention of Claims 1 thru | or 4, the voltage of DC power supply (1)And before or after the discharge lamp (2) is litAccording toThe,The duty ratio is set so that predetermined power is supplied from the DC power supply (1) to the discharge lamp (2).When the voltage of the DC power supply (1) dropsThan before the declineLower switching frequencySet and set the switching frequency lower than before lighting regardless of the voltage of the DC power supply (1) before lighting.It is characterized by that.
[0009]
If the switching frequency is lowered in accordance with the voltage drop of the DC power supply (1), the primary current is not only when the voltage of the DC power supply (1) is low but also when the voltage of the DC power supply (9) is low. Become big enough. For this reason, even when the voltage of the DC power supply (9) decreases, the total sum (W) of energy accumulated on the primary side of the transformer (29) can be increased.
[0010]
  Also, because the frequency is low,Switching meansThe time during which (31) is turned off also becomes longer, and energy can be sufficiently supplied to the secondary side of the transformer (29). Thereby, even when the voltage of the DC power supply (1) is lowered, it is possible to sufficiently supply energy to the secondary side of the transformer (29).
[0011]
Specifically, the switching frequency may be set linearly, as shown in claim 2, such that the switching frequency is lowered as the voltage of the DC power supply (1) is lowered. As such, it may be performed step by step.
In order to lower the switching frequency, for example, the frequency of the sawtooth wave may be lowered.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present embodiment, the discharge lamp device 100 of the present invention is applied to a vehicle headlamp. FIG. 1 is an overall configuration diagram of a discharge lamp device 100 in the present embodiment, and FIG. 2 is a block diagram of a control system of the discharge lamp device 100 in the present embodiment.
[0013]
Reference numeral 1 denotes a DC power source (hereinafter referred to as a battery, rated voltage (battery voltage VB) 12V) mounted on the vehicle, 1a being a power terminal, 1b being a ground terminal, and 2 being a high voltage such as a metal halide lamp which is a vehicle headlamp. It is a discharge lamp (hereinafter referred to as a lamp). SW is a lighting switch that is provided in the passenger compartment and sets the lamp 2 to be turned on or off by a user operation. Reference numeral 50 denotes a fuse that is blown when an overcurrent flows through the discharge lamp device 100.
[0014]
As shown in FIG. 1, the discharge lamp device 100 includes a reverse connection protection circuit 3, a smoothing circuit 4, a DC power supply circuit 5 having a flyback transformer 29, a takeover circuit 6, an inverter circuit 7 including an H bridge circuit 7a, and a starting circuit 8. Etc. have a circuit function unit.
In the present embodiment, as shown in FIG. 2, as a control circuit for controlling the circuit function unit, the lamp power is changed to a desired power based on a PWM (pulse width modulation) control circuit 9, a lamp voltage VL and a lamp current IL described later. A lamp power control circuit 10 for controlling the H bridge, an H bridge control circuit 11 for controlling the H bridge circuit 7a, and the like.
[0015]
In the present embodiment, in addition to the control circuit, a sample hold circuit 12 that samples and holds the lamp voltage VL at a predetermined timing, and the start circuit 8 is controlled at the start of lamp lighting to control the lamp 2 with a high voltage. Is applied to the high voltage generation control circuit 13 for causing the lamp 2 to break down between the electrodes, and the discharge lamp device 100 is a fail for controlling the H bridge circuit 7a through the H bridge control circuit 11 when the discharge lamp device 100 enters an abnormal state to be described later. A safe circuit 14 and a connector disconnection detection circuit 15 that detects disconnection of the connector 35 of the lamp 2 are provided.
[0016]
Furthermore, the driving power of each control circuit 9-15 is performed based on the battery voltage VB or the like, but when the primary side voltage becomes an overvoltage, the overvoltage for protecting each control circuit 9-15 from this overvoltage. The protection circuit 16 is also provided in the discharge lamp device 100.
Here, first, an outline of the lighting operation of the discharge lamp device 100 will be described. When the lighting switch SW is turned on, the battery voltage VB is boosted by the flyback transformer 29, whereby the capacitor 53 of the starting circuit 8 is charged through the H bridge circuit 7a. When the capacitor 53 is charged, the charge charged in the starting circuit 8 is discharged, and the voltage further increased by the transformer 47 is applied to the lamp 2, and the lamp 2 is dielectrically broken between the electrodes. Then it comes on.
[0017]
Thereafter, when the lamp 2 is lit, the polarity of the discharge voltage to the lamp 2 (the direction of the discharge current) is alternately switched by the H bridge circuit 7a, whereby the lamp 2 is lit in an alternating current.
Next, the outline of the configuration of the circuit function unit and the control circuit will be briefly described.
[0018]
  The reverse connection protection circuit 3 includes a resistor 17, a capacitor 19, and a MOS transistor21It consists of. The reverse connection protection circuit 3 protects the MOS transistor 21 when a negative high voltage is generated at a power supply terminal to be described later. In addition, the fuse 50 is prevented from being blown when the battery 1 is reversely connected to the vehicle with the polarity reversed.
[0019]
The smoothing circuit 4 smoothes the voltage generated at the power supply terminal 1a, and is a capacitor input type smoothing circuit (choke input type smoothing circuit) comprising capacitors 23 and 25 and a coil 27.
The DC power supply circuit 5 has a flyback transformer 29 in which the primary side and the secondary side are both constituted by windings. The flyback transformer 29 has a primary winding 29a disposed on the battery side and a secondary winding 29b disposed on the lamp 2 side. In the flyback transformer 29, the primary winding 29a and the secondary winding 29b can be electrically connected as shown in FIG. The DC power supply circuit 5 is provided with a MOS transistor 31 that is switching-controlled by the PWM circuit 9. The primary current of the primary winding 29a is controlled by the MOS transistor 31.
[0020]
That is, in the flyback transformer 29, when the MOS transistor 31 is on, a primary current flows through the primary winding 29a, so that energy is stored in the primary winding 29a. The flyback transformer 29 supplies the energy of the primary winding 29a to the secondary winding 29b when the MOS transistor 31 is turned off.
[0021]
The secondary winding 29 b of the DC power supply circuit 5 is provided with a rectifying diode 33 and a smoothing capacitor 35.
The takeover circuit 6 includes a capacitor 37 and a resistor 39. The capacitor 37 is charged when the lighting switch SW is turned on. The takeover circuit 6 causes the lamp 2 to break down between the electrodes by the starting circuit 8 and then promptly shifts to arc discharge.
[0022]
The inverter circuit 7 is provided on the secondary winding 29b side of the flyback transformer 29, and turns on the lamp 2 by alternating current by converting the power from the battery 1 into alternating current.
The H bridge circuit 7a constituting the inverter circuit 7 alternately reverses the direction of the discharge current of the lamp 2. The H bridge circuit 7a includes four MOS transistors 41a to 41d that form a plurality of bridge semiconductor switching elements arranged in an H bridge shape. These four MOS transistors 41a to 41d are controlled by a bridge drive circuit (in this example, an IC element, hereinafter referred to as an IC element) indicated by 43a and 43b in the drawing.
[0023]
The bridge control circuit 11 controls the IC elements 43a and 43b so that when the MOS transistors 41a and 41d on the diagonal line in the H bridge circuit 7a are in the off state, the MOS transistors 41b and 41c on the diagonal line are switched. When the MOS transistors 41b and 41c are in the on state, the MOS transistors 41a and 41d are switched to the off state. As a result, the direction of the discharge current of the lamp 2 is alternately switched, in other words, the polarity of the applied voltage (discharge voltage) of the lamp 2 is reversed, so that the lamp 2 is turned on by alternating current.
[0024]
The H bridge circuit 7a is configured to turn on / off the MOS transistors 41a to 41d with a long constant cycle at the start of lamp lighting, and thereafter turn on / off the MOS transistors 41a to 41d with a short constant cycle. In the figure, reference numeral 45 denotes a protective capacitor for protecting the H-bridge circuit 7a from a high-voltage pulse generated at the start of lighting.
[0025]
The starting circuit 8 starts lighting the lamp 2, and is installed between the midpoint potential point of the H bridge circuit 7a and the ground terminal 1b. The starting circuit 8 includes a transformer 47 including a primary winding 47a and a secondary winding 47b, diodes 49 and 51, a capacitor 53, a resistor 55, and a thyristor 57 that is a unidirectional semiconductor element.
[0026]
The thyristor 57 is turned off when the lighting switch SW is turned on, whereby the capacitor 53 starts charging. Thereafter, the high voltage generation control circuit 13 turns on the thyristor 57. As a result, the capacitor 53 starts discharging. Then, the energy stored in the capacitor 53 is increased to a high voltage through the transformer 47 so that a high voltage is applied to the lamp 2. As a result, the lamp 2 is turned on with dielectric breakdown between the electrodes.
[0027]
The PWM control circuit 9 controls the on / off time of the MOS transistor 31, that is, the duty ratio, by making the threshold level for the sawtooth wave variable.
The lamp power control circuit 10 controls the lamp power to be a desired value based on the lamp current IL and the lamp voltage VL sampled and held by the sample hold circuit 12. The lamp current IL is detected by a current detection resistor 59 provided in the H bridge circuit 7a.
[0028]
The lamp power control by the lamp power control circuit 10 in the present embodiment is as follows.
Since the lamp power control circuit 10 is likely to turn off the lamp 2 if the electrode temperature of the lamp 2 is low at the start of lighting of the lamp 2, the lamp power is set to a large value (for example, 75 W) and the electrode temperature is quickly increased. When the lamp gradually increases, the lamp power is gradually decreased, and when the lamp 2 is in a stable state, the lamp power is controlled to be constant at a predetermined value (35 W).
[0029]
In addition, immediately after the lamp voltage VL becomes a high voltage (for example, 400 V) and the lighting of the lamp 2 is started, the lamp voltage VL becomes the smallest, and then the lamp voltage VL gradually increases. On the other hand, the lamp current IL gradually decreases against the lamp voltage VL immediately after the lamp 2 is turned on.
In order to perform such lamp power control, the PWM control circuit 9 receives a command signal from the lamp power control circuit 10 and varies the on / off duty ratio of the MOS transistor 31. Control lamp power.
[0030]
The sample hold circuit 12 masks a later-described transient voltage generated when the H bridge circuit 7a is switched in the lamp voltage VL, and performs the control by the lamp power control circuit 10 with high accuracy.
The fail-safe circuit 14 stops the control of the PWM control circuit 9 and turns off all conduction of the MOS transistors 41a to 41d of the H bridge circuit 7a when any abnormality occurs in the discharge lamp device 100. is there.
[0031]
The control circuits 9 to 15 are all provided in an integrated circuit (not shown).
[Starting circuit 8]
Next, details of the starting circuit 8 will be described. The starting circuit 8 starts lighting the lamp 2, and is installed between the midpoint potential point of the H bridge circuit 7a and the ground terminal 1b.
[0032]
The operation of the starting circuit 8 will be described based on the time chart shown in FIG. However, in FIG. 3, (a) is the voltage Vlamp across the lamp 2, (b) is the capacitor charging voltage Vc, (c) is the gate drive signal output to the gate of the thyristor 57, (d ) Is a high voltage generated in the secondary winding 47b.
When the lighting switch SW is turned on, the MOS transistors 41a to 41d constituting the H bridge circuit 7a are turned on / off (at time t1 in FIG. 3). When the MOS transistors 41a and 41d are turned on, a low level signal is output as the gate drive signal, and the thyristor 57 is turned off. As a result, the capacitor 53 starts to be charged (time t2 in FIG. 3). After the capacitor 53 is sufficiently charged during the ON period of the MOS transistors 41a and 41d, the MOS transistors 41a and 41d are turned off and the MOS transistors 41b and 41c are turned on (at time t3 in FIG. 3).
[0033]
When the gate drive signal of the thyristor 57 is changed to a high level signal, the thyristor 57 is turned on and a current flows, and a high voltage is generated in the secondary winding 47b of the transformer 47 (at time t4 in FIG. 3). This high voltage is applied to the lamp 2, and dielectric breakdown occurs between the electrodes of the lamp 2, and the lamp 2 starts to light (at the time point t5 in FIG. 3).
Further, by connecting the diode 51 in parallel to the thyristor 57, LC resonance is caused by the capacitor 53 and the primary winding 47a when the thyristor 57 is turned on. When dielectric breakdown occurs between the electrodes of the lamp 2 due to a high voltage from the secondary winding 47b, a spark discharge current flows between the electrodes of the lamp 2, and this spark discharge current becomes a damped oscillation current due to the LC resonance. Thereby, the duration of the spark discharge current can be made much longer than when the diode 51 is not connected.
[0034]
The lamp voltage while the spark discharge current is flowing in the lamp 2 becomes lower than the charging voltage of the capacitor 35 and the capacitor 37. At this time, the lamp 2 is turned on by flowing into the lamp 2 via the H bridge circuit 7a. Start. Therefore, by connecting the diode 51, the duration of the spark discharge current is lengthened, and a current sufficient to reliably start lighting from the capacitor 35 and the capacitor 37 via the H bridge circuit 7a is allowed to flow. Thus, the lamp 2 can be reliably turned on. That is, the lighting performance of the lamp 2 can be improved.
[0035]
Since the capacitor 53 is charged at the midpoint potential point of the H bridge circuit 7a, the high voltage side potential of the capacitor becomes 0V when the MOS transistors 41a to 41d are switched on / off. For this reason, the thyristor 57 can be reliably turned off. That is, once the thyristor 57 is turned on, it is not turned off until a predetermined condition (for example, the anode side potential of the thyristor 57> the cathode side potential) is satisfied. In such a case, the capacitor 53 cannot be charged again. For this reason, if the lamp 2 is not lit in the first cycle of turning on / off the MOS transistors 41a to 41d, the lamp 2 cannot be lit after that. However, depending on the midpoint potential point of the H bridge circuit 7a. Since the capacitor 53 is charged, this can be prevented, and the lamp 2 can be reliably turned on.
[0036]
Further, since the capacitor 53 is charged at the midpoint potential point that is the secondary side of the flyback transformer 29, the capacitor 53 is charged by the voltage that has been converted into a high voltage by the DC power supply circuit 5. . Conventionally, a transformer for increasing the voltage across the capacitor 53 is provided separately from the DC power supply circuit 5. However, it is not necessary to provide a transformer only for this purpose. Thus, since the start circuit 8 and the DC power supply circuit 5 share the flyback transformer 29, the number of transformers can be reduced to one, and the cost can be reduced.
[0037]
The gate drive signal is output from the high voltage generation control circuit 13 in synchronization with the switching timing of the MOS transistors 41a to 41d. The high voltage generation control circuit 13 is connected to the MOSs 41a to 41d from the H bridge control circuit 11. A signal notifying the switching timing is input, and the output timing of the gate drive signal is set based on this signal.
[0038]
Further, when the lamp 2 is turned on, there is no need to drive the starter circuit 8, so that a low level signal is output as the gate drive signal. This lamp lighting is determined by whether or not the lamp current IL is a predetermined value or more. That is, when the lamp 2 is turned on, the lamp current IL flows through the current detection resistor 32 via the H bridge circuit 7a. Therefore, when the lamp current IL is detected, the gate drive signal is set to a low level signal.
[0039]
[Driving circuit for IC elements 43a and 43b]
Next, driving of the IC elements 43a and 43b will be described. FIG. 4 shows a circuit diagram for driving the IC elements 43a and 43b. However, FIG. 4 partially deletes the configuration requirements in FIG.
The IC element 43a uses a high-and-low driver circuit (International Rectifier, IR2101). The configurations of the IC elements 43a and 43b are exactly the same.
[0040]
Each power supply terminal Vcc of the IC elements 43 a and 43 b is connected to the secondary side of the flyback transformer 29. That is, on the secondary side of the flyback transformer 29, a first power supply circuit 96 composed of a resistor 95 and a Zener diode 97 is provided, and the voltage applied to the power supply terminal Vcc is generated by the first power supply circuit 96. It becomes a predetermined voltage V2 (15V).
[0041]
  Further, the high voltage side input terminal Hin of the IC element 43a and the low voltage side input terminal Lin of the IC element 43b are connected. A high level signal or a low level signal from the terminal 11a in the H bridge control circuit 11 is similarly input to these two terminals Hin and Lin. Further, the low voltage side input terminal Lin of the IC element 43a and the high voltage side input terminal Hin of the IC element 43b are connected. A high level signal or a low level signal from the terminal 11b of the H bridge control circuit 11 is similarly input to these two terminals Hin and Lin. And the H bridge control circuit 11Terminals 11a, 11bThe high level signal and the low level signal are inverted from each other.
[0042]
Briefly, when a high level signal is output from the terminal 11a of the H bridge control circuit 11 and a low level signal is output from the terminal 11b, the MOS transistors 41a and 41d are turned on and the MOS transistors 41b and 41c are turned off. Become. When a low level signal is output from the terminal 11a of the H bridge control circuit 11 and a high level signal is output from the terminal 11b, the MOS transistors 41b and 41c are turned on and the MOS transistors 41a and 41d are turned off.
[0043]
As described above, in the present embodiment, the IC elements 43a and 43b are controlled by the H-bridge control circuit 11 using the secondary voltage (the lamp voltage) generated in the secondary winding 29b. It has become. Thereby, even if the battery voltage VB decreases, the drive voltage is obtained from the secondary side of the flyback transformer 29, whereby the MOS transistors 41a to 41d can be stably driven and controlled.
[0044]
By the way, the IC elements 43a and 43b can be driven and controlled by the primary side voltage (battery voltage VB) through the diode 99 which is a unidirectional semiconductor switching element in addition to the secondary side voltage of the transformer 29. ing. This is because of the following two reasons.
(1) By the lamp power control circuit 10 described above, the lamp power of the lamp 2 is a lamp voltage VL (voltage signal) corresponding to the discharge voltage of the lamp 2, and a lamp current IL (current signal) corresponding to the discharge current of the lamp 2. Based on the above, feedback control is performed so as to obtain a desired value.
[0045]
For example, immediately after the lighting switch SW is turned on, no voltage is generated on the secondary winding 29b side. Therefore, immediately after the lighting switch SW is turned on, the H bridge circuit 7a cannot be driven and control delay or feedback control may become unstable in the worst case.
Therefore, in this example, the IC elements 43a and 43b can be driven by the battery voltage VB so that the H bridge circuit 7a can be driven and controlled immediately after the lighting switch SW is turned on.
[0046]
(2) If the lamp voltage VL drops below the predetermined voltage Vr1 and enters an abnormal state to be described later, the driving power for the IC elements 43a and 43b is insufficient, and the H bridge circuit 7a is turned off (the MOS transistors 41a to 41d are turned on). All are in a cut-off state, and hereinafter this cannot be referred to as turning off the H-bridge circuit 7a).
Therefore, in this example, when the IC elements 43a and 43b are in the abnormal state, the driving power is obtained from the battery voltage VB. Thereby, the H bridge circuit 7a can be reliably turned off in the abnormal state.
[0047]
In the abnormal state, the H bridge circuit 7a is turned off through the IC elements 43a and 43b by setting the two output signals of the first abnormality circuit indicated by 242 in FIG. 4 to high level signals.
When the battery voltage VB is 12V, the voltage applied to each power supply terminal Vcc of the IC elements 43a and 43b is controlled to a constant voltage of 15V by the Zener diode 97. Accordingly, the diode 99 in FIG. 4 functions to prevent backflow. Reference numeral 101 denotes a noise removing capacitor, and reference numeral 420 denotes a current limiting resistor.
[0048]
[About the driving power source of the MOS transistor 31]
Next, how to obtain the driving power source of the MOS transistor 31 will be described with reference to FIG.
On the secondary side of the transformer 29, there is provided a first power supply circuit 96 that makes the high voltage generated on the secondary side constant to a predetermined voltage V2 (for example, 15V) by the resistor 95 and the Zener diode 97. Yes.
[0049]
On the battery 1 side (primary side), a second power supply circuit 110 that obtains a predetermined voltage V3 (second predetermined voltage) determined by the battery voltage by a resistor 105 and a capacitor 107 is provided.
Between the first power supply circuit 96 and the second power supply circuit 110, a diode 111 serving as switching means is provided on the first power supply circuit 96 side via a resistor 120.
[0050]
The diode 111 allows a current to flow when the predetermined voltage V3 is higher between the predetermined voltage V3 and the predetermined voltage V4 (first predetermined voltage) obtained by dropping the voltage from the predetermined voltage V2 with the resistor 120. In this example, when the battery voltage VB is substantially at the rated voltage, the predetermined voltage V3 is made higher than the predetermined voltage V4 by the resistor 120 (hereinafter, this is a normal state).
[0051]
Connected between the first power supply circuit 96 and the second power supply circuit 110 are two NPN transistors 112 and 113 connected in Darlington that constitute the drive circuit 124 for driving the MOS transistor 31 via a resistor 114. Yes. The diode 111 is provided between the collectors of the NPN transistors 112 and 113.
[0052]
Accordingly, in the normal state, the predetermined voltage V3 is as high as the predetermined voltage V4. Therefore, a base current flows from the primary side of the transformer 29 to the NPN transistor 112, and the NPN transistor 112 is turned on. Then, the collector current of the NPN transistor 112 becomes the base current of the NPN transistor 113, and the collector current flows from the primary side of the transformer 29 to the NPN transistor 113.
[0053]
On the other hand, when the predetermined voltage V4 is higher than the predetermined voltage V3, for example, when the battery voltage decreases, the base current of the NPN transistor 112 flows from the secondary side, and the NPN transistor 112 is turned on. Then, the NPN transistor 113 is also turned on, and a collector current flows from the primary side of the transformer 29 to the NPN transistor 113.
[0054]
At this time, since the predetermined voltage V4 is higher than the predetermined voltage V3, the diode 111 does not flow current. For this reason, the relationship that the predetermined voltage V4 is higher than the predetermined voltage V3 is maintained.
The operation of the NPN transistors 112 and 113 is controlled by five NPN transistors 115 to 119 which are turned on / off in response to the output signal of the PWM control circuit 9 as shown in FIG. Hereinafter, the five NPN transistors 115 to 119 will be described.
[0055]
The NPN transistors 115 and 116 are turned on / off according to the output signal (duty signal) of the PWM control circuit 9. Hereinafter, among the output signals, a high level signal will be described as an on signal and a low level signal as an off signal.
For example, when the output signal is an on signal, the NPN transistors 115 and 116 are turned on, and the constant current from the constant current source 121 becomes the collector current of the NPN transistor 115. As a result, the NPN transistors 117 and 118 are turned off, and the NPN transistor 119 is also turned off.
[0056]
That is, when the duty signal is an on signal, the NPN transistors 115 and 116 are turned on, and the NPN transistors 117 to 119 are turned off. Accordingly, the collector current of the NPN transistor 112 flows into the base of the NPN transistor 113, and the NPN transistor 113 is turned on. As a result, the collector current of the NPN transistor 113 flows into the gate of the MOS transistor 31, and the MOS transistor 31 is turned on.
[0057]
On the other hand, when the output signal is an off signal, the NPN transistors 115 and 116 are turned off, so that the NPN transistor 117 is turned on by the constant current source 121. As a result, a constant current from the constant current source 122 flows through the NPN transistor 117. At this time, the NPN transistor 118 is also turned on by the constant current source 121. As a result, the collector current of the NPN transistor 112 flows into the NPN transistor 118. As a result, the NPN transistor 113 is turned off.
[0058]
Since the NPN transistor 116 is off, the collector current that has flowed through the NPN transistor 117 flows into the base of the NPN transistor 119, and the NPN transistor 119 is turned on. Thereby, the collector current of the NPN transistor 113 does not flow into the gate of the MOS transistor 31, but becomes the collector current of the NPN transistor 119, and the MOS transistor 31 is turned off.
[0059]
Thus, the MOS transistor 31 is turned on / off by the on signal and the off signal.
As shown in FIG. 5, a diode 123 is provided between the gate of the MOS transistor 31 and the constant current source 122.
The diode 123 increases the switching speed when the MOS transistor 31 is turned off. That is, when the MOS transistor 31 is turned from on to off, the charge stored in the gate of the MOS transistor 31 is extracted through the diode 123, and the collector current of the NPN transistor 117 is increased. As a result, the base current of the NPN transistor 119 increases, so that the NPN transistor 131 is quickly turned off. As a result, the switching speed of the MOS transistor 31 can be improved.
[0060]
Next, the operation of the circuit of FIG. 5 will be described in detail.
(1) As a premise, the battery voltage VB is almost the rated voltage, and the second power supply circuit 110 generates a predetermined voltage V3. At this time, the lighting switch SW is turned on, and the output signal of the PWM control circuit 9 is an on signal. Suppose.
At this time, immediately after the lighting switch SW is turned on, no voltage is generated on the secondary side of the transformer 29. Therefore, in this case, the NPN transistor 112 is turned on by the predetermined voltage V3 of the second power supply circuit 110, and the NPN transistor 113 is also turned on. That is, the base current and collector current of the NPN transistors 112 and 113 flow (obtained) by the second power supply circuit 110. As a result, the MOS transistor 31 is turned on after obtaining the driving power from the primary side of the flyback transformer 29, that is, the second power circuit 110.
[0061]
Thereafter, when the PWM control circuit 9 repeats the on / off signal, the secondary winding 29b receives the energy of the primary winding 29a, so that the voltage on the secondary side gradually increases. As a result, the predetermined voltage V2 is generated in the first power supply circuit 96, and further, the predetermined voltage V4 is generated.
(2) Next, it is assumed that the battery voltage has dropped while the lamp is lit, so that the predetermined voltage V3 has also dropped and the predetermined voltage V3 has become lower than the predetermined voltage V4.
[0062]
Then, the diode 111 switches the current path so that the base current of the NPN transistors 112 and 113 is obtained from the secondary side (first power supply circuit 96) of the transformer 29. That is, the NPN transistor 112 obtains drive power from the secondary side (first power supply circuit 96) of the transformer 29.
As a result, in this embodiment, when the power supply voltage VB of the battery 1 decreases during lighting, the NPN transistors 112 and 113 and the MOS transistor 31 are stably driven by the first power supply circuit 96 on the secondary side of the transformer 29. Can be controlled.
[0063]
Therefore, in the present embodiment, the driving power supply for the NPN transistor 112 is obtained from the first power supply circuit 96 only when the predetermined voltage V3 becomes lower than the predetermined voltage V4. This has the following effects.
As described above, a high voltage of 400 V is generated on the secondary side of the transformer 29. Therefore, if the Zener diode 97 is small and inexpensive, it is necessary to use a resistor 95 having a very large resistance value. However, in this case, there is a problem that a large amount of power is consumed by the resistor 95 having a large resistance value.
[0064]
Therefore, in this example, only when the predetermined voltage V3 becomes lower than the predetermined voltage V4, a current flows through the resistor 95, so that power consumption at the resistor 95 can be reduced.
Further, as described above, a high voltage of 400 V is generated on the secondary side of the transformer 29. However, the power consumption of the resistor 95 decreases as the resistance value increases. The maximum value R (95) = (VL−V2) / Is of the resistance value of the resistor 95 is established.
[0065]
Note that VL is a secondary side voltage of the transformer 29 (the minimum value necessary for normal operation of the NPN transistor 112), and Is is a current that the first power supply circuit 96 supplies to the load.
In such a relationship, V2 and Is are fixed values determined by the circuit. Therefore, the resistance value of the resistor 95 is determined by how many volts the minimum value of the VL is set. Therefore, in this example, the driving power supply for the NPN transistor 112 is obtained from the first power supply circuit 96 only when the predetermined voltage V3 becomes lower than the predetermined voltage V4. Thereby, since the resistance value of the resistor 95 can be increased, the power consumption in the resistor 95 can be reduced.
[0066]
In this embodiment, the NPN transistor 112 and the NPN transistor 113 are Darlington-connected, and the following effects are obtained. However, the description will be made ignoring the voltage drop at the resistor 114.
When the battery voltage VB is substantially the rated voltage, the base current and the collector current of the NPN transistors 112 and 113 flow from the primary side (second power supply circuit 110) of the transformer 29 as described above. Therefore, the collector-emitter potential difference of the NPN transistor 113 is the sum of the voltage drop, the collector-emitter potential drop, and the forward voltage drop of the diode 111.
[0067]
That is, in this example, the voltage applied to the gate of the MOS transistor 31 is V3− (VBE112 + VBE113) = V3−1.4 (V).
VBE 112 is a forward voltage drop between the emitter and base of the transistor 112, and VBE 113 is a forward voltage drop between the emitter and base of the transistor 113.
[0068]
For example, it is assumed that the battery voltage VB gradually decreases from the rated voltage, and the predetermined voltage V3 becomes lower than the predetermined voltage V4. In this case, as described above, the NPN transistor 113 is turned on by the first power supply circuit 96, and the potential difference between the predetermined voltage V4 and the emitter of the NPN transistor 113 is between the base and emitter of the NPN transistors 112 and 113. It is the sum of each voltage drop.
[0069]
However, in this case, it is considered that the first power supply circuit 96 and the second power supply circuit 110 are separated by the diode 111. In this case, the potential difference between the emitter and the collector of the NPN transistor 113 is between the emitter and the collector. Only voltage drop.
That is, the voltage applied to the gate of the MOS transistor 31 is V3-VCE113 = V3 (V). Note that VCE is the voltage drop between the collector and the emitter of the transistor 113 = 0 (V).
[0070]
Therefore, the MOS transistor 31 can be reliably turned on until the battery voltage VB decreases to the gate voltage necessary for performing the switching operation of the MOS transistor 31.
In FIG. 5, reference numeral 246 denotes an NPN transistor, which stops the control of the PWM control circuit 9 when an abnormal state described later occurs, that is, in order to turn off the MOS transistor 31, the second abnormality circuit 244 Thus, both NPN transistors 115 and 116 are forcibly turned off.
[0071]
[Lamp power control circuit 10]
Next, a specific configuration of the lamp power control circuit 10 is shown in FIG. The lamp power control circuit includes an error amplification circuit (integration circuit) 61 that generates an output corresponding to a lamp voltage VL, a lamp current IL, and the like, which are signals indicating the discharge lighting state of the lamp 2, and this error amplification circuit. The output of 61 is input to the PWM control circuit. The lamp power control circuit 10 finally controls the lamp power by inverting the output voltage (output signal) of the error amplification circuit (integration circuit) 61 in the PWM control circuit 9.
[0072]
In other words, the PWM control circuit 9 controls the MOS transistor 31 so that the ON / OFF duty ratio of the MOS transistor 31 is increased by decreasing the threshold level with respect to the sawtooth wave as the output potential of the error amplifier circuit 61 increases. This increases lamp power.
On the other hand, the PWM control circuit 9 controls the MOS transistor 31 so that the ON / OFF duty ratio of the MOS transistor 31 is decreased by increasing the threshold level with respect to the sawtooth wave as the output potential of the error amplifier circuit 61 is decreased. Thereby, lamp electric power falls.
[0073]
As shown in FIG. 6, the reference voltage Vref is input to the non-inverting input terminal of the error amplifying circuit 61, and the voltage V1 serving as a parameter for controlling the lamp power PL is input to the inverting input terminal. Yes. Thereby, the error amplification circuit 61 generates an output corresponding to the voltage V1, and the on / off duty ratio is set based on this output.
[0074]
When the voltage V1 becomes higher than the reference voltage Vref, the output voltage of the error amplifying circuit 61 is lowered. When the voltage V1 becomes lower than the reference voltage Vref, the output voltage of the error amplifying circuit 61 is increased.
The voltage V1 is a composite signal such as the lamp current IL and the lamp voltage VL, that is, the lamp current IL, the current i1 flowing by the constant voltage V2, the current i2 set by the first current setting circuit 63, and the second current. It is determined based on the current i3 set by the setting circuit 65.
[0075]
  NaThe ramp voltage VL is an output value from the sample and hold circuit 12. The sum of the current i1, the current i2 and the current i3 is set sufficiently smaller than the lamp current IL.
[0076]
Here, as shown in the drawing, the first current setting circuit 63 sets the current i2 to be larger as the lamp voltage VL is higher. Further, as shown in the figure, the current i2 is set in such a relationship that different straight lines are connected such that the slope becomes gentler as the lamp voltage VL increases.
The second current setting circuit 65 sets the current i3 so as to increase as the time T increases as shown in the figure. This time T corresponds to the elapsed time after the lamp 2 is turned off, and indirectly estimates the state of the electrode temperature.
[0077]
That is, when the lamp 2 is continuously turned on for a certain period of time, the electrode temperature is sufficiently warm, and when the lamp 2 is turned off for a short time and then the lamp 2 is turned on again, the amount of decrease in the electrode temperature is small. . Therefore, in this case, the lamp power may be smaller than that in a state where the electrode is completely cooled to, for example, the outside air temperature. As a result, in this embodiment, the lamp power control circuit 10 can indirectly predict the electrode temperature and control the lamp power according to the electrode temperature.
[0078]
Thus, since the lamp power control circuit 10 performs control based on the lamp current IL and the lamp voltage VL, it is important to accurately detect the lamp current IL and the lamp voltage VL. In the present embodiment, a clamp circuit 69 and a sample hold circuit 12 are provided to accurately detect the lamp voltage VL and the lamp current IL. Hereinafter, the clamp circuit 69 and the sample hold circuit 12 will be described.
[0079]
The clamp circuit 69 clamps the voltage V1 input to the inverting input terminal of the error amplifier circuit 61.
As shown in the figure, the clamp circuit 69 constitutes a voltage follower circuit. A voltage of Vref−α that is lower than the predetermined voltage Vref input to the non-inverting input terminal of the error amplifier circuit 61 is input to the non-inverting input terminal of the operational amplifier 69 a provided in the clamp circuit 69. However, a diode 69b is connected to the output terminal of the clamp circuit 69 so that the operational amplifier 69a cannot draw current from the output terminal side.
[0080]
In such a configuration, when the voltage V1 is higher than the predetermined voltage Vref-α, the inverting input terminal has a higher voltage than the non-inverting input terminal of the operational amplifier 69a. Try to pull in. However, since the diode 69 b is provided on the output terminal side, the operational amplifier 69 a cannot draw current, and the voltage V 1 is input to the error amplifier circuit 61 without being affected by the clamp circuit 69.
[0081]
Further, when the voltage V1 becomes lower than the predetermined voltage Vref-α, the non-inverting input terminal of the operational amplifier 69a becomes higher than the inverting input terminal, so that the operational amplifier 69a pushes current toward the output terminal side. Thereby, the voltage V1 is maintained so as not to be equal to or lower than the predetermined voltage Vref−α.
FIG. 7 shows a change in the voltage V1 when the clamp circuit 69 is provided in this way. As shown in FIG. 7, when the MOS transistors 41a to 41d are switched on / off in the H-bridge circuit 7a, the lamp current IL greatly decreases for a moment, and the voltage V1 changes instantaneously. However, the clamp circuit 69 prevents the voltage V1 from being equal to or lower than the predetermined voltage Vref−α, and is maintained at a voltage equal to or higher than the predetermined voltage Vref−α. For this reason, the rapid change of the voltage V1 does not occur.
[0082]
As a result, the change in voltage V1 at the time of switching of MOS transistors 41a to 41d (at the time of switching the discharge current of lamp 2) can be reduced. Therefore, when the power supplied from battery 1 is feedback controlled, The influence by an instantaneous change can be suppressed.
Further, the time during which the lamp current IL is reduced increases as the inductance of the transformer 47b increases. In this embodiment, since the transformer required for the starting circuit 8 and the DC power supply circuit 5 is shared by the flyback transformer 29, the inductance of the transformer 47b is large, and the influence of the lamp current IL is large. However, since the clamp circuit 69 is provided as described above, the influence on the feedback control by the lamp current IL can be effectively suppressed even in such a case.
[0083]
Note that, when the switching frequency of the MOS transistors 41a to 41d is high, the influence on the feedback control due to the change in the lamp current IL becomes remarkable due to the delay of the feedback control. This is effective because the influence can be suppressed.
Further, the error amplifying circuit 61 is provided with an integrating capacitor 61a, and it is possible to reduce the influence of the lamp current IL by increasing the capacitance of the capacitor 61a. Since the response of the error amplifier circuit 61 cannot be ensured when the value is increased, it is effective to provide the clamp circuit 69.
[0084]
FIG. 8 shows a circuit configuration of the sample hold circuit 12. The sample hold circuit 12 eliminates a transient voltage generated by the secondary winding 47b and the capacitor 35. The sample hold circuit 12 includes a buffer amplifier circuit 129 to which an inverting input terminal 125 and an output terminal 147 are connected, and a mask circuit 131 for maintaining an output from the buffer amplifier circuit 129 for a predetermined period. The transient voltage is excluded from the lamp voltage VL including The sample hold circuit 12 is provided with an operational amplifier 152. The operational amplifier 152 generates an output of the sample hold circuit 12, and finally gives a control signal corresponding to the lamp voltage VL to the lamp power control circuit 10. sending.
[0085]
FIG. 9 shows a schematic diagram of the ramp voltage VL detected through the sample and hold circuit 12. Hereinafter, the operation of the sample and hold circuit 12 will be described with reference to FIG.
The sample hold circuit 12 turns on / off the NPN transistors 133a and 133b in the mask circuit 131 based on a timing signal from a digital circuit (not shown). When the timing signal (input signal) to the mask circuit 131 is a low level signal, the sample hold circuit 12 samples the ramp voltage VL at that time and generates an output corresponding to the ramp voltage VL. Is switched to a high level signal, the output corresponding to the ramp voltage VL sampled immediately before is maintained (held). Hereinafter, specific operations will be described separately for a case where the timing signal is a low level signal and a case where the timing signal is switched to a high level signal.
[0086]
(1) When the timing signal is a low level signal
In this case, since the NPN transistors 133a and 133b are off, an output corresponding to the ramp voltage VL is generated.
When the ramp voltage VL input to the non-inverting input terminal 127 increases, the voltage difference between the voltage of the inverting input terminal 125 and the voltage of the non-inverting input terminal 127 increases, and the differential circuit using the transistors 135, 155, 137, and 139. The voltage at the base terminal of the transistor 141, which is the output of, rises and is amplified by the transistors 141 and 145 constituting the emitter follower circuit, and the voltage at the output terminal 147 of the buffer amplifier circuit 129 rises. By this operation, the voltage of the non-inverting input terminal 127 and the voltage of the inverting input terminal 125 (the voltage of the output terminal 147 of the buffer amplifier circuit 129) are operated to be equal.
[0087]
That is, the buffer amplifier circuit 129 operates as a differential amplifier circuit so that the voltage of the output terminal 147 becomes the same voltage as the ramp voltage VL.
Therefore, the current flowing into the capacitor 151 via the ripple smoothing resistor 149 increases, and the charging voltage of the capacitor 151 increases. The operational amplifier 152 outputs an output accompanying the increase in the charging voltage.
[0088]
Note that, due to the decrease in the value of the current flowing through the PNP transistor 135, the current flowing from the constant current source 143 through the PNP transistor 155 increases, and the bias current flowing through the inverting input terminal 125 increases. 151 charging is not affected.
Further, when the lamp voltage VL input to the non-inverting input terminal 127 is decreased, an operation opposite to the above-described operation is performed so that the voltage at the output terminal 147 becomes the same voltage as the lamp voltage VL.
[0089]
That is, when the timing signal is a low level signal, a voltage corresponding to the ramp voltage VL at that time is accumulated in the capacitor 151, and the sample hold circuit 12 samples the ramp voltage VL at that time.
(2) When the timing signal is switched to a high level signal
In this case, the NPN transistors 133a and 133b are turned on. Therefore, the current from the constant current source 143 flows into the transistor 133a, the current from the constant current source 157 flows into the transistor 133b, and the NPN transistors 145, 159 and 161 are turned off. Accordingly, at this time, no current flows through the capacitor 151, and the capacitor 151 holds the charging voltage immediately before the timing signal is switched to the high level signal. That is, when the timing signal is switched to a high level, the buffer amplifier circuit 129 does not operate as a differential amplifier circuit.
[0090]
In this way, the buffer amplifier circuit 129 operates as a differential amplifier circuit when a transient voltage is not generated, and the transient voltage is set so that the buffer amplifier circuit 129 does not operate as a differential amplifier circuit when a transient voltage is generated. The part is masked.
As a result, the ramp voltage VL can be prevented from being sampled when a transient voltage is generated, and the ramp voltage VL at a normal time other than when the transient voltage is generated can be detected. In the past, the choke coil was used to flatten the lamp voltage VL so that the normal lamp voltage VL could be detected. By providing the sample hold circuit 12 in this way, the choke coil was used. Without it, the normal lamp voltage VL can be detected.
[0091]
The timing signal generated by the digital circuit described above is synchronized with the switching timing of the MOS transistors 41a to 41d in the H bridge circuit 7a. Specifically, after the switching of the MOS transistors 41a to 41d, several tens of μs. It is configured to output a high level signal for ˜several hundred μs.
[PWM control circuit 9]
Next, details of the PWM control circuit 9 will be described. FIG. 10 shows a circuit diagram of the PWM control circuit 9.
[0092]
As shown in FIG. 10, the PWM control circuit 9 includes a sawtooth wave forming circuit 163 that forms a sawtooth wave, a threshold level setting circuit 165 that sets a threshold level (duty ratio) in the sawtooth wave, and a sawtooth wave and threshold level. And a comparator 167 for setting the ON / OFF duty ratio of the MOS transistor 31.
[0093]
The sawtooth wave forming circuit 163 will be described. The sawtooth wave forming circuit 163 can vary the charging voltage of the capacitor 177 charged by the current It flowing from the constant current source 169 via the diode 171 and the current It flowing via the resistor 175 based on the voltage at the constant voltage source 173. By doing so, a sawtooth wave is formed. That is, the NPN transistors 183a and 183b are turned on / off based on the output of the comparator 181, thereby changing the threshold voltage set by the resistors 179a to 179c to form a sawtooth wave. Hereinafter, the basic operation of the sawtooth wave forming circuit 163 will be described.
[0094]
A sawtooth wave formed by this basic operation is shown in FIG. Hereinafter, the formation of the sawtooth wave will be described with reference to FIGS. 10 and 11A.
The capacitor 177 is charged by a current Ik flowing from the constant current source 169 via the diode 171 and a current It flowing through the resistor 175 based on the voltage at the constant voltage source 173.
[0095]
The capacitor 177 continues to be charged until the charging voltage of the capacitor 177 reaches the first threshold voltage Va, which is the voltage across the resistors 179b and 179c. The charging voltage of the capacitor 177 is predetermined until this charging is completed. It increases with the slope of.
Thereafter, when the charging voltage of the capacitor 177 becomes the voltage Va, the comparator 181 outputs a high level signal, and the NPN transistors 183a and 183b are turned on. As a result, the first threshold voltage Va is reduced to the second threshold voltage Vb, which is the voltage across the resistor 179b, and the capacitor 177 is discharged via the resistor 201. Due to the discharge of the capacitor 177, the charging voltage of the capacitor 177 rapidly decreases.
[0096]
When the charging voltage of the capacitor 177 decreases to the second threshold voltage Vb, the comparator 181 outputs a low level signal, and the NPN transistors 183a and 183b are turned off. As a result, the second threshold voltage Vb returns to the first threshold voltage Va. Further, thereafter, charging / discharging of the capacitor 177 is repeated in the same manner, and a sawtooth wave having a relatively short period, that is, a relatively high frequency is formed.
[0097]
The sawtooth wave forming circuit that performs such an operation includes a frequency changing circuit 185, and the frequency changing circuit 185 changes the frequency of the sawtooth wave. The frequency changing circuit 185 includes a circuit 185a that changes the switching frequency before and after the lamp 2 is turned on, and a circuit 185b that changes the switching frequency according to the battery voltage VB.
[0098]
These circuits 185a and 185b mainly affect the operation of the sawtooth wave forming circuit 163 before and after the lamp is lit.
Hereinafter, the operation of the sawtooth wave forming circuit 163 will be described separately for the circuit 185a and the circuit 185b.
First, the configuration of the circuit 185a will be described. The circuit 185a has a comparator 187 that compares a voltage VIL (high voltage side of the current detection resistor 59) obtained by voltage conversion of the lamp current IL with a predetermined voltage Vs, and ON / OFF control is performed by an output signal of the comparator 187. NPN transistor 189 is provided. By providing the circuit 185a configured as described above, the frequency of the sawtooth wave formed by the sawtooth wave forming circuit 163 is changed as shown below. Hereinafter, the formation of the sawtooth wave will be described separately before and after the lamp 2 is turned on.
[0099]
▲ 1 ▼ Before lighting of lamp 2
A sawtooth wave formed before the lamp 2 is turned on is shown in FIG.
Since the voltage VIL is zero before the lamp 2 is lit, the comparator 187 outputs a high level signal and the NPN transistor 189 is turned on.
As a result, the current Ik from the constant current source 169 does not flow into the capacitor 177, and the capacitor 177 is charged only by the current It flowing through the resistor 175 based on the voltage at the constant voltage source 173. Therefore, as shown in FIG. 11 (b), the charging time of the capacitor 177 becomes longer and the period of the sawtooth wave becomes longer.
[0100]
Thereafter, the capacitor 177 is repeatedly discharged and charged in the same manner as the basic operation described above, and the frequency is lower than that of the sawtooth wave formed by the basic operation of the sawtooth wave forming circuit 163. A long sawtooth wave is formed.
(2) After the lamp is lit
Since the voltage VIL becomes a predetermined voltage after the lamp 2 is turned on, the comparator 187 outputs a low level signal and the NPN transistor 189 is turned off. Therefore, the sawtooth wave forming circuit 163 forms a sawtooth wave without being affected by the circuit 185a.
[0101]
Next, the configuration of the circuit 185b will be described. The circuit 185b includes resistors 191a and 191b that divide the battery voltage VB. The voltage VB 1 divided by these is input to the operational amplifier 193. Accordingly, when the voltage VB1 is equal to or higher than the constant voltage of the constant voltage source 173, the transistor 197 is turned off, and when the voltage VB1 is lower than the constant voltage, the transistor 197 flows a current corresponding to the battery voltage VB. . When the battery voltage VB decreases, a current proportional to the current flowing through the transistor 197 flows through the current mirror circuit 199 through the transistor 199a.
[0102]
By providing the circuit 185a configured as described above, the frequency of the sawtooth wave formed by the sawtooth wave forming circuit 163 is changed as shown below. Hereinafter, the formation of the sawtooth wave will be described separately when the battery voltage VB is sufficient and when the battery voltage VB decreases.
(1) When battery voltage VB is sufficient
In this case, as described above, the transistor 197 is off. For this reason, the capacitor 177 is charged by the current Ik flowing from the constant current source 169 via the diode 171 and the current It flowing via the resistor 175 based on the voltage at the constant voltage source 173. Accordingly, the sawtooth wave forming circuit 163 performs the basic operation described above to form a sawtooth wave similar to that shown in FIG.
[0103]
(2) When battery voltage VB is low
A sawtooth wave formed when the battery voltage VB is lowered is shown in FIG.
As described above, the transistor 197 flows a current proportional to the battery voltage VB. Therefore, a current corresponding to the battery voltage VB flows into the transistor 199a through the current mirror circuit 199. As a result, a constant current from the constant current source 169 is drawn out according to the battery voltage VB.
[0104]
For this reason, the current Ik from the constant current source 169 is reduced and flows into the capacitor 177. Therefore, charging of the capacitor 177 is performed by the current It flowing through the resistor 175 based on the current Ik reduced by the decrease of the battery voltage VB and the voltage in the constant voltage source 173.
As a result, the charging time of the capacitor 177 becomes longer than when the battery voltage VB is sufficient, and the period of the sawtooth wave becomes longer as shown in FIG.
[0105]
Thereafter, the sawtooth wave forming circuit 163 repeats discharging and charging of the capacitor 177 in the same manner as described above, and the battery voltage VB is sufficient and the frequency is lower than that when the lamp 2 is lit. Forms a long sawtooth wave.
Thus, before the lamp 2 is turned on, the frequency of the sawtooth wave is uniformly changed to a relatively low frequency by the circuit 185a as described above, and after the lamp is turned on, the circuit voltage 185b changes the battery voltage to VB. The frequency of the sawtooth wave is changed accordingly.
[0106]
Next, the threshold level setting circuit 165 will be described. The threshold level setting circuit 165 sets a threshold level according to a command signal from the lamp power control circuit 10 (error amplification circuit 61), and the lamp voltage VL exceeds a predetermined voltage when the lamp is not lit. A threshold level for constant voltage control (for example, 400 V control) is set so as not to occur. The threshold level setting circuit 165 has an inverting circuit that inverts a command signal from the lamp power control circuit 10 (error amplification circuit 61). The level of the command signal from the lamp power control circuit 10 changes according to the lamp power PL to be supplied, and it is necessary to increase the power supply by lowering the duty ratio as the lamp power PL to be supplied is larger. An inversion circuit is provided in the circuit 165 so that the level of the command signal and the threshold level are inverted.
[0107]
As will be described in detail later, the threshold level setting circuit 165 is provided with a circuit for setting a duty limit value that is an upper limit value of the duty ratio.
Next, the comparator 167 will be described. The comparator 167 compares the sawtooth wave and the threshold level to set the duty ratio for turning on / off the MOS transistor 31.
[0108]
Further, since the switching frequency of the MOS transistor 31 at this time is the same as the frequency of the sawtooth wave formed by the sawtooth wave forming circuit 163, {circle around (1)} before the lamp 2 is turned on, the battery voltage VB Regardless of the height of the lamp, the frequency is relatively low, (2) when the lamp 2 is lit, and when the battery voltage VB is sufficient, the frequency is relatively high, and (3) the lamp 2 is lit. When the battery voltage VB is decreasing, the frequency is relatively low according to the decrease of the battery voltage VB.
[0109]
Here, the waveform of the lamp voltage VL before the lamp 2 is turned on is shown in FIG. The dashed-dotted line (a) in FIG. 12 shows the case where the battery voltage VB is sufficient, the solid line (b) shows the case where the battery voltage VB is lowered, and the broken line (c) shows the case where the switching frequency is not lowered.
As shown in FIGS. 12A and 12B, when the switching frequency of the MOS transistor 31 is relatively low, the lamp voltage VL reaches a predetermined value required for lamp lighting and reaches a predetermined value (for example, as described above). 400V). When the switching frequency is not changed, the lamp voltage VL changes with the battery voltage VB as shown in (c), and the lamp voltage VL decreases as the battery voltage VB decreases. That is, by lowering the switching frequency, the cutoff current value of the primary current flowing through the primary winding 29a of the transformer 29 can be increased, and the output power of the DC power supply circuit 5 can be increased as compared with the case where the switching frequency is not changed. .
[0110]
Further, the total energy W (≈output power of the DC power supply circuit 5) accumulated in the primary winding 29a per unit time is expressed by Equation 1.
[0111]
[Expression 1]
W = f × 1 / 2LI²
However, f: switching frequency, L: inductance of primary winding 29a, I: primary current.
As expressed in Equation 1, the total energy W accumulated in the primary winding 29a per unit time increases in proportion to the switching frequency and the square of the current. For this reason, by increasing the ON / OFF cycle (= 1 / switching frequency) of the MOS transistor 31, the primary current increases even if the switching frequency is lowered. Therefore, the MOS transistor 31 accumulates in the primary winding 29a per unit time. The total energy W is increased.
[0112]
In this embodiment, since the switching frequency of the MOS transistor 31 is relatively low, the total sum W of energy accumulated in the primary winding per unit time becomes large as described above. That is, the output power of the DC power supply circuit 5 increases, and the lamp voltage VL having a predetermined voltage value necessary for lamp lighting can be supplied even when the battery voltage VB is lowered.
[0113]
As described above, the circuit 185a supplies the power necessary for lighting the lamp 2 by uniformly lowering the switching frequency of the MOS transistor 31 when the lamp 2 is not lit than when the lamp 2 is lit. Therefore, the lighting performance of the lamp 2 can be improved.
Further, after the lamp 2 is turned on, the lamp 2 is subjected to AC lighting at a predetermined switching frequency, so that the ripple of the lamp current can be reduced, thereby suppressing the acoustic resonance phenomenon.
[0114]
Subsequently, when the lamp 2 is turned on, FIGS. 13A and 13B show comparative diagrams of waveforms of primary currents when the battery voltage VB is sufficient and when the battery voltage VB is lowered, respectively. Show.
In this embodiment, since the switching frequency of the MOS transistor 31 is lowered in accordance with the battery voltage drop, as shown in FIGS. 13A and 13B, only when the battery voltage VB is sufficient. Even when the battery voltage VB is reduced, the primary current becomes sufficiently large. For this reason, as described above, the total energy W per unit time that can be supplied to the secondary winding 29b increases. In addition, since the frequency is low, the time during which the MOS transistor 31 is turned off is lengthened, and energy can be sufficiently supplied to the secondary winding 29b.
[0115]
As described above, when the battery voltage VB is sufficient when the lamp 2 is lit, the switching frequency of the MOS transistor 31 is set to a relatively high predetermined frequency, and the battery voltage VB is decreased. Since the predetermined frequency is lowered according to the decrease in the battery voltage VB, the energy supply to the secondary side of the flyback transformer 29 can be sufficiently performed.
[0116]
Therefore, even when the battery voltage VB is lowered when the lamp 2 is lit, the energy consumption efficiency can be improved, and for example, it is suppressed that the lamp 2 disappears while the lamp 2 is lit. can do.
[About the threshold level setting circuit 165]
Next, details of the threshold level setting circuit 165 will be described with reference to FIG.
[0117]
  The threshold level setting circuit 165 sets an inversion circuit 165a that inverts a command signal output from the lamp power control circuit 10 (error amplification circuit 61), and the duty limit value (hereinafter, limit value) that is an upper limit value of the duty ratio. Limit value setting circuit 165b, LaAnd a control circuit 165c for constant voltage control of the lamp voltage VL before lighting the amplifier 2 to a predetermined value.
[0118]
The limit value is for ensuring that sufficient energy is supplied to the secondary side of the flyback transformer 29 as described above. That is, the secondary side output of the flyback transformer 29 has a convex relationship with respect to the duty ratio. Therefore, for example, when the lamp power control circuit 10 functions to increase the duty ratio in order to increase the lamp power significantly, the secondary output of the flyback transformer 29 is prevented from decreasing. Is set.
[0119]
  First, the inverting circuit 165a will be described. The inverting circuit 165a includes a current mirror circuit 205 through which a current flows from the constant voltage source 203, and an NPN transistor 207 having a current iS flowing through the current mirror circuit 205 as a base current. The output terminal of the error amplifier circuit 61 is connected to the current mirror circuit 205 including two NPN transistors 205a and 205b through a resistor 209. Here, when the lamp power is controlled by the output of the error amplification circuit 61, the control circuit 165cNPNTransistor 404Is in the off state. Therefore, the operation of the inverting circuit 165a in this case is as follows.
[0120]
When the lamp power is lowered, the output voltage of the error amplifier circuit 61 is lowered and the current isa flowing through the resistor 209 is increased. At this time, the current isb obtained by mirroring this current by the current mirror circuit 205 is isa. The voltage VM obtained by converting the current isb into a voltage by the resistor 210 becomes high, and this voltage VM becomes the input voltage VN of the inverting input terminal of the comparator 167 via the transistor 207 forming the emitter follower circuit. Therefore, the input voltage VN increases, the threshold level increases, and the duty ratio decreases.
[0121]
On the other hand, when the lamp power is increased, the output voltage of the error amplifier circuit 61 increases and the current isa flowing through the resistor 209 decreases. As a result, the voltage VM obtained by converting the current isb into a voltage by the resistor 210 decreases. Accordingly, the input voltage VN at the inverting input terminal of the comparator 167 decreases, the threshold level decreases, and the duty ratio increases.
[0122]
Next, the limit value setting circuit 165b will be described. The limit value setting circuit 165b includes a first limit value setting circuit 211 that varies the limit value according to the battery voltage VB, and the limit value according to the lamp voltage VL that is information indicating (corresponding to) the power supplied to the lamp 2. A second limit value setting circuit 213 that changes the value, and a third limit value setting circuit 215 that sets the limit value to a maximum value that can be set on the circuit when the battery voltage VB becomes a predetermined value or less.
[0123]
The first limit value setting circuit 211 detects only the battery voltage VB from the terminal A provided between the battery 1 and the primary winding 29a of the flyback transformer 29 (see FIG. 1).
The first limit value setting circuit 211 includes resistors 223 to 225. The voltage V0 at the connection point of these resistors 223 to 225 is determined only by the voltage division of the resistors 223 to 225 when the transistor 227 described later is off (when the battery voltage is sufficient) and the lamp voltage VL is 0, It becomes a value according to VB. When the battery voltage VB decreases, the voltage V0 decreases. When the battery voltage VB increases, the voltage V0 increases.
[0124]
The second limit value setting circuit 213 includes a resistor 222 and a current mirror circuit 221 (NPN transistors 221a and 221b), and detects only the lamp voltage VL indicating the power supplied to the lamp 2 from the terminal C. ing. When the lamp voltage VL increases, the second limit value setting circuit 213 sets the limit value to a large value accordingly.
[0125]
That is, the current flowing through the current mirror circuit 221 is varied only in accordance with the lamp voltage VL, and increases as the lamp voltage increases. When the lamp voltage VL increases, the collector current of the NPN transistor 221b of the current mirror circuit 221 increases. To do. Accordingly, the voltage V0 decreases as the collector current of the NPN transistor 221b increases. On the other hand, when the lamp voltage VL decreases, the collector current of the NPN transistor 221b decreases and the voltage V0 increases.
[0126]
That is, the threshold level setting circuit 165 assumes that the voltage determined by the battery voltage VB and the ramp voltage VL is V0, and the base side voltage of the NPN transistor 207 corresponding to the output voltage of the error amplifier circuit 61 is VM. It fulfills functions like However, for easy understanding, the voltage drop between the base and collector of the NPN transistor 207 and the NPN transistor 217 is ignored.
[0127]
For example, it is assumed that the voltage VM is lowered by an attempt to increase lamp power by the output signal of the error amplifier circuit 61. At this time, if the voltage VM is higher than the voltage V0, the NPN transistor 217 is turned off. As a result, the input voltage VN becomes the voltage VM, and the threshold level is set according to the output signal of the error amplification circuit 61.
[0128]
On the other hand, it is assumed that, for example, the voltage VM becomes lower than the voltage V0 in order to increase the lamp power significantly by the output signal of the error amplifier circuit 61. Then, the NPN transistor 207 is turned off and the NPN transistor 217 is turned on. As a result, the input voltage VN is the voltage V0, the voltage V0 becomes the limit value, and the threshold level is limited so as not to increase any more.
[0129]
That is, according to only the battery voltage VB, the first limit value setting circuit 211 sets the limit value larger as the battery voltage VB decreases because the voltage V0 also decreases as the battery voltage VB decreases. Further, the second limit value setting circuit 213 sets the limit value larger as the lamp voltage VL becomes higher because the voltage V0 becomes lower as the lamp voltage VL becomes higher only in response to the lamp voltage VL.
[0130]
Thus, in this example, as a means for detecting only the battery voltage VB, the terminal A is provided as shown in FIG. 1, and the limit value is varied according to the battery voltage VB detected from the terminal A. I made it. Thus, the limit value can be set with high accuracy according to the battery voltage VB.
Further, as means for detecting only the lamp voltage VL described above, a terminal C is provided as shown in FIG. 1, and the limit value is made variable according to the lamp voltage VL detected from the terminal C. Accordingly, the limit value can be set with high accuracy according to the lamp voltage VL that is the load of the lamp 2.
[0131]
Further, since the control signal (VL) used in the lamp power control circuit 10 is used as the load of the lamp 2, it is not necessary to provide a means for specifically detecting the load of the lamp 2, and the cost can be reduced. .
By the way, the first and second limit value setting circuits 211 and 213 described above set the limit values by circuit constants determined by the resistors 223 and 225, for example. In this example, the first limit value setting circuit 211 can set the limit value with high accuracy while the battery voltage VB decreases from the rated voltage 12V to about 7V.
[0132]
Therefore, for example, when the battery voltage VB is greatly reduced and becomes smaller than 7V, the limit value is not appropriate, and the limit value needs to be further increased. In other words, when the battery voltage VB is further significantly reduced, the secondary output of the flyback transformer 29 is also greatly reduced. Therefore, if the limit value is not increased accordingly, the secondary output can be sufficiently obtained. Absent.
[0133]
Therefore, when the battery voltage VB falls below 7V, the limit value is appropriately set by the third limit value setting circuit 215. This will be described below. Note that the limit value in this case is set in a range where energy can be sufficiently supplied to the secondary winding 29b of the flyback transformer 29 when the duty ratio becomes high as described above.
[0134]
As shown in FIG. 14, the third limit value setting circuit 215 includes an NPN transistor 227 connected in parallel with the resistor 225 and a comparator 229 for turning on / off the NPN transistor 227.
In the comparator 229, the predetermined voltage VK (7V) is input to the non-inverting input terminal, and the battery voltage VB is input from the terminal A to the inverting input terminal. Therefore, when the battery voltage VB drops below 7V, the NPN transistor 227 is turned on. As a result, the voltage V0 is not divided by the resistors 223 and 225, but is substantially 0V.
[0135]
As a result, the limit value is lowered to a value at which the duty ratio can be almost 100%. Thereby, even when the battery voltage VB falls below 7V, an optimum limit value can be set.
Next, the control circuit 165c will be described. The control 165c is a circuit that controls the lamp voltage VL before lighting the lamp 2 to a predetermined value (for example, 400V). The terminal 401 is a terminal for detecting the lamp voltage VL and is connected to the terminal C in FIG. Until the lighting switch SW is turned on and the lamp 2 is lit (the lamp current is not flowing through the lamp 2), the voltage at the output terminal of the error amplifying circuit 61 becomes the highest voltage, and the current flows through the resistor 209. Absent. That is, the error amplification circuit 61 outputs a command signal for supplying maximum power to the lamp 2.
[0136]
Therefore, the PWM control circuit 9 operates in a maximum duty state determined by the second limit value setting circuit 165b. As a result, when the DC power supply circuit 5 is activated and the lamp voltage VL increases and reaches the predetermined value, the control circuit 165c performs constant voltage control on the lamp voltage VL.
More specifically, the voltage obtained by dividing the lamp voltage VL by the resistors 402 and 403 and the reference voltage Vd are compared by the comparator 230, and the NPN transistor 404 is controlled to be turned on / off. That is, the NPN transistor 404 is turned off when the ramp voltage VL is equal to or lower than a predetermined value, and the NPN transistor 404 is turned on when the lamp voltage VL is higher than the predetermined value. When the NPN transistor 404 is turned on, a current determined by the resistor 405 flows through the NPN transistor 205a. Then, the same current as this current flows through the NPN transistor 205b, the voltage VM increases, and the input voltage VN increases.
[0137]
However, at this time, the output voltage VN becomes higher than the peak voltage (Va in FIG. 11) of the sawtooth wave input to the non-inverting input terminal of the comparator 167 by setting the resistance value of the resistor 405. Therefore, the output signal of the comparator 167 is fixed to the low level signal, the MOS transistor 31 is turned off, and the ramp voltage VL stops increasing.
[0138]
After that, when the lamp voltage VL gradually decreases and falls below the predetermined value due to the power consumption by the places other than the lamp 2 with the passage of time, the NPN transistor 404 performs the switching operation again, and the lamp voltage VL is reduced. To rise. In this way, the lamp voltage VL is controlled at a constant voltage by repeating this operation.
[Fail-safe circuit 14]
Next, the fail safe circuit 14 will be described. First, the vehicle mounting structure of the lamp 2 which is a premise of the function of the fail safe circuit 14 will be described with reference to FIG.
[0139]
As shown in FIG. 15, the vehicle headlamp 231 includes a reflector 233 that reflects the light of the lamp 2 toward the front of the vehicle. The reflector 233 is formed in a bowl shape and houses the lamp 2 therein. The lamp 2 is inserted into the reflector 233 from the left side in FIG. 15 and is attached to the reflector 233 by a connector 235.
[0140]
Briefly, the connector 235 includes detachable connector portions 235a and 235b. The connector portion 235a is inserted into the reflector 233 from the left side in FIG. 15, and is attached to the reflector 233 by rotating after insertion. It has been. Thereafter, when the connector portion 235b is fitted into the 235a, the lamp 2 can be turned on.
[0141]
A shield part 237 made of aluminum or the like is attached to the connector 235b so as to cover it. The shield portion 237 is grounded as shown in FIG. 15 and is attached to the connector portion 235b so as to press the electric wiring portion 239 of the lamp 2.
Here, the shield part 237 is for preventing radio waves generated when the lamp 2 is turned on from leaking outside the lamp 2 (reflector 233). Thereby, it is possible to prevent adverse effects on the electric devices of the own vehicle and other vehicles due to the radio waves. In order to prevent the generation of such radio waves, aluminum is deposited on the inner surface of the reflector 233, and this aluminum is grounded. Further, for the same reason, although not shown, a cup-shaped shield portion is also provided in the reflector 233 on the vehicle front side of the lamp 2.
[0142]
In the all-vehicle illumination lamp 231 having such a configuration, when the lamp 2 is replaced, the electric wiring portion 239 of the lamp 2 is sandwiched between the shield portions 237, and the electric wiring portion 239 of the lamp 2 is grounded. There is a possibility.
As a result, an overcurrent flows, for example, to the H bridge circuit 7a through the primary winding 29a and the secondary winding 29b, so that a great amount of heat is generated in the H bridge circuit 7a and the worst fuse 50 is blown. .
[0143]
  Therefore, in order to deal with the abnormal state in this way, the following abnormal control is performed by the fail safe control circuit 14. Hereinafter, the specific configuration of the fail-safe control circuit 14 and the contents of the abnormality control will be described with reference to FIG. The following abnormality control is performed when the lighting switch SW is set to ON. Fail-safe control circuit as shown in FIG.14Is roughly divided into five functional blocks 241a to 241e.
[0144]
The reference numeral 241 a includes a comparator 243 and a resistor 245. In the comparator 243, the ramp voltage VL is input from the sampling hold circuit 12 to the inverting input terminal, and the predetermined voltage Vr1 is input to the non-inverting input terminal. That is, 241a constitutes voltage determination means for determining whether or not the lamp voltage VL is in the first state that is lower than a predetermined voltage Vr1 (for example, 20V).
[0145]
The reference numeral 241b includes a comparator 247, a capacitor 248, and a resistor 249. In the comparator 247, the lamp current IL (voltage conversion VIL) is input to the inverting input terminal, and the predetermined voltage Vr2 is input to the non-inverting input terminal. That is, 241b constitutes a current determination unit that determines whether or not the lamp current IL is in the second state smaller than the predetermined current by comparing the VIL and the predetermined voltage Vr2.
[0146]
Reference numeral 241c denotes an AND gate that outputs a high level signal when both outputs of the comparators 243 and 247 become high level signals. That is, the fact that the output signal of the AND gate 241c becomes a high level signal means that the abnormal state described above has been detected.
That is, the AND gate 241c is a means for detecting an abnormal state in which the electric wiring portion 239 is grounded, and the lamp voltage VL (voltage signal) is lower than a predetermined voltage value and the lamp current (current signal) is a predetermined current value. When it is lower, an abnormal state is detected.
[0147]
Here, the reason why the abnormality determination can be easily performed by the lamp voltage VL and the lamp current IL will be described. As described above, when the power of the lamp 2 is controlled, the lamp voltage VL is in a predetermined range of, for example, 20V to 400V. At this time, if the electrical wiring portion 239 is grounded, an overcurrent flows to the secondary side of the flyback transformer 29, and the lamp voltage VL becomes lower than 20V. Therefore, in this case, the electric wiring portion 239 may be grounded.
[0148]
Further, as described above, when the power of the lamp 2 is controlled, the lamp current IL is in a predetermined range (0.35 to 2.6 A). Then, when the electrical wiring portion 239 is grounded, the overcurrent from the secondary winding 29b falls from the electrical wiring portion 243 to the ground without flowing through the H bridge circuit 7a. Thereby, the lamp current IL is smaller than the predetermined range and is equal to or less than a predetermined current (for example, 0.2 A). Therefore, in this case, the electrical wiring portion 239 may be grounded.
[0149]
Thus, in this example, the abnormal state is detected by the AND condition of the lamp voltage VL and the lamp current IL.
In this example, the abnormal state is detected when both the first state and the second state are established. When both of these two states are satisfied, the abnormal state is determined for the following reason.
[0150]
For example, if some abnormality occurs and both ends of the lamp 2 are short-circuited, the lamp voltage VL becomes smaller than the predetermined voltage Vr1, but the lamp current IL becomes larger than the predetermined current. When the lamp 2 is opened due to some abnormality, the lamp current IL becomes smaller than the predetermined current, but the lamp voltage VL becomes larger than the predetermined voltage Vr1.
[0151]
Therefore, under only one condition, it cannot be determined whether the electric wiring part 239 is grounded or whether the lamp 2 is short-circuited or opened.
Therefore, in this example, in order to reliably detect the ground of the electric wiring portion 239, it is determined that the abnormal state is satisfied when both the first state and the second state are satisfied. As a result, it is possible to reliably grasp the abnormal state in which the electrical wiring portion 239 is grounded, and to prevent overcurrent from flowing with high accuracy.
[0152]
The time counting circuit 241d includes a D-type flip-flop 251, a NOR gate 253, an AND gate 255, and a JK-type flip-flop 257. The time counting circuit 241d determines whether or not a time satisfying both the first state and the second state has passed a predetermined time T or more. The same clock signal CL is input to the clock terminals of the D-type flip-flop 251 and the JK-type flip-flop 257.
[0153]
The reset circuit 241e is configured by a D-type flip-flop. A constant voltage source 259 is input to the D input terminal of the D-type flip-flop preset circuit 241e. The H bridge control circuit 11 is connected to the output terminal of the D flip-flop preset circuit 241e. The constant voltage source 259 generates a constant voltage (for example, 5 V) when the lighting switch SW is on.
[0154]
Next, the operation from the circuit 241a to the reset circuit 241e will be described with reference to the time chart of FIG. However, the output signal of the AND gate 241c is α, the output signal of the JK flip-flop 257 is β, and the output signal of the D flip-flop 241e is γ. When the lighting switch SW is turned on, the D flip-flop preset circuit 241e is reset by a reset signal from a reset circuit (not shown). In this embodiment, the H bridge circuit 7a is turned off by the H bridge control circuit 11 when the output signal γ of the D-type flip-flop preset circuit 241e is a high level signal.
[0155]
First, when the lighting switch SW is turned on, for example, at time t3, the electrical wiring portion 239 is grounded again, and the output signal α changes from the low level signal to the high level signal, and this state continues thereafter. When the state in which the output signal α is a high level signal continues for longer than one cycle time of the clock pulse CL, the output signal β of the JK flip-flop 257 is inverted via the AND gate 255c and the NOR gate 253. Becomes a high level signal. Then, the output signal γ of the D-type flip-flop 241e becomes a high level signal. Thereby, as shown in FIG. 4, low level signals are output to the IC elements 43a and 43b from the two output terminals of the first abnormality circuit 242, and the H bridge circuit 7a is turned off.
[0156]
As a result, the overcurrent caused by the ground of the electric wiring portion 239 is blocked by the MOS transistors 41a and 41c. As a result, it is possible to prevent an overcurrent larger than a predetermined value from flowing in the H bridge circuit 7a and the current path after the H bridge circuit 7a, prevent the fuse 50 from being blown, and generate a large amount of heat in the discharge lamp device 100. Can be prevented.
[0157]
In addition, when the output signal γ becomes a high level signal, the control of the PWM control circuit 9 is stopped, that is, the conduction of the MOS transistor 31 is cut off. Specifically, when such an abnormal state occurs, a high-level signal is output from the second abnormality circuit 244 as shown in FIG. 5, so that the NPN transistor 246 is turned on. Therefore, the NPN transistors 115 and 116 are turned off regardless of the output signal of the PWM control circuit 9. Thereby, the conduction of the MOS transistor 31 is cut off, and all power supply to the discharge lamp device 100 is stopped. The reason for this will be described below.
[0158]
For example, it is assumed that there is a contact resistance between the electric wiring portion 239 and the shield 237 when the electric wiring portion 239 is grounded. Then, it is assumed that there is a problem that the energy (electric power) on the secondary side of the flyback transformer 29 is consumed greatly due to this contact resistance. Then, the lamp power control circuit 9 performs control so that the duty ratio of the PWM control circuit 9 is increased so as to increase the energy stored in the primary winding 29a. As a result, there is a problem that an excessive current flows in the primary winding 29a of the flyback transformer 29.
[0159]
Therefore, in consideration of such a case, the control of the PWM control circuit 9 is stopped, that is, the conduction of the MOS transistor 31 is interrupted, so that the primary current can be prevented from becoming excessive.
In addition to the above, various modes can be considered in the abnormal state. For example, when the breakdown voltage of the MOS transistor 31 deteriorates, a lamp voltage (for example, 400 V) necessary to start lighting is generated. Cannot illuminate. In this case, the MOS transistor 31 performs a switching operation by receiving a drive signal having the maximum duty from the PWM control circuit 9. However, since the breakdown voltage is deteriorated, most of the energy accumulated in the primary winding 29 a is confident that the MOS transistor 31 is confident. If the operation is continued as it is, abnormal heat is generated and the MOS transistor 31 is short-circuited. As a result, a secondary failure such as blowing of the fuse 50 is reached.
[0160]
In such an abnormal state, the result does not change even if the H-bridge circuit 7a is turned off. Therefore, in the case of such an abnormal state, the secondary control can be avoided by stopping the control of the PWM control circuit 9 and holding the MOS transistor 31 in the off state.
As described above, there are cases where it is effective to turn off the H-bridge circuit 7a depending on the result of abnormality determination in various abnormal states, and cases where it is effective to turn off the MOS transistor 31, and the H-bridge circuit 7a depending on the abnormal state. It is possible to select whether to turn off the MOS transistor 31 or to turn off the MOS transistor 31. However, such a proper use is not a good solution because the circuit becomes complicated and the scale increases. Accordingly, when an abnormality is determined, the circuit can be simplified and the scale can be reduced by turning off the MOS transistor 31 simultaneously with turning off the H bridge circuit 7a.
[0161]
As shown in FIG. 17, it is assumed that at time t1, the electrical wiring portion 239 is grounded and the output signal α changes from a low level signal to a high level signal, and this state continues until time t2.
In this case, since the high level period of the signal α which is an input signal to the time counting circuit 241d is shorter than one cycle time of the clock pulse CL, the output signal β of the time counting circuit 241d does not change and the previous state is maintained. Yes. Therefore, the signal γ does not change as well. That is, the H bridge control circuit 11 is not affected at all.
[0162]
That is, the condition for turning off the above-described H bridge circuit 7a is when the predetermined time T has elapsed for the time in which the first state and the second state are both achieved. The reason for this is as follows.
For example, when the lighting switch SW is on, after the first state and the second state are established for the first time, the grounding of the electrical wiring unit 239 is restored in a short time, and the electrical wiring unit 239 becomes normal. Suppose. In this case, in order to ensure the visibility of passengers at night, it is necessary to keep the lamp 2 in the lighting state as much as possible.
[0163]
Therefore, the H-bridge circuit 7a is not turned off immediately at the time of abnormality for a short time, and the H-bridge circuit 7a is turned off for the first time when the predetermined time T has elapsed between the first state and the second state. The predetermined time T is set to a time in a range where the fuse 50 is not blown, so that the fuse 50 can be prevented from being blown. The predetermined time T is set as follows. In this example, the abnormal state is detected with a relatively simple circuit configuration as shown in FIG.
[0164]
However, the electric wiring part 239 has wiring parts 239a and 239b at both ends of the lamp 2 as shown in FIG. 2, and these two wiring parts 239a and 239b are rarely grounded together. In many cases, only one electrical wiring portion 239a in FIG. 1 is grounded. Therefore, for example, when the polarity of the discharge voltage of the lamp 2 is changed in the H bridge circuit 7a when the abnormal state continues, the lamp voltage VL becomes higher than the predetermined voltage Vr1.
[0165]
Therefore, since the first state is not entered despite the occurrence of an abnormal state, the output signal of the AND gate 241c does not become a high level signal and the abnormal state cannot be detected.
Therefore, in this example, the predetermined time T is shorter than the switching cycle time of the H-bridge circuit 7a and set to half or less (0.8 ms) of the switching cycle time. Thereby, the abnormal state can be reliably detected with a simple circuit configuration.
[0166]
Further, in order to detect the abnormal state, the lamp voltage VL and the lamp current IL, which are the above-described lamp power control signals, are used. Thereby, it is not necessary to separately provide a voltage detection circuit and a current detection circuit in order to determine abnormality.
[About the connector disconnection detection circuit 15]
Next, the connector disconnection detection circuit 15 will be described with reference to FIG.
[0167]
The lamp 2 is detachable with a connector 235 including two connector portions 235a and 235b in the event of a breakage failure or the like. Therefore, the lamp 2 is electrically connected to the battery 1 and can be turned on when the connector portions 235a and 235b are fitted.
As shown in FIG. 18, an electrical wiring portion 261 is formed in the connector 235 so that when the connector portions 235 a and 235 b are disconnected, the internal electrical conduction is interrupted. More specifically, one end side of the electrical wiring portion 261 is connected to the power supply terminal 1a. Further, the other end side of the electric wiring portion 261 is grounded.
[0168]
The connection point 261a of the electric wiring part 261 of each connector 235a, 235b serves as a connector disconnection detection terminal for detecting the disconnection of the connector 235. The transistor 263 of the disconnection detection circuit 15a is turned on from off. The disconnection detecting circuit 15a is provided between the signal generating circuit 13a and the starting circuit 8, and when the disconnection of the connector 235 is detected, the signal from the signal generating circuit 13a is forcibly activated. This is a signal to be stopped.
[0169]
Next, the high voltage generation control circuit 13 will be described. The high voltage generation control circuit 13 includes a signal generation circuit 13a that generates a gate drive signal for the thyristor 57 and outputs a signal in synchronization with the on / off timing of the H bridge circuit 7a as described above. For example, when the start circuit 8 is activated and the lamp 2 is not turned on but is turned off, the signal generation circuit 13a causes the thyristor 57 to turn on until the lamp 2 is turned on. On-off is repeated and a high voltage is applied to the lamp 2.
[0170]
When the signal generation circuit 13a generates a high level signal, the transistor 265 is turned on. Accordingly, the transistor 267 is turned off and the transistors 269 and 275 are turned on. Further, the transistors 271 and 273 are turned off. As a result, the gate drive signal of the thyristor 57 becomes a low level signal, and the thyristor 57 is turned off.
[0171]
On the other hand, when a low level signal is generated in the signal generating circuit 13a, the transistor 265 is turned off. Accordingly, the transistor 267 is turned on and the transistors 269 and 275 are turned off. Further, the transistors 271 and 273 are turned on. As a result, the gate drive signal of the thyristor 57 becomes a high level signal, and the thyristor 57 is turned on.
[0172]
When the signal generated by the signal generation circuit 13a is a high level signal, the gate drive signal becomes a low level signal and the thyristor 57 is turned off. On the other hand, if the signal generated by the signal generation circuit 13a is a low level signal, the gate drive signal becomes a high level signal and the thyristor 57 is turned on.
In this example, the gate drive signal of the thyristor 57 can be forced to be a low level signal by the ON signal of the transistor 263. That is, when the disconnection detection circuit 15a detects that the connector 235 is disconnected and the transistor 263 is turned on, even if a low level signal for turning on the thyristor 57 is generated in the signal generation circuit 13a, the transistor 267 Turn off.
[0173]
Accordingly, the transistors 269 and 275 are turned on, the transistors 271 and 273 are turned off, and the thyristor 57 is turned off. As a result, for example, when the connector 235 is disconnected and the lamp 2 is turned off, generation of a high voltage by the thyristor 57 is prevented.
By the way, when it is detected that the connector 235 described above is disconnected, for example, when the electrical wiring portion 261 has a poor contact, the lighting function of the lamp 2 is normal. In such a case, it is not necessary to stop the control of the PWM control circuit 9 to turn off the lamp 2, and it is preferable to keep the lamp 2 on.
[0174]
Accordingly, in parallel with the detection of the disconnection of the connector 235, the fail-safe circuit 14 detects an abnormal state in which the lamp 2 is turned off although the lighting switch SW is set to ON. That is, when it is detected by the connector disconnection detection circuit 15 that the connector 235 is disconnected, it is not a contact failure of the electric wiring portion 261 but whether the connector 235 is really disconnected and the lamp 2 is turned off. judge.
[0175]
A logic circuit diagram representing the fail-safe circuit 14 is shown in FIG.
The fail safe circuit 14 includes a comparator 277 serving as a lighting detection means, a delay circuit (timer circuit) 279, an OR gate 281 and a D-type flip-flop 241e.
A predetermined voltage VR is input to the non-inverting input terminal of the comparator 277. On the other hand, the terminal E is connected to the inverting input terminal of the comparator 277 (see FIG. 1). That is, the comparator 277 outputs a low level signal when the lamp 2 is lit and a lamp current is flowing, and outputs a high level signal that the lamp 2 is extinguished when the lamp current falls below a predetermined value. .
[0176]
The delay circuit 279 outputs a high level signal when the output signal of the comparator 277 is a high level signal and this high level signal continues for a predetermined time Tm. That is, the delay circuit 279 outputs a high level signal when the predetermined time Tm elapses when the lamp 2 is turned off.
The OR gate 281 outputs a high level signal when the output signal of the delay circuit 279 becomes a high level signal. When the output signal of the OR gate 281 becomes a high level signal, the D-type flip-flop 241e outputs a high level signal using this high level signal as a clock pulse. When the output signal of the D-type flip-flop 241e becomes a high level signal, the control of the PWM control circuit 9 serving as power control means for supplying power from the battery 1 to the lamp 2 is stopped (the MOS transistor 31 is turned off). At the same time, the first bridge circuit 242 turns off the H bridge circuit 7a.
[0177]
By doing so, the lamp 2 is turned off from the lit state, and when the turn-off time elapses a predetermined time Tm, the supply of power to the lamp 2 is stopped by stopping the control of the PWM control circuit 9. It becomes like this. Further, the control of the PWM control circuit 9 is continued until the predetermined time Tm elapses after the lamp 2 is turned off, and power is supplied to the lamp 2.
[0178]
As shown in FIG. 19, the OR gate 281 has an input terminal for responding to the abnormal wiring state where the electrical wiring unit 261 is grounded, and an input for responding to another abnormal state. Terminals are provided. That is, the OR gate 281 is provided between the JK flip-flop 257 and the D flip-flop 241e shown in FIG.
[0179]
Next, the operation of the disconnection detection circuit 15a, the high voltage generation control circuit 13, and the fail safe circuit 14 will be described with reference to the time chart of FIG.
However, the signal detected by the disconnection detection circuit 15a is g, a high level signal when the connector 235 is disconnected, a low level signal when the connector is not disconnected, the gate drive signal of the thyristor 57 is f, and the lighting switch SW. When the lighting switch SW is on, it is a high level signal, and when it is off, it is a low level signal.
[0180]
The output signal of the signal generation circuit 13a is d, the control signal of the PWM control circuit 9 is c, a high level signal when the PWM control circuit 9 is controlling, and a low level signal when the control is stopped. The output signal of the comparator 277 is k, a high level signal when the lamp 2 is turned off, and a low level signal when the lamp 2 is turned on. Further, let the C input signal of the D-type flip-flop 241e be n.
[0181]
First, when the lighting switch SW is turned on at time t1, the lamp voltage VL gradually increases. For example, at time t2, the gate drive signal f of the thyristor 57 becomes a high level signal. As a result, the lamp 2 is turned on and the lamp current IL starts to flow. Thereafter, the lamp 2 enters the stable control state (35 W), and at time t3, the signal g becomes a high level signal, and it is detected that the connector 235 has been disconnected ((1) in FIG. 20).
Then, at time t3, the lamp current IL is smaller than a predetermined value, for example, becomes 0, and the lamp 2 is turned off, that is, when the connector 235 is really disconnected without the contact failure of the electric wiring portion 261, the signal k is High level signal. However, at this time, the signal n remains a low level signal by the delay circuit 279, and the control of the PWM control circuit 9 is continued.
[0182]
Thus, when the lamp 2 is turned off, as shown in FIG. 20, at time t4, the signal d of the signal generation circuit 13a becomes a high level signal so that the thyristor 57 is turned on and the lamp 2 is turned on again. Switches to a low level signal.
However, in this example, if the disconnection of the connector is detected regardless of the lighting of the lamp 2, the signal g becomes a high level signal, so that the signal f becomes a low level signal. Therefore, when the disconnection of the connector 235 is detected, the discharge of the capacitor 53 by the starting circuit 8 is stopped, and the generation of a high voltage at the connector 235 can be prevented.
[0183]
If the predetermined time Tm has elapsed at time t5, the signal n becomes a high level signal, the control of the PWM control circuit 9 is stopped, and the H bridge circuit 7a is turned on. Turn off. That is, when the connector 235 is disconnected and the lamp 2 is turned off, the thyristor 57 is turned off, and after the predetermined time Tm has elapsed, the control of the PWM control circuit 9 is stopped and the power supply to the lamp 2 is stopped.
[0184]
As a result, when the electrical wiring portion 261 of the lamp 2 causes a contact failure for a short time, the power supply to the lamp 2 can be maintained to keep the lamp 2 on, and the lamp 2 can continue for a predetermined time Tm. When the light is turned off, the power supply to the lamp 2 can be quickly stopped.
Next, it is assumed that the lighting switch SW is once turned off at time t6 and turned on again at time t7 from the state of (1) above, that is, the state in which the connector 235 is actually disconnected. ((2) in Fig. 20)
Then, when the lamp voltage VL gradually increases and at time t8, the signal d of the signal generation circuit 13a switches from the high level signal to the low level signal so that the lamp 2 is turned on by turning the thyristor 57 on from off. Change. However, as described above, when the disconnection of the connector is detected regardless of the lighting of the lamp 2, the signal g becomes a high level signal, so that the signal f becomes a low level signal. Therefore, when the connector 235 is disconnected, the start circuit 8 can prevent the generation of a high voltage at the connector 235.
[0185]
Thereafter, when the predetermined time Tm elapses when it is detected that the connector 235 is disconnected at time t9, the signal n becomes a high level signal, the control of the PWM control circuit 9 is stopped, and the H bridge circuit 7a is turned on. Turn off.
Next, from the state of (2) above, that is, from the state in which the connector 235 is actually disconnected, it is assumed that the lighting switch SW is turned off once at time t10, the connector 235 is reset, and turned on again at time t11. . (▲ 3 ▼ in Fig. 20)
At time t12, the signal g becomes a low level signal as described above, so that the signal f becomes a high level signal, and the lamp 2 is turned on by the starting circuit 8. After that, for example, it is assumed that the electrical wiring part 261 has a poor contact at time t13. In this case, since the lamp 2 is lit and the lamp current is larger than a predetermined value, the signal k is a low level signal.
[0186]
  Therefore, if the lamp 2 is lit when the electrical wiring part 261 has a poor contact, the power supply to the lamp 2 is maintained. As a result, even if the contact failure of the electric wiring part 261 occurs, if the lighting function of the lamp 2 is not abnormal, the lighting of the lamp 2 can be maintained.
  [Reverse connection protection circuit 3]
  Next, the reverse connection protection circuit 3 will be described with reference to FIG. 21 is the same as FIG.As an electrical loadAlternator, a vehicle electrical device71Is added.
[0187]
The reverse connection protection circuit 3 is provided between the battery 1 and the lamp 2. The gate (G) of the MOS transistor 21 is grounded via the resistor 17 to the positive electrode side (power supply terminal 1a) of the battery. The source (S) and drain (D) of the MOS transistor 21 are connected to the ground terminal 1b side so that the current flowing through the discharge lamp device 100 flows from the source toward the drain.
[0188]
When the lighting switch SW is turned on, a gate voltage is applied from the battery 1 to the gate (G), the MOS transistor 21 is turned on, and the power of the battery 1 is supplied to the discharge lamp device 100. Thereby, the discharge lamp device 100 operates.
Between the gate and the source of the MOS transistor 21, a capacitor 19 which is a conduction means is connected in parallel. The resistor 17 is connected in series with the parallel connection of the MOS transistor 21 and the capacitor 19 between the power supply terminal 1 a and the gate of the MOS transistor 21.
[0189]
When the lighting switch SW is turned on, the capacitor 19 is charged via the resistor 17. The charging current path of the capacitor 19 flows from the positive side of the battery 1 to the negative side of the battery 1 via the resistor 17, the capacitor 19, and the parasitic diode between the source and drain of the MOS transistor 21. When the charging voltage of the capacitor 19 reaches a predetermined value, the MOS transistor 21 is turned on. Further, until the MOS transistor 21 is turned on, the current flowing through the discharge lamp device 100 flows through a parasitic diode between the source and drain of the MOS transistor 21.
[0190]
The MOS transistor 21 has a protection function for protecting the discharge lamp device 100 from being applied with a reverse voltage in the following cases.
For example, when the battery 1 is replaced, it is assumed that the polarity of the battery 1 is mistakenly attached and the lighting switch SW is turned on by the operation of the passenger in this state. In this case, the reverse voltage applied to the discharge lamp device 100 is the battery voltage VB (first reverse voltage).
[0191]
And when the polarity of the battery 1 is reversely attached to the discharge lamp device 100 in this way, the reverse voltage application to the discharge lamp device 100 is cut off with the breakdown voltage between the drain and source of the MOS transistor 21, and the discharge lamp device Protect 100. As a result, no overcurrent flows through the fuse 50 through the Zener diode as in the prior art, and the fuse 50 can be prevented from being blown.
[0192]
The alternator 71 is connected to the battery 1 in parallel with the discharge lamp device 100. The alternator 71 is an inductive load (electric device for a vehicle) having a reactance component such as a field coil (not shown), and starts generating power when an ignition switch IG that is a means for starting a traveling drive source of the vehicle is turned on. To do.
When the ignition switch IG is turned on and the lighting switch SW is turned on, when the ignition switch IG is turned off, the current flowing through the alternator 71 is cut off, so that a large negative polarity pulse is applied to the power supply terminal 1a. Voltage is generated. Therefore, a larger reverse voltage is applied to the discharge lamp device 100 than when the battery 1 is reversely connected.
[0193]
However, at this time, the electric charge charged in the capacitor 19 is discharged with a time constant determined by the capacitor 19 and the resistor 17. As a result, the gate voltage is applied to the gate of the MOS transistor 21 for a predetermined time, so that the MOS transistor 21 is kept conductive for the predetermined time. When a large pulse voltage is generated between the power supply terminal 1a and the ground terminal 1b for a moment, the parasitic diode between the source and drain of the MOS transistor 31 and the flyback transformer 29 are connected via the MOS transistor 21 which is turned on. By passing a pulse current through a current path such as the primary winding 29a and the coil 27, energy of the negative polarity pulse is consumed.
[0194]
As described above, when a large reverse voltage is generated between the power supply terminal 1a and the ground terminal 1b, the MOS transistor 21 is forcibly maintained in the conductive state by the capacitor 19, so that the above breakdown voltage of the MOS transistor 21 is completely reduced. No need to consider. That is, the withstand voltage may be such that no reverse voltage is applied to the discharge lamp device 100 when the battery 1 is reversely connected (for example, slightly over 12V).
[0195]
Therefore, the withstand voltage of the MOS transistor 21 can be made very small, thereby reducing the driving resistance of the MOS transistor 21 and reducing the power loss in the MOS transistor 21. As a result, the chip size of the MOS transistor 21 can be reduced, and the inexpensive MOS transistor 21 can be used.
[0196]
Further, as described above, the MOS transistor 21 is forcibly turned on by the capacitor 19, but the capacitor 19 and the resistor 17 constitute a time constant circuit, so that the discharge time of the capacitor 19 is extended by the resistor 17. Is done. As a result, the conduction time of the MOS transistor 21 can be lengthened, so that destruction and breakage of the MOS transistor 21 can be reliably prevented. According to the study by the present inventor, when the time constant of the time constant circuit is 0.01 seconds or more, the MOS transistor 21 can be reliably turned on while the pulse voltage is generated. The discharge lamp device 100 can be reliably protected.
[0197]
[About overvoltage protection circuit 16]
FIG. 22 shows a circuit configuration diagram of the overvoltage protection circuit 16 shown in FIG. Hereinafter, the overvoltage protection circuit 16 will be described with reference to FIG.
The overvoltage protection circuit 16 protects the control circuits 9 to 15 included in the integrated circuit 73 from overvoltage. This overvoltage protection circuit 16 includes an overvoltage detection circuit 77 that detects overvoltage when the primary side voltage reaches a predetermined threshold voltage, and divides the primary side voltage when the primary side voltage reaches the threshold voltage. And a voltage dividing circuit 79 for pressing. The primary voltage applied through the overvoltage protection circuit 16 is converted to a constant voltage by the constant voltage circuit 75 and used as a drive voltage for the control circuits 9 to 15.
[0198]
The overvoltage detection circuit 77 includes a resistor 81, a Zener diode 83, and a resistor 85 having a relatively large resistance value. The threshold voltage is set by the Zener die voltage of the Zener diode 83. Further, the resistor 81 is provided in series with the Zener diode 83 for limiting the current I, whereby the withstand voltage of the Zener diode 83 can be lowered. The resistor 85 is a reverse bias resistor for preventing leakage.
[0199]
The voltage dividing circuit 79 includes resistors 87 and 89 and NPN transistors 91 and 93 connected in Darlington connection.
Next, the operation of the overvoltage protection circuit 16 configured as described above will be described.
When the primary side voltage is lower than the predetermined threshold voltage, the Zener diode 83 does not flow current, and thus the Darlington-connected NPN transistors 91 and 93 are not turned on. Therefore, the voltage VIC applied to the constant voltage circuit 75 in the integrated circuit 73 is a voltage obtained by subtracting a voltage drop at the resistor 87 from the primary side voltage.
[0200]
When the primary side voltage rises above a predetermined voltage, the Zener diode 83 causes a current to flow due to Zener breakdown, and the NPN transistors 91 and 93 are turned on. Therefore, the voltage VIC applied to the constant voltage circuit 75 in the integrated circuit 73 is a voltage obtained by dividing the primary side voltage by the resistor 87 and the resistor 89. Note that it is necessary to set the resistance values of the resistors 87 and 89 so that the voltage divided at this time is equal to or lower than the withstand voltage of the control circuits 9 to 15.
[0201]
Note that the constant voltage circuit 75 and the control circuits 9 to 15 are formed in the integrated circuit 73, but the components of the overvoltage protection circuit 16 such as the Zener diode 83, the resistor 85, and the NPN transistors 91 and 93 are shown. May also be formed in the integrated circuit 73. In this case, it is only necessary to form each of these components together with the other parts of the integrated circuit, so that the cost can be further reduced.
[0202]
Thus, since the overvoltage is divided by the voltage dividing circuit 79, it is possible to prevent the overvoltage from being applied to the integrated circuit 73.
Accordingly, the control circuits 9 to 15 in the integrated circuit 73 can be protected from overvoltage without using a relatively high withstand voltage power Zener diode, and the cost can be reduced. Further, since the current hardly flows through the resistor 81 in the overvoltage detection circuit 77 except when an overvoltage occurs, it is possible to prevent the power consumption of the resistor 81 when no overvoltage occurs. it can.
[0203]
[Inspection of discharge lamp device]
Next, the inspection before attaching the discharge lamp device 100 to the vehicle will be described based on the circuit configuration in the connector 15 shown in FIG. 23 and the circuit configuration diagram of the clock circuit 285 shown in FIG.
In order to artificially shorten the frequency of the signal generated by the clock circuit 285 at the time of inspection, as shown in FIGS. 23 and 24, clock switching detection circuits 286 and 287 are provided in the discharge lamp device. The clock switching detection circuits 286 and 287 will be described.
[0204]
The clock switching detection circuits 286 and 287 pseudo-accelerate the time at which the clock circuit 285 counts based on the clock switching detection signal and the detection time detection circuit 286 that detects the time of testing and outputs a clock switching detection signal. And a time shortening circuit 287.
The battery voltage VB applied to the connector disconnection detection terminal 261 is similarly applied to the inspection detection circuit 286. As described above, since the connector disconnection detection is performed by the battery voltage VB, a voltage higher than the battery voltage VB is not applied to the connector disconnection detection terminal 261a. By utilizing this, when only a voltage lower than the battery voltage VB + α is applied to the connector disconnection detection terminal 261a, the inspection time detection circuit 286 outputs a high level signal as not being detected, and the battery disconnection detection terminal 261a receives the battery. When a voltage equal to or higher than the voltage VB + α is applied, the inspection time detection circuit 286 outputs a low level signal as a clock switching detection signal. Thus, the connector disconnection detection terminal 261a is shared as a terminal for inspection and connector disconnection detection.
[0205]
The time reduction circuit 287 is built in the clock circuit 285 as shown in FIG. The clock circuit 285 includes a plurality of D-type flip-flops 289a to 289j arranged in series, and the time is counted by these D-type flip-flops 289a to 289j. That is, when a clock signal CL output from a converter (not shown) is input to the D-type flip-flop 289a, the D-type flip-flop 289a outputs a signal having a cycle twice that of the clock signal, and the next D-type flip-flop In step 289b, the signal is output as a signal having a double cycle. This operation is repeated in each of the D-type flip-flops 289a to 289j, and the cycle of the clock signal is doubled. Each control circuit selects a suitable signal from the signals output from the D-type flip-flops 401a to 401j, and uses it for the time when performing each control. For example, in the lamp power control circuit 10, the control time is set based on the frequency of the output signal of the D-type flip-flop 289i.
[0206]
  A time reduction circuit 287 is arranged between the plurality of D-type flip-flops arranged in this way. Hereinafter, the clock circuit 285 and the clock switching detection circuit 28 will be described.6The operation at 287 will be described separately when the lamp 2 is actually used and at the time of inspection.
  (1) When the lamp 2 is actually used At this time, since the lamp 2 is connected to the connector 35, the clock switching detection circuit 286287 is grounded. In this case, since a voltage higher than the battery voltage VB + α is not applied to the connector disconnection detection connection terminal 261a, the inspection detection circuit 286 outputs a high level signal.
[0207]
At this time, the output signal of the D-type flip-flop 289f is input to the clock C of the D-type flip-flop 289g. That is, by the processing in the time shortening circuit 287, the clock signal output from the converter is ignored, and the output signal of the D-type flip-flop 289f is input to the clock C as the clock signal of the D-type flip-flop 289g. Therefore, except for the inspection, the cycle of the clock signal CL from the converter is doubled through the D-type flip-flops 289a to 289f, and the signal with the doubled cycle becomes the clock signal of the D-type flip-flop 289g. For this reason, the lamp power control circuit 10 performs lamp power control in a normal time.
[0208]
  Even when the lamp 2 is disconnected from the connector 35, the clock switching detection circuit 28 is used.6Since only the battery voltage VB is applied to 287, the inspection time detection circuit 286 outputs a high level signal, and the clock circuit 285 and the clock switching detection circuit 286287 performs the same operation as described above.
  (2) When performing inspection
  At this time, the connector disconnection detection terminal 261a is shared as a terminal for inspection and connector disconnection detection. And the voltage similar to a battery voltage is applied to a battery connection part using a predetermined power supply. As a result, the battery voltage VB is applied to the connector disconnection detection terminal 261a. At this stage, the inspection time detection circuit 286 outputs a high level signal.
[0209]
Then, a voltage equal to or higher than the battery voltage VB + α is applied to the connector disconnection detection terminal 261a. As a result, the inspection detection circuit 286 outputs a low level signal as a clock switching detection signal.
At this time, the clock signal from the converter is directly input to the clock C of the D-type flip-flop 289g. That is, the signal output from the D-type flip-flop 289f is ignored by the processing in the time shortening circuit 287, and the clock signal from the converter is input as the clock of the D-type flip-flop 289g. Therefore, at the time of inspection, the clock signal from the converter is directly used as the clock signal of the D flip-flop 289g without passing through the D flip-flops 289a to 289f. Therefore, the D-type flip-flop 289g outputs the clock signal from the converter as a signal having a double period.
[0210]
Therefore, the period of the output signal in the D-type flip-flops 289g to 289j after the time shortening circuit 287, that is, the time based on each control circuit 9 to 15 is reduced in a pseudo manner, and each control circuit 9 to 15 is shortened. Lamp power control is performed based on time. For this reason, the lamp power control time is shortened.
As described above, when the voltage VB higher than the voltage used for connector disconnection detection is applied to the connector disconnection detection terminal 261a, the inspection detection circuit 286 detects that the inspection is in progress, and in this case, the time is shortened. Each control circuit 9-15 performs each control based on the time shortened by the circuit 287.
[0211]
Thereby, the control time which each control circuit 9-15 performs can be shortened, and test | inspection time can be shortened. Further, since the terminal for inputting the clock switching signal to the time shortening circuit 287 is provided at the connector disconnection detection terminal 261a, it is not necessary to form a terminal only for inputting the clock switching signal. Since the connector disconnection detection terminal 261a is covered with the lamp when the lamp 2 is connected, no special treatment for preventing rust is required.
[0212]
In the present embodiment, when the battery voltage VB decreases, the switching frequency of the MOS transistor 31 is linearly decreased. However, the switching frequency may be changed stepwise.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a discharge lamp device 100 according to an embodiment of the present invention.
2 is a block diagram showing a control system of the discharge lamp device 100 shown in FIG. 1. FIG.
FIG. 3 is a time chart showing waveforms at various points of the starting circuit in the embodiment.
FIG. 4 is a configuration diagram of a bridge drive circuit in the embodiment.
FIG. 5 is a configuration diagram of a drive circuit of a MOS transistor 31 in the embodiment.
FIG. 6 is a configuration diagram of a lamp power control circuit in the embodiment.
7 is a time chart showing the waveform of the voltage V1 in FIG.
FIG. 8 is a configuration diagram of a sample hold circuit 12 in the embodiment.
9 is an explanatory diagram showing a waveform of a lamp voltage VL in FIG. 8. FIG.
10 is a configuration diagram of a sawtooth wave forming circuit in the PWM control circuit 9 in the embodiment. FIG.
11 is a diagram showing a sawtooth wave formed by the sawtooth wave forming circuit in FIG. 10;
12 is a diagram showing a waveform of a primary current that appears in response to the sawtooth wave in FIG. 11. FIG.
13 is a diagram showing a waveform of a primary current that appears according to the sawtooth wave in FIG. 11. FIG.
FIG. 14 is a configuration diagram of a threshold level setting circuit 165 in the embodiment.
FIG. 15 is a mounting structure diagram of the lamp 2 in the embodiment.
FIG. 16 is a circuit configuration diagram for detecting an abnormal state of the discharge lamp device in the embodiment.
17 is a time chart showing abnormality detection in the circuit shown in FIG. 16;
FIG. 18 is a circuit configuration diagram for detecting disconnection of a connector in the embodiment.
FIG. 19 is a circuit configuration diagram for detecting an abnormal state in which the connector is disconnected in the embodiment.
20 is a time chart showing detection of connector disconnection in FIGS. 18 and 19. FIG.
FIG. 21 is a configuration diagram of a reverse connection protection circuit in the embodiment.
FIG. 22 is a configuration diagram of an overvoltage protection circuit in the embodiment.
FIG. 23 is a detail view of a main part of the connector disconnection detection circuit in the embodiment.
FIG. 24 is an explanatory diagram of a clock circuit used when inspecting the discharge lamp device in the embodiment.
FIG. 25 is a diagram showing a waveform of a primary current of a conventional discharge lamp device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Battery, 2 ... Lamp, 5 ... DC power supply circuit, 7 ... Inverter circuit,
7a ... H bridge circuit, 9 ... PWM control circuit, 10 ... lamp power control circuit,
29 ... Flyback transformer, 29a ... Primary winding, 29b ... Secondary winding,
31 ... MOS transistors, 41a to 41d ... MOS transistors.

Claims (5)

When a primary current is passed through a winding (29a) arranged on the primary side based on a DC power supply (1) arranged on the primary side, energy is stored in the winding (29a) and the primary current is cut off. A transformer (29) sometimes supplying the energy to the secondary side;
Switching means (31) for controlling the primary current;
A duty control means (9) for controlling the duty of the switching means (31) at a predetermined switching frequency,
Wherein the transformer the DC power supply which is arranged on the primary side of (29) (1), so that the predetermined power to the discharge lamp (2) which is arranged on the secondary side of the transformer (29) is supplied, the duty The control means (9) is configured to set the duty ratio,
The duty control means (9) is predetermined from the DC power supply (1) to the discharge lamp (2) depending on the voltage of the DC power supply (1) and whether the discharge lamp (2) is before or after lighting. The duty ratio is set so that power is supplied, and when the voltage of the DC power supply (1) decreases after the lighting, the switching frequency is set lower than before the decrease, and before the lighting, The discharge lamp device characterized in that the switching frequency is set lower than after the lighting regardless of the voltage of the DC power supply (1) .   The discharge lamp device according to claim 1, wherein the duty control means (9) sets the switching frequency lower as the voltage of the DC power supply (1) decreases.   The discharge lamp according to claim 1, characterized in that the duty control means (9) is adapted to set the switching frequency lower stepwise when the voltage of the DC power supply (1) decreases. apparatus.   The duty control means (9) sets the duty ratio by comparing a threshold level set according to the state of the discharge lamp (2) with a predetermined sawtooth wave, and the DC power supply ( The switching frequency is set to be low by lowering the frequency of the sawtooth wave in accordance with the decrease in 1). Discharge lamp device. The duty control means (9) sets the switching frequency lower before the lighting than when the voltage of the DC power supply (1) drops after the lighting. The discharge lamp device according to claim 1.

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