JP4349923B2 - Software defined radio - Google Patents

Description

  The present invention relates to a software defined radio including a microprocessor having control corresponding to a plurality of wireless communication systems with the same hardware.

  FIG. 1 shows an example of functional blocks of such a software defined radio 100. The software defined radio 100 includes an antenna 102, a transmission / reception amplification unit 104, a radio unit 108, a baseband signal processing unit 110, a control unit 120, an audio processing unit 142, an LED 146, a ringer 148, and a display unit 150. An input unit 152, a speaker 154, a microphone 156, and a recording media drive 158. The software defined radio 100 is an example of a software defined radio according to the present invention.

  The antenna 102 transmits the upstream RF signal amplified by the transmission amplifier, receives the broadband downstream RF signal, and sends it to the low noise amplifier. The transmission / reception amplifier 104 includes a transmission amplifier that amplifies the transmission RF signal and a low noise amplifier that amplifies the reception RF signal, and demultiplexes the RF transmission signal and the RF reception signal.

  The radio unit 108 performs pure synchronous detection on the received signal received from the transmission / reception amplification unit 104, performs A / D conversion, and sends the signal to the baseband signal processing unit 110. In radio section 108, baseband signal processing section 110 performs D / A conversion on the baseband-spread transmission signal and converts it into an RF signal by orthogonal modulation. The baseband signal processing unit 110 performs baseband signal processing on the transmission signal and the reception signal. For example, the baseband signal processing unit 110 performs processing such as despreading, bus setting, chip synchronization, error correction decoding, data demultiplexing, and diversity handover combining on the received signal transmitted from the radio unit 108. The transmission data is subjected to processing such as error correction coding, framing, data modulation, and spread modulation. Further, the antenna 102, the transmission / reception amplification unit 104, the radio unit 108, and the baseband signal processing unit 110 receive information related to program update or addition of the software defined radio 100 via the radio channel, and send it to the control unit 120. send. The information related to program update or addition is information used to realize program update or addition, such as program modules, setting parameters, etc. of the entire program including OS and application programs. . That is, updating or adding a program is realized by replacing the entire program, replacing an updated part of the program, adding an additional part of the program, changing a setting parameter, or the like.

In the conventional microprocessor used in this type of software defined radio, the operating frequency of the core part of the arithmetic processing reaches several GHz, and higher speed processing is possible. This is practical due to the fact that finer wiring is possible in the semiconductor manufacturing technology, and the technology that changes the operating clock frequency depending on the added state of the processor, which is introduced in the products of major microprocessor manufacturers. It has become a thing.
A method of realizing a high-performance microprocessor function at a low cost by mounting a plurality of core circuits of a processor having a medium or low operation clock in a rewritable logic device such as FPGA or CPLD (for example, , See Patent Document 1).
On the other hand, the hardware of a software defined radio generally has a configuration using an FPGA, DSP, and MPU. For example, real-time signal processing is FPGA, and mid-low speed signal processing is DSP (Digital Signal Processing) or MPU (Micro -Processor Unit), and control-related processing is realized by a configuration called MPU (see, for example, Patent Document 2).
JP-A-5-20282 JP 2003-69470 A

  In order to improve the processing capability with the hardware configuration of such a conventional software defined radio, the operation clock of the processor to be used is further increased, the number of processor devices to be used is increased, and the parallel operation is increased. A method for increasing the overall computing ability by processing is used as a general countermeasure method. However, these methods have a large increase in cost and a physical increase in hardware scale, and there are many problems such as an increase in power consumption and an increase in the amount of heat generated by the device. Become.

  In addition to simultaneously improving processing performance, reducing costs, and reducing the size of hardware, the present invention can also realize suppression of extreme increases in power consumption and device heat generation. The software radio which can be provided is provided.

In order to achieve this object, a software defined radio according to the present invention is a software defined radio including a microprocessor that performs control corresponding to a plurality of wireless communication systems with the same hardware,
The microprocessor includes a memory, an arithmetic circuit connected to the memory,
A clock control circuit for controlling the clock of the arithmetic circuit,
In the arithmetic circuit, when m and n are integers of 2 or more, (m × n) arithmetic units are arranged in a matrix, and the (m × n) arithmetic units are arranged in the vertical, horizontal, and horizontal directions. Connected by a bus that can be arbitrarily connected in an oblique direction of ± 45 ° to the vertical and horizontal directions,
Each of the (m × n) arithmetic units is configured to perform control to distribute and process in parallel at individual operation speeds for each command in a predetermined unit.

That is, in the present invention, as will be described later, the arithmetic circuit 11 of the microprocessor 10 (corresponding to the control unit 120 in the wireless device 100 of FIG. 5) uses a plurality of medium-low speed operation units 1 to form a superlattice. Each computing unit 1 is configured to be connectable by connection, and each computing unit 1 is configured to perform distributed parallel processing at the hardware level by performing processing in a distributed manner on a thread or task basis. In addition, by adopting a configuration in which the operation speed can be individually switched, a configuration in which the operation can be performed at an optimum operation speed suitable for the processing load.
Furthermore, by making this hardware configuration a one-chip ASIC or SoC (System on Chip) one-package device, the hardware of a system that requires large-scale software processing is greatly reduced in size. It becomes possible.
In addition, if each arithmetic unit has an interface with a high-speed serial bus, the wiring is simplified by connecting each arithmetic unit with a high-speed serial bus. In addition, since it is possible to connect discrete arithmetic units, a hardware configuration with a higher degree of freedom can be realized. Therefore, since more processing functions can be processed by one processor device, the hardware can be further downsized.
A similar hardware configuration can also be realized by mounting a plurality of processor cores on an FPGA having a large number of gates that can be obtained in recent years.

According to the present invention, the hardware of a software defined radio can be reduced in size, efficiency, and power consumption at low cost.
Furthermore, since parallel processing by a plurality of arithmetic units is possible, it is possible to construct a highly reliable system by operating each arithmetic unit in a complementary relationship.

  Examples of the present invention will be described below.

  FIG. 1 shows a configuration example of a microprocessor 10 used in the present invention corresponding to the control unit 120 in the wireless device 100 of FIG. 5, wherein 11 is an arithmetic circuit, 12 is a memory, 13 is a bus interface circuit, and 14 is a clock. A control circuit 15 is a state monitoring circuit. Hereinafter, each circuit will be described sequentially.

  FIG. 2 shows an example of the configuration of the arithmetic circuit 11. As will be described in sequence, when m and n are integers of 2 or more, (m × n) arithmetic units are arranged in a matrix. The (m × n) computing units are connected by a bus that can be arbitrarily connected in an oblique direction of ± 45 ° with respect to the vertical, horizontal and vertical and horizontal directions. Each of the arithmetic units is configured to perform control to distribute and process in parallel at individual operation speeds for each command in a predetermined unit.

  FIG. 3 is a block diagram illustrating a configuration example of the arithmetic circuit 11. The arithmetic circuit 11 of the processor 10 is composed of a processor core having 16 arithmetic units in a 4 × 4 array. These arithmetic units can be connected in a superlattice bus as shown in FIG. 3, and can also be connected in the vertical, horizontal, and diagonal directions.

  Next, a case where a plurality of types of processing is performed by the processor 10 will be described. As shown in FIG. 4, as the five types of processing having different processing loads on the arithmetic unit during software execution, the processing A, B, C, D, and other I / O control, the frequency is small, and the processing amount is relatively When the processor 10 executes and uses a small number of processes, the process A having the largest load is the five arithmetic units (101) of the arithmetic units <1> to <3>, <5>, and <6>. The processing B with a large load is the three computing units (102) of the computing units <4>, <7>, <8>, and the next processing C is the two computations of the computing units <9>, <13>. Unit (103), processing D is two computing units (104) <10> and <14>, and other processing is performed by computing units <11>, <12>, <15> and <16>. Each of the four arithmetic units performs distributed processing. Furthermore, even when each process is a multitask composed of a plurality of tasks, tasks can be processed in parallel by the number of computing units to be used. A processing capability equivalent to that of a processor can be obtained at a lower operation speed. In addition, since each arithmetic unit can operate independently, high-speed data buses that require high-load processing such as signal processing, monitoring, and control that require high real-time performance, and high-speed protocol processing. At the same time, it is possible to perform parallel processing without reducing both processing capabilities.

  In addition to this, the configuration of each microprocessor 10 is as shown in FIG. 1, and the operation clock can be individually controlled by the clock control circuit 14, thereby increasing the processing load and the processing time. It is possible to operate at an appropriate clock speed for each arithmetic unit depending on the presence or absence of restrictions. As a result, it is possible to realize processing capacity equal to or higher than that using a single processor capable of high-speed operation with lower power consumption. Furthermore, by loading a sleep control function that can pause the operation in units of computing units, it is possible to significantly reduce power consumption during idling with a light processing load.

  In this example, the process A performs a process that becomes the backbone of the system including the OS, the process B executes a process of a signal that requires real-time property, and the process C performs a protocol process for connecting to the Internet or a LAN. And other network-related processing, and processing D is processing of applications that require high-level processing such as MPEG, JPEG, and encryption / decoding processing, access to the serial interface and peripheral memory, and peripheral bus System processing such as I / O control such as connection processing, and execution processing of an application with low real-time performance are distributed by the remaining four computing units. In addition, this makes it possible to significantly reduce the number of data bus connections, thereby reducing the hardware.

Further, the behavior of each circuit in each process will be described.
A group of arithmetic units that execute the process A is referred to as a group A. Since this group A101 performs processing that is the backbone of the system, a plurality of processes that require real-time performance are executed. In this case, real-time performance can be reliably guaranteed by performing distributed parallel processing with a plurality of arithmetic units. Furthermore, by assigning a certain arithmetic unit as a backup, even if a hang-up occurs in the arithmetic unit that is executing processing that requires the OS or strict real-time property, the state monitoring circuit 15 After switching to a backup computing unit by using monitoring information that is acquired in step 2 and stored in a shared memory space or storage device, this information is used for normal operation before the failure occurs. Since the process can be executed continuously, it is possible to increase the reliability of the system. In addition, by resetting only the hung-up arithmetic unit after being restarted by the processing in the backup arithmetic unit, it becomes possible to make this processor stand by as a backup arithmetic unit after the reset processing is completed. .

  Next, a group of arithmetic units that execute the process B is set as a group B. In order to perform high-speed signal processing, this group can be specialized in computation by setting the operation clock at a higher speed.

  Furthermore, if the group of arithmetic units that execute the process C is a group C, this group performs a network-related process, and therefore when a protocol process, a connection process to a bus, and other processes such as security and gateway are also executed, By dedicating one arithmetic unit to protocol processing and bus connection processing and performing other related application layer processing on the other, efficient software processing becomes possible.

  In addition, when a group of arithmetic units that execute the process D is a group D, here, it is used to execute an application that requires high-level processing. However, such processing is temporarily performed rather than being always executed. Since it is often a high-load process, it operates only when an execution request occurs. Otherwise, processing is performed with only one computing unit, and the other computing unit is placed in a standby state, thereby consuming it. It becomes possible to suppress electric power.

  Finally, for other operations such as I / O control and application execution processing that does not require real-time performance, multiple processes of various types and various loads are executed, so depending on the processing load, When multiple applications are executed individually with four arithmetic units, distributed processing is performed with two arithmetic units according to the processing load, or when several applications are related, cooperation between the arithmetic units is established. However, efficient processing can be realized by adaptively changing the connection state between the arithmetic units according to the processing load, such as performing parallel processing.

  The present invention can maintain the function and performance of a radio device only by changing software without changing hardware, so that it can be widely used for radio devices in general and exhibit excellent effects. .

It is a block diagram which shows the structural example of the microprocessor used for this invention. FIG. 2 is a block diagram illustrating a configuration example of an arithmetic circuit illustrated in FIG. 1. FIG. 3 is a block diagram illustrating a specific example of an arithmetic circuit illustrated in FIG. 2. It is a block diagram which shows the specific example of the microprocessor used for this invention. It is a block diagram which shows the structural example of the conventional software defined radio.

Explanation of symbols

1 arithmetic unit (processor core)
DESCRIPTION OF SYMBOLS 10 Microprocessor 11 Arithmetic circuit 12 Memory 13 Bus interface 14 Clock control circuit 15 State monitoring circuit 100 Software defined radio

Claims (1)

A software defined radio including a microprocessor that performs control corresponding to a plurality of wireless communication systems with the same hardware,
The microprocessor includes a memory, an arithmetic circuit connected to the memory,
A clock control circuit for controlling the clock of the arithmetic circuit,
In the arithmetic circuit, when m and n are integers of 2 or more, (m × n) arithmetic units are arranged in a matrix, and the (m × n) arithmetic units are arranged in the vertical, horizontal, and horizontal directions. Connected by a bus that can be connected in an angle of ± 45 ° to the vertical and horizontal directions.
The (m × n) arithmetic units are configured so as to perform control to be distributed and processed in parallel in a predetermined unit arithmetic unit group.
The first computing unit group is configured to switch between the computing unit that executes processing and the computing unit for backup, and the computing unit that performs the processing and the backup computing unit using the monitoring information of the state monitoring unit. age,
The second arithmetic unit group is configured to control the clock control circuit to perform high-speed signal processing and to input a high-speed clock from other arithmetic unit groups ,
The third computing unit group is configured to perform protocol and bus connection processing with one computing unit and perform application processing with the other computing unit.
The fourth computing unit group is configured to perform processing in one computing unit when an execution request is generated and to put the other computing unit in a standby state.
A software defined radio.

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