JP4346391B2 - Phase shift type high frequency inverter device - Google Patents

Description

  The present invention relates to a phase shift type high frequency inverter device capable of performing output power control and frequency control (load change tracking control) with respect to load change with a single unit.

  The high-frequency inverter device is used as a high-frequency power source for industrial equipment using induction heating technology such as pre-heating prior to melting, quenching, tempering, annealing, brazing, rolling and forging of metals. In addition, high-frequency inverter devices are also expected to be used as high-frequency power sources such as superheated steam generators using induction heating technology, large food processing cookers, and detoxifying treatment devices for harmful substances.

  The induction heating high-frequency power supply has "load fluctuation tracking frequency control (control that changes the operating frequency in response to fluctuations in the load frequency)" and "output power control (output power that becomes insufficient or surplus due to load fluctuations). Both functions of “control for changing” ”are often required. In this case, in the prior art, “load fluctuation tracking frequency control” is realized by PLL control of the high frequency inverter circuit, and “output power control” is realized by the voltage control function of the converter provided in the previous stage of the high frequency inverter circuit. (Non-patent document 1 and Non-patent document 2). Therefore, there has been a problem that the high frequency power source becomes complicated and the cost becomes high. FIG. 17 is a block diagram showing an outline of the circuit configuration of this conventional high-frequency inverter device. In this conventional high-frequency inverter circuit, the operating frequency is different from the resonance frequency of the load.

The inventors therefore shifted the phase between the conduction signals for the two semiconductor switching elements that are controlled in conduction in the high-frequency inverter circuit on condition that the operating frequency matches the resonance frequency, A phase shift type high frequency inverter device that controls power supplied from a high frequency inverter circuit to a load was proposed, and a phase shift type high frequency inverter device that performs power control without using a converter was proposed (Non-Patent Document 3).
Atsushi Okuno, Hitoshi Kawano, Junming Sun, Manabu Kurokawa, Akira Kojina and Mutsuo Nakaoka is "Feasible Development of Soft-Switched SIT Inverter with Load-Adaptive Frequency-Tracking Control Scheme for Induction Heating" paper, which was published under the name of (IEEE Transactions on INDUSTRY APPLICATIONS, VOL.34, NO.4, JULY / AUGUST 1998) The title of the “Surge Analysis of Induction Heat Induction Heat I L” was published by Mu-Ping Chen, Jan-Ku Chen, Katsuki Murata, Masatoshi Nakahara and Kosuke Harada. 5, SEPTEMBER 2001) A paper published by Takumi Yamaguchi, Daisuke Higashi, Hiroyasu Kifune and Yoshihiro Hatanaka under the name of “phase shift control full bridge type high frequency ZCS / ZVS inverter” (The Institute of Electrical Engineers of Japan, Semiconductor Power Conversion Study Group, SPC-02-95 / IEA-02) -36, pp. 105-110, 2002)

  However, in the phase shift type high frequency inverter device previously proposed by the inventors, the variation of the resonance frequency of the load has not been sufficiently studied.

  An object of the present invention is to provide a phase shift type high frequency inverter device capable of output power control and frequency control with respect to load fluctuations without using a converter or PLL control.

  Another object of the present invention is to provide a phase shift type high frequency inverter device having a small number of parts.

  The phase shift type high-frequency inverter device to be improved by the present invention is a high-frequency inverter configured by connecting two or more arm circuits in which two semiconductor switching elements having diodes connected in reverse parallel are connected in series. A circuit and a conduction signal generating circuit for providing a conduction signal to each of the plurality of semiconductor switching elements so as to cause the high-frequency inverter circuit to perform an inverter operation. The conduction signal generation circuit shifts the phase between the conduction signals for the two semiconductor switching elements controlled in conduction in pairs in a state where the load resonance frequency and the operating frequency of the high-frequency inverter circuit match. Thus, the power supplied from the high-frequency inverter circuit to the load is controlled.

  In the present invention, a conduction signal generating circuit is included in each arm in the operation cycle period of two semiconductor switching elements that detect the current flowing through the semiconductor switching element or the diode included in each arm and are controlled to conduct in pairs. Compare the period or time (current detection period or current detection time) during which current is flowing in the semiconductor switching element or diode to be changed, and change the frequency of the conduction signal so that two or more periods or times to be compared match To be configured.

  Here, the operation cycle refers to a time or period corresponding to the reciprocal of the frequency of the conduction signal output from the conduction signal generating circuit.

  More specific conduction signal generating circuits include semiconductor switching elements respectively included in two or more arm circuits (for example, two arm circuits in the case of a single-phase power supply and three arm circuits in the case of a three-phase power supply) A current detection period or a current in which two or more current detection circuits detect the current in an operation cycle period of a current detection circuit that detects a current flowing through the diode and two semiconductor switching elements that are conductively controlled in pairs. Frequency detection means for comparing the detection times and changing the frequency of the conduction signal so that two or more current detection periods or current detection times to be compared coincide with each other.

  Another conduction signal generating circuit used in the present invention is provided for one DC bus line of two DC bus lines that electrically connect the DC power source and the two arm circuits of the high-frequency inverter circuit. A first current detecting means for detecting a direct current supplied to the high-frequency inverter circuit and a second current detecting means for detecting a current flowing in one arm circuit, or a semiconductor switching element included in the two arm circuits or A current detection circuit for detecting a current flowing through the diode and a current flowing through the semiconductor switching element or the diode included in the two arm circuits in the operation cycle period of the two semiconductor switching elements whose conduction is controlled in pairs Compare the current detection period or current detection time for detecting each of the two currents to be compared. And frequency changing means for changing the frequency of the conduction signals as time or current detection time matched output may be further configured with. In this case, the current detection circuit includes a current obtained by subtracting the current detected by the second current detection means from the direct current detected by the first current detection means in the other arm circuit of the two arm circuits. The current flowing through the semiconductor switching element or the diode is detected, and the current detected by the second current detecting means is detected as the current flowing through the semiconductor switching element or the diode included in the one arm circuit. . When two current detection means are used for one DC bus line in this way, the length of the DC bus line can be shortened in an actual circuit design, and the influence of inductance should be reduced. Can do.

  The present invention shifts the phase between conduction signals for two semiconductor switching elements that are controlled in conduction in a state where the resonant frequency of the load and the operating frequency of the high-frequency inverter circuit match. When controlling the power supplied to the load from the high-frequency inverter circuit, when the operating frequency and the resonance frequency coincide with each other, the currents flowing through the two semiconductor switching elements or diodes that are controlled to conduct in pairs When the current detection period or current detection time of the two currents coincides and the operating frequency and the resonance frequency do not coincide, the current detection period or current of the current flowing through the two semiconductor switching elements or diodes that are controlled to conduct in pairs This is based on the discovery of a phenomenon that the detection times do not match. Therefore, in the present invention, the current detection periods or the current detection times of the currents flowing through the two semiconductor switching elements or diodes controlled in pairs by the frequency changing means are compared, and the conduction signal is set so that they match. Decided to change the frequency. As a result, according to the present invention, not only power control but also frequency control can be realized with a simple configuration without using a converter and PLL control with a single high-frequency inverter circuit.

  If a single-phase high-frequency inverter device is configured, it is easy to configure a high-frequency inverter circuit using two arm circuits and provide a current detection means for each arm circuit.

  As the conduction signal generation circuit, a circuit including a control oscillator whose oscillation frequency is changed by a control signal and configured to output a conduction signal based on the output of the control oscillator can be used. In this case, the frequency changing unit includes a comparison unit that compares a current detection period or a current detection time and outputs a comparison signal according to the comparison result, and a control signal generation unit that generates a control signal based on the comparison signal. Can be configured. According to such a configuration, a comparison result can be obtained with a simple configuration, and the frequency of the conduction signal can be changed. In this case, for example, the controlled oscillator can be composed of a voltage controlled oscillator. The comparison circuit is preferably configured so that the comparison signal indicates a comparison result by a change in voltage, and the comparison signal is preferably supplied to the voltage controlled oscillator through a low-pass filter. By adopting such a configuration, the conduction signal generating circuit can be configured most inexpensively and easily at the present stage.

  In the case of a single-phase high-frequency inverter device, the current detection unit detects two current sensors that detect currents flowing in the two arm circuits, and one polarity signal (positive or negative) of each output of the two current sensors. It is preferable to have a structure including conversion means for outputting the generation period or generation time of the polarity signal waveform) as the current detection period or current detection time.

  According to the present invention, it is possible to perform power control and frequency control simultaneously with a single high-frequency inverter device, and it is possible to easily realize downsizing, weight reduction, and cost reduction of the entire device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The load fluctuation tracking frequency control which is the core technology of the present invention is applied to a full bridge type phase shift high frequency inverter. First, the operation principle of the phase shift type high frequency inverter circuit will be briefly described. FIG. 1 shows the configuration of a phase shift type high-frequency inverter circuit that has become known from Non-Patent Document 3.

  In FIG. 1, a phase shift type high frequency inverter circuit 1 includes two arm circuits 2 and 3 in which two semiconductor switching elements S1 and S2 or diodes D1 to D4 connected in antiparallel are connected in series. Are constituted by a bridge circuit connected in parallel. Actually, power semiconductor switches (Q1 to Q4) in which diodes are connected in reverse parallel to one semiconductor switching element are used. As the power semiconductor switches Q1 to Q4, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors), SITs (Static Induction Transistors, etc.) can be used. The member indicated by the symbol Ed is a DC power supply, and this DC power supply rectifies a single-phase or three-phase AC input to generate DC power. Reference numerals a and b denote output terminals of the inverter circuit 1, respectively. The output terminals a and b are connected to a load series resonance circuit 4 including an inductor Lo, a capacitor Cs, and a resistor Ro that consumes AC power. . When the load is an induction heating load, the equivalent circuit is represented by a series circuit of an inductor Lo and a resistor Ro.

As shown in FIG. 1, the power semiconductor devices Q1 to Q4 constitute a full bridge circuit. The semiconductor switching elements S1 to S4 are on / off controlled by gate voltages (v _{G1 to} v _G4 ) as conduction signals. When the gate voltage is input, the semiconductor switching elements S1 to S4 are turned on. FIG. 2 shows waveforms of a gate voltage (conduction signal) for operating the phase shift high-frequency inverter, an inverter output voltage v _ab , an inverter output current i _o , and currents i _{1 to} i ₄ flowing through the semiconductor switching elements.

The condition for outputting the voltage v _ab between the inverter output terminals _ab is as follows:
1. 1. Gate voltages (v _G1 , v _G4 ) are simultaneously input to S1 and S4. That is, gate voltages (v _G2 , v _G3 ) are simultaneously input to S2 and S3. In other states (3 to 5 below), no voltage is output to the inverter output terminal.

3. 3. The gate voltage is input to only one of S1 to S4. 4. Gate voltages (v _G1 , v _G3 ) are simultaneously input to S1 and S3. In the phase shift type high frequency inverter circuit in which the gate voltages (v _G2 , v _G4 ) are simultaneously input to S2 and S4, a time difference PD is given between the gate voltages v _G1 and v _G4 , and v _G2 and v _G3 are simultaneously _generated. A time difference PD is also given between the two. The larger the time difference PD, the shorter the period Tw in which v _G1 and v _G4 or v _G2 and v _G3 are simultaneously input, the smaller the effective value of the inverter output voltage, and the lower the output power. Conversely, the smaller the time difference PD is, the longer Tw is, the effective value of the inverter output voltage is increased, and the output power is increased. In the present specification, the time difference PD of the timing at which this gate voltage is input to the semiconductor switching element is called a phase difference. Since the output voltage width Tw changes due to this phase difference, it is also called a phase shift PWM (Pulse Width Modulation) high-frequency inverter (Electrical Society High Frequency Resonance Switching Power Supply System and Applied Technology Research Special Committee Edition: IEEJ Technical Report “High Frequency Trends of Resonant Switching Power Supply Systems and Applied Technologies, "November 1992, pp. 22-23s).

When the operation frequency of this phase shift type high frequency inverter circuit is driven to coincide with the load resonance frequency, a load current _io as shown in FIG. 2 flows. The current waveforms i _{1 to} i ₄ flowing through the semiconductor switching elements are waveforms obtained by cutting out the load current with the gate voltage.

First, the current waveform i ₁ (i ₂ ) will be described in detail. If the semiconductor switching element S2 (S1) is turned off while a current is flowing through the semiconductor switching element S2 (S1), the current is instantaneously commutated to the diode D1 (D2). If the gate voltage v _G1 (v _G2 ) is input to the semiconductor switching element S1 (S2) while the diode D1 (D2) is conducting, current starts to flow through the semiconductor switching element S1 (S2) due to current resonance. . Thus, the semiconductor switching element S1 / diode D1 (or the semiconductor switching element S2 / diode D2) is in an operating state in which the diode is first conducted and the semiconductor switching element is subsequently conducted. This is also referred to as “current delay operation”.

Next, the current waveform i ₃ (i ₄ ) will be described. When the gate voltage V _G3 (V _G4 ) is input to the semiconductor switching element S3 (S4) while the current flows through the diode D4 (D3), the current of the diode D4 (D3) instantaneously changes to the semiconductor switching element S3 (S4). To commutate. The current flowing through the semiconductor switching element S3 (S4) changes in a resonant manner, and the current starts to flow through the diode D3 (D4) after the current of the semiconductor switching element S3 (S4) becomes zero. The gate voltage v _G3 (v _G4 ) is set to 0 while the diode D3 (D4) is conducting. As described above, the semiconductor switching element S3 / diode D3 (semiconductor switching element S4 / diode D4) is in an operation state in which a current flows through the diode after a current flows through the semiconductor switching element. This is also referred to as “current advance operation”.

  When the phase shift type high frequency inverter circuit 1 is operated at the load resonance frequency, the operation of the semiconductor switching element is divided into “current delay operation” and “current advance operation”.

  FIG. 3 is a waveform diagram in which only the current waveform is extracted. When carefully observing FIG. 3, the time Td1 during which the diode D1 is on and the time Td4 during which the diode D4 is on are approximately equal. The same applies to the diode D2 and the diode D3.

  FIG. 4 shows a current waveform when the load resonance frequency is lowered (fo ≧ fr) from the state where the operating frequency fo = the load resonance frequency fr due to load fluctuation or the like. It can be seen that Td4 when the diode D4 is on is longer than the time Td1 when the diode D1 is on. When the operating frequency fo ≦ the load resonance frequency fr, the current waveform is as shown in FIG. 5 and Td1 ≧ Td4. If the operating frequency is again matched with the load resonance frequency from these states, the absolute values of Td1 and Td4 change, but Td1 = Td4.

  Therefore, in the phase shift type high frequency inverter circuit, when the operating frequency does not coincide with the load series resonance frequency, a difference occurs in the time for conducting each diode as shown in FIGS. When this is the case, the current flows through each diode as shown in FIG. Further, when this idea is extended and applied to control, if the operating frequency is always controlled so that Td1 = Td4, the operating frequency and the load resonance frequency always coincide (follow the load fluctuation).

  Based on this principle, the present invention is based on a new concept that does not exist in the past, which samples the times Td1 and Td4 during which current flows through a diode (or a semiconductor switching element) and compares them to control the operating frequency of the high-frequency inverter. To do.

  For example, paying attention to the current waveform flowing through the semiconductor switching element S1 / diode D1 and the semiconductor switching element S4 / diode D4, it can be seen that if Td1 ≦ Td4, the operating frequency is lower than the load resonance frequency. Lower it. Conversely, if Td1 ≧ Td4, it can be seen that the operating frequency is higher than the load resonance frequency, and the operating frequency can be lowered. In the description, a method of comparing Td1 and Td4 has been presented, but basically, it can be realized by sampling the current waveform flowing through the semiconductor switching elements S1 to S4 or the antiparallel diodes D1 to D4 at two locations.

  As will be described later, combinations of semiconductor devices to be subjected to current sampling by a current sensor as current detection means are as follows.

a) D1 and D4
b) D2 and D3
c) D1 and D3
d) D2 and D4
e) S1 and S4
f) S2 and S3
g) S1 and S3
h) S2 and S4
When the current is sampled by any combination of a) to h) and any one of the following relational expressions (1) to (8) is established, the load follow-up control of the present invention is possible.

Td1-Td4 = 0 (1)
Td2-Td3 = 0 (2)
Td1-Td3 = 0 (3)
Td2-Td4 = 0 (4)
Ts1-Ts4 = 0 (5)
Ts2-Ts3 = 0 (6)
Ts1-Ts3 = 0 (7)
Ts2-Ts4 = 0 (8)
In the above formula, Td1 to Td4 are periods or times when the diodes D1 to D4 are conducting, and Ts1 to Ts4 are periods or times when the semiconductor switching element is conducting.

  As will be described later, the first point of the present invention is to control the operating frequency by detecting the period or time during which a current flows through a semiconductor device (diode or semiconductor switching element) and comparing it. In the present specification, this is referred to as conduction time balanced control (CTBC).

  As can be seen from the above equations (1) to (8), in the conduction time balancing control, only the difference in the conduction time of each semiconductor device is taken out as information, so how many μs the current flows through the semiconductor device. Does not matter. This is the second point of the present invention.

  As described in detail above, the phase shift type high frequency inverter circuit controls the output power by the magnitude of the phase difference applied to the gate voltage. In this control method, the absolute value (for example, Td1, Td4) of the time during which each semiconductor device is conducted changes depending on the power control state (phase difference). However, as long as fo = fr, the conduction time difference remains zero. This is the third point of the present invention. That is, the state of output power control by phase shift does not affect the state of operation frequency control by CTBC. Therefore, even when load resonance frequency tracking control of the operating frequency by CTBC is performed, the high frequency inverter circuit can freely control the output power by phase shift control.

  From the above, by applying conduction time balancing control to the phase shift high frequency inverter, it is possible to simultaneously realize “load fluctuation tracking frequency control” and “output power control” with one high frequency inverter device.

  FIG. 6 shows a basic block diagram of an example of a specific embodiment of the present invention. As can be seen from FIG. 6, there is no signal loop in the control circuit in this embodiment. In FIG. 6, CTBC is a conduction time balancing control circuit, CTC is a conduction time comparator, LF is a low-pass filter, and VCO is a voltage controlled oscillator. FIG. 7 is a block diagram of an experimental circuit and its control system of a phase-shift type high-frequency inverter device actually fabricated. FIG. 8 is a timing chart of signal waveforms in each part of the block diagram of FIG. In addition, the numbers 1-14 attached | subjected to FIG. 8 mean that it is a signal generate | occur | produced in the part of the numbers 1-14 attached | subjected to each part of FIG.

  In the configuration of FIG. 7, insulated gate bipolar transistors (generally called IGBTs) are used for the semiconductor devices Q1 to Q4. A current sensor CT1 is attached as a current detection means to the current branch of the semiconductor switching element S1 / diode D1, and a current sensor CT2 is attached to the current branch of the semiconductor switching element S4 / diode D4. In this embodiment, only the negative part of the detected current is detected by passing the detected current sampled using the current sensors CT1 and CT2 (see signals “1” and “2” in FIG. 8) through the diodes D11 and D12. As an information source (see signals “3” and “4” in FIG. 8). Next, this current is converted into a pulsed voltage signal through the A / D converters AD1 and AD2 (see signals “5” and “6” in FIG. 8). In this embodiment, the current sensors CT1 and CT2, diodes D11 and D12, and A / D converters AD1 and AD2 constitute a current detection circuit. Then, the comparison circuit CC compares the two pulse voltage signals (see the comparison circuit output signal “7” in FIG. 8) and then smoothes them through the low-pass filter LF (see the signal “8” in FIG. 8). Here, when the signal of the output of the A / D converter AD2 (see signal “6” in FIG. 8) is longer than the signal of the output of the A / D converter AD1 (see “5” in FIG. 8), it is higher than the reference voltage. The voltage (see “8” in FIG. 8) is output. When the signal of the output of the A / D converter AD1 (see signal “5” in FIG. 8) is longer than the signal of the output of the A / D converter AD2 (see signal “6” in FIG. 8), the reference voltage is used. A low voltage (see signal “8” in FIG. 8) is output. As a result, the oscillation frequency of the voltage controlled oscillator VCO (see signal “9” in FIG. 8) is changed and controlled. In the phase shift control circuit PSC, a phase difference is given to each gate pulse given to each of the semiconductor switching elements S1 to S4 (see signal “10” in FIG. 8). Then, conduction signals are input to the semiconductor switching elements S1 to S4 through the dead time insertion circuits DTI1 to DTI4 (see signals “11” to “14” in FIG. 8). The dead time inserted here is also used in the known configuration described with reference to FIGS. 1 and 2, and the semiconductor switching elements S1 and S2 and the semiconductor switching elements S3 and S4 should not be turned on simultaneously. It is inserted for the purpose of preventing the occurrence of short circuit accidents that occur in Therefore, when implementing this invention, it can employ | adopt arbitrarily and providing a dead time is not an essential requirement.

  9 to 13 are voltage / current waveforms during an experiment performed using a simulated load. In order to simulate the change in the load resonance frequency due to the change in the load inductance Lo (see FIG. 1), a test was conducted with a plurality of high permeability ferrites approaching or moving away from the pancake-type working coil. FIG. 9 shows a waveform in the initial condition of the experiment, Ed = 100V, Lo = 67 μH, Ro = 3.3Ω, Cs = 0.6 μF, phase angle 45 ° (= 360 · PD · fo), and operating frequency. (Fo) and the load resonance frequency (fr = 25.0 kHz) coincide. FIGS. 10 and 11 show that the ferrite Lo is removed from this state and the inductance Lo is changed to 46 μH, which is about 2/3.

  FIG. 10 shows voltage / current waveforms when frequency control according to the present invention is performed, and FIG. 11 shows voltage and current waveforms when frequency control is not introduced. As the inductance Lo decreases, the load resonance frequency increases (fr = 30.3 kHz). When control is performed in response to this, fo is controlled from 25.0 kHz to 30.3 kHz ( (See FIG. 10). As a result, the operation waveforms of voltage and current are similar. On the other hand, when the control is not performed (see FIG. 11), a difference occurs between fo and fr, and the voltage / current waveforms change in the same manner as those shown in FIG.

  Next, FIGS. 12 and 13 show that the ferrite Lo is increased from the state of FIG. 9 to change the inductance Lo to 100 μH, which is about 3/2 times. FIG. 12 shows voltage / current waveforms when frequency control according to the present invention is performed, and FIG. 13 shows voltage and current waveforms when frequency control is not introduced. As the inductance Lo increases, the load resonance frequency decreases (fr = 20.5 kHz). When control is performed in response to this, fo is controlled from 25.0 kHz to around 20.5 kHz. (See FIG. 12). As a result, the operation waveforms of voltage and current are similar. On the other hand, when the control is not performed (see FIG. 13), a difference occurs between fo and fr, and the voltage / current waveform changes in the same manner as seen in FIG.

  Whether or not the load resonance frequency is tracked in this way affects the magnitude of the output power. FIG. 14 shows an example. Compared to the initial condition before changing the load inductance, it can be seen that the power is decreased in the “no control” after the change, but the same power is maintained in the “control”.

  Now consider the current sampling method. In the current advance operation switch such as the power semiconductor switch Q3 (S3 / D3) and the power semiconductor switch Q4 (S4 / D4), the inductance component of the wiring does not affect the operation. On the other hand, in a current delayed operation switch such as the power semiconductor switch Q1 (S1 / D1) and the power semiconductor switch Q2 (S2 / D2), when the inductance component of the equivalent series wiring with respect to the switch increases, The surge voltage may increase and exceed the withstand voltage of the power semiconductor switch (semiconductor switching element).

  In the current sampling methods a) to h) described above, it is necessary to sample the current flowing through the power semiconductor switch Q1 (S1 / D1) and the power semiconductor switch Q2 (S2 / D2) that are in a current delay operation. For example, when sampling the current of the semiconductor switching element S1 or the diode D1, a current sensor must be attached between the + side of the DC bus line and the power semiconductor switch Q1. At this time, an inductance component is generated by wiring between the DC bus line and Q1. Similarly, when the current of the semiconductor switching element S2 or the diode D2 is sampled, a current sensor must be attached between the GND side of the DC bus line and the power semiconductor switch Q2. For this reason, an inductance component is generated by wiring between the DC bus line and the power semiconductor switch Q2. Therefore, in carrying out the present invention, it is desirable to shorten the wiring for attaching the current sensor to the power semiconductor Q1 or Q2 as much as possible to minimize the inductance of the wiring.

  Moreover, although it is easier to make a DC bus line in a straight line shape, when sampling the current of the current delay operation switch and the current advance switch, a straight bus bar cannot be used. For this reason, as shown in FIG. 15, when the current sensor CT2 is arranged, it is necessary to bypass a part of the wiring. However, if it is difficult to change the bus bar as shown in FIG. 15 with an existing high-frequency inverter, or if it is difficult to attach a current sensor to the power semiconductor switch Q1 or Q2 for some reason, the following method is adopted. .

For example, when the currents of the power semiconductor switches Q1 and Q3 are sampled (combination patterns are c) and g), the relational expressions are considered (3) and (7)). As shown in FIG. 1, the current flowing through the positive side of the DC bus line is expressed as id _high and the current flowing through the GND side of the DC bus line is expressed as id _low . At this time, Kirchhoff's current law is established between the current id _high flowing through the DC bus line, the current i1 flowing through the power semiconductor switch Q1, and the current i3 flowing through the power semiconductor switch Q3.

id _high = i1 + i3 (9)
Therefore, the current i1 flowing through the power semiconductor switch Q1 is i1 = id _high −i3 (10)
Applying this, the following method can be found. The current sensor CT1 is attached so as to sample the positive side of the DC bus line and the power semiconductor switch Q3. Since the difference between the id _high and i3 waveforms is i1, this difference waveform and the i3 waveform can be used as information for frequency control. When this concept is applied, the following combinations can be raised in addition to the above-mentioned a) to h) for sampling by the current sensor.

i) DC _high and S3
j) DC _high and D3
k) DC _high and S4
l) DC _high and D4
m) DC _low and S3
n) DC _low and D3
o) DC _low and S4
p) DC _low and D4
However, DC _high is a wiring on the plus side of the DC bus line, and DC _low represents a wiring on the GND side of the DC bus line. With this method, the attachment positions of the current sensors CT1 and CT2 can be set as in the example of FIG. 16, and the DC bus line can use a straight bus bar for both DC _high and DC _low .

  The above description assumes that the DC power supply is closer to the current delay operation IGBT module than the current advance operation IGBT module. On the contrary, the DC power supply is connected to the current advance operation IGBT module closer to the current advance operation IGBT module. The case where it is done is also considered. In this case, the sampling target by the current sensor is also established in the following combination.

q) DC _high and S1
r) DC _high and D1
s) DC _high and S2
t) DC _high and D2
u) DC _low and S1
v) DC _low and D1
w) DC _low and S2
x) DC _low and D2
In the case of the wiring pattern shown in FIG. 16, a current obtained by subtracting the current detected by the current sensor CT2 as the second current detection means from the direct current detected by the current sensor CT1 as the first current detection means. The semiconductor circuit included in the arm circuit in the current advance operation IGBT module detects the current flowing through the semiconductor switching element S1 or the diode D1 included in the arm circuit in the current delay operation IGBT module and detects the current detected by the current sensor CT2. What is necessary is just to comprise a current detection circuit so that it may detect as a current which flows through switching element S3 or diode D3. Thus, when two current detection means (CT1 and CT2) are used for one DC bus line, the length of the DC bus line can be shortened in the actual circuit design, and the influence of the inductance can be reduced. Can be small.

In addition, as a precondition for comparing the prior art and the present invention technique, when a power factor correction converter is included in the system connection part, both functions of “load resonance frequency tracking control” and “output power control” are provided. In the prior art, the following parts configuration is required. That is: 1. PLL control circuit and sensors 2. Drive circuit for driving a high-frequency inverter and its insulated power supply High frequency inverter 4. 4. Converter control circuit for output power control 5. Drive circuit for driving the converter and its isolated power supply Converter with Controllable Elements On the other hand, applying the present invention reduces the number of circuit components as follows.

1. 1. CTBC control circuit and sensors for tracking load fluctuations 2. Insulated power supply for driving the high-frequency inverter. 3. Phase shift control circuit of high frequency inverter for output power control In this way, by applying the present invention, the number of circuit components can be greatly reduced, and not only the entire circuit system can be reduced in size but also the cost can be reduced.

  Although the induction heating which is the object of the above embodiment is used for a low voltage and a large current, it is needless to say that the high frequency inverter device of the present invention can be applied to a high voltage and a small current (for example, an ozone generator). Further, the present invention can be applied not only to an induction heating high-frequency inverter but also to an inverter portion of a DC / DC converter having an inductive load or a capacitive load whose reactance component changes.

  According to the above embodiment, as a method for realizing “load fluctuation tracking frequency control”, “load fluctuation tracking frequency control” and “output power control” are obtained by applying conduction time balancing control to a phase shift high frequency inverter. A single high-frequency inverter can be realized simultaneously. This eliminates the need for a voltage-controllable converter, which is necessary in the prior art, and simplifies the circuit configuration and reduces the cost.

It is a figure which shows the structure of the phase shift type high frequency inverter circuit made public by the nonpatent literature 3. FIG. The gate voltage for operating the phase shift high-frequency inverter (conduction signal) is a diagram showing the inverter output voltage v _ab, inverter output current i _o, the waveform of the current i ₁ through i ₄ flowing through the semiconductor switching devices. It is the wave form diagram which extracted only the current waveform. It is a figure which shows the current waveform when load resonant frequency becomes low (fo> = fr). It is a figure which shows the current waveform when a load resonant frequency becomes high (fo <= fr). It is a basic block diagram of an example of the specific Example of this invention. It is an experimental circuit of the phase shift type high frequency inverter apparatus actually manufactured and a block diagram of its control system. It is a timing chart of the signal waveform in each part of the block diagram of FIG. It is a voltage / current waveform at the time of an experiment conducted using a simulated load. It is a voltage / current waveform at the time of an experiment conducted using a simulated load. It is a voltage / current waveform at the time of an experiment conducted using a simulated load. It is a voltage / current waveform at the time of an experiment conducted using a simulated load. It is a voltage / current waveform at the time of an experiment conducted using a simulated load. It is a figure which shows whether electric power falls by the presence or absence of control. It is a figure which shows an example of the actual mounting state of an Example. It is a figure which shows the example of the actual mounting state of another Example. It is a block diagram which shows the outline of the circuit structure of the conventional high frequency inverter apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase shift type high frequency inverter circuit 2, 3 Arm circuit 4 Load series resonance circuit Q1-Q4 Power semiconductor switch S1-S4 Semiconductor switching element D1-D4, D11, D12 Diode DC1, DC2 Current sensor (current detection means)

Claims (8)

A high-frequency inverter circuit configured by connecting in parallel two or more arm circuits in which two semiconductor switching elements having diodes connected in anti-parallel are connected in series;
A conduction signal generating circuit for providing a conduction signal to each of the plurality of semiconductor switching elements so as to cause the high-frequency inverter circuit to perform an inverter operation;
The phase between the conduction signals for the two semiconductor switching elements that are conduction-controlled in pairs in a state in which the conduction signal generation circuit matches the load resonance frequency and the operating frequency of the high-frequency inverter circuit. Is a phase shift type high frequency inverter device configured to control the power supplied to the load from the high frequency inverter circuit,
The conduction signal generating circuit detects a current flowing through the semiconductor switching element or the diode included in each arm, and in each operation period period of the two semiconductor switching elements controlled in conduction as a pair, A period or time during which a current flows through the semiconductor switching element or the diode included is compared, and the frequency of the conduction signal is changed so that two or more of the periods or times to be compared coincide with each other. A phase-shift type high-frequency inverter device characterized by that. A high-frequency inverter circuit configured by connecting in parallel two or more arm circuits in which two semiconductor switching elements having diodes connected in anti-parallel are connected in series;
A conduction signal generating circuit for providing a conduction signal to each of the plurality of semiconductor switching elements so as to cause the high-frequency inverter circuit to perform an inverter operation;
The phase between the conduction signals for the two semiconductor switching elements that are conduction-controlled in pairs in a state in which the conduction signal generation circuit matches the load resonance frequency and the operating frequency of the high-frequency inverter circuit. Is a phase shift type high frequency inverter device configured to control the power supplied to the load from the high frequency inverter circuit,
The conduction signal generation circuit includes a current detection circuit that detects a current flowing through the semiconductor switching element or the diode respectively included in the two or more arm circuits;
In an operation cycle period of the two semiconductor switching elements whose conduction is controlled in pairs, the current detection periods or current detection times in which the two or more current detection circuits detect the current are compared, and a comparison target The phase shift type high frequency inverter device further comprising: a frequency changing unit that changes the frequency of the conduction signal so that the two or more current detection periods or current detection times that coincide with each other. A high-frequency inverter circuit configured by connecting in parallel two or more arm circuits in which two semiconductor switching elements having diodes connected in anti-parallel are connected in series;
A conduction signal generating circuit for providing a conduction signal to each of the plurality of semiconductor switching elements so as to cause the high-frequency inverter circuit to perform an inverter operation;
The phase between the conduction signals for the two semiconductor switching elements that are conduction-controlled in pairs in a state in which the conduction signal generation circuit matches the load resonance frequency and the operating frequency of the high-frequency inverter circuit. Is a phase shift type high frequency inverter device configured to control the power supplied to the load from the high frequency inverter circuit,
The conduction signal generation circuit includes two or more current detection means provided for the two or more arm circuits, respectively, for detecting a current flowing through the semiconductor switching element or the diode included in each arm. Current detection circuit,
In an operation cycle period of the two semiconductor switching elements whose conduction is controlled in a pair, the current detection period or current detection time in which the two or more current detection means detect the current is compared, and a comparison target The phase shift type high frequency inverter device further comprising: a frequency changing unit that changes the frequency of the conduction signal so that the two or more current detection periods or current detection times that coincide with each other. A high-frequency inverter circuit configured by connecting in parallel two arm circuits in which two semiconductor switching elements having diodes connected in reverse parallel are connected in series;
A conduction signal generating circuit for providing a conduction signal to each of the plurality of semiconductor switching elements so as to cause the high-frequency inverter circuit to perform an inverter operation;
The phase between the conduction signals for the two semiconductor switching elements that are conduction-controlled in pairs in a state in which the conduction signal generation circuit matches the load resonance frequency and the operating frequency of the high-frequency inverter circuit. Is a phase shift type high frequency inverter device configured to control the power supplied to the load from the high frequency inverter circuit,
The conduction signal generating circuit is provided for one DC bus line of two DC bus lines that electrically connect a DC power source and two arm circuits of the high-frequency inverter circuit, and the high-frequency inverter circuit. A first current detecting means for detecting a direct current supplied to the first and second current detecting means for detecting a current flowing in one of the arm circuits, and the semiconductor switching element included in the two arm circuits or the A current detection circuit for detecting a current flowing through the diode;
In the operation cycle period of the two semiconductor switching elements whose conduction is controlled in pairs, the current detection circuit detects the current flowing through the semiconductor switching element or the diode included in the two arm circuits, respectively. Frequency change means for comparing the current detection period or current detection time, and changing the frequency of the conduction signal so that the two current detection periods or current detection times to be compared coincide with each other. A phase shift type high frequency inverter device characterized by The conduction signal generation circuit includes a control oscillator whose oscillation frequency is changed by a control signal, and is configured to output the conduction signal based on an output of the control oscillator,
The frequency changing unit compares the current detection period or the current detection time, outputs a comparison signal according to a comparison result, and a control signal generation unit that generates the control signal based on the comparison signal. The phase shift type high frequency inverter apparatus according to claim 2, 3 or 4. The controlled oscillator comprises a voltage controlled oscillator;
6. The phase shift according to claim 5, wherein the comparison circuit is configured so that the comparison signal indicates a comparison result according to a change in voltage, and the comparison signal is supplied to the voltage controlled oscillator through a low-pass filter. Type high frequency inverter device. The current detection means includes two current sensors that detect currents flowing through the two arm circuits;
The phase shift type high frequency inverter according to claim 3, further comprising: a conversion unit that outputs a generation period or generation time of one of the output signals of the two current sensors as the current detection period or current detection time. apparatus.   The current detection circuit is included in the other arm circuit of the two arm circuits by subtracting the current detected by the second current detection means from the DC current detected by the first current detection means. Detecting the current flowing through the semiconductor switching element or diode, and detecting the current detected by the second current detection means as the current flowing through the semiconductor switching element or diode included in the one arm circuit. The phase shift type high frequency inverter device according to claim 4.

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