JP4343347B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4343347B2
JP4343347B2 JP26883499A JP26883499A JP4343347B2 JP 4343347 B2 JP4343347 B2 JP 4343347B2 JP 26883499 A JP26883499 A JP 26883499A JP 26883499 A JP26883499 A JP 26883499A JP 4343347 B2 JP4343347 B2 JP 4343347B2
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Prior art keywords
semiconductor wafer
grinding
main surface
resin
manufacturing
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JP2001093869A (en
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紀子 村上
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector

Description

【０００１】
【発明の属する技術分野】
本発明は，半導体装置の製造方法に関する。
【０００２】
【従来の技術】
従来の樹脂封止半導体装置の製造方法について，図３を参照しながら説明する。まず，半導体ウェハ１の主面（回路形成面）上に電気メッキ等によりＣｕの配線（以下，「Ｃｕポスト」と称する。）２を形成する（図３（Ａ））。次いで，Ｃｕポスト２を完全に覆うように半導体ウェハ１の主面に対して樹脂３を充填する（図３（Ｂ））。
【０００３】
次いで，半導体ウェハ１の裏面に研削テープ４を貼付する。そして，樹脂３に埋もれてしまっているＣｕポスト２が露出するまで，研磨剤５によって樹脂３の表面を研削する（図３（Ｃ））。Ｃｕポスト２を露出させた後，後工程で半導体ウェハ１を個片化する部分に切断刃６で溝（切り込み）７を形成し，所定の深さまで到達させる（図３（Ｄ））。この溝７を形成することをハーフカットするという。
【０００４】
次いで，溝７が形成された半導体ウェハ１の主面に研削テープ９を貼付する。（図３（Ｅ））。この研削テープ９は上記工程で用いた研削テープ４と同じものである。そして，研削テープ９を貼付した面を研削ステージ（図示しない）に固定した状態で半導体ウェハ１の裏面側の全面を研削する。この研削は前工程で形成した溝７の底部に達するまで行う（図３（Ｆ））。以上の工程により，半導体ウェハ１を個々の半導体装置に個片化することができる。
【０００５】
後工程では，個片化された半導体装置の主面にＣｕポストに接続するバンプ電極が形成される。
【０００６】
【発明が解決しようとする課題】
ところで，半導体装置の主面に形成されるバンプ電極は，ウェハレベルで一括して形成を行うことが好ましいが，上記従来の製造方法では，バンプ電極のウェハレベルでの一括形成は困難である。上記従来の製造方法では，図３（Ｆ）に示したように，半導体ウェハ１の裏面側を研削すると同時に個々の半導体装置に個片化されてしまうからである。
【０００７】
また，半導体ウェハ１の裏面研削工程（図３（Ｆ））前に予めＣｕポスト２と接続するバンプ電極をウェハレベルで一括して形成してしまうことも可能である。しかしながら，半導体ウェハの裏面研削工程（図３（Ｆ））以前にバンプ電極を形成してしまうと，半導体ウェハの裏面研削に必要な研削テープを貼付する工程（図３（Ｅ））で，バンプ電極に直接研削テープ４を接着することになる。この場合，バンプ電極と研削テープ４との接点が小さく，密着が弱まって不安定となるため，半導体ウェハ１の裏面研削工程（図３（Ｆ））が困難となるという問題があった。
【０００８】
本発明は，従来の半導体装置の製造方法が有する上記問題点に鑑みてなされたものであり，本発明の目的は，ウェハレベルで一括してバンプ電極を形成した場合であっても，半導体ウェハの（裏面）研削工程を容易に行うことの可能な，新規かつ改良された半導体装置の製造方法を提供することである。
【０００９】
【課題を解決するための手段】
上記課題を解決するため，半導体装置の製造方法において，半導体ウェハの主面に配線を形成する工程と，配線と実質的に同じ高さまで半導体ウェハの主面を樹脂で覆う工程と，樹脂表面から半導体ウェハの所定の深さまで達する溝を形成する工程と，配線と電気的に接続するバンプ電極を形成する工程と，半導体ウェハの主面側に研削テープを貼付する工程と，半導体ウェハの裏面を研削する工程とを含み，研削テープは，少なくともその一部が樹脂表面に密着していることを特徴とする半導体装置の製造方法が提供される。
【００１０】
かかる製造方法によれば，半導体ウェハの裏面研削工程の前にウェハレベルで一括してバンプ電極を形成した場合であっても，研削テープが樹脂表面に密着しているため，半導体ウェハを研削用のステージ（以下，「研削ステージ」と称する。）に十分に固定することができる。このため，半導体ウェハの裏面研削工程を容易に行うことができる。
【００１１】
上記方法の実現のための一例としては，半導体ウェハの主面のバンプ電極が形成される領域に対応して穴が形成された研削テープを用いることができる。このとき，穴とバンプ電極とが１対１に対応して形成されていると，研削テープの樹脂表面と半導体ウェハとの密着面積を増大させ，より安定した研削工程を行うことができる。
【００１２】
上記方法の実現のための他の一例としては，半導体ウェハの主面のバンプ電極が形成される領域に対応して凹部が形成された研削テープを用いることができる。このとき，凹部とバンプ電極とが１対１に対応して形成されていると，研削テープの樹脂表面と半導体ウェハとの密着面積を増大させ，より安定した研削工程を行うことができる。
【００１３】
【発明の実施の形態】
以下に添付図面を参照しながら，本発明にかかる半導体装置の製造方法の好適な実施の形態について詳細に説明する。なお，本明細書及び図面において，実質的に同一の機能構成を有する構成要素については，同一の符号を付することにより重複説明を省略する。
【００１４】
（第１の実施の形態）
本実施の形態にかかる半導体装置の製造方法を，図１を参照しながら説明する。
まず，厚み６２５μｍ程度の半導体ウェハ１１の主面（回路形成面）上に電気メッキ等により，高さ約７０μｍのＣｕポスト（配線）１２を形成する（図１（Ａ））。このＣｕポスト１２は，後工程で半導体ウェハ１１上に形成されるはんだボール（バンプ電極）１８と電気的に接続される。なお，半導体ウェハ１１の厚みは６２５μｍに限定されず，例えば７２５μｍ程度とすることができる。また，Ｃｕポスト１２の高さは７０〜１００μｍ程度であればよい。
【００１５】
次いで，Ｃｕポスト１２を完全に覆うように半導体ウェハ１１の主面に対して樹脂１３を充填する（図１（Ｂ））。樹脂充填の方法はトランスファーモールド法，ポッティング法，印刷法等で行う。
【００１６】
次いで，半導体ウェハ１１の裏面に研削テープ１４を貼付する。そして，樹脂１３に埋もれてしまっているＣｕポスト１２が露出するまで，研磨剤１５によって樹脂１３の表面を研削する（図１（Ｃ））。この研削テープ１４は，例えば紫外線を照射すること等によって，粘着力が落ち，簡単にはがせるものを用いる。以下で用いられる研削テープについても同様である。この研削工程により，Ｃｕポスト１２は高さ約５０μ程度となる。
【００１７】
Ｃｕポスト１３を露出させた後，ハーフカットを行う。すなわち，後工程で半導体ウェハ１１を個片化する部分に切断刃１６で溝１７を形成し，所定の深さまで到達させる（図１（Ｄ））。この溝１７の深さは最終的に個々の半導体装置とした場合の厚みに基づいて決定される。半導体ウェハ１１の厚みを１００μｍとする場合，溝１７は約２０μｍ深く形成し約１２０μｍとする。そして，樹脂１２の厚みも加えて合計で溝１７の深さは約１７０μｍとなる。以上の工程は従来技術と同様である。
【００１８】
次いで，本実施の形態では，半導体ウェハ１１上にＣｕポスト１２と電気的に接続するはんだボール１８を形成する（図１（Ｅ））。このはんだボール１８は，ウェハレベルで一括して形成を行うことができる。
【００１９】
次いで，はんだボール１８が形成された面，すなわち，溝１７が形成された半導体ウェハ１１の主面に研削テープ１９を貼付する（図１（Ｆ））。この研削テープ１９は上記工程で用いた研削テープ１４と異なり，はんだボール１８が形成される領域に対応して穴１９ａが形成されている。この穴１９ａは，図示の例では，バンプ電極１８と１対１に対応して形成されている。かかる研削テープ１９によれば，はんだボール１８が形成されていても研削テープ１９を半導体ウェハ１１の樹脂表面に密着させることができる。
【００２０】
そして，研削テープ１９を貼付した半導体ウェハ１１の裏面を研削ステージ（図示しない）に固定して，半導体ウェハ１１の裏面側の全面を研削する。この研削は前工程で形成した溝１７の底部に達するまで行う（図１（Ｇ））。以上の工程により，半導体ウェハ１１を個々の半導体装置に個片化することができる。
【００２１】
以上のように本実施の形態によれば，はんだボール１８が形成される領域に対応して穴１９ａが形成された研削テープ１９を用いたので，半導体ウェハ１１の裏面研削工程の前にウェハレベルで一括してはんだボール１８を形成した場合であっても，半導体ウェハ１１を研削ステージに十分に固定することができる。このため，半導体ウェハ１１の裏面研削工程を容易に行うことができる。
【００２２】
また，研削テープ１９の穴１９ａがはんだボール１８と１対１に対応して形成されているので，研削テープ１９と半導体ウェハ１１の樹脂表面との密着面積を増大させ，より安定した研削工程を行うことができる。
【００２３】
（第２の実施の形態）
本実施の形態にかかる半導体装置の製造方法を，図２を参照しながら説明する。
まず，厚み６２５μｍ程度の半導体ウェハ２１の主面（回路形成面）上に電気メッキ等により，高さ約７０μｍのＣｕポスト（配線）２２を形成する（図２（Ａ））。このＣｕポスト２２は，後工程で半導体ウェハ２１上に形成されるはんだボール（バンプ電極）２８と電気的に接続される。なお，半導体ウェハ２１の厚みは６２５μｍに限定されず，例えば７２５μｍ程度とすることができる。また，Ｃｕポスト２２の高さは７０〜１００μｍ程度であればよい。
【００２４】
次いで，Ｃｕポスト２２を完全に覆うように半導体ウェハ２１の主面に対して樹脂２３を充填する（図２（Ｂ））。樹脂充填の方法はトランスファーモールド法，ポッティング法，印刷法等で行う。
【００２５】
次いで，半導体ウェハ２１の裏面に研削テープ２４を貼付する。そして，樹脂２３に埋もれてしまっているＣｕポスト２２が露出するまで，研磨剤２５によって樹脂２３の表面を研削する（図２（Ｃ））。
【００２６】
Ｃｕポスト２３を露出させた後，ハーフカットを行う。すなわち，後工程で半導体ウェハ２１を個片化する部分に切断刃２６で溝２７を形成し，所定の深さまで到達させる（図２（Ｄ））。この溝２７の深さは最終的に個々の半導体装置とした場合の厚みに基づいて決定される。半導体ウェハ２１の厚みを１００μｍとする場合，溝２７は約２０μｍ深く形成し約１２０μｍとする。そして，樹脂２２の厚みも加えて合計で溝１７の深さは約１７０μｍとなる。以上の工程は従来技術と同様である。
【００２７】
次いで，第１の実施の形態と同様に，半導体ウェハ２１上にＣｕポスト２２と電気的に接続するはんだボール２８を形成する（図２（Ｅ））。このはんだボール２８は，ウェハレベルで一括して形成を行うことができる。
【００２８】
次いで，はんだボール２８が形成された面，すなわち，溝２７を入れた半導体ウェハ２１の主面に研削テープ２９を貼付する（図２（Ｆ））。この研削テープ２９は，本実施の形態では，はんだボール２８が形成される領域に対応して凹部２９ａが形成されている。この凹部２９ａは，図示の例では，はんだボール２８と１：１に対応して形成されている。かかる研削テープ２９によれば，はんだボール２８が形成されていても研削テープ２９を半導体ウェハ２１の樹脂表面に密着させることができる。
【００２９】
そして，研削テープ２９を貼付した半導体ウェハ２１の裏面を研削ステージ（図示しない）に固定して，半導体ウェハ２１の裏面側の全面を研削する。この研削は前工程で形成した溝２７の底部に達するまで行う（図２（Ｇ））。以上の工程により，半導体ウェハ２１を個々の半導体装置に個片化することができる。
【００３０】
以上のように本実施の形態によれば，はんだボール２８が形成される領域に対応して凹部２９ａが形成された研削テープ２９を用いたので，半導体ウェハ２１の裏面研削工程の前にウェハレベルで一括してはんだボール２８を形成した場合であっても，半導体ウェハ２１を研削ステージに十分に固定することができる。このため，半導体ウェハ２１の裏面研削工程を容易に行うことができる。
【００３１】
また，研削テープ２９の凹部２９ａがはんだボール２８と１対１に対応して形成されているので，研削テープ２９と半導体ウェハ２１の樹脂表面との密着面積を増大させ，より安定した研削工程を行うことができる。
【００３２】
以上，添付図面を参照しながら本発明にかかる半導体装置の製造方法の好適な実施形態について説明したが，本発明はかかる例に限定されない。当業者であれば，特許請求の範囲に記載された技術的思想の範疇内において各種の変更例または修正例に想到し得ることは明らかであり，それらについても当然に本発明の技術的範囲に属するものと了解される。
【００３３】
例えば，上記実施の形態においては，研削テープの穴あるいは凹部がはんだボールと１対１に対応して形成されている場合の一例につき説明したが，本発明はこれに限定されない。はんだボールが複数形成される所定の領域に対して１つの穴あるいは凹部が形成されていてもよく，さらには，半導体ウェハ上のすべてのはんだボールに対して１つの穴あるいは凹部が形成されていてもよい。ただし，研削テープの穴あるいは凹部がはんだボールと１：１に対応して形成されていると，研削テープと半導体ウェハの樹脂表面との密着面積を増大させ，より安定した研削工程を行うことができるため，上記実施の形態の方が好ましい。
【００３４】
また，研削テープの少なくともその一部が半導体ウェハの樹脂表面に密着していればよく，例えば，研削テープに１または２以上の穴と１または２以上の凹部とが混在して形成されていてもよい。また，研削テープに，一般に穴あるいは凹部とは称されない形状，例えば溝状のものが形成されていてもよい。
【００３５】
【発明の効果】
以上のように本実施の形態によれば，半導体ウェハの裏面研削工程の前にウェハレベルで一括してバンプ電極を形成した場合であっても，半導体ウェハの（裏面）研削工程を容易に行うことができる。
【００３６】
また特に，半導体ウェハを研削ステージに十分に固定することができるため、より安定した研削工程を行うことができる。
【図面の簡単な説明】
【図１】第１の実施の形態にかかる半導体装置の製造方法を示す説明図である。
【図２】第２の実施の形態にかかる半導体装置の製造方法を示す説明図である。
【図３】従来の半導体装置の製造方法を示す説明図である。
【符号の説明】
１１ 半導体ウェハ
１２ Ｃｕポスト（配線）
１３ 樹脂
１４ 研削テープ
１５ 研削剤
１６ 切断刃
１７ 溝（切り込み）
１８ はんだボール（バンプ電極）
１９ 穴が形成された研削テープ
１９ａ 穴
２９ 凹部が形成された研削テープ
２９ａ 凹部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
A conventional method for manufacturing a resin-encapsulated semiconductor device will be described with reference to FIG. First, Cu wiring (hereinafter referred to as “Cu post”) 2 is formed on the main surface (circuit forming surface) of the semiconductor wafer 1 by electroplating or the like (FIG. 3A). Next, a resin 3 is filled into the main surface of the semiconductor wafer 1 so as to completely cover the Cu post 2 (FIG. 3B).
[0003]
Next, the grinding tape 4 is attached to the back surface of the semiconductor wafer 1. Then, the surface of the resin 3 is ground by the abrasive 5 until the Cu post 2 buried in the resin 3 is exposed (FIG. 3C). After the Cu post 2 is exposed, a groove (cut) 7 is formed by a cutting blade 6 in a part where the semiconductor wafer 1 is separated in a later process, and is reached to a predetermined depth (FIG. 3D). Forming the groove 7 is called half-cutting.
[0004]
Next, a grinding tape 9 is attached to the main surface of the semiconductor wafer 1 in which the grooves 7 are formed. (FIG. 3E). This grinding tape 9 is the same as the grinding tape 4 used in the above process. Then, the entire back surface of the semiconductor wafer 1 is ground with the surface to which the grinding tape 9 is attached fixed to a grinding stage (not shown). This grinding is performed until the bottom of the groove 7 formed in the previous step is reached (FIG. 3F). Through the above steps, the semiconductor wafer 1 can be separated into individual semiconductor devices.
[0005]
In the post-process, bump electrodes connected to the Cu posts are formed on the main surface of the separated semiconductor device.
[0006]
[Problems to be solved by the invention]
Incidentally, the bump electrodes formed on the main surface of the semiconductor device are preferably formed collectively at the wafer level, but it is difficult to collectively form the bump electrodes at the wafer level with the above-described conventional manufacturing method. This is because, in the conventional manufacturing method, as shown in FIG. 3F, the back side of the semiconductor wafer 1 is ground and simultaneously separated into individual semiconductor devices.
[0007]
It is also possible to collectively form bump electrodes to be connected to the Cu posts 2 in advance at the wafer level before the back surface grinding step (FIG. 3F) of the semiconductor wafer 1. However, if bump electrodes are formed before the semiconductor wafer back surface grinding step (FIG. 3F), the bumps are applied in the step (FIG. 3E) for applying a grinding tape necessary for semiconductor wafer back surface grinding. The grinding tape 4 is bonded directly to the electrode. In this case, since the contact between the bump electrode and the grinding tape 4 is small and the contact is weakened and unstable, there is a problem that the back grinding process (FIG. 3F) of the semiconductor wafer 1 becomes difficult.
[0008]
The present invention has been made in view of the above-described problems of the conventional method for manufacturing a semiconductor device, and the object of the present invention is to provide a semiconductor wafer even when bump electrodes are collectively formed at the wafer level. It is an object of the present invention to provide a new and improved method of manufacturing a semiconductor device that can easily perform the (back surface) grinding step.
[0009]
[Means for Solving the Problems]
To solve the above problems, in the method for manufacturing a semi-conductor device, forming a wiring on the main surface of the semiconductor wafer, a step of covering the main surface of the semiconductor wafer with a resin to the wiring substantially the same height, the resin surface Forming a groove reaching a predetermined depth of the semiconductor wafer, forming a bump electrode electrically connected to the wiring, applying a grinding tape to the main surface side of the semiconductor wafer, and back surface of the semiconductor wafer A method for manufacturing a semiconductor device is provided in which at least a portion of the grinding tape is in close contact with the resin surface.
[0010]
According to such a manufacturing method, even when bump electrodes are formed collectively at the wafer level before the backside grinding process of the semiconductor wafer, the grinding tape is in close contact with the resin surface, so that the semiconductor wafer is ground. Can be sufficiently fixed to the stage (hereinafter referred to as “grinding stage”). For this reason, the back surface grinding process of a semiconductor wafer can be performed easily.
[0011]
As an example for the realization of the method, it is possible to use a grinding tape hole corresponds to a region where the bump electrodes of the main surface of the semi-conductor wafer is formed is formed. At this time , if the holes and the bump electrodes are formed in a one-to-one correspondence, the contact area between the resin surface of the grinding tape and the semiconductor wafer can be increased, and a more stable grinding process can be performed.
[0012]
As another example for the realization of the method, it is possible to use a grinding tape recess corresponds to a region where the bump electrodes of the main surface of the semi-conductor wafer is formed is formed. At this time, when the the concave portion and the bump electrodes are formed to correspond to one to one, to increase the contact area between the resin surface and the semiconductor wafer grinding tape, it is possible to perform more stable grinding process.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.
[0014]
(First embodiment)
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG.
First, a Cu post (wiring) 12 having a height of about 70 μm is formed on the main surface (circuit formation surface) of the semiconductor wafer 11 having a thickness of about 625 μm by electroplating or the like (FIG. 1A). The Cu post 12 is electrically connected to a solder ball (bump electrode) 18 formed on the semiconductor wafer 11 in a later process. Note that the thickness of the semiconductor wafer 11 is not limited to 625 μm, and can be, for example, about 725 μm. Further, the height of the Cu post 12 may be about 70 to 100 μm.
[0015]
Next, a resin 13 is filled into the main surface of the semiconductor wafer 11 so as to completely cover the Cu post 12 (FIG. 1B). Resin filling is performed by transfer molding, potting, printing, or the like.
[0016]
Next, a grinding tape 14 is attached to the back surface of the semiconductor wafer 11. Then, the surface of the resin 13 is ground by the abrasive 15 until the Cu post 12 buried in the resin 13 is exposed (FIG. 1C). As the grinding tape 14, for example, a tape that can be easily peeled off by irradiating ultraviolet rays or the like is used. The same applies to the grinding tape used below. By this grinding process, the Cu post 12 has a height of about 50 μm.
[0017]
After the Cu post 13 is exposed, half cut is performed. That is, a groove 17 is formed by a cutting blade 16 in a part where the semiconductor wafer 11 is separated in a later process, and the groove is reached to a predetermined depth (FIG. 1D). The depth of the groove 17 is determined based on the thickness in the case of finally forming individual semiconductor devices. When the thickness of the semiconductor wafer 11 is 100 μm, the groove 17 is formed approximately 20 μm deep and approximately 120 μm. The total depth of the groove 17 is about 170 μm including the thickness of the resin 12. The above steps are the same as in the prior art.
[0018]
Next, in the present embodiment, solder balls 18 that are electrically connected to the Cu posts 12 are formed on the semiconductor wafer 11 (FIG. 1E). The solder balls 18 can be formed collectively at the wafer level.
[0019]
Next, a grinding tape 19 is attached to the surface on which the solder balls 18 are formed, that is, the main surface of the semiconductor wafer 11 on which the grooves 17 are formed (FIG. 1 (F)). Unlike the grinding tape 14 used in the above process, the grinding tape 19 has holes 19a corresponding to the areas where the solder balls 18 are formed. In the illustrated example, the holes 19a are formed in one-to-one correspondence with the bump electrodes 18. According to the grinding tape 19, the grinding tape 19 can be brought into close contact with the resin surface of the semiconductor wafer 11 even if the solder balls 18 are formed.
[0020]
Then, the back surface of the semiconductor wafer 11 to which the grinding tape 19 is attached is fixed to a grinding stage (not shown), and the entire back surface of the semiconductor wafer 11 is ground. This grinding is performed until the bottom of the groove 17 formed in the previous step is reached (FIG. 1G). Through the above steps, the semiconductor wafer 11 can be separated into individual semiconductor devices.
[0021]
As described above, according to the present embodiment, since the grinding tape 19 in which the hole 19a is formed corresponding to the region where the solder ball 18 is formed is used, the wafer level before the back surface grinding process of the semiconductor wafer 11 is used. Even when the solder balls 18 are formed in a lump, the semiconductor wafer 11 can be sufficiently fixed to the grinding stage. For this reason, the back surface grinding process of the semiconductor wafer 11 can be performed easily.
[0022]
Further, since the holes 19a of the grinding tape 19 are formed in one-to-one correspondence with the solder balls 18, the contact area between the grinding tape 19 and the resin surface of the semiconductor wafer 11 is increased, and a more stable grinding process is achieved. It can be carried out.
[0023]
(Second Embodiment)
A method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG.
First, a Cu post (wiring) 22 having a height of about 70 μm is formed on the main surface (circuit formation surface) of the semiconductor wafer 21 having a thickness of about 625 μm by electroplating or the like (FIG. 2A). The Cu post 22 is electrically connected to a solder ball (bump electrode) 28 formed on the semiconductor wafer 21 in a later process. The thickness of the semiconductor wafer 21 is not limited to 625 μm, and can be, for example, about 725 μm. Further, the height of the Cu post 22 may be about 70 to 100 μm.
[0024]
Next, a resin 23 is filled into the main surface of the semiconductor wafer 21 so as to completely cover the Cu post 22 (FIG. 2B). Resin filling is performed by transfer molding, potting, printing, or the like.
[0025]
Next, a grinding tape 24 is attached to the back surface of the semiconductor wafer 21. Then, the surface of the resin 23 is ground by the abrasive 25 until the Cu post 22 buried in the resin 23 is exposed (FIG. 2C).
[0026]
After the Cu post 23 is exposed, a half cut is performed. That is, a groove 27 is formed by the cutting blade 26 in a part where the semiconductor wafer 21 is separated in a later process, and the groove is reached to a predetermined depth (FIG. 2D). The depth of the groove 27 is determined based on the thickness in the case of finally forming an individual semiconductor device. When the thickness of the semiconductor wafer 21 is 100 μm, the groove 27 is formed to be about 20 μm deep and about 120 μm. The total depth of the groove 17 is about 170 μm including the thickness of the resin 22. The above steps are the same as in the prior art.
[0027]
Next, as in the first embodiment, solder balls 28 that are electrically connected to the Cu posts 22 are formed on the semiconductor wafer 21 (FIG. 2E). The solder balls 28 can be formed collectively at the wafer level.
[0028]
Next, a grinding tape 29 is attached to the surface on which the solder balls 28 are formed, that is, the main surface of the semiconductor wafer 21 with the grooves 27 (FIG. 2 (F)). In this embodiment, the grinding tape 29 has a recess 29a corresponding to a region where the solder ball 28 is formed. In the illustrated example, the recess 29a is formed corresponding to the solder ball 28 and 1: 1. According to the grinding tape 29, the grinding tape 29 can be brought into close contact with the resin surface of the semiconductor wafer 21 even if the solder balls 28 are formed.
[0029]
Then, the back surface of the semiconductor wafer 21 to which the grinding tape 29 is attached is fixed to a grinding stage (not shown), and the entire back surface side of the semiconductor wafer 21 is ground. This grinding is performed until the bottom of the groove 27 formed in the previous step is reached (FIG. 2G). Through the above steps, the semiconductor wafer 21 can be separated into individual semiconductor devices.
[0030]
As described above, according to the present embodiment, since the grinding tape 29 in which the concave portion 29a is formed corresponding to the region where the solder ball 28 is formed is used, the wafer level before the back surface grinding process of the semiconductor wafer 21 is used. Even when the solder balls 28 are formed in a lump, the semiconductor wafer 21 can be sufficiently fixed to the grinding stage. For this reason, the back surface grinding process of the semiconductor wafer 21 can be easily performed.
[0031]
Further, since the recess 29a of the grinding tape 29 is formed in one-to-one correspondence with the solder ball 28, the adhesion area between the grinding tape 29 and the resin surface of the semiconductor wafer 21 is increased, and a more stable grinding process is achieved. It can be carried out.
[0032]
The preferred embodiments of the method for manufacturing a semiconductor device according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.
[0033]
For example, in the embodiment described above, an example in which the holes or recesses of the grinding tape are formed in one-to-one correspondence with the solder balls has been described, but the present invention is not limited to this. One hole or recess may be formed in a predetermined region where a plurality of solder balls are formed, and one hole or recess is formed in all the solder balls on the semiconductor wafer. Also good. However, if the holes or recesses in the grinding tape are formed corresponding to the solder balls 1: 1, the contact area between the grinding tape and the resin surface of the semiconductor wafer can be increased, and a more stable grinding process can be performed. Therefore, the above embodiment is preferable.
[0034]
Further, it is sufficient that at least a part of the grinding tape is in close contact with the resin surface of the semiconductor wafer. For example, the grinding tape is formed with a mixture of one or more holes and one or more recesses. Also good. In addition, the grinding tape may be formed with a shape generally not called a hole or a recess, for example, a groove shape.
[0035]
【The invention's effect】
As described above, according to the present embodiment, even when bump electrodes are formed collectively at the wafer level before the backside grinding process of the semiconductor wafer, the (backside) grinding process of the semiconductor wafer is easily performed. be able to.
[0036]
In particular, since the semiconductor wafer can be sufficiently fixed to the grinding stage, a more stable grinding process can be performed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment;
FIG. 2 is an explanatory diagram illustrating the manufacturing method of the semiconductor device according to the second embodiment.
FIG. 3 is an explanatory view showing a conventional method of manufacturing a semiconductor device.
[Explanation of symbols]
11 Semiconductor wafer 12 Cu post (wiring)
13 Resin 14 Grinding tape 15 Abrasive agent 16 Cutting blade 17 Groove (Incision)
18 Solder balls (bump electrodes)
19 Grinding tape 19a with holes 19a Hole 29 Grinding tape 29a with recesses Recess

Claims (4)

半導体装置の製造方法において：
半導体ウェハの主面に配線を形成する工程と；
前記配線と実質的に同じ高さまで前記半導体ウェハの主面を樹脂で覆う工程と；
前記樹脂表面から前記半導体ウェハの所定の深さまで達する溝を形成する工程と；
前記配線と電気的に接続するバンプ電極を形成する工程と；
前記半導体ウェハの主面側に研削テープを貼付する工程と；
前記研削テープが貼付された前記半導体ウェハの前記主面を研削ステージに固定する工程と、
前記研削ステージに固定された前記半導体ウェハの裏面を前記溝の底部に達するまで研削して前記半導体ウェハを個々の半導体装置に個片化する工程と；
を含み，
前記研削テープは，少なくともその一部が前記樹脂表面に密着しており、前記半導体ウェハの主面の前記バンプ電極が形成される領域に対応して前記研削テープの厚さ方向に貫通し、前記バンプ電極が嵌る穴が形成されていることを特徴とする，半導体装置の製造方法。In a method for manufacturing a semiconductor device:
Forming wiring on the main surface of the semiconductor wafer;
Covering the main surface of the semiconductor wafer with resin to substantially the same height as the wiring;
Forming a groove reaching the predetermined depth of the semiconductor wafer from the resin surface;
Forming a bump electrode electrically connected to the wiring;
Applying a grinding tape to the main surface of the semiconductor wafer;
Fixing the main surface of the semiconductor wafer to which the grinding tape is affixed to a grinding stage;
Grinding the back surface of the semiconductor wafer fixed to the grinding stage until it reaches the bottom of the groove, and dividing the semiconductor wafer into individual semiconductor devices ;
Including
The grinding tape is at least partially in close contact with the resin surface, and penetrates in the thickness direction of the grinding tape corresponding to a region where the bump electrode is formed on the main surface of the semiconductor wafer, A method of manufacturing a semiconductor device, wherein a hole into which a bump electrode is fitted is formed . 前記穴は，前記バンプ電極と１対１に対応して形成されていることを特徴とする，請求項１に記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1 , wherein the holes are formed in one-to-one correspondence with the bump electrodes. 半導体装置の製造方法において：In a method for manufacturing a semiconductor device:
半導体ウェハの主面に配線を形成する工程と；Forming wiring on the main surface of the semiconductor wafer;
前記配線と実質的に同じ高さまで前記半導体ウェハの主面を樹脂で覆う工程と；Covering the main surface of the semiconductor wafer with resin to substantially the same height as the wiring;
前記樹脂表面から前記半導体ウェハの所定の深さまで達する溝を形成する工程と；Forming a groove reaching the predetermined depth of the semiconductor wafer from the resin surface;
前記配線と電気的に接続するバンプ電極を形成する工程と；Forming a bump electrode electrically connected to the wiring;
前記半導体ウェハの主面側に研削テープを貼付する工程と；Applying a grinding tape to the main surface of the semiconductor wafer;
前記研削テープが貼付された前記半導体ウェハの前記主面を研削ステージに固定する工程と、Fixing the main surface of the semiconductor wafer to which the grinding tape is affixed to a grinding stage;
前記研削ステージに固定された前記半導体ウェハの裏面を前記溝の底部に達するまで研削して前記半導体ウェハを個々の半導体装置に個片化する工程と；Grinding the back surface of the semiconductor wafer fixed to the grinding stage until it reaches the bottom of the groove, and dividing the semiconductor wafer into individual semiconductor devices;
を含み，Including
前記研削テープは，少なくともその一部が前記樹脂表面に密着しており、前記半導体ウェハの主面の前記バンプ電極が形成される領域に対応して、前記バンプ電極が嵌る凹部が形成されていることを特徴とする，半導体装置の製造方法。At least a part of the grinding tape is in close contact with the resin surface, and a recess into which the bump electrode is fitted is formed corresponding to a region where the bump electrode is formed on the main surface of the semiconductor wafer. A method of manufacturing a semiconductor device. 前記凹部は，前記バンプ電極と１対１に対応して形成されていることを特徴とする，請求項３に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3 , wherein the recess is formed in one-to-one correspondence with the bump electrode.
JP26883499A 1999-09-22 1999-09-22 Manufacturing method of semiconductor device Expired - Fee Related JP4343347B2 (en)

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