JP4342475B2 - Photoelectric conversion circuit - Google Patents

Description

  The present invention relates to a photoelectric conversion circuit that converts the intensity of light into an electric signal, and more particularly to a configuration of a photoelectric conversion circuit that receives a differential optical signal and obtains a differential electric signal.

  In general, as an example of using a differential optical input signal, a receiving circuit of a human body communication system that performs communication between wearable devices using a human body or a dielectric as a transmission medium can be given. In this receiving circuit, an electric field corresponding to an alternating electric signal transmitted through the human body is applied to the electro-optic crystal, and the electro-optic crystal is irradiated with a light beam, and the light beam emitted from the electro-optic crystal is P-polarized with a polarized beam. And S-polarized light, which are used for differential optical signals (L1 and L2) to be described later.

  Conventionally, in a receiving circuit of a human body communication system, a load resistor is connected to a photodiode, which is a light receiving element, to configure a photoelectric conversion circuit that converts a change in light intensity into an electrical signal. A technique of amplifying with a dynamic amplifier is disclosed (for example, see Patent Document 1).

  FIG. 8 is a circuit diagram showing a configuration of a conventional photoelectric conversion circuit that can obtain a differential output in particular by using two differential amplifiers whose inputs are cross-connected. The photoelectric conversion circuit shown in the figure is connected to the photodiode PD1, a load resistor R6 having one end connected to the cathode of the photodiode PD1, and the other end of the load resistor R6, and supplies a positive power supply voltage VDD. It consists of a voltage source. The same applies to the other set of the photodiode PD2, the load resistor R7, and the voltage source that supplies the power supply voltage VDD.

  When the optical signals L1 and L2 enter the photodiodes PD1 and PD2, respectively, the photodiodes PD1 and PD2 generate a photocurrent corresponding to the light intensity of the incident optical signal. This photocurrent causes a voltage drop in the load resistor R6 or R7 and is output as a voltage signal. When the optical signals L1 and L2 have a differential relationship in intensity, the pair of voltage signals output from R6 and R7 are also in a differential relationship. Necessary output amplitude can be obtained by amplifying the minute signal voltage output from R6 and R7 by the differential amplifier of the next stage.

Incidentally, the photocurrent from the photodiodes PD1 and PD2 is composed of a bias current of several mA and a signal current of several tens of μA. Therefore, the signal voltage output from the load resistors R6 and R7 is extremely smaller than the reverse bias voltage of the photodiode (for example, about 2V with a 3V power supply). In order to amplify only the signal component of this voltage to an amplitude of 1 V or more and to drive a digital circuit connected to the next stage of the photoelectric conversion circuit by this voltage, a differential amplifier of the photoelectric conversion circuit has an in-phase bias. It is common to use an operational amplifier capable of removing components.
JP 2003-110368 A

  However, since an operational amplifier is expensive and often requires a high power supply voltage, it is low in price and low in operating voltage to be incorporated in a photoelectric conversion circuit constituting a receiving circuit of a human body communication system. It is not suitable in terms of low power consumption.

  On the other hand, when an operational amplifier is not used for the differential amplifier of the photoelectric conversion circuit, there is a problem that the output of the amplifier is saturated with the in-phase component included in the input signal, and the signal component cannot be amplified.

  In view of the above-described problems, the present invention eliminates the need for an operational amplifier in a photoelectric conversion circuit that obtains a differential electrical signal by inputting a differential optical signal, and has an in-phase bias component included in the differential optical signal. The purpose is to amplify only the signal component.

  The photoelectric conversion circuit according to the present invention includes first and second conversion means for converting the respective photocurrents received by the first and second photodiodes into voltage signals, and the converted voltage signals. The first and second folded cascode amplifiers that input and output the amplified voltage signals, and the current value of the first constant current source in the first folded cascode amplifier is the second The control voltage of the first constant current source is adjusted so as to be a value obtained by adding the current value of the photocurrent from the photodiode and a constant bias current, and the second folded cascode amplifier has a second control voltage. Current adjusting means for adjusting the control voltage of the second constant current source so that the current value of the constant current source becomes a value obtained by adding the current value of the photocurrent from the first photodiode and a constant bias current. Characterized in that it has a.

  In the present invention, the current adjustment means for adjusting the control voltage of the first and second constant current sources adds the current value of the photocurrent from the second photodiode and a constant bias current to the first constant current source. By adjusting the control voltage of the first constant current source so that the current value of the constant current source slightly exceeds the maximum value of the photocurrent from the first photodiode, the photocurrent from the second photodiode is adjusted. The excess bias current contained can be removed, and the signal component can be extracted.

  Further, the current value of the second constant current source obtained by adding the current value of the photocurrent from the first photodiode and the constant bias current is slightly higher than the maximum value of the photocurrent from the second photodiode. By adjusting the control voltage of the second constant current source, an excess bias current included in the photocurrent from the first photodiode can be removed, and a signal component can be extracted.

  The control electrode of the first MOS transistor in the cascode stage constituting the first folded cascode amplifier is connected to the drain electrode of the second MOS transistor in the cascode stage constituting the second folded cascode amplifier, The control electrode of the second MOS transistor is connected to the drain electrode of the first MOS transistor.

  In the present invention, the control electrode of the first MOS transistor is connected to the drain electrode of the second MOS transistor, and the control electrode of the second MOS transistor is connected to the drain electrode of the first MOS transistor. The gate-source voltage of the first and second MOS transistors can be increased, and the amplitude of the drain current in the first and second MOS transistors can be increased.

  According to the photoelectric conversion circuit of the present invention, it is possible to amplify only the differential signal component by eliminating the operational amplifier and removing the in-phase bias component included in the differential optical signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of the photoelectric conversion circuit according to the first embodiment. The photoelectric conversion circuit 11 shown in FIG. 1 has a first conversion means 1a for converting a photocurrent i1 received by the first photodiode PD1 into a voltage signal, and a photocurrent i2 received by the second photodiode PD2. A second conversion means 1b for converting the signal into the signal; a first folded cascode amplifier 2a that inputs the converted voltage signal and outputs an amplified voltage signal; and the converted voltage signal is input and amplified. The second folded cascode amplifier 2b for outputting the voltage signal, the current value of the first constant current source 3a in the first folded cascode amplifier 2a, and the second constant current in the second folded cascode amplifier 2a. Current adjusting means 4 for adjusting the current value of the source 3b. Here, for example, n-channel MOS transistors (hereinafter referred to as nMOS transistors) Q11 and Q12 are used for the constant current sources 3a and 3b, respectively.

  In the first conversion means 1a, the anode terminal of the photodiode PD1 is grounded, and the cathode terminal of PD1 is connected to the photocurrent input terminal Tin1. The input terminal Tin1 is connected to the drain terminal of a p-channel MOS transistor (hereinafter referred to as pMOS transistor) Q1 in which the drain terminal and the gate terminal are connected. The source terminal of Q1 is connected to the voltage electrode terminal to which the power supply voltage VDD is supplied. Here, Q1 operates as an active load of PD1, and the drain voltage and gate voltage of Q1 are uniquely determined from the photocurrent i1 flowing through PD1. Thereby, the photocurrent i1 received by the first photodiode PD1 is converted into the drain voltage of Q1.

  In the second conversion means 1b, the anode terminal of the photodiode PD2 is grounded, and the cathode terminal of PD2 is connected to the photocurrent input terminal Tin2. The input terminal Tin2 is connected to the drain terminal of Q2, which is a pMOS transistor in which the drain terminal and the gate terminal are connected. The source terminal of Q2 is connected to the voltage electrode terminal to which the power supply voltage VDD is supplied. Here, Q2 operates as an active load of PD2, and the drain voltage and gate voltage of Q2 are uniquely determined from the photocurrent i2 flowing through PD2. Thereby, the photocurrent i2 received by the second photodiode PD2 is converted into the drain voltage of Q2.

  In the first folded cascode amplifier 2a, Q9 (nMOS transistor) cascode-connected to the input transistor Q3 (pMOS transistor), Q7 (pMOS transistor) used as a load for obtaining an amplified signal voltage, a constant current source It is composed of Q11 (nMOS transistor).

  Specifically, the source terminal of Q3 (pMOS transistor) is connected to the voltage electrode terminal that supplies the power supply voltage VDD, and the drain terminal of Q3 is connected to the drain terminal of Q11 (nMOS transistor). The source terminal of Q11 is grounded. A bias voltage Vb11 for adjusting the current value is supplied from the current adjusting means 4 to the gate terminal of Q11 which is the constant current source 3a. The source terminal of Q9 (nMOS transistor) is connected to the drain terminal of Q11, and the drain terminal of Q9 is connected to the drain terminal of Q7 (pMOS transistor) in which the drain terminal and the gate terminal are connected. The source terminal of Q7 is connected to a voltage electrode terminal that supplies a power supply voltage VDD. Here, the bias voltage Vb2 necessary for operating Q9 in the saturation region is supplied to the gate terminal of Q9. The value of the bias voltage Vb2 is set in advance to an appropriate bias value by dividing the power supply voltage VDD by resistance voltage division or the like.

  As a result, the voltage signal applied to the gate terminal of Q3 is converted into a current by Q3, folded at Q11, and input to the source of Q9. Since the gate-source voltages of Q1 and Q3 are equal, the photocurrent i1 flowing through Q1 and the current flowing through the drain of Q3 are equal (current mirror effect) when the sizes of Q1 and Q3 are the same with respect to the gate length and channel width. Here, since the drain current of Q11 is the sum of the drain current i1 of Q3 and the drain current of Q9, the gate current of Q11 is set so that the drain current of the constant current source Q11 slightly exceeds the maximum value of the drain current i1 of Q3. By adjusting the bias voltage Vb11 supplied to the terminal, it is possible to remove an excess bias current included in the drain current of Q3 and extract a signal component.

  Further, an output buffer composed of Q5 (pMOS transistor) and an external load resistor R1 is connected to the subsequent stage of the first folded cascode amplifier 2a, and the current i3 flowing through Q5 is converted into a voltage by the external load resistor R1. And output from the output terminal Tout1. Specifically, the source terminal of Q5 is connected to the voltage electrode terminal that supplies the power supply voltage VDD, and the drain terminal is connected to the output terminal Tout1. The output terminal Tout1 is connected to one terminal of the external load resistor R1, and the other terminal is grounded. Here, since the gate-source voltages of Q5 and Q7 are equal, when the sizes of Q5 and Q7 are the same with respect to the gate length and the channel width, the current flowing through Q7 and the current i3 flowing through Q5 are equal (current mirror effect). ).

  With such a configuration, the first folded cascode amplifier 2a receives the converted voltage signal and outputs the amplified voltage signal.

  In the second folded cascode amplifier 2b, Q10 (nMOS transistor) cascode-connected to the input transistor Q4 (pMOS transistor), Q8 (pMOS transistor) used as a load for obtaining an amplified signal voltage, a constant current source It is composed of Q12 (nMOS transistor).

  Specifically, the source terminal of Q4 (pMOS transistor) is connected to the voltage electrode terminal that supplies the power supply voltage VDD, and the drain terminal of Q4 is connected to the drain terminal of Q12 (nMOS transistor). The source terminal of Q12 is grounded. A bias voltage Vb12 for adjusting the current value is supplied from the current adjusting means 4 to the gate terminal of Q12 which is the constant current source 3b. The source terminal of Q10 (nMOS transistor) is connected to the drain terminal of Q12, and the drain terminal of Q10 is connected to the drain terminal of Q8 (pMOS transistor) in which the drain terminal and the gate terminal are connected. The source terminal of Q8 is connected to a voltage electrode terminal that supplies a power supply voltage VDD. Here, in order to operate Q10 in the saturation region, a voltage common to the bias voltage Vb2 supplied to the gate terminal of Q9 in the first folded cascode amplifier 2a is supplied to the gate terminal of Q10.

  As a result, the voltage signal applied to the gate terminal of Q4 is converted into a current at Q4, turned back at Q12, and input to the source of Q10. Since the gate-source voltages of Q2 and Q4 are equal, the photocurrent i2 flowing through Q2 and the current flowing through the drain of Q4 are equal when the sizes of Q2 and Q4 are the same with respect to the gate length and channel width (current mirror effect). Here, since the drain current of Q12 is the sum of the Q4 drain current i2 and the drain current of Q10, the gate current of Q12 is set so that the drain current of the constant current source Q12 slightly exceeds the maximum value of the drain current i2 of Q4. By adjusting the bias voltage Vb12 supplied to the terminal, it is possible to remove the excess bias current included in the drain current of Q4 and extract the signal component.

  Further, an output buffer composed of Q6 (pMOS transistor) and an external load resistor R2 is connected to the subsequent stage of the second folded cascode amplifier 2b, and the current i4 flowing through Q6 is converted into a voltage by the external load resistor R2. And output from the output terminal Tout2. Specifically, the source terminal of Q6 is connected to the voltage electrode terminal that supplies the power supply voltage VDD, and the drain terminal is connected to the output terminal Tout2. The output terminal Tout2 is connected to one terminal of the external load resistor R2, and the other terminal is grounded. Here, since the gate-source voltages of Q6 and Q8 are equal, when the sizes of Q6 and Q8 are the same with respect to the gate length and the channel width, the current flowing through Q8 and the current i4 flowing through Q6 are equal (current mirror effect). ).

  With such a configuration, the second folded cascode amplifier 2b receives the converted voltage signal and outputs the amplified voltage signal.

  Next, the operation of the photoelectric conversion circuit 11 will be described. FIG. 2 shows operation waveforms of the photoelectric conversion circuit 11. As shown in (a) of the figure, the photocurrent i1 output from the PD1 receiving the optical signal is obtained by superimposing a signal current (AC current) of several tens of μA on a bias current (DC current) of several mA. Is. The current i1 is copied by a current mirror circuit composed of Q1 and Q3, and a current of the same value flows into the drain terminal of Q11.

  Further, the photocurrent i2 output from the PD2 that receives the optical signal L2 having a differential relationship with the L1 from the PD2 has a signal current (AC current) of several tens of μA in addition to a bias current (DC current) of several mA. It is a superposition. The current i2 is copied by a current mirror circuit composed of Q2 and Q4, and a current of the same value flows into the drain terminal of Q12.

  FIG. 2B shows voltage waveforms at nodes N1 and N2 in FIG. FIG. 2C shows voltage waveforms at nodes N3 and N4 in FIG. Here, in the first folded cascode amplifier 2a, when the signal current from Q3 is folded by the constant current source Q11, an excess bias component included in the drain current of Q3 is removed. That is, the bias voltage Vb11 supplied to the gate voltage of Q11 is adjusted so that the current value of the drain current of the constant current source Q11 slightly exceeds the maximum value of the current flowing from Q3. Thereby, the bias component of the current flowing from the source of Q3 to the source of Q9 can be reduced.

  Similarly, in the second folded cascode amplifier 2b, the bias voltage Vb12 supplied to the gate voltage of Q12 is adjusted so that the current value of the drain current of the constant current source Q12 slightly exceeds the maximum value of the current flowing from Q4. Thereby, the bias component of the current flowing from the source of Q4 to the source of Q10 can be reduced. A method for adjusting the bias voltages Vb11 and Vb12 will be described later.

  FIG. 2D shows voltage waveforms at nodes N5 and N6 in FIG. The voltages N5 and N6 are voltages generated between the source and drain of Q7 and Q8 according to the drain current flowing through the load Q7 and Q8.

  FIG. 2E shows the drain current i3 of Q5 and the drain current i4 of Q6. The drain current flowing through the load Q7 is copied by a current mirror circuit composed of Q7 and Q5, and the copied current i3 flows into the external load resistor R1 and is converted into a voltage signal. Here, also in the current mirror circuit composed of Q8 and Q6, the copied current i4 flows into the external load resistor R2 and is converted into a voltage signal. As a result, differential electrical signals obtained by converting the intensity change of the light input to the photodiode into the voltage level are obtained at the output terminals Tout1 and Tout2.

The maximum value V _H and the minimum value V _L of the voltages at the nodes N1 to N6 satisfy the following relational expression (1). Here, V _thn is the threshold voltage of the nMOS transistor, and V _thp is the threshold voltage of the pMOS transistor.

V _thn <V _L <V _H <VDD − | V _thp | (1)
Next, the current adjustment means 4 that outputs the control voltages Vb11 and Vb12 of the constant current sources 3a and 3b will be described.

  First, the operation in which the current adjusting means 4 outputs the control voltage Vb12 of Q12 that is the constant current source 3b will be described. Q1 and Q15 (pMOS transistor), Q12 and Q17 (nMOS transistor), Q13 (pMOS transistor) and Q19 (pMOS transistor) each constitute a current mirror circuit. Here, R3 is a resistor for setting a bias current, and the bias current value can be changed by changing the resistance value.

  Specifically, the source terminal of Q15 is connected to the electrode terminal of the power supply voltage VDD, and the drain terminal is connected to the gate electrode of Q12. The drain terminal of Q15 is connected to the drain terminal of Q17 in which the drain terminal and the gate terminal are connected. The source terminal of Q17 is grounded.

The drain terminal of Q17 is connected to the drain terminal of Q13, and the source terminal of Q13 is connected to the electrode terminal of the power supply voltage VDD. The gate terminal of Q13 is connected to the gate terminal of Q19 connected to the gate terminal and the drain terminal. The source terminal of Q19 is connected to the electrode terminal of the power supply voltage VDD, and the drain terminal is connected to one end of the bias current setting resistor R3. The other end of the load resistor is grounded.

  With such a configuration, the bias current i5 set by the load resistor R3 is copied by the current mirror circuit formed by Q13 and Q19, and is output as the drain current of Q13. On the other hand, the photocurrent i1 from the photodiode PD1 is copied by a current mirror circuit composed of Q1 and Q15, and is output as a drain current i1 ′ of Q15. i1 'and i5 flow into Q17, which is an nMOS transistor provided as a current addition load, and become the drain current of Q17. Further, the drain current of Q17 is copied by a current mirror circuit composed of Q17 and Q12, and is output as the drain current of Q12 of the constant current source 3b.

  Here, the drain current of Q12 which is the constant current source 3b obtained by adding the photocurrent i1 from the photodiode PD1 and the constant bias current i5 is the sum of the Q4 drain current i2 and the drain current of Q10. Therefore, by adjusting the bias voltage Vb12 supplied to the gate terminal of Q12 so that the drain current of the constant current source Q12 slightly exceeds the maximum value of the drain current i2 of Q4, an extra bias included in the drain current of Q4. The current can be removed and the signal component can be extracted.

  Next, an operation in which the current adjusting unit 4 outputs the control voltage Vb11 of Q11 that is the constant current source 3a will be described. Q2 and Q16 (pMOS transistor), Q11 and Q18 (nMOS transistor), Q14 (pMOS transistor) and Q19 (pMOS transistor) each constitute a current mirror circuit. Here, R3 is a load resistor for setting the bias current, and the bias current value can be changed by changing the resistance value.

  Specifically, the source terminal of Q16 is connected to the electrode terminal of the power supply voltage VDD, and the drain terminal is connected to the gate electrode of Q11. The drain terminal of Q16 is connected to the drain terminal of Q18 in which the drain terminal and the gate terminal are connected. The source terminal of Q18 is grounded.

The drain terminal of Q18 is connected to the drain terminal of Q14, and the source terminal of Q14 is connected to the electrode terminal of the power supply voltage VDD. The gate terminal of Q14 is connected to the gate terminal of Q19 connected to the gate terminal and the drain terminal. The source terminal of Q19 is connected to the electrode terminal of the power supply voltage VDD, and the drain terminal is connected to one end of the load resistor R3 for setting the bias current. The other end of the load resistor is grounded.

  With this configuration, the bias current i5 set by the load resistor R3 is copied by the current mirror circuit formed by Q14 and Q19, and is output as the drain current of Q14. On the other hand, the photocurrent i2 from the photodiode PD2 is copied by a current mirror circuit composed of Q2 and Q16, and is output as a drain current i2 ′ of Q16. i2 'and i5 flow into Q18 which is an nMOS transistor provided as a current addition load, and become the drain current of Q18. Further, the drain current of Q18 is copied by a current mirror circuit composed of Q18 and Q11 and is output as the drain current of Q11 of the constant current source 3a.

  Here, the drain current of Q11 which is the constant current source 3a obtained by adding the photocurrent i2 from the photodiode PD2 and the constant bias current i5 is the sum of the drain current i1 of Q3 and the drain current of Q9. Therefore, by adjusting the bias voltage Vb11 supplied to the gate terminal of Q11 so that the drain current of the constant current source Q11 slightly exceeds the maximum value of the drain current i1 of Q3, an extra bias included in the drain current of Q3. The current can be removed and the signal component can be extracted.

  FIG. 3A shows the waveforms of Vb11 and Vb12 output from the current adjusting means 4, and FIG. 3B shows the drain current of each MOS transistor shown in FIG. Vb12 in FIG. 3 (a) is a back electromotive force generated between the drain and the source due to the drain current of Q17 in FIG. 3 (b). The drain current of Q12 equivalent to the drain current of Q17 is the sum of the drain current i1 flowing through Q3 and the bias current i5 adjusted to slightly exceed the drain current i1. Thus, the signal component is amplified by the difference between the drain current of Q12 and the drain current of Q4, and becomes the drain current i4 of Q8. The drain current i4 is copied by the current mirror circuit and flows into the external load resistor R2, so that the bias component is removed from the output terminal Tout2, and the change in intensity of the differential light input to the photodiodes PD1 and PD2 is changed to the voltage. An electric signal converted into a high and low is obtained.

  Vb11 in FIG. 3A is a back electromotive force generated between the drain and the source due to the drain current of Q18 in FIG. 3B. The drain current of Q11, which is equivalent to the drain current of Q18, is the sum of the drain current i2 flowing through Q4 and the bias current i5 adjusted to slightly exceed the drain current i2. Thereby, the signal component is amplified by the difference between the drain current of Q11 and the drain current of Q3, and becomes the drain current i3 of Q7. The drain current i3 is copied by the current mirror circuit and flows into the external load resistor R1, whereby the bias component is removed from the output terminal Tout1, and the change in the intensity of the differential light input to the photodiodes PD1 and PD2 is changed to the voltage. An electric signal converted into a high and low is obtained.

The bias voltages Vb11 and Vb12 satisfy the following relational expressions (2) and (3). Here, V _thn is the threshold voltage of the nMOS transistor, and V _thp is the threshold voltage of the pMOS transistor.

_Vthn <Vb11 < _VL < _VH <VDD- | _Vthp | (2)
_Vthn <Vb12 < _VL < _VH <VDD- | _Vthp | (3)
Therefore, in the first embodiment, the current value of the first constant current source 3a obtained by adding the current value of the photocurrent i2 from the second photodiode PD2 and the constant bias current i5 by the current adjusting means 4 is used. However, by adjusting the control voltage Vb11 of the first constant current source 3a so as to slightly exceed the maximum value of the photocurrent i1, an excess bias current included in the photocurrent i1 from the first photodiode PD1 is removed. Thus, the signal component can be extracted.

  Further, the second constant current source 3b obtained by adding the current value of the photocurrent i1 from the first photodiode PD1 and the constant bias current i5 is set so that the current value of the second constant current source 3b slightly exceeds the maximum value of the photocurrent i2. By adjusting the control voltage Vb12 of the constant current source 3b, an excess bias current included in the photocurrent i2 from the second photodiode PD2 can be removed and a signal component can be extracted.

  This eliminates the need for an operational amplifier, removes the in-phase bias component included in the differential optical signal, and amplifies only the differential signal component.

  Further, the photoelectric conversion circuit may be configured by using a dual MOS transistor of the MOS transistor used in the first embodiment. FIG. 4 is a circuit diagram in which the photoelectric conversion circuit according to the first embodiment is configured by dual MOS transistors.

  The photoelectric conversion circuit 12 shown in FIG. 1 differs from the photoelectric conversion circuit 11 shown in FIG. 1 in that the nMOS transistor and the pMOS transistor of the photoelectric conversion circuit 12 are replaced, the polarities of the photodiodes PD1 and PD2 are reversed, and the voltage source The voltage supplied from is a negative power supply voltage VSS. Here, since the operation and effect of the photoelectric conversion circuit 12 are the same as those of the photoelectric conversion circuit 11, the description thereof is omitted.

[Second Embodiment]
Hereinafter, a second embodiment will be described. The photoelectric conversion circuit according to the second embodiment has the same basic configuration as that of the first embodiment described with reference to FIG.

  FIG. 5 is a circuit diagram showing a configuration of the photoelectric conversion circuit according to the second embodiment. In the photoelectric conversion circuit 11 according to the first embodiment, the gate terminals of Q9 and Q10 are connected to the input terminal of the bias voltage Vb2, whereas in the photoelectric conversion circuit 13 of FIG. Is connected to the drain electrode (node N6) of Q10, and the control electrode of Q10 is connected to the drain electrode (node N5) of Q9. Otherwise, the photoelectric conversion circuit 11 and the photoelectric conversion circuit 13 have the same configuration.

  By applying a larger signal voltage higher than the threshold voltage between the gate and source of Q9 constituting the first folded cascode amplifier 2a, the voltage amplitude of the node N5 can be increased by the positive feedback action by Q9 and Q10. it can. FIG. 6 shows operation waveforms of the photoelectric conversion circuit 13. As shown in the figure, during the period when the voltage at N3 is low, the voltage at N6 is high, and this voltage is applied between the gate and source of Q9. Thereby, the amplitude of the drain current i3 can be increased, and as a result, the amplitude of the output voltage at the output terminal Tout1 can be increased.

  This is because the Q10 constituting the second folded cascode amplifier 2b has the same effect except that the phase relationship of the voltage between the gate and the source is different by 180 degrees. Therefore, the amplitude of the drain current i4 As a result, the amplitude of the output voltage at the output terminal Tout2 can be increased.

The maximum value V _H and the minimum value V _L of the voltages at the nodes N1 to N6 satisfy the following relational expression (4). Here, V _thn is the threshold voltage of the nMOS transistor, and V _thp is the threshold voltage of the pMOS transistor.

V _thn <V _L <V _H < _VDD− | V _thp | (4)
Therefore, according to the second embodiment, the Q9 control electrode is connected to the Q10 drain electrode, and the Q10 control electrode is connected to the Q9 drain electrode. The amount can be increased, and the amplitude of the drain current i3 of Q9 and the drain current i4 of Q10 can be increased. Thereby, the amplitude of the output voltage of the output terminals Tout1 and Tout2 can be increased.

  Further, the photoelectric conversion circuit may be configured by using a dual MOS transistor of the MOS transistor used in the second embodiment. FIG. 7 is a circuit diagram in which the photoelectric conversion circuit according to the second embodiment is composed of dual MOS transistors.

  5 is different from the photoelectric conversion circuit 13 in FIG. 5 in that the nMOS transistor and the pMOS transistor of the photoelectric conversion circuit 13 are switched, the polarities of the photodiodes PD1 and PD2 are reversed, and the voltage source The voltage supplied from is a negative power supply voltage VSS. Here, since the operation and effect of the photoelectric conversion circuit 14 are the same as those of the photoelectric conversion circuit 13, the description thereof is omitted.

  In each of the above embodiments, the constant current source is configured to obtain a constant current by operating in the saturation region using one n-channel MOS transistor or one p-channel MOS transistor. The constant current source may be configured to have at least one MOS transistor and control the value of the current flowing through the constant current source by the voltage supplied to the control electrode of the MOS transistor.

It is a circuit diagram which shows the structure of the photoelectric conversion circuit which concerns on 1st Embodiment. It is a wave form diagram explaining the photoelectric conversion circuit which concerns on 1st Embodiment. It is a wave form diagram explaining the electric current adjustment means of the photoelectric conversion circuit which concerns on 1st Embodiment. FIG. 2 is a circuit diagram in which the photoelectric conversion circuit according to the first embodiment is configured by dual MOS transistors. It is a circuit diagram which shows the structure of the photoelectric conversion circuit which concerns on 2nd Embodiment. It is a wave form diagram explaining operation | movement of the photoelectric conversion circuit which concerns on 2nd Embodiment. It is a circuit diagram which comprised the photoelectric conversion circuit which concerns on 2nd Embodiment with the dual MOS transistor. It is a block diagram which shows the schematic structure of the conventional photoelectric conversion circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... 1st conversion means 1b ... 2nd conversion means 2a ... 1st return type | mold cascode amplifier 2b ... 2nd return type | mold cascode amplifier 3a ... 1st constant current source 3b ... 2nd constant current source 4 ... Current adjusting means 11... Photoelectric conversion circuit 12 according to the first embodiment... Photoelectric conversion circuit 13 according to the first embodiment constituted by dual MOS transistors... Photoelectric conversion according to the second embodiment Conversion circuit 14: photoelectric conversion circuits PD1, PD2 according to the first embodiment configured by dual MOS transistors ... photodiodes Q1-Q19 ... MOS transistors R1, R2 ... external load resistors R3, R6, R7 ... fixed load resistance

Claims (2)

First and second conversion means for converting respective photocurrents received by the first and second photodiodes into voltage signals;
First and second folded cascode amplifiers for inputting the converted voltage signals and outputting the amplified voltage signals,
The current value of the first constant current source in the first folded cascode amplifier is such that the current value of the photocurrent from the second photodiode and a constant bias current are added. The control voltage of one constant current source is adjusted so that the current value of the second constant current source in the second folded cascode amplifier is equal to the current value of the photocurrent from the first photodiode and the constant value. Current adjusting means for adjusting the control voltage of the second constant current source so as to obtain a value obtained by adding the bias current;
A photoelectric conversion circuit comprising: The control electrode of the first MOS transistor in the cascode stage constituting the first folded cascode amplifier is connected to the drain electrode of the second MOS transistor in the cascode stage constituting the second folded cascode amplifier,
2. The photoelectric conversion circuit according to claim 1, wherein a control electrode of the second MOS transistor is connected to a drain electrode of the first MOS transistor.

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