JP4330926B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electronic apparatus in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
In particular, active matrix liquid crystal display devices in which a switching element composed of a TFT is provided for each display pixel arranged on a matrix have been actively developed.
[0005]
In an active matrix liquid crystal display device, development for expanding an effective screen area in a pixel portion is underway. In order to increase the area of the effective screen area, it is necessary to reduce the area occupied by TFTs (pixel TFTs) arranged in the pixel portion as much as possible. In addition, in order to reduce the manufacturing cost, development in which a driver circuit is formed on the same substrate as the pixel portion is also in progress. When the driver circuit and the pixel portion are formed over the same substrate, an area occupied by a region other than the pixel region called a frame portion tends to be larger than that in which the driver circuit is mounted by the TAB method. In order to reduce the area of the frame portion, there is an urgent need to reduce the circuit scale constituting the drive circuit.
[0006]
The pixel TFT is composed of an n-channel TFT, and is driven by applying a voltage to the liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, in order to keep power consumption low, it is important that the characteristics required for the pixel TFT have a sufficiently low off-current value (drain current that flows when the TFT is off).
[0007]
As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling.
[0008]
However, in the conventional TFT, when the LDD region is formed, the off-current value can be reduced, but the on-current value is also lowered at the same time.
[0009]
A so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film is known as means for preventing deterioration of an on-current value due to hot carriers. . The GOLD structure is more effective than the LDD structure in that the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection. It is known that such a GOLD structure reduces the electric field strength near the drain, prevents hot carrier injection, and is effective in preventing a deterioration phenomenon. In this specification, a TFT structure in which the LDD region overlaps with the gate electrode through the gate insulating film is referred to as a GOLD structure, and a TFT structure in which the LDD region does not overlap with the gate electrode through the gate insulating film is referred to as an LDD structure.
[0010]
Further, the GOLD structure has a higher effect of preventing deterioration of the on-current value than the LDD structure, but there is a problem that the off-current value becomes larger than that of the LDD structure.
[0011]
In the following patent document, it is described that the source region or the drain region of the TFT is formed by irradiating the substrate with accelerated impurity ions from an oblique direction.
[0012]
[Patent Literature]
Japanese Patent Laid-Open No. 8-139337
[Problems to be solved by the invention]
Conventionally, when a TFT having an LDD structure or a TFT having a GOLD structure is formed, there is a problem that the manufacturing process becomes complicated and the number of processes increases. It is clear that an increase in the number of processes not only increases the manufacturing cost but also decreases the manufacturing yield.
[0014]
The present invention relates to an electro-optical device typified by a liquid crystal display device, a light-emitting device having an EL element, and a semiconductor device. It is an object to form a plurality of elements in a limited area so that the area occupied by the elements is reduced and integrated.
[0015]
[Means for Solving the Problems]
In the present invention, a TFT having a GOLD structure is manufactured by performing doping by tilting a substrate by 30 ° to 60 ° with respect to an irradiation direction and forming a low concentration impurity region (Lov) overlapping with a gate electrode in a self-aligned manner. It is characterized by that. The length in the channel length direction of the low-concentration impurity region (Lov) overlapping with the gate electrode is 20 nm to 150 nm, preferably 50 nm to 120 nm.
[0016]
In the TFT, the channel length has become longer depending on the wiring width. Therefore, it is difficult to increase the on-current of the TFT. In addition, since the channel length of the TFT cannot be shortened, it is difficult to reduce the gate capacitance, which hinders the speeding up of the operation of the integrated circuit including the TFT.
[0017]
According to the present invention, the channel length can be shortened by adjusting the region and the amount of wraparound by appropriately adjusting the conditions for oblique doping, for example, the channel length can be 0.2 μm to 1 μm. In addition, the on-state current may be increased by reducing the thickness of the gate insulating film.
[0018]
The present invention realizes an increase in on-current (shortening of channel length, thinning of gate insulating film, reduction of parasitic resistance) and reduction of gate capacitance (shortening of channel length), and a circuit that operates at high speed (representative) Specifically, a CMOS circuit or an NMOS circuit) can be obtained.
[0019]
In addition, when a metal element for promoting crystallization is introduced into a semiconductor film and crystallization is performed, and then the metal element is removed (also referred to as gettering), if the channel length is shortened according to the present invention, channel formation is performed. This is preferable because the residual metal element in the region can be efficiently moved to a gettering site (for example, a semiconductor region containing phosphorus at a high concentration).
[0020]
The configuration of the invention disclosed in this specification is as follows.
A semiconductor device comprising a plurality of TFTs including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
The semiconductor layer includes a channel formation region overlapping with the gate electrode, a low concentration impurity region partially overlapping with the gate electrode, and a source region and a drain region including high concentration impurity regions,
The TFT has a channel length of 0.2 μm to 1 μm.
[0021]
In the above structure, the low-concentration impurity region is present between the channel formation region and the source region, or between the channel formation region and the drain region. Alternatively, in the above structure, the low-concentration impurity region is present either between the channel formation region and the source region or between the channel formation region and the drain region.
[0022]
In addition, the configuration of other inventions is as follows:
A semiconductor device comprising a plurality of TFTs including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
An NMOS circuit comprising a first n-channel TFT and a second n-channel TFT;
The semiconductor layer includes a channel formation region overlapping with the gate electrode, a low concentration impurity region partially overlapping with the gate electrode, and a source region and a drain region including high concentration impurity regions,
The semiconductor device is characterized in that channel lengths of the first n-channel TFT and the second n-channel TFT are 0.2 μm to 1 μm.
[0023]
In addition, the configuration of other inventions is as follows:
A semiconductor device comprising a plurality of TFTs including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
It has a CMOS circuit consisting of an n-channel TFT and a p-channel TFT,
The semiconductor layer includes a channel formation region overlapping with the gate electrode, a low concentration impurity region partially overlapping with the gate electrode, and a source region and a drain region including high concentration impurity regions,
In the semiconductor device, the channel length of the n-channel TFT is 0.2 μm to 1 μm.
[0024]
In each of the above structures, the low concentration impurity region partially overlapping with the gate electrode is formed in a self-aligned manner.
[0025]
The configuration of the invention for realizing the above structure is as follows.
A method for manufacturing a semiconductor device including a plurality of TFTs on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer;
Forming a gate electrode on the first insulating film;
Adding an impurity element imparting n-type to the semiconductor layer using the gate electrode as a mask to form an n-type high-concentration impurity region;
Using the first gate electrode as a mask, an impurity element that imparts n-type to the semiconductor layer is added obliquely within an angle range of 30 ° to 60 ° with respect to the surface of the semiconductor layer to overlap the gate electrode. Forming a concentration impurity region in a self-aligning manner;
Forming a second insulating film covering the gate electrode;
Forming a source wiring or a drain wiring in contact with the high-concentration impurity region over the second insulating film.
[0026]
In addition, the configuration of another invention related to the manufacturing method is as follows:
A method for manufacturing a semiconductor device including a plurality of TFTs on an insulating surface,
Forming a semiconductor film having an amorphous structure on an insulating surface;
Adding a metal element to the semiconductor film having the amorphous structure;
Crystallization of the semiconductor film to form a semiconductor film having a crystal structure;
Forming an island-shaped semiconductor layer by patterning;
Forming a first insulating film on the semiconductor layer;
Forming a gate electrode on the first insulating film;
Adding an impurity element imparting n-type to the semiconductor layer using the gate electrode as a mask to form an n-type high-concentration impurity region;
Using the first gate electrode as a mask, an impurity element that imparts n-type to the semiconductor layer is added obliquely within an angle range of 30 ° to 60 ° with respect to the surface of the semiconductor layer to overlap the gate electrode. Forming a concentration impurity region in a self-aligning manner;
Forming a second insulating film covering the gate electrode;
Selectively removing or reducing the metal element in the semiconductor film having a crystal structure by gettering the metal element in the high-concentration impurity region;
Forming a source wiring or a drain wiring in contact with the high-concentration impurity region over the second insulating film.
[0027]
In the above structure, the step of selectively removing or reducing the metal element in the semiconductor film having a crystal structure by gettering is heat treatment. Alternatively, in the above structure, the step of selectively removing or reducing the metal element in the semiconductor film having a crystal structure by gettering is a process of irradiating the semiconductor film having an amorphous structure with strong light. It is characterized by being.
[0028]
In each structure related to the manufacturing method, the gate electrode has a tapered portion, and the tapered portion overlaps with the low concentration impurity region.
[0029]
The present invention is also characterized by a manufacturing apparatus that performs doping with the substrate inclined. The ion doping apparatus of the present invention is configured to irradiate the ion beam 602 in the horizontal direction with the substrate standing vertically. Also, a robot is connected to the substrate stage that holds the substrate, and it is designed so that it can be moved in two types while carrying the substrate. One is a method of transporting a substrate while tilting the substrate by an angle α (angle α = 90 ° −θ formed by the substrate surface and the ion beam irradiation direction) as shown in FIG. One is a method of transporting a substrate while tilting the substrate by an angle α as shown in FIG. Further, during irradiation with the ion beam, the substrate stage may be fixed at a certain angle α, or the angle α may be constantly changed within a certain angle range.
[0030]
Further, in this specification, the channel length L of the TFT and the length Lov of the GOLD regions 102a and 102b in the channel length direction are defined as the length shown in FIG. Note that the GOLD region refers to the low concentration impurity regions 102 a and 102 b overlapping with the gate electrode 100. Basically, it is assumed that the gate electrode width = L + 2 × Lov holds as shown in FIG. In the case where an impurity element doped by relatively high-temperature heat treatment is diffused after the substrate is obliquely doped, the boundary of the channel formation region 103 becomes difficult to be clarified. ).
[0031]
The doped low-concentration impurity regions 102a and 102b can be observed with an SCM (Scanning Capacitance Microscope). Note that the concentration range of the impurity element imparting N-type or P-type in the low-concentration impurity region is 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁹ / cm ³ . The concentration range of the impurity element imparting N-type or P-type in the high-concentration impurity region is 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ .
[0032]
Further, depending on doping conditions, the peak of the concentration profile 104 may be located on the upper side of the semiconductor layer or on the gate insulating film 101 as shown by a dotted line in FIG. In FIG. 7B, the length Lov of the low-concentration impurity regions 105a and 105b overlapping the gate electrode 100 and the channel length L of the channel formation region 106 are the same as those in FIG.
[0033]
Further, depending on doping conditions, as indicated by a dotted line in FIG. 7C, the peak of the concentration profile 107 may be located in the base insulating film or the substrate of the semiconductor layer. In this case, the formula of gate electrode width = L + 2 × Lov does not hold. Since the channel is formed at the interface between the channel formation region and the gate insulating film 101, the channel length L is the length shown in FIG. 7C, and the low-concentration impurity regions 108a and 108b overlapping the gate electrode 100 are long. The point where Lov is the longest.
[0034]
Note that the structure illustrated in FIG. 7C has a structure in which, when a semiconductor substrate is used, the concentration profiles overlap with each other below the gate, or are too close to each other, and thus cannot be manufactured unless using a TFT. is there.
[0035]
Note that the definitions shown in FIGS. 7A to 7C can be applied not only to an n-channel TFT but also to a p-channel TFT.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0037]
(Embodiment 1)
FIG. 1 shows an example of a method for manufacturing a CMOS circuit and an NMOS circuit using the present invention.
[0038]
First, a base insulating film is formed on a substrate. As the substrate, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.
[0039]
As the base insulating film, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example using a two-layer structure (as the base film is shown; however, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Note that the base insulating film may not be formed. .
[0040]
Next, a semiconductor layer is formed over the base insulating film. The semiconductor layer is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then known crystallization treatment (laser crystallization method, thermal crystallization method). Or a crystalline semiconductor film obtained by performing a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape using a first photomask. The semiconductor layer is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0041]
Next, after removing the resist mask, an insulating film 20 covering the semiconductor layer is formed. The insulating film 20 is formed by a single layer or a laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm using a plasma CVD method or a sputtering method. This insulating film 20 becomes a gate insulating film of the TFT.
[0042]
Next, a conductive film having a thickness of 100 to 600 nm is formed over the insulating film 20. Here, a conductive film made of a W film is formed by sputtering. Note that although the conductive film is W, it is not particularly limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or a single layer of an alloy material or a compound material containing the element as a main component, or You may form by these laminated | stacked. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.
[0043]
Next, a resist mask is formed using a second photomask, and a first etching step is performed using a dry etching method or a wet etching method. In this first etching step, the conductive film is etched to obtain conductive layers 14, 24, 44, and 50 as shown in FIG. The conductive layers 14, 24, 44, and 50 become the gate electrodes of the TFT.
[0044]
Alternatively, an ICP etching apparatus may be used to form a conductive layer having a tapered portion at the end portion (tapered portion). The angle of the tapered portion (taper angle) is defined as the angle formed by the substrate surface (horizontal plane) and the inclined portion of the tapered portion. The taper angle of the conductive layer can be in the range of 5 to 45 ° by appropriately selecting the etching conditions.
[0045]
Next, after removing the resist mask, a resist mask 35 is newly formed using a third photomask, and an impurity element imparting n-type conductivity (typically phosphorus or As) to the semiconductor is doped at a high concentration. A first doping process is performed for the purpose. The conditions of the ion doping method in the first doping step are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 60 to 100 keV. The resist mask 35 covers a region to be a p-channel TFT and the vicinity of the conductive layer 24. Through-doping is performed through the insulating film 20 by this first doping step, and high-concentration impurity regions 17, 18, 41, 42, 47, and 48 are formed. (Fig. 1 (A))
[0046]
Next, after removing the resist mask, a resist mask 36 is newly formed using a fourth photomask, and a second doping step is performed for doping the semiconductor with an n-type impurity element at a low concentration. . In this second doping step, the substrate is doped obliquely to form the low concentration impurity regions 25, 26a, 26b, 27a, 27b overlapping the conductive layers 24, 44, 50 in a self-aligned manner. (Fig. 1 (B))
[0047]
In addition, when performing doping diagonally, it is preferable that angle (theta) which the surface perpendicular | vertical to a substrate surface and the direction which irradiates ion make is 30 degrees-60 degrees. In the case of performing doping at an angle, a simulation was performed to investigate the optimum angle θ formed by the direction of ion irradiation and the plane perpendicular to the substrate surface. The simulation shown in FIGS. 4B and 5 The result was derived. Assuming the model diagram shown in FIG. 4A, simulation was performed using software called TRIM (Transport of Ion in Matter). TRIM is software for simulating the ion implantation process by the Monte Carlo method. The numerical values used in the simulation in FIG. 4B are a phosphorus (P) dose of 3 × 10 ¹⁵ / cm ² , an acceleration voltage of 80 keV, and a gate insulating film thickness of 150 nm.
[0048]
Further, FIG. 1 shows an example of an n-channel TFT doped obliquely with respect to the substrate, but in the p-channel TFT, an impurity element imparting p-type is formed with respect to a plane perpendicular to the substrate surface. Low concentration impurity regions overlapping with the gate electrode may be formed by performing doping obliquely. Further, the numerical values used in the simulation in FIG. 5 are boron (B) dose amount 2 × 10 ¹⁶ / cm ² , acceleration voltage 80 keV, and gate insulating film thickness 150 nm. 4B and 5, the vertical axis represents the wraparound amount L (Lateral length), which is the distance from the mask end face shown in FIG. 4A, and the horizontal axis represents a plane perpendicular to the substrate surface. Is a tilt angle (angle θ shown in FIG. 4A), which is an angle formed by the ion irradiation direction.
[0049]
A part of the ion doping apparatus of the present invention is shown in FIG. Since there is a problem of particles, it is preferable that the substrate 601 be configured to irradiate the ion beam 602 in the horizontal direction with the substrate 601 standing vertically. Note that FIG. 6A shows a diagram in which the ion beam irradiated from the ion beam irradiation means 603 is linear, but is not particularly limited. There are two ways of moving a substrate stage (not shown) that holds and moves the substrate. One is a method of inclining the substrate by an angle α as shown in FIG. 6B, and the other is a method of inclining the substrate by an angle α as shown in FIG. 6C. Further, during irradiation with the ion beam, the substrate stage may be fixed at a certain angle α, or the angle α may be constantly changed within a certain angle range.
[0050]
Further, in order to dope obliquely and form an impurity region below the gate electrode, it is necessary to consider the arrangement of TFTs. As shown in FIGS. 6B and 6C, it is preferable to design a circuit including TFTs by matching the movement of the substrate stage for tilting the substrate and the channel length direction.
[0051]
Next, after removing the resist mask, a resist mask 37 is newly formed using a fifth photomask, and an impurity element imparting p-type conductivity (typically boron) to the semiconductor is doped at a high concentration. A third doping step is performed. Through-doping is performed through the insulating film 20 by this third doping step, and the high concentration impurity regions 11 and 12 are formed. (Figure 1 (C))
[0052]
Thereafter, after an insulating film 22 containing hydrogen is formed, the impurity element added to the semiconductor layer is activated and hydrogenated. In addition, when the semiconductor film is crystallized using a metal element that promotes crystallization, typically nickel, gettering can be performed simultaneously with activation. (Figure 1 (D))
[0053]
Note that phosphorus may be added to the end portion of the semiconductor layer to be the p-channel TFT 31 to separately form a gettering site containing phosphorus. In that case, only the resist mask 35 may be changed so that phosphorus is added to the end portion. Since phosphorus is added only to the end portion, the characteristics as a p-channel TFT hardly change.
[0054]
Next, after forming the interlayer insulating film 23, a contact hole is formed using a sixth mask, and after forming a conductive film, etching is performed using a seventh mask, and the electrodes 15, 16, 21, 45 are formed. , 46, 51 are formed. (Figure 1 (E))
[0055]
In this manner, four types of TFTs 31 to 34 having different structures shown in FIG. 1E can be formed on the same insulating surface.
[0056]
The n-channel TFT 33 has a low-concentration impurity region (Lov) 25 that is in contact with one side of the channel formation region 43 and overlaps the gate electrode 44.
[0057]
The n-channel TFT 34 has low-concentration impurity regions (Lov) 26 a and 26 b that are in contact with both sides of the channel formation region 49 and overlap the gate electrode 50.
[0058]
The p-channel TFT 31 does not have a low concentration impurity region.
[0059]
Further, the n-channel TFT 32 has a low concentration impurity region (Lov) overlapping with the gate electrode 24 and a low concentration impurity region (Loff) not overlapping with the gate electrode 24 on both sides of the channel formation region 19.
[0060]
Further, a CMOS circuit can be manufactured by complementarily combining the obtained n-channel TFT 32 and p-channel TFT 31. In addition, an NMOS circuit can be manufactured by combining the obtained n-channel TFT 33 and the n-channel TFT. In the case of manufacturing an NMOS circuit or a CMOS circuit, it is desirable to make a depletion type TFT and an enhancement type TFT separately by doping a semiconductor region which becomes a channel formation region with a small amount of phosphorus or boron in advance. For example, an n-channel depletion type TFT may be doped with a small amount of phosphorus, and a p-channel type depletion type TFT may be doped with a small amount of boron.
[0061]
(Embodiment 2)
Here, an example is shown in which four types of TFTs having different structures are formed in a doping order different from that in the first embodiment. Since the order other than the doping order is the same as in the first embodiment, the same reference numerals are used.
[0062]
First, the layers up to the conductive layer are formed according to the first embodiment.
[0063]
Here, after the conductive layer is formed, doping is performed obliquely in the first doping step to form a low concentration impurity region (FIG. 2A), and a high concentration impurity region is formed in the second doping step (FIG. 2). 2 (B)). Then, an impurity element imparting p-type conductivity is added in the third doping step to form a high concentration impurity region (FIG. 2C).
[0064]
In the subsequent steps, according to Embodiment Mode 1, TFTs 31 to 34 having four different structures shown in FIG. 2E can be formed.
[0065]
(Embodiment 3)
Here, an example is shown in which four types of TFTs having different structures are formed in a different doping order from the first and second embodiments. Since the order other than the doping order is the same as in the first embodiment, the same reference numerals are used.
[0066]
First, the layers up to the conductive layer are formed according to the first embodiment.
[0067]
Here, after forming a conductive layer, an impurity element imparting p-type is added in the first doping step to form a high concentration impurity region (FIG. 3A), and obliquely formed in the second doping step. Doping is performed to form a low concentration impurity region (FIG. 3B). Then, a high concentration impurity region (FIG. 3C) is formed in the third doping step.
[0068]
In the subsequent steps, according to Embodiment Mode 1, four types of TFTs 31 to 34 having different structures shown in FIG. 3E can be formed.
[0069]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0070]
[Example]
Example 1
Here, an example in which a CPU and a memory are formed using the TFT and the circuit obtained in Embodiment Modes 1 to 3 on a substrate having an insulating surface (typically, a glass substrate or a plastic substrate) with reference to FIG. explain.
[0071]
Reference numeral 1001 denotes a central processing unit (also referred to as a CPU), 1002 denotes a control unit, 1003 denotes a calculation unit, 1004 denotes a storage unit (also referred to as memory), 1005 denotes an input unit, and 1006 denotes an output unit (such as a display unit).
[0072]
The central processing unit 1001 is a combination of the arithmetic unit 1003 and the control unit 1002, and the arithmetic unit 1003 performs arithmetic operations such as addition and subtraction, and logical operations such as AND, OR, and NOT (arithmetic). logic unit (ALU), various registers for temporarily storing operation data and results, and a counter for counting the number of input ones. A circuit that constitutes the arithmetic unit 1003, for example, an AND circuit, an OR circuit, a NOT circuit, a buffer circuit, or a register circuit can be formed using a TFT, and in order to obtain high field-effect mobility, a continuous wave laser beam is used. A semiconductor film that has been crystallized by using a TFT may be formed as an active layer of a TFT. A method of obtaining a polysilicon film by irradiating an amorphous silicon film with a continuous wave laser beam may be used. Alternatively, after a polysilicon film is obtained by heating an amorphous silicon film, a continuous wave laser beam is irradiated. A method of obtaining a polysilicon film may be used, or after adding a metal element serving as a catalyst to an amorphous silicon film, heating to obtain a polysilicon film, and then irradiating a continuous wave laser beam to polysilicon A method of obtaining a film may be used. In this embodiment, the channel length direction of the TFT constituting the arithmetic unit 1003 is aligned with the scanning direction of the laser beam. Further, at the time of doping, the channel length direction of the TFT constituting the arithmetic unit 1003 is matched with the tilt direction of the substrate.
[0073]
In addition, the control unit 1002 plays a role of executing an instruction stored in the storage unit 1004 and controlling the overall operation. The control unit 1002 includes a program counter, an instruction register, and a control signal generation unit. In addition, the control unit 1002 can also be formed using a TFT, and a semiconductor film crystallized using continuous wave laser light may be formed as an active layer of the TFT. In this embodiment, the channel length direction of the TFT constituting the control unit 1002 is aligned with the scanning direction of the laser beam. At the time of doping, the channel length direction of the TFT constituting the control unit 1002 is aligned with the tilt direction of the substrate.
[0074]
The storage unit 1004 is a place for storing data and instructions for calculation, and stores data and programs that are frequently executed by the CPU. The storage unit 1004 includes a main memory, an address register, and a data register. Further, a cache memory may be used in addition to the main memory. These memories may be formed by SRAM, DRAM, flash memory, or the like. In the case where the memory portion 1004 is also formed using a TFT, a semiconductor film crystallized using continuous wave laser light can be manufactured as an active layer of the TFT. In this embodiment, the channel length direction of the TFT constituting the storage unit 1004 is aligned with the scanning direction of the laser beam. At the time of doping, the channel length direction of the TFT constituting the memory portion 1004 and the tilt direction of the substrate are matched.
[0075]
An input unit 1005 is a device that takes in data and programs from the outside. The output unit 1006 is a device for displaying the result, typically a display device.
[0076]
By aligning the TFT channel length direction and the laser beam scanning direction, a CPU with little variation can be formed on an insulating substrate. Further, the CPU and the display portion can be formed on the same substrate. Also in the display portion, it is preferable to align the channel length direction of the plurality of TFTs arranged in each pixel with the scanning direction of the laser beam.
[0077]
In this example, according to the first embodiment, a substrate (such as a CPU) that operates at high speed is manufactured by doping the substrate obliquely and setting the channel length to 0.2 μm to 1 μm.
[0078]
Further, although the circuit design and manufacturing process are complicated, the CPU, the display unit, and the memory can be formed on the same substrate.
[0079]
In this manner, a semiconductor device which can operate on an insulating substrate at high speed and has little variation in electrical characteristics can be completed.
[0080]
Further, this embodiment mode can be freely combined with any one of Embodiment Modes 1 to 3.
[0081]
(Example 2)
In this embodiment, a structure example of a semiconductor device in which at least a pixel portion, a driver circuit for driving a pixel, and an image processing circuit are formed over a substrate having an insulating surface, and an operation method for reducing power consumption will be described.
[0082]
FIG. 9 illustrates an example of a system having a display portion formed over a glass substrate. On the glass substrate, a pixel portion 801, a source line driver circuit 802, a gate line driver circuit 603, and three different functions are provided. Two image processing circuits 804 to 806, a memory 807, an interface circuit 808, and a power supply timing control circuit 809 are provided. The semiconductor device may be a liquid crystal display device or a light emitting display device using an EL material.
[0083]
In the block diagram shown in FIG. 9, a pixel portion 801 is a portion that displays an image, and a source line driver circuit 802 and a gate line driver circuit 803 are driver circuits that drive pixels. Image data is input to the source line driver circuit 802. The interface circuit 808 receives image data or image base data from the outside, converts the image data into an appropriate internal signal, and outputs the internal signal to the source line driver circuit 802, the image processing circuits 804 to 806, or the memory 807. .
[0084]
As a function of this semiconductor device, a semiconductor device that performs various image processing using three image processing circuits 804 to 806 and a memory 807 can be considered. For example, by using one or more of these image processing circuits, image conversion such as image distortion correction, resizing, mosaic processing, scrolling, and inversion, multi-window processing, image generation using the memory 807, and these Complex processing can be considered.
[0085]
Corresponding to this, various operation modes can be considered, and in the semiconductor device of this configuration, it is effective to apply a nonvolatile latch circuit to the registers and latch circuits included in the image processing circuits 804 to 806. . That is, a configuration in which the logical states of the image processing circuits 804 to 806 can be restored by a nonvolatile latch circuit is effective. By doing so, it is possible to cut off the power supply while maintaining the operation state of the image processing circuits 804 to 806, and it is possible to cut off the power supply of the image processing circuits that are not used. As a result, power consumption can be reduced.
[0086]
In addition, even during standby, the power supply can be stopped while maintaining the system status, so it is possible to simultaneously achieve high-speed transition between standby and operation and reduction of power consumption during standby. It becomes.
[0087]
The operation mode switching control is performed by a power supply timing control circuit 809. Specifically, in accordance with the operation mode, the storage procedure and the restoration procedure may be performed on the image processing circuit that is not used before and after the mode switching.
[0088]
In this embodiment, the case where the entire image processing circuits 804 to 806 can be restored has been described. However, the present invention is not necessarily limited to this. The image processing circuits 804 to 806 may be configured to be able to restore the logic states of some of the circuits (for example, the circuit C). In that case, power can be supplied to the circuit C only when the circuit C is used, and power consumption can be reduced.
[0089]
Note that a nonvolatile latch circuit can also be applied to an interface circuit, a source line driver circuit, or a gate line driver circuit. As a result, when each logic circuit does not operate, power consumption can be reduced by shutting off the power supply of the logic circuit.
[0090]
Various circuits in this embodiment (pixel portion 801, source line driver circuit 802, gate line driver circuit 603, three image processing circuits 804 to 806 having different functions, memory 807, interface circuit 808, and power supply timing control circuit 809) Can be manufactured using a TFT capable of high-speed operation obtained according to Embodiment Modes 1 to 3.
[0091]
Note that this embodiment can be freely combined with any of Embodiment Modes 1 to 3 and Embodiment 1.
[0092]
(Example 3)
Various electronic devices can be manufactured by incorporating TFTs obtained by implementing the present invention. Electronic devices include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebook-type personal computers, game devices, and portable information terminals (mobile computers, A mobile phone, a portable game machine, an electronic book, or the like), an image playback device including a recording medium (specifically, a display capable of playing back a recording medium such as a digital versatile disc (DVD) and displaying the image) Apparatus). Specific examples of these electronic devices are shown in FIGS.
[0093]
FIG. 10A illustrates a television which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be applied to the display portion 2003. Note that all information display televisions such as a personal computer, a TV broadcast reception, and an advertisement display are included.
[0094]
FIG. 10B illustrates a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The present invention can be applied to the display portion 2102.
[0095]
FIG. 10C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be applied to the display portion 2203.
[0096]
FIG. 10D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The present invention can be applied to the display portion 2302.
[0097]
FIG. 10E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the present invention can be applied to the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0098]
FIG. 10F shows a game machine, which includes a main body 2501, a display portion 2505, operation switches 2504, and the like.
[0099]
FIG. 10G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The present invention can be applied to the display portion 2602.
[0100]
FIG. 10H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be applied to the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0101]
As described above, the display device obtained by implementing the present invention may be used as a display unit of any electronic device. Note that a semiconductor device manufactured using any structure of Embodiment Modes 1 to 3, Example 1, and Example 2 may be used for the electronic device of this embodiment.
[0102]
【The invention's effect】
According to the present invention, an increase in on-current (shortening of channel length, thinning of gate insulating film, reduction of parasitic resistance) and reduction of gate capacitance (shortening of channel length) are realized, and a circuit that operates at high speed (for example, Circuit constituting the CPU) can be obtained.
[Brief description of the drawings]
FIG. 1 is a process diagram showing Embodiment Mode 1;
FIG. 2 is a process diagram showing Embodiment Mode 2;
FIG. 3 is a process diagram showing Embodiment 3;
FIG. 4 is a diagram illustrating a model diagram and results used for simulation. (Embodiment 1)
FIG. 5 is a diagram showing simulation results. (Embodiment 1)
FIG. 6 is a diagram showing a part of an ion doping apparatus. (Embodiment 1)
FIG. 7 is a diagram illustrating a definition.
FIG. 8 is a block diagram of a CPU. Example 1
FIG. 9 is a diagram showing a system block diagram having a display unit. (Example 2)
FIG 10 illustrates an example of an electronic device. (Example 3)

Claims (15)

A first n-channel having a first island-shaped semiconductor film, an insulating film provided to cover the first island-shaped semiconductor film, and a first gate electrode provided on the insulating film Type TFT,
A second n having a second island-shaped semiconductor film, the insulating film provided to cover the second island-shaped semiconductor film, and a second gate electrode provided on the insulating film An NMOS circuit having a channel-type TFT;
A p-channel TFT having a third island-shaped semiconductor film, the insulating film provided to cover the third island-shaped semiconductor film, and a third gate electrode provided on the insulating film When,
A third n having a fourth island-shaped semiconductor film, the insulating film provided to cover the fourth island-shaped semiconductor film, and a fourth gate electrode provided on the insulating film A CMOS circuit having a channel type TFT,
The first island-shaped semiconductor film has a first low-concentration impurity region only between one of the channel formation region and the source region or between the channel formation region and the drain region,
The second island-shaped semiconductor film has a second low-concentration impurity region only under the second gate electrode,
The fourth island-shaped semiconductor film has a third low-concentration impurity region so as to overlap with a part of the fourth gate electrode;
An upper surface of the first to third low-concentration impurity regions has a smaller area than a lower surface of the low-concentration impurity region. A first n-channel having a first island-shaped semiconductor film, an insulating film provided to cover the first island-shaped semiconductor film, and a first gate electrode provided on the insulating film Type TFT,
A second n having a second island-shaped semiconductor film, the insulating film provided to cover the second island-shaped semiconductor film, and a second gate electrode provided on the insulating film An NMOS circuit having a channel-type TFT;
A p-channel TFT having a third island-shaped semiconductor film, the insulating film provided to cover the third island-shaped semiconductor film, and a third gate electrode provided on the insulating film When,
A third n having a fourth island-shaped semiconductor film, the insulating film provided to cover the fourth island-shaped semiconductor film, and a fourth gate electrode provided on the insulating film A CMOS circuit having a channel type TFT,
The first island-shaped semiconductor film has a first low-concentration impurity region only between one of the channel formation region and the source region or between the channel formation region and the drain region,
The second island-shaped semiconductor film has a second low-concentration impurity region only under the second gate electrode,
The fourth island-shaped semiconductor film has a third low-concentration impurity region so as to overlap with a part of the fourth gate electrode;
The top surface of the first to third low concentration impurity regions is narrower than the bottom surface of the low concentration impurity region. A first n-channel having a first island-shaped semiconductor film, an insulating film provided to cover the first island-shaped semiconductor film, and a first gate electrode provided on the insulating film Type TFT,
A second n having a second island-shaped semiconductor film, the insulating film provided to cover the second island-shaped semiconductor film, and a second gate electrode provided on the insulating film An NMOS circuit having a channel-type TFT;
A p-channel TFT having a third island-shaped semiconductor film, the insulating film provided to cover the third island-shaped semiconductor film, and a third gate electrode provided on the insulating film When,
A third n having a fourth island-shaped semiconductor film, the insulating film provided to cover the fourth island-shaped semiconductor film, and a fourth gate electrode provided on the insulating film A CMOS circuit having a channel type TFT,
The first island-shaped semiconductor film has a first low-concentration impurity region only between one of the channel formation region and the source region or between the channel formation region and the drain region,
The second island-shaped semiconductor film has a second low-concentration impurity region only under the second gate electrode,
The fourth island-shaped semiconductor film has a third low-concentration impurity region so as to overlap with a part of the fourth gate electrode;
An upper surface of the first to third low concentration impurity regions has a larger area than a lower surface of the low concentration impurity region. A first n-channel having a first island-shaped semiconductor film, an insulating film provided to cover the first island-shaped semiconductor film, and a first gate electrode provided on the insulating film Type TFT,
A second n having a second island-shaped semiconductor film, the insulating film provided to cover the second island-shaped semiconductor film, and a second gate electrode provided on the insulating film An NMOS circuit having a channel-type TFT;
A p-channel TFT having a third island-shaped semiconductor film, the insulating film provided to cover the third island-shaped semiconductor film, and a third gate electrode provided on the insulating film When,
A third n having a fourth island-shaped semiconductor film, the insulating film provided to cover the fourth island-shaped semiconductor film, and a fourth gate electrode provided on the insulating film A CMOS circuit having a channel type TFT,
The first island-shaped semiconductor film has a first low-concentration impurity region only between one of the channel formation region and the source region or between the channel formation region and the drain region,
The second island-shaped semiconductor film has a second low-concentration impurity region only under the second gate electrode,
The fourth island-shaped semiconductor film has a third low-concentration impurity region so as to overlap with a part of the fourth gate electrode;
An upper surface of the first to third low concentration impurity regions is wider than a lower surface of the low concentration impurity region. Semiconductor equipment as claimed in any one of claims 1 to 4, wherein a is a liquid crystal display device. Semiconductor equipment as claimed in any one of claims 1 to 4, wherein a is a light emitting device. The semiconductor device according to claim 1, wherein the semiconductor device is a central processing unit. Semiconductor equipment as claimed in any one of claims 1 to 7, a video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, portable information terminal or an electronic plaything, A semiconductor device characterized by the above. First through fourth island-shaped semiconductor film over the insulation surface is formed,
An insulating film is formed to cover the first to fourth island-shaped semiconductor films ;
The insulating film through the forming the first to fourth gate electrodes of the first to the fourth island-shaped semiconductor film,
The first source region in each of the second and fourth island-shaped semiconductor film first by adding an impurity element imparting n-type, the second and fourth island-shaped semiconductor film, the drain region and forming a channel forming region,
The first, second and fourth gate electrodes, a part of the first gate electrode, and a resist provided on a part of the first island-shaped semiconductor film as a mask . 2 and impurity element imparting n-type fourth island-shaped semiconductor film, the angularly added pressure from 30 ° to 60 ° with respect to the first through fourth island-shaped semiconductor film surface first, to form a first through third lightly doped region of each of the second and fourth island-shaped semiconductor film,
Using the third gate electrode as a mask, an impurity element imparting p-type conductivity is added to the third island-shaped semiconductor film, so that a source region, a drain region, and a channel formation region are formed in the third island-shaped semiconductor film. A method for manufacturing a semiconductor device to be formed, comprising:
The first low-concentration impurity region is formed only between the channel formation region and the source region or between the channel formation region and the drain region by the resist mask,
The second low-concentration impurity region is formed only under the second gate electrode,
The method for manufacturing a semiconductor device, wherein the third low-concentration impurity region is formed so as to overlap with a part of the fourth gate electrode . The first through fourth island-shaped semiconductor film is formed over an insulating surface,
An insulating film is formed to cover the first to fourth island-shaped semiconductor films ;
Before forming the first to fourth gate electrodes of the first to the fourth island-shaped semiconductor film through the Kize' Enmaku,
Before SL first, the first as a mask and a resist provided on a portion of a part and the first island-shaped semiconductor film of the second and fourth gate electrode and the first gate electrode of the A source region, a part of the drain region of the island-shaped semiconductor film, a region to be the first low-concentration impurity region, a source region, a drain region, and a second region of the second and fourth island-shaped semiconductor films; It was added pressure from the corner of the 30 ° to 60 ° relative to the third low concentration the impurity region and a region with an impurity element imparting n-type first through fourth island-shaped semiconductor film surface,
A source region is added to each of the first, second, and fourth island-shaped semiconductor films by adding an impurity element imparting n-type to the first, second, and fourth island-shaped semiconductor films. Forming a drain region, a channel formation region, and first to third low-concentration impurity regions;
Using the third gate electrode as a mask, an impurity element imparting p-type conductivity is added to the third island-shaped semiconductor film, so that a source region, a drain region, and a channel formation region are formed in the third island-shaped semiconductor film. A method for manufacturing a semiconductor device to be formed, comprising:
The first low-concentration impurity region is formed only between the channel formation region and the source region or between the channel formation region and the drain region by the resist mask,
The second low-concentration impurity region is formed only under the second gate electrode,
The method for manufacturing a semiconductor device, wherein the third low-concentration impurity region is formed so as to overlap with a part of the fourth gate electrode . Forming first to fourth island-shaped semiconductor films on the insulating surface;
An insulating film is formed to cover the first to fourth island-shaped semiconductor films;
Forming first to fourth gate electrodes on the first to fourth island-shaped semiconductor films via the insulating film;
Using the third gate electrode as a mask, an impurity element imparting p-type conductivity is added to the third island-shaped semiconductor film, so that a source region, a drain region, and a channel formation region are formed in the third island-shaped semiconductor film. Forming,
Using the first, second and fourth gate electrodes, a part of the first gate electrode, and a resist provided on a part of the first island-shaped semiconductor film as a mask, the first island A source region, a part of the drain region, a region to be the first low-concentration impurity region, a source region, a drain region, and second and fourth regions of the second and fourth island-shaped semiconductor films. An impurity element imparting n-type to a region to be a low-concentration impurity region 3 is added at an angle of 30 ° to 60 ° with respect to the surface of the first to fourth island-shaped semiconductor films,
A channel formation region is formed in each of the first, second, and fourth island-shaped semiconductor films by adding an impurity element imparting n-type to the first, second, and fourth island-shaped semiconductor films. A method for manufacturing a semiconductor device for forming first to third low-concentration impurity regions, a source region, and a drain region,
The first low-concentration impurity region is formed only between the channel formation region and the source region or between the channel formation region and the drain region by the resist mask,
The second low-concentration impurity region is formed only under the second gate electrode,
The method for manufacturing a semiconductor device, wherein the fourth low-concentration impurity region is formed so as to overlap with a part of the fourth gate electrode. In any one of Claims 9 to 11,
The island-shaped semiconductor film forms a semiconductor film having an amorphous structure on an insulating surface;
Adding a metal element to the semiconductor film having an amorphous structure;
Crystallizing the semiconductor film by heat treatment or laser irradiation to form a semiconductor film having a crystal structure,
A method for manufacturing a semiconductor device, which is formed by patterning the semiconductor film. In claim 12,
  A method for manufacturing a semiconductor device, wherein the metal element is gettered to a source region or a drain region of the island-shaped semiconductor film. 14. The method for manufacturing a semiconductor device according to claim 13 , wherein heat treatment is performed in order to selectively remove or reduce the metal element in the semiconductor film having a crystal structure after gettering. In claim 13, a benzalkonium be irradiated with strong light to the semiconductor film having the amorphous structure to selectively remove or reduce the metal element in the semiconductor film having the gettering to crystal structure A method for manufacturing a semiconductor device.

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