JP4328045B2 - OFDM signal receiving circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to, for example, an OFDM (Orthogonal Frequency Division Multiplex) signal receiving circuit applied to a system such as a wireless LAN.
[0002]
[Prior art]
An OFDM signal is called a multicarrier system, and data is allocated to a plurality of subcarrier signals. Each subcarrier signal has information in the signal amplitude direction by QAM (Quadrature Amplitude Modulation). For this reason, the ratio of the maximum amplitude and the minimum amplitude of the signal is increased, and a large dynamic range is required for the receiving circuit. Digital signal processing such as FFT (Fast Fourier Transform) is used for OFDM signal reception processing, and ADC (Analog Digital Converter) having a sampling rate about twice the signal band is used for digitization of the received signal. It is done.
[0003]
The number of ADC sampling bits needs to be designed in accordance with the dynamic range of the received signal. However, it is technically difficult to realize a high-speed, multi-bit ADC. For this reason, it is important to use an ADC having the minimum number of bits.
[0004]
The power of signals received in wireless communication varies greatly depending on the transmission distance and the presence or absence of obstacles. For example, a wireless LAN defined by IEEE802.11a requires that it can cope with a large reception power difference of −82 dBm to −30 dBm. For this reason, in general, a variable gain amplifier called an AGC (Automatic Gain Control) amplifier is used to absorb variations in received power, adjust to a convenient signal amplitude level, and then sampled by the ADC.
[0005]
FIG. 10 schematically shows a configuration of a conventional OFDM signal receiving circuit. This receiving circuit uses, for example, antenna switching diversity. The first and second antennas 11 and 12 are connected to the RF circuit 14 via the antenna switching circuit 13. The RF circuit 14 converts the received signal into an intermediate frequency (IF). An AGC circuit 15 is connected to the output terminal of the RF circuit 14. The AGC circuit 15 has an AGC amplifier (not shown), and adjusts the amplification degree of the AGC amplifier according to a control signal supplied from an AGC signal generation circuit 20 described later. The output signal of the AGC circuit 15 is supplied to the IF circuit 16. The IF circuit 16 converts the intermediate frequency into baseband. The output signal of the IF circuit 16 is supplied to the IQ detection circuit 17. The IQ detection circuit 17 is a so-called quadrature demodulator, and detects I and Q signals from baseband signals.
[0006]
On the other hand, the output signal of the RF circuit 14 is supplied to an RSSI (Received Signal Strength Indicator) circuit 18. The RSSI circuit 18 measures the received electric field intensity from the output signal of the RF circuit 14. The measured received electric field strength is converted to dB (decibel). An output signal of the RSSI circuit 18 is supplied to an AGC signal generation circuit 20 via an LPF (Low Pass Filter) 19. The AGC signal generation circuit 20 includes, for example, an ADC 21, an AGC correction circuit 22, and a DAC (Digital Analog Converter) 23.
[0007]
The output signal of the LPF 19 is supplied to the AGC correction circuit 22 via the ADC 21. The AGC correction circuit 22 calculates an AGC correction value from the output signal of the LPF 19. This correction value is converted into an analog signal by the DAC 23 and supplied to the AGC circuit 15. In this way, the AGC circuit 15 is controlled according to the power of the received signal.
[0008]
[Problems to be solved by the invention]
By the way, the control system of the AGC circuit using the output signal of the RSSI detection circuit 18 for measuring the received electric field strength has the following problems.
[0009]
Since the RSSI circuit 18 is generally provided in the IF stage, it integrates the power of a broadband signal. Therefore, since the component outside the desired band increases the noise floor, it is difficult to accurately measure the received electric field strength when the received power is low.
[0010]
The RF circuit 14 extracts a signal in a desired frequency band using, for example, a SAW (Surface Acoustic Wave) filter. However, in a wireless LAN system in which a channel frequency is set every 20 MHz specified by IEEE 802.11a, it is difficult to sufficiently eliminate transmission signals of adjacent channels. Therefore, the RSSI circuit 18 sometimes measures the received electric field strength together with such a signal outside the desired band.
[0011]
Furthermore, the received power is not constant during the measurement period of the received electric field strength. For this reason, in order to increase the measurement accuracy, a smoothing process using an LPF having a sufficiently long time constant is required. However, the preamble period used in a wireless LAN or the like is very short, and it is difficult to complete the AGC operation within this period.
[0012]
Specifically, in the wireless LAN system, in order to determine the AGC control signal, it is possible to use the preamble portion added to the head of the packet. This preamble portion has a known transmission pattern and has a period of 16 μsec. During this preamble period, a time of 8 μsec in which the amplitude characteristic is almost stable can be used for the measurement of the received electric field strength. However, actually, it is necessary to perform processing such as AFC (Automatic Frequency Control) during the preamble period. For this reason, the period that can be used for the measurement of the received electric field strength is only 4 μsec.
[0013]
Moreover, the wireless LAN system performs diversity reception using two antennas as described above in order to reduce the influence of fading due to multipath or the like. For this reason, the measurement time per antenna is only 2 μsec.
[0014]
As described above, the measurement using the RSSI detection circuit needs to use the LPF in order to smooth the amplitude fluctuation of the preamble pattern itself. For this reason, the measurement error due to the residual ripple and the time required for smoothing are in a trade-off relationship, and in order to perform measurement at 2 μsec, there is a possibility that the residual ripple of ± 0.5 dB may cause a measurement error.
[0015]
Further, as shown in FIG. 10, in order to correct the nonlinearity of the characteristics of the RSSI detection circuit 18 and the AGC circuit 15 and the variation of the component characteristics, the detection result of the RSSI detection circuit 18 is sampled by the ADC 21, and the AGC correction circuit 22 is sampled. After the correction by digital processing, the control signal for the AGC circuit 15 is generated by the DAC 23. However, even in this configuration, the ADC 21 and the DAC 23 vary in nonlinear characteristics and component characteristics, and it is difficult to obtain sufficient measurement accuracy.
[0016]
On the other hand, a method is conceivable in which received power is measured by digital processing without using an RSSI detection circuit, and a control signal for the AGC circuit is generated based on the measurement result. In this case, the residual ripple can be completely removed from the amplitude fluctuation of the preamble pattern by performing the moving average process of the received power. Considering the periodicity of the preamble pattern, a moving average process of 400 nsec is necessary. This requires that the received signal be sampled by the ADC.
[0017]
However, as described above, the received signal has a large dynamic range. For this reason, it is necessary to use an ADC having a large number of bits in order to accurately sample the received signal. That is, assuming that the received field intensity is measured using, for example, a 10-bit ADC, there is only a dynamic range of about 30 dB. For this reason, it is necessary to use an ADC having a large circuit scale of 10 bits or more in order to sample a received signal having a dynamic range of 50 dB or more in one operation as in a wireless LAN. In addition, measurement by digital processing requires a processing time of about 1 μsec for the entire processing such as ADC, LPF, and moving average. For this reason, if the measurement is repeated a plurality of times using an ADC with a small number of bits, the measurement cannot be completed within 2 μsec.
[0018]
As described above, the conventional AGC circuit adjustment method using the RSSI detection circuit has a sufficient dynamic range, but it has been difficult to obtain sufficient accuracy in a short time. Further, the AGC circuit adjustment method by digital processing cannot adjust the amplitude of the input signal with high accuracy and high speed with an ADC having a small number of bits. For this reason, it is necessary to design in advance with a margin in the number of bits of the ADC, and there is a problem that the circuit scale of the ADC becomes large.
[0019]
The present invention has been made to solve the above-described problems, and the object of the present invention is to be able to measure the received electric field strength with high accuracy in a short time and to reduce the adjustment error of the AGC circuit. It is an object of the present invention to provide a possible OFDM signal receiving circuit.
[0020]
[Means for Solving the Problems]
  Of the present inventionAccording to one aspectThe OFDM signal receiving circuit isAn automatic gain control circuit that varies the amplification degree of the reception signal, a measurement circuit that measures the electric field strength of the reception signal, and a first adjustment that adjusts the amplification degree of the automatic gain control circuit according to the output signal of the measurement circuit A signal generation circuit for generating a control signal, a demodulation circuit for demodulating a signal output from the automatic gain control circuit adjusted according to the first control signal into a baseband signal, and an output signal of the demodulation circuit An analog-to-digital converter that converts the signal into a digital signal; and a power calculation circuit that calculates power from the output signal of the analog-to-digital converter and supplies the power to the signal generation circuit. Generating a second control signal for adjusting an amplification degree of the automatic gain control circuit according to the power supplied from the calculation circuit; the signal generation circuit having a plurality of reference voltages; A plurality of comparison circuits for decomposing the output signal of the path into a plurality of levels; a level shift circuit to which the output signals of the plurality of comparison circuits are supplied; and a conversion circuit for converting the output signal of the power calculation circuit into a decibel value; A switch circuit for supplying an output signal of the level shift circuit to a first input terminal and an output signal of the conversion circuit to a second input terminal, and sequentially switching the first and second input terminals; An output signal of the switch circuit is supplied, a second correction circuit that generates the first and second control signals, and the first and second control signals supplied from the second correction circuit are analog. And a digital / analog converter for converting the signal into a signal.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
(Reference example)
  FIG. 1 illustrates the present invention.Reference exampleThe same parts as those in FIG. 10 are denoted by the same reference numerals, and different parts will be described.
[0023]
In FIG. 1, an RSSI detection circuit 18 is connected to the output terminal of the RF circuit 14. The connection position of the RSSI detection circuit 18 is not limited to the output end of the RF circuit 14 and may be another part of the intermediate frequency stage. The RSSI detection signal output from the RSSI detection circuit 18 is supplied to the AGC signal generation circuit 31 via the LPF 19. The AGC signal generation circuit 31 includes an RSSI correction circuit 32, a level shift circuit 33, a dB conversion circuit 34, and a switch circuit 35 in addition to the ADC 21, the AGC correction circuit 22, and the DAC 23.
[0024]
The RSSI correction circuit 32 corrects the nonlinearity of the RSSI amplifier used in the RSSI detection circuit 18. That is, the RSSI correction circuit 32 linearly corrects the digitized RSSI detection signal output from the ADC 21. The output signal of the RSSI correction circuit 32 is supplied to the level shift circuit 33 and shifted to a predetermined level. An output signal of the level shift circuit 33 is supplied to one input terminal of the switch circuit 35. An output signal of a dB conversion circuit 34 described later is supplied to the other input terminal of the switch circuit 35. The switch circuit 35 switches the input signal every 1 μsec, for example, when adjusting the AGC circuit 15. That is, when adjusting the AGC circuit 15, the switch circuit 35 first selects the output signal of the level shift circuit 33, and after 1 μsec has elapsed, selects the output signal of the dB conversion circuit 34. An output signal of the switch circuit 35 is supplied to the AGC correction circuit 22.
[0025]
On the other hand, baseband I and Q signals output from the IQ detection circuit 17 are supplied to ADCs 36 and 37, respectively. The I and Q signals sampled by the ADCs 36 and 37 are supplied to the reception power calculation circuit 38. The received power calculation circuit 38 calculates the power of the baseband signal from the sampled I and Q signals. That is, the received power calculation circuit 38 is configured by, for example, a digital filter 39 and a power integration processing circuit 40. The digital filter 39 extracts a desired band signal component from the I and Q signals. The extracted I and Q signals are supplied to the power integration processing circuit 40. The power integration processing circuit 40 performs a moving average process on the I and Q signals to calculate power. The power calculated by the power integration processing circuit 40 is supplied to the dB conversion circuit 34.
[0026]
The dB conversion circuit 34 is configured by a ROM, for example. The ROM stores a plurality of dB converted values obtained by converting the integrated power into dB. These dB converted values are read out corresponding to the power supplied from the power integration processing circuit 40. The signal output from the dB conversion circuit 34 is supplied to the other input terminal of the switch circuit 35.
[0027]
In FIG. 1, the configuration of the data processing system that processes the data in the received signal is omitted.
[0028]
FIG. 2 shows an example of the digital filter 39. The digital filter 39 is constituted by a known FIR (Finite Impulse Response) filter, for example. That is, the digital filter 39 includes a plurality of delay elements (D) 51-1, 51-2 to 51-n-1, 51-n that constitute a shift register, and a plurality of multipliers 52-0, 52-1 to 52-n and an adder 53. The multipliers 52-0 and 52-1 to 52-n are connected to the input terminals and output terminals of the delay elements 51-1 to 51-n, and are used as input signals and output signals of the delay elements 51-1 to 51-n. Weighting is performed by multiplying predetermined values W0 to Wn. The adder 53 extracts signals in a desired band by sequentially adding the output signals of the multipliers 52-0 and 52-n.
[0029]
FIG. 3 shows an example of the power integration processing circuit 40. This power integration processing circuit 40 includes an arithmetic circuit 56 that calculates the sum of squares of I and Q signals, and a plurality of delay elements (D) 54-1 and 54-2 to 54- connected in series that constitute, for example, a shift register. n and an adder 55. The output signal of the arithmetic circuit 56 is supplied to the delay element 54-1. The input terminals and output terminals of the delay elements 54-1 to 54-n are connected to the adder 55. The adder 55 calculates the moving average of the power values obtained from the I and Q signals by sequentially adding the input signals and output signals of the delay elements 51-1 to 51-n. The power calculated in the power integration processing circuit 40 in this way is supplied to the dB conversion circuit 34 shown in FIG.
[0030]
Next, a schematic operation of the circuit shown in FIG. 1 will be described.
[0031]
The RSSI detection circuit 18 is characterized by a wide dynamic range for input signals. For this reason, if high accuracy is not required for the measurement value, the measurement can be completed with a smoothing process in a short time. However, since the RSSI detection circuit 18 also detects a signal outside the desired band, the noise floor increases. For this reason, it is difficult to generate a highly accurate AGC control signal based on the output signal of the RSSI detection circuit 18.
[0032]
The received power calculation circuit 38 calculates the integrated power by the power integration processing circuit 40 from the I and Q digital signals output from the ADCs 36 and 37 and passed through the digital filter 39. Therefore, the received power can be measured with high accuracy, and the AGC correction circuit 22 can generate a highly accurate AGC control signal based on this measurement value. However, the ADCs 36 and 37 cause sampling errors when the level of the input signal is not suitable for conversion. For this reason, in the power integration processing circuit 40, the error of the integrated power becomes large.
[0033]
  Therefore,Reference exampleFirst, the first control signal is generated by using the RSSI detection circuit 18 and the AGC signal generation circuit 31. The AGC circuit 15 is adjusted by the first control signal and set so that the baseband signal is within the conversion range of the ADCs 36 and 37. Next, a second control signal is generated using the received power calculation circuit 38 and the AGC signal generation circuit 31. The AGC circuit 15 is accurately adjusted by the second control signal.
[0034]
FIG. 4 shows the adjustment timing of the AGC circuit 15. As shown in FIG. 4, the AGC circuit 15 is adjusted in a period in which the power of the received signal is relatively stable in the preamble section. That is, the received power of the first and second antennas 11 and 12 is measured within the period of 4 μsec at the beginning of the preamble portion, and the AGC circuit 15 is adjusted. Therefore, the adjustment time of the AGC circuit 15 that can be used per antenna is 2 μsec, and AGC adjustment using the first and second control signals is performed within the time of 2 μsec.
[0035]
Next, the adjustment operation of the ACG circuit 15 related to one antenna will be specifically described.
[0036]
When adjusting the AGC circuit 15, the switch circuit 35 first selects the output signal of the level shift circuit 33. In this state, the RF circuit 14 converts the high frequency signal supplied from the antenna switching circuit 13 into an intermediate frequency. The output signal of the RF circuit 14 is supplied to the AGC circuit 15 and also to the RSSI circuit 18. The AGC circuit 15 varies the amplification factor for the received signal based on the control signal supplied from the AGC signal generation circuit 31, and controls the extracted baseband signal to have a desired amplitude. The intermediate frequency signal output from the AGC circuit 15 is supplied to the IF circuit 16.
[0037]
The RSSI circuit 18 performs envelope detection on the intermediate frequency signal and converts the signal intensity into a signal converted into a dB value. The output signal of the RSSI circuit 18 is smoothed by the LPF 19 having an appropriate time constant. The output signal of the LPF 19 is converted into a digital signal by the ADC 21 and supplied to the RSSI correction circuit 32. The signal whose nonlinearity is corrected in the RSSI correction circuit 32 is shifted by a predetermined level by the level shift circuit 33 and supplied to the AGC correction circuit 22 via the switch circuit 35. The AGC correction circuit 22 corrects the nonlinearity of the AGC amplifier used in the AGC circuit 15. That is, the AGC correction circuit 22 corrects the output signal to the DAC 23 so that the amplification degree of the AGC circuit 15 matches the output of the switch circuit 35. This correction value is changed to an analog signal by the DAC 23 and supplied to the AGC circuit 15 as a first control signal. In this way, the AGC circuit 15 is controlled according to the first control signal.
[0038]
Next, the received power calculation circuit 38 calculates the integrated power after waiting for the time when the gain adjustment of the AGC circuit 15 by the first control signal is stabilized. At this time, the switch circuit 35 selects the other input terminal.
[0039]
In this state, the IF circuit 16 changes the intermediate frequency signal output from the AGC circuit 15 into a baseband signal. This baseband signal is supplied to the IQ detection circuit 17. The IQ detection circuit 17 performs quadrature demodulation on the input signal and outputs baseband I and Q signals. The I and Q signals are supplied to ADCs 36 and 37, respectively. The output signal level of the AGC circuit 15 is set within the conversion range of the ADCs 36 and 37 by the first control signal. Therefore, the ADCs 36 and 37 can reliably sample the I and Q signals. In this manner, the ADCs 36 and 37 output digital signals having the number of bits necessary for reception processing. This digital signal is supplied to the digital filter 39. The digital filter 39 extracts only the frequency band component of the reception target channel from the input digital signal by the above-described operation. The extracted baseband signal is supplied to the power integration processing circuit 40. The power integration processing circuit 40 calculates the power of the baseband signal from the sum of squares of the I and Q signal components by the above-described operation, and calculates the power obtained by smoothing the received power by performing a moving average process.
[0040]
The power calculated by the power integration processing circuit 40 is supplied to the dB conversion circuit 34 of the AGC signal generation circuit 31. The dB conversion circuit 34 reads out and outputs a dB converted value corresponding to the supplied power. The electric power converted into dB is supplied to the AGC correction circuit 22 via the switch circuit 35. The AGC correction circuit 22 calculates an AGC correction value according to the supplied signal. This correction value is calculated based on the received power precisely measured by the received power calculation circuit 38. Therefore, the value is more accurate than the correction value calculated based on the output signal of the RSSI circuit 18 described above. This correction value is converted into an analog signal by the DAC 23 and supplied to the AGC circuit 15 as a second control signal. The AGC circuit 15 controls the gain of the AGC amplifier more accurately based on the second control signal.
[0041]
As described above, the wireless LAN system adjusts the AGC circuit 15 during the preamble period when the power of the reception signal is stable, and fixes the AGC circuit 15 to the adjusted state during the data reception period when the power fluctuates. .
[0042]
  Reference exampleHowever, since antenna switching is not a gist, a specific description is omitted. However, the relationship between antenna switching and AGC circuit adjustment may be as follows. For example, as shown in FIG. 4, first, the first antenna 11 is selected and the AGC circuit 15 is adjusted, and then the second antenna 12 is selected and the AGC circuit 15 is adjusted. At this time, the second control signal corresponding to the first antenna 11 is stored in the memory 41, for example. The memory 41 is provided between the DAC 23 and the AGC circuit 15, for example. After selecting the second antenna 12 and adjusting the AGC circuit 15, the first or second antenna 12 is switched according to the received electric field strength. In this case, for example, when the received electric field strength of the first antenna 11 is stronger than that of the second antenna 12, the first antenna 11 is selected. Accordingly, the second control signal stored in the memory 41 may be read and the AGC circuit 15 may be adjusted according to the second control signal.
[0043]
When the second antenna 12 is selected according to the received electric field strength, the AGC circuit 15 is adjusted according to the second control signal output from the DAC 23.
[0044]
  the aboveReference exampleAccording to the above, when adjusting the AGC circuit 15, first, the first control signal is generated by using the RSSI detection circuit 18 and the AGC signal generation circuit 31, and the AGC circuit 15 is adjusted by the first control signal. Thus, the baseband signal level is set so as to be within the conversion range of the ADCs 36 and 37, and then the second control signal generated using the reception power calculation circuit 38 and the AGC signal generation circuit 31 is used. The AGC circuit 15 is adjusted. For this reason, the received electric field strength can be measured with high accuracy by using the advantages of the RSSI detection circuit 18 having a large dynamic range and the received power calculation circuit 38 that can accurately calculate the received power. And can be adjusted in a short time.
[0045]
In addition, by adjusting the AGC circuit 15 using the first control signal, the number of bits of the ADCs 36 and 37 can be reduced to the minimum necessary number. Therefore, there is an advantage that the circuit scale of the ADCs 36 and 37 can be reduced.
[0046]
  The AGC signal generation circuit 31 includes an ADC 21 and an RSSI correction circuit.32have. For this reason, the nonlinearity of the signal output from the RSSI circuit 18 can be corrected by digital processing. Furthermore, it becomes easy to correct the characteristic variation for each component as well.
[0047]
(No.1Embodiment)
  FIG. 5 shows the first of the present invention.1The embodiment of is shown. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.
[0048]
For example, a dynamic range in which power can be measured from signals sampled by 10-bit ADCs 36 and 37 is about 60 dB in principle. However, when the amplitude of the input signal is small, the power cannot be measured with high accuracy due to the influence of the quantization error. Therefore, in reality, only a narrow dynamic range of about 30 dB can be measured.
[0049]
  So, first1In this embodiment, the output signal of the RSSI detection circuit 18 is discriminated by several stages of comparators so that it can be decomposed into a narrower range than the narrow dynamic range, for example, about 20 dB. A first control signal is generated in accordance with the signal in the determined range, and the AGC circuit 15 is adjusted by the first control signal, so that the received power calculation circuit 38 can accurately measure the I and Q signals. Is generated.
[0050]
  That is,Reference exampleThe AGC signal generation circuit 31 has an ADC 21 and an RSSI correction circuit 22. On the other hand,1The AGC signal generation circuit 31 in this embodiment has a comparison circuit 61 instead of the ADC 21 and the RSSI correction circuit 22. The comparison circuit 61 adjusts the output signal of the RSSI detection circuit 18 so that it falls within the measurement range of the received power calculation circuit 38.
[0051]
FIG. 6 shows an example of the comparison circuit 61. The comparison circuit 61 is composed of, for example, a plurality of comparators 61-1 to 61-4. The non-inverting input terminals of the comparators 61-1 to 61-4 are connected in common, and different reference potentials Vref1 to Vref4 are supplied to the inverting input terminals, respectively. The output terminals of the comparators 61-1 to 61-4 are supplied to the level shift circuit 33, respectively.
[0052]
  First1In the embodiment, the adjustment operation of the AGC circuit 15 is as follows.Reference exampleIt is the same. That is, first, a first control signal is generated using the AGC signal generation circuit 31 including the RSSI detection circuit 18 and the comparison circuit 61, and the AGC circuit 15 is adjusted by the first control signal. Thus, the baseband signal level is set so as to be within the conversion range of the ADCs 36 and 37. Thereafter, the AGC circuit 15 is adjusted using the second control signal generated by using the received power calculation circuit 38 and the AGC signal generation circuit 31.
[0053]
  First1According to this embodiment, the AGC signal generation circuit 31 is provided with the comparison circuit 61, the level of the signal supplied from the RSSI detection circuit 18 is decomposed into a narrow range by the comparison circuit 61, and the output signal of the comparison circuit 61 is The AGC circuit 15 is adjusted by the first control signal generated according to the above. For this reason, it is possible to generate I and Q signals that can be accurately measured by the received power calculation circuit 38. Therefore, since the power of the received signal can be measured with high accuracy, the AGC circuit 15 can be adjusted accurately.
[0054]
  Moreover, the comparison circuit 61Reference exampleSince the circuit scale is smaller than those of the ADC 21 and the RSSI correction circuit 22, there is an advantage that the occupied area in the chip can be reduced.
[0055]
(No.2Embodiment)
  7 and 8 show the first aspect of the present invention.2The embodiment of is shown. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.
[0056]
The dynamic range of the reception electric field strength assumed in the wireless LAN is as wide as −82 dBm to −30 dBm. On the other hand, since the RF circuit 14 amplifies extremely weak radio waves, a large amplification degree is set assuming operation at the minimum electric field strength. When a signal with a large electric field strength is supplied by the RF circuit 14 having such a large amplification degree, the signal is saturated in the circuits after the RF circuit 14. For this reason, the signal supplied to the AGC circuit 15 is distorted, and it becomes difficult to control the amplitude of the received signal only by the AGC circuit 15.
[0057]
  So, first2In this embodiment, distortion is suppressed by adjusting the level of the received signal at the stage of the RF circuit in accordance with the power of the received signal measured by the RSSI detection circuit 18 and the received power calculation circuit 38.
[0058]
That is, in FIG. 7, the RF circuit 71 includes an amplifier 71-1 that can change the amplification degree as shown in FIG. A threshold determination circuit 72 is connected between the switch circuit 35 and the AGC correction circuit 22. As shown in FIG. 8B, the threshold determination circuit 72 is configured by, for example, a comparator 72-1. A signal supplied from the switch circuit 35 is supplied to the non-inverting input terminal of the comparator 72-1, and a predetermined threshold value Wth is supplied to the inverting input terminal. The comparator 72-1 outputs a third control signal when the power of the reception signal supplied from the switch circuit 35 exceeds the threshold value Wth. This third control signal is supplied to the amplifier 71-1 of the RF circuit 71. The amplification degree of the amplifier 71-1 is lowered according to the third control signal. For this reason, in the circuit after the RF circuit 71, distortion is prevented from occurring in the signal.
[0059]
The third control signal may be supplied not only to the amplifier 71-1 but also to the IF circuit 16 as indicated by a broken line in FIG. If the IF circuit 16 is provided with an amplifier whose amplification degree can be changed in the same manner as the amplifier 71-1, and this amplifier is controlled by the third control signal, the occurrence of further distortion can be prevented.
[0060]
  Above2According to the embodiment, the threshold determination circuit 72 is provided in the AGC signal generation circuit 31, and the threshold determination circuit 72 determines the power of the reception signal measured by the RSSI detection circuit 18 and the reception power calculation circuit 38. When this power exceeds the threshold value Wth, a third control signal is generated, and the RF signal 71 and IF circuit 16 reduce the level of the received signal. For this reason, even when a signal with a large electric field strength is received, the occurrence of distortion can be suppressed. Therefore, the received power can be measured accurately.
[0061]
  FIG.2The deformation | transformation of this embodiment is shown. First2In the embodiment, the RF circuit 71 has an amplifier having a variable amplification degree. On the other hand, in FIG. 9, the RF circuit 71 has an amplifier 71-3 and an attenuator 71-4 connected to the output terminal of the amplifier 71-3. A third control signal is supplied to the attenuator 71-4. The number of attenuators is not limited to one, and a plurality of stages can be provided.
[0062]
When the third control signal is supplied from the threshold determination circuit 72, the attenuator 71-4 attenuates the output signal of the amplifier 71-3. For this reason, even when a signal with a large electric field strength is received, the occurrence of distortion can be suppressed. Therefore, the received power can be measured accurately.
[0063]
  The present invention is the above-mentioned first.2Embodiments ofReference exampleThe case where it was applied to was explained. However, it is not limited to this.2The embodiment shown in FIG.1It is also possible to apply to the embodiment. That is, in FIG. 5, the RF circuit 17 is replaced with the RF circuit 71, and a threshold determination circuit 72 is connected between the switch circuit 35 and the AGC correction circuit 22, and the RF circuit 71 is controlled by the output signal of the threshold determination circuit 72. To do. Further, the IF circuit 16 may be controlled by the output signal of the threshold determination circuit 72.
[0064]
Of course, various modifications can be made without departing from the scope of the present invention.
[0065]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an OFDM signal receiving circuit capable of measuring the received electric field intensity with high accuracy in a short time and reducing the adjustment error of the AGC circuit.
[Brief description of the drawings]
FIG. 1 of the present inventionReference exampleFIG.
FIG. 2 is a circuit diagram showing an example of a digital filter shown in FIG.
FIG. 3 is a circuit diagram showing an example of a power integration processing circuit shown in FIG. 1;
[Fig. 4]Reference exampleThe wave form shown in order to explain operation of.
FIG. 5 shows the first of the present invention.1The block diagram which shows embodiment of this.
6 is a circuit diagram showing an example of the comparison circuit shown in FIG. 5;
FIG. 7 shows the first of the present invention.2The block diagram which shows embodiment of this.
8A is a circuit diagram illustrating an example of an RF circuit illustrated in FIG. 7, and FIG. 8B is a circuit diagram illustrating an example of a threshold determination circuit illustrated in FIG.
FIG. 92The circuit diagram which shows the deformation | transformation of embodiment.
FIG. 10 is a block diagram schematically showing a configuration of a conventional OFDM signal receiving circuit.
[Explanation of symbols]
    11, 12 ... first and second antennas,
    13: Antenna switching circuit,
    14, 71 ... RF circuit,
    15 ... AGC circuit,
    16 ... IF circuit,
    17 ... IQ detection circuit,
    18 ... RSSI circuit,
    21 ... ADC,
    22 ... AGC correction circuit,
    23 ... DAC,
    31 ... AGC signal generation circuit,
    32. RSSI correction circuit,
    33 ... Level shift circuit,
    34 ... dB conversion circuit,
    35 ... Switch circuit,
    36, 37 ... ADC,
    38 ... Received power calculation circuit,
    39: Digital filter,
    40. Power integration processing circuit,
    61 ... comparison circuit,
    71-1 ... an amplifier,
    72... Threshold determination circuit,
    71-3... Amplifier
    71-4: Attenuator.

Claims (1)

An automatic gain control circuit for varying the amplification of the received signal;
  A measurement circuit for measuring the electric field strength of the received signal;
  A signal generation circuit for generating a first control signal for adjusting an amplification degree of the automatic gain control circuit according to an output signal of the measurement circuit;
  A demodulation circuit for demodulating a signal output from the automatic gain control circuit adjusted according to the first control signal into a baseband signal;
  An analog / digital converter for converting the output signal of the demodulation circuit into a digital signal;
  A power calculation circuit that calculates power from the output signal of the analog-digital converter and supplies the power to the signal generation circuit;
  The signal generation circuit generates a second control signal for adjusting an amplification degree of the automatic gain control circuit according to the power supplied from the power calculation circuit;
  The signal generation circuit has a plurality of reference voltages, and a plurality of comparison circuits that decompose the output signal of the measurement circuit into a plurality of levels;
  A level shift circuit to which output signals of the plurality of comparison circuits are supplied;
  A conversion circuit for converting the output signal of the power calculation circuit into a decibel value;
  An output signal of the level shift circuit is supplied to a first input terminal, an output signal of the conversion circuit is supplied to a second input terminal, and a switch circuit that sequentially switches the first and second input terminals; A second correction circuit which is supplied with an output signal of the switch circuit and generates the first and second control signals;
  An OFDM signal receiving circuit comprising: a digital-to-analog converter that converts the first and second control signals supplied from the second correction circuit into analog signals.

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