JP4327533B2 - Arithmetic processing program, arithmetic processing method, and arithmetic processing apparatus - Google Patents

Description

  The present invention relates to an arithmetic processing program, an arithmetic processing method, and an arithmetic processing device for translating a polynomial operation included in a source program.

  Conventionally, when executing a multinomial operation described in a source program using a hardware instruction using a compiler, the operation is performed sequentially from left to right according to the priority order of the operators described in the multinomial operation. It was expanded to the instruction sequence to do.

For example, when there is a 16-byte binary = 8-byte binary * 2-byte binary * 4-byte binary * 2-byte binary shown in FIG. 4A as a polynomial operation, a 32-bit (4 bytes) CPU In this case, the calculation (multiplication) between 32 bits (4 bytes) can be performed at once, and if it exceeds this, it is necessary to divide, so the multiplications shown in (1) to (3) in FIG. 4 are expanded into hardware instructions as shown in (1) to (3) of FIG.

For this reason,
4 (b) (1) requires two multiplications FIG. 4 (b) (2) requires three multiplications FIG. 4 (b) (3) four times In other words, a total of 9 multiplications (multiplication by hardware instructions) are necessary.

  Conventionally, as shown in (a) of FIG. 4 above, since the polynomial operation is expanded into hardware instructions in order from the left to the right, the number of hardware instructions to be expanded increases, so that There was a problem that it could not be executed.

  In the present invention, in order to solve these problems, the operation sorting means 8 sorts the operations in the polynomial operation included in the source program in ascending order of the number of digits, and the dividing means 9 sorts the head of the polynomial operation after sorting in ascending order. When generating hardware instructions that are operated in order, the hardware instructions are divided into ranges that do not exceed when the number of digits of hardware instructions of the device to be executed is exceeded, and the object generation means 11 calculates hardware in order from the beginning of the multinomial operation When an instruction is generated or divided, a hardware instruction is generated for each operation after division.

  Also, the combination selection means 10 selects two operations of the combination having the smallest number of digits of the operation result among the operations in the polynomial operation included in the source program, or the number of digits of the operation result of the two selected operations. And, when selecting two operations of the combination having the smallest number of digits of the operation result among the remaining operations and generating the hardware instruction to perform the operation for the selected operation set, the dividing unit 9 When the number of digits of the hardware instruction of the device to be executed is exceeded, it is divided into a range that does not exceed, and when the object generation means 11 generates or divides the hardware instruction for calculating in order from the beginning of the multinomial operation, A hardware instruction is generated for each operation.

  Therefore, when expanding a multinomial operation to a hardware instruction at compile time, it is sorted into the hardware instruction after sorting in ascending order of the number of digits of the multinomial operation, or from the combination that minimizes the operation result including intermediate results. By expanding to hardware instructions, it is possible to minimize the number of hardware instructions that execute a multinomial operation, or to suppress the expansion of instructions that require processing time, thereby improving the execution speed.

  In the present invention, since the number of hardware instructions for executing a polynomial operation at the time of compilation is expanded to a minimum, the execution speed of the polynomial operation appearing in the source program can be improved.

  In the present invention, when a multinomial operation is expanded into a hardware instruction at the time of compilation, the operation is sorted into the hardware instruction after the number of digits of the multinomial operation is reduced, or the operation result of the operation including the intermediate result is minimized. By expanding the hardware instructions in order from the combination, the number of hardware instructions that execute multinomial operations is minimized, or the expansion of instructions that require processing time is suppressed, and the execution speed is improved. .

  FIG. 1 shows a system configuration diagram of the present invention.

  In FIG. 1, a compiler 1 is a computer that executes a program to compile (translate) a source program 2 to generate an executable object program 3. Here, a lexical analysis unit 2, It comprises a syntax analysis means 3, a semantic analysis means 4, an optimization means 5, an object generation means 11, and the like.

  The lexical analysis means 2 is a known means for reading the source program 2 to be compiled and analyzing the lexical of the source program 2.

  The syntax analysis means 3 is a known means for analyzing the syntax (structure) of the source program 2 based on the result of the lexical analysis of the source program 2 by the lexical analysis means 2.

  The semantic analysis means 4 analyzes the meaning of the source program 2 analyzed by the syntax analysis means 3, and is a known means.

  The optimization means 5 performs optimization (optimization such as execution of an object program in an executable format or effective use of registers) based on the result analyzed by the semantic analysis means 4 In this example, the branch optimization unit 6 and the operation optimization unit 7 are included.

  The branch optimization means 6 optimizes the branch of the source program 2 and is a known means.

  The operation optimizing means 7 relates to the present invention and is intended to optimize the number of hardware instructions when compiling a multinomial operation. The operation optimizing means 8, the dividing means 9, The combination selection means 10 and the like (which will be described later with reference to FIGS. 2 and 3).

  The arithmetic sorting means 8 sorts the multiple arithmetic operations in ascending order of digits (described later with reference to FIG. 2).

  The dividing means 9 divides a multinomial operation into hardware instructions when it exceeds the number of digits to be calculated by the hardware (for example, divided into upper 4 bytes and lower 4 bytes) (FIG. 2). And will be described later with reference to FIG.

  The combination selection means 10 selects a combination with a small number of digits in the polynomial operation (described later with reference to FIG. 3).

  The object generation means 11 generates an object program 3 in an executable format of the source program.

  The source program 2 is a source program to be compiled (translated).

  The object program 3 is an executable program after being compiled.

  Next, in accordance with the order of the flowchart of FIG. 2B, the procedure for sorting the hardware operations in ascending order of the number of digits and expanding them into hardware instructions in order and minimizing the number of hardware instructions will be described in detail. To do.

  FIG. 2 is an explanatory diagram (part 1) of the present invention.

FIG. 2A shows an example of a polynomial operation. Here, the following polynomial operation shown: 16 bytes binary = 8 bytes binary * 2 bytes binary * 4 bytes binary * 2 bytes binary
= A * b * c * d
(A represents an arbitrary numerical value expressed in 8-byte binary, and so on).

  FIG. 2B shows a flowchart. This shows a situation such as expansion when the CPU executes the polynomial operation of FIG. 2A with a 4-byte (32-bit) operation instruction.

In FIG. 2B, an arithmetic expression is fetched in S1. This takes in the expression of the polynomial operation (multiplicative operation of multiplication) in FIG. 2A, where, as described on the right side,
a * b * c * d
And capture.

In S2, rearrangement is performed in ascending order of the number of bits. This is because the a * b * c * d of the polynomial operation of FIG. 2A taken in S1 is rearranged in ascending order of the number of bits, and as described on the right side,
b * d * c * a
And

  In S3, the first data is fetched. This is the first one data of the polynomial operation after the rearrangement in S2, and b is taken in the first time.

  In S4, it is determined whether division is necessary. This determines whether the data fetched in S3 is larger than 4 bytes of the arithmetic instruction that can be executed by the CPU and needs to be divided. At the first time, b is fetched in S3, and b is smaller than 4 bytes in 2 bytes binary and no division is required, and the process proceeds to S6. On the other hand, in the case of YES, the process advances to S6 after being divided into upper and lower parts in S5 and smaller than 4 bytes of the arithmetic instruction that can be executed by the CPU (in addition, when the upper and lower parts are still exceeded 4 bytes) Is further divided into 3 or 4 so as not to exceed 4 bytes, and the process proceeds to S6).

  In S6, the next data is fetched. Here, the second d (2-byte binary) is taken in.

  In S7, it is determined whether division is necessary. This is also determined on the multiplication side, as in S4 (multiplicand side), if it is larger than 4 bytes of the arithmetic instruction that can be executed by the CPU and needs to be divided. In the case of YES, in S8, it is divided into higher order and lower order (further, if it is larger than 4 bytes, it is divided into 3 divisions, 4 divisions, etc.), and the process proceeds to S9. If NO, the process proceeds to S9.

  In S9, development for processing the calculation is performed. This is because the multiplicand is set to 4 bytes or less in S3 to S5, and the multiplier is set to 4 bytes or less in S7 and S8, so that the dividend and the multiplier can be calculated (for example, as shown in FIG. It is expanded so that it can be executed by a hardware instruction such as “2-byte binary * 2-byte binary”).

  In S10, it is determined whether or not the end. If YES, the process proceeds to S12. In the case of NO, the result is placed at the top in S11, and S3 and subsequent steps are repeated, and the second and third processes are performed.

  In S12, the expansion for performing the calculation is performed. Since this is expanded to an operation (arithmetic expression) of the number of digits or less that can be performed by a hardware instruction in S9, the arithmetic (arithmetic expression) is expanded into a form using a hardware instruction.

  By the above procedure, here, the polynomial operation a * b * c * d in FIG. 2A is rearranged to b * d * c * a in ascending order of the number of digits in S2, and the order shown in FIG. The first (no division), second (no division), and third (intermediate results are divided into three) processes are performed, and the first, second, and third shown in FIG. It is possible to develop an object program that can be executed at high speed, and can be executed three times from the total of nine times of the conventional method described above.

  FIG. 2 (c) schematically shows the result of processing the polynomial operation of FIG. 2 (a) according to the flowchart of FIG. 2 (b).

  ・ First time: Corresponding to the first time in FIG. 2 (b), b * d (where b = 2 bytes binary, d = 2 bytes binary) is 4 bytes or less, so the calculation is performed as it is. The intermediate result is 4 bytes.

  Second time: Corresponding to the second time in FIG. 2B, the intermediate result 4 bytes * c (where c = 4 bytes binary) is 4 bytes or less, so the calculation is performed as it is, and the intermediate result 8 It shows how it becomes a byte.

  -Third time: Corresponding to the third time of FIG. 2 (b), the intermediate result 8 bytes * a (where a = 8 bytes binary) is 4 bytes or more. Each of the operations is shown as an intermediate result of 16 bytes. Here, the upper 4 bytes and the lower 4 bytes are divided and combined, and expanded into a total of four operations as shown in the figure.

  FIG. 2 (d) shows that the multiplication of FIG. 2 (c) may be six times in total. This is 6 times compared to the conventional 9 times in FIG. 4 described above, and the multiplication of 3 times is reduced.

  FIG. 3 is an explanatory diagram (part 2) of the present invention.

FIG. 3A shows an example of a polynomial operation. Here, the following polynomial operation shown below: 8-byte binary = 2-byte binary * 2-byte binary * 2-byte binary * 2-byte binary
= A * b * c * d
(A represents an arbitrary numerical value expressed in 2-byte binary, and so on).

  FIG. 3B shows a flowchart. This shows a situation such as expansion when the CPU executes the multinomial operation of FIG. 3A with a 4-byte (32-bit) operation instruction.

In FIG. 3B, an arithmetic expression is fetched in S21. This takes in the expression of the polynomial operation (multiplicative operation of multiplication) in FIG.
a * b * c * d
And capture.

  In S22, rearrangement is performed in ascending order of the number of bits. This rearranges the a * b * c * d of the polynomial operation of FIG. 3A taken in S21 in ascending order of the number of bits. Here, since all the numbers of bits are the same, a * b * c * d remains as it is.

  In S23, the first and second are calculated. This calculates (a * b) the first (first) a and the second b. When the number of digits of the multiplicand or multiplier (here, a, b) exceeds 4 bytes, it is divided so as not to exceed S3 to S5 or S6 to S8 in FIG. Then, the operation of these divided parts is performed.

  In S24, the combination of the operation result and the remaining bits that finds the minimum number of operation result bits is found. This is to find the combination that minimizes the number of bits (number of digits) of the operation result by combining the two results including the previous operation result and the remaining operation after the first operation result calculated in S23. .

  In S25, the image is divided. This does not exceed when the two operations (operation and other operations or the previous intermediate result and operation) found in S24 exceed 4 bytes (4 bytes which is the size of the hardware instruction that can be executed by the CPU). (Similar to S3 to S8 in FIG. 2 described above).

  In S26, the expansion for processing the calculation is performed. This is expanded so that the two dividends and multipliers selected in S24 (or two after division in S25) can be processed (for example, “2-byte binary * in FIG. 3D described later). It is expanded so that it can be executed by hardware instructions such as “2-byte binary”).

  In S27, it is determined whether or not the end. If YES, the process proceeds to S28. In the case of NO, S24 and subsequent steps are repeated.

  In S28, the expansion for performing the calculation is performed. Since this is expanded to an operation (arithmetic expression) of the number of digits or less that can be performed by a hardware instruction in S26, the operation (arithmetic expression) is expanded into a form using a hardware instruction.

Through the above procedure, here, the polynomial operation a * b * c * d in FIG. 3A is rearranged in ascending order of the number of digits of a * b * c * d in S22, and the first is the first one. And then the second operation, and then select the combination of the previous operation result and the remaining operation that gives the minimum operation result (if it exceeds 4 bytes, perform the operation after dividing). By repeating the above, for example, in the example of FIG. 3A, as shown in FIG.
・ First time: a * b
・ Second time: c * d
・ 3rd: First calculation result e * Second calculation result f
Thus, it is possible to generate the object program 3 to be executed by a total of three operations (multiplication).

  FIG. 3C schematically shows the result of processing the polynomial operation of FIG. 3A according to the flowchart of FIG.

  -First time: a * b (a, b = 2 bytes binary) in FIG. 3A is selected. Since these are 4 bytes or less, the calculation is performed as it is, and the intermediate result e is 4 bytes. It shows how it becomes.

  Second time: Select c * d (where c, d = 2 bytes binary) in (a) of FIG. 3. Since these are 4 bytes or less, the calculation is performed as it is, and the intermediate result f is 4 bytes. It shows how it becomes.

  -Third time: The first a * b calculation result e and the second c * d calculation result f in FIG. 3A are selected. Since these are four bytes or less, the calculation is performed as it is. The intermediate result is 8 bytes.

  FIG. 3D shows a state in which the operation of FIG. 3C can be expanded using hardware instructions.

  First time: Corresponding to the first time in (c) of FIG.

  Second time: Corresponding to the second time in (c) of FIG.

  Third time: Corresponding to the third time in (C) of FIG. 3, a state where the first calculation result e and the second calculation result f are calculated is shown.

  FIG. 3 (e) shows that the multiplication may be three times in total. As described in FIGS. 3C and 3D, the polynomial operation of FIG. 3A is called a total of 3 operations (multiplication) according to the flowchart of FIG. 3B. It can be executed with a small number of operations.

  In an arithmetic processing program for translating a polynomial operation included in a source program, when expanding a polynomial operation into a hardware instruction at the time of compilation, the polynomial operation is sorted into a hardware instruction after being sorted in ascending order of digits. In addition, it is possible to expand the hardware instructions in order starting from the combination that minimizes the operation result of other operations including intermediate results, thereby minimizing the number of hardware instructions that execute multinomial operations and improving the execution speed. It becomes.

It is a system configuration diagram of the present invention. It is explanatory drawing (the 1) of this invention. It is explanatory drawing (the 2) of this invention. It is explanatory drawing of a prior art.

Explanation of symbols

1: compiler 2: lexical analysis means 3: syntax analysis means 4: semantic analysis means 5: optimization means 6: branch optimization means 7: calculation optimization means 8: calculation sort means 9: division means 10: combination selection means 11 : Object generation means 2: Source program 3: Object program

Claims (5)

In an arithmetic processing program for causing a computer to translate a polynomial operation included in a source program,
In the computer,
Sorting the polynomial multiplications in the polynomial operations included in the source program in ascending order of the number of digits;
Generate a hardware instruction that operates in order from the top of the sorted polynomial multiplication , and if the hardware instruction of the device that executes the operation exceeds the number of digits that can be calculated, it is divided into a plurality of operations in a range not exceeding Generating hardware instructions after
Arithmetic processing program for causing a run. In an arithmetic processing program for causing a computer to translate a polynomial operation included in a source program,
In the computer,
A selection step for selecting two operations of a combination in which the number of digits of the operation result is the smallest from the multiplicative multiplication in the polynomial operation included in the source program;
When two of the combinations are selected, a hardware instruction that calculates the selected two is generated, and when the hardware instruction of the device on which the calculation is performed exceeds the number of digits that can be calculated, A generation step of generating a hardware instruction after dividing into a plurality of operations;
Repeating the selection step and the generation step in order until all terms of the polynomial operation are selected;
Arithmetic processing program for causing a run. In an arithmetic processing method for translating a multinomial operation included in a source program,
Computer
Sorting the polynomial multiplications in the polynomial operations included in the source program in ascending order of the number of digits;
Generate a hardware instruction that operates in order from the top of the sorted polynomial multiplication , and if the hardware instruction of the device that executes the operation exceeds the number of digits that can be calculated, it is divided into a plurality of operations in a range not exceeding And a step of generating a hardware instruction after that. In an arithmetic processing method for translating a polynomial operation included in a source program,
Computer
A selection step for selecting two operations of a combination in which the number of digits of the operation result is the smallest from the multiplicative multiplication in the polynomial operation included in the source program;
When two of the combinations are selected, a hardware instruction that calculates the selected two is generated, and when the hardware instruction of the device on which the calculation is performed exceeds the number of digits that can be calculated, A generation step for generating a hardware instruction after dividing into a plurality of operations;
An operation processing method , comprising: repeating the selection step and the generation step in order until all terms of the polynomial operation are selected . In an arithmetic processing device that translates a polynomial operation included in a source program,
Means for sorting the polynomial multiplications in the polynomial operations included in the source program in ascending order of the number of digits;
Generate a hardware instruction that operates in order from the top of the sorted polynomial multiplication , and if the hardware instruction of the device that executes the operation exceeds the number of digits that can be calculated, it is divided into a plurality of operations in a range not exceeding And a means for generating a hardware instruction after that.

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