JP4326546B2 - Data input processing circuit and controller - Google Patents

Description

  The present invention relates to a data input processing circuit and a controller that are applied to a car audio system having a main body side device and a display side device separate from the main body side device, and from the data input processing circuit mounted on the display side device side to the main body A signal with a long sampling period output from a key scan circuit or rotary encoder and a signal with a short sampling period output from a remote control device, etc., output to a controller mounted on the side device side via a small number of signal lines Technology to output to the controller.

  FIG. 10 shows a configuration of a data input processing system 1 applied to a car audio system or the like. The data input processing system 1 includes a main body side device 10 and a display side device 20 that is separable from the main body side device 10.

  The main body side device 10 is mounted with a mechanism and a circuit for realizing the functions of a car audio system such as a CD player, a DVD player, and a radio receiver. On the other hand, the display-side device 20 is provided with a display panel 21 on which information related to the control and operation of the car audio system is displayed, and further includes a data input processing circuit 22, a key scan circuit 23, a rotary encoder 24, and a remote control receiver 25. Has been implemented.

  The main body side device 10 is mounted with a controller 11 for receiving display control of the display panel 21 and signals from the key scan circuit 23, the rotary encoder 24, and the remote control receiver 25. The controller 11 inputs the clock signal CL, the data input signal DI, and the chip enable signal CE to the input interface 221 of the display side device 20 in order to perform the display control and reception of the signal.

  The data input processing circuit 22 of the display-side device 20 includes an input interface 221 that communicates with the controller 11, a control register 222 that stores input data input from the controller 11, and the display data input as the input data. A display control unit 223 that controls the display panel 21, a signal generation unit 224 that supplies a drive signal for the display control unit 223 such as an operation clock, and an address that is input from the controller 11 as a data output request and stored in the control register 222 A signal selection circuit 225 for selecting a key scan signal or a rotary encoder detection signal (hereinafter referred to as a low speed processing signal) corresponding to the data and outputting the selected low speed processing signal to the multiplexer 226 is included.

The display-side device 20 is mounted with a circuit (for example, a remote control receiver 25) that generates a signal with a short sampling period (hereinafter referred to as a high-speed processing signal). Such a high-speed processing signal cannot be synchronized with the clock signal CL input from the main body-side device 20 because the processor mounted on the display-side device 20 has insufficient processing capability. The signal is output to the main device 10 via a signal line different from the signal line.
JP-A-8-221174

  If a signal line for outputting a high-speed processing signal and a signal line for a low-speed processing signal are separately provided as described above, the number of signal lines connecting the main body side device 10 and the display side device 20 is increased. This increases the wiring complexity. This also increases the possibility of problems such as poor connections, and increases the manufacturing cost as the number of parts increases.

  The present invention has been made in view of the above problems, and an object thereof is to provide a data input processing circuit and a controller capable of outputting a low speed processing signal and a high speed processing signal to a controller via a small number of signal lines. And

  A main invention of the present invention for achieving the above object is a data input processing circuit, which is a low-speed processing signal (first digital signal) which is a signal synchronized with a clock signal input from an external controller. And one high-speed processing signal selected from among a plurality of high-speed processing signals (second digital signals) that are asynchronous to the clock signal is output to the controller by time division multiplexing.

  According to the present invention, even when there are a plurality of high-speed processing signals, each high-speed processing signal and low-speed processing signal can be output to the controller with a small number of signal lines. This simplifies wiring routing, reduces the possibility of problems such as poor connection, and reduces the manufacturing cost as the number of components is small.

  One of the other main inventions of the present invention is the data input processing circuit, which is output when each high-speed processing signal (second digital signal) is output in response to a request from the controller. A synchronization signal that can be synchronized with the clock signal is output to the controller as the low-speed processing signal (first digital signal), and the controller detects the synchronization signal, The high-speed processing signal in which the synchronization signal is detected is output to the controller by time division multiplexing with the low-speed processing signal.

  According to the present invention, since the high-speed processing signal is output by time division multiplexing only when the synchronization signal is detected, that is, when the high-speed processing signal is output, for example, the processing of the data input processing circuit Load can be reduced and power consumption can be reduced.

  According to the present invention, a low-speed processing signal and a high-speed processing signal can be output to the controller via a small number of signal lines.

<< Example 1 >>
Hereinafter, one embodiment of the present invention will be described in detail. FIG. 1 shows a configuration of a data input processing system 1 applied to a car audio system, which will be described as an embodiment of the present invention. The data input processing system 1 includes a main body side device 10 and a display side device 20 that is separable from the main body side device 10.

  The main body side device 10 is mounted with a mechanism and a circuit for realizing the functions of a car audio system such as a CD player, a DVD player, and a radio receiver. The display-side device 20 includes a display panel 21 on which information related to control and operation of the car audio system is displayed, a data input processing circuit 22, a key scan circuit 23, a rotary encoder 24, and a remote control receiver 25.

  In the following description, a signal having a long sampling period, such as a signal output from the key scan circuit 23 or the rotary encoder 24, is referred to as a low speed processing signal (first digital signal) and is output from the remote control receiver 25. A signal having a short sampling period such as a signal is referred to as a high-speed processing signal (second digital signal). In this embodiment, the sampling period of the low-speed processing signal is 500 μs, and the sampling period of the high-speed processing signal is 50 μs (see FIG. 2).

  The main body side device 10 is mounted with a controller 11 for receiving display control of the display panel 21 and signals from the key scan circuit 23, the rotary encoder 24, and the remote control receiver 25. The controller 11 and the input interface 221 are connected by three signal lines. The controller 11 sends the clock signal CL, the data input signal DI, and the chip enable signal CE to the input interface 221 of the display side device 20 through these signal lines in order to perform the display control and the reception of the signal. input. The controller 11 and the multiplexer 226 are connected by a single signal line, and the output data DO is output from the multiplexer 226 to the controller 11 via this signal line.

  The controller 11 includes a synchronous data processing unit 111 that processes a low-speed processing signal input as output data DO from the display-side device 20, and an asynchronous data processing unit 112 that processes a high-speed processing signal. The low speed processing signal is input to the synchronous data processing unit 111 in a state of being synchronized with the clock signal CL. On the other hand, the high-speed processing signal is input to the asynchronous data processing unit 112 by digital through in a state asynchronous with the clock signal CL. Here, “digital through” refers to outputting an input signal without performing a synchronization process without breaking the waveform. The asynchronous data processing unit 112 processes a high-speed processing signal input through digital through at a sampling frequency equal to or higher than the sampling period (50 μs) of the high-speed processing signal.

  The data input processing circuit 22 of the display-side device 20 includes an input interface 221, a control register 222, a display control unit 223, a signal generation unit 224, a signal selection circuit 225, and a multiplexer 226 (MPX (Multiplexer)). Among these, the input interface 221 receives the clock signal CL, the data input signal DI, and the chip enable signal CE input from the main body side device 10 and stores the input data input as the data input signal DI in the control register 222. .

  FIG. 3 is a timing chart for explaining the operation of the input interface 221 when input data is input from the main device 10. The data input signal DI in this case is composed of address data (adrs1) and input data. The input data includes, for example, display data to be described later, a flag that is referred to when the multiplexer 226 selects one of a plurality of high-speed processing signals.

  FIG. 4 is a timing chart showing the operations of the input interface 221 and the multiplexer 226 when a data output request is made from the main device 10. In this case, address data (adrs2) that designates a low-speed processing signal that is an output request target is input as the data input signal DI. Corresponding to the address data (adrs2), the output data DO is output from the multiplexer 226 to the main unit 10.

  The display control unit 223 of the data input processing circuit 22 controls the display panel 21 based on the display data that is input from the main unit 10 as the input data and stored in the control register 222. The signal generation unit 224 supplies a drive signal to the display control unit 223.

  The signal selection circuit 225 selects a low-speed processing signal (key scan signal or rotary encoder detection signal) corresponding to the address data (adrs2) input from the main unit 10 as a data output request and stored in the control register 222, The selected low speed processing signal is output to the multiplexer 226. The signal selection circuit 225 is a parallel / serial conversion circuit. The low-speed processing signal is input to the signal selection circuit 225 as a parallel signal, and the low-speed processing signal output from the signal selection circuit 225 is a multiplexer as a serial signal synchronized with the clock signal CL. 226 is input.

  The multiplexer 226 multiplexes the low-speed processing signal input from the signal selection circuit 225 and the high-speed processing signal input from the remote control receiver 25 by time division multiplexing, and inputs this to the main unit 10 as output data DO. . Note that the output period of the low-speed processing signal and the output period of the high-speed processing signal that constitute one frame of the time division multiplexing can be set in the multiplexer 226 in advance. Here, the one frame is set to 500 μs, the output period of the low-speed processing signal is set to 50 μs, and the output period of the high-speed processing signal is set to 450 μs.

FIG. 5 is a timing chart showing the temporal relationship between the chip enable signal CE input from the main unit 10, the data input signal DI, and the output data DO output from the multiplexer 226.
First, the address data (adrs2) is input as the data input signal DI, and the output of the low-speed processing signal is requested from the main body side device 10, and in response to this, the low-speed processing signal (data2) is output as the output data DO ( t1 → t2).
Subsequently, the address data (adrs1) and the input data are input from the main body side device 10 as the data input signal DI (t3 → t5).
Subsequently, the address data (adrs2) is input as the data input signal DI from the main body side apparatus 10, and the output request of the low speed processing signal is requested from the main body side apparatus 10 (t6 → t7). A processing signal (data2) is output (t7 → t8).
Subsequently, the address data (adrs2) is input as the data input signal DI from the main body side apparatus 10, and the output request of the low speed processing signal is requested from the main body side apparatus 10 (t9 → t10). The processing signal (data2) is output (t10 → t11).

  As shown in the figure, the multiplexer 226 outputs a high-speed processing signal as output data DO in a digital through manner during a period other than the output period of the low-speed processing signal.

  As described above, in the data input processing system 1 described above, the low-speed processing signal from the key scan circuit 23 and the rotary encoder 24 and the high-speed processing signal from the remote control receiver 25 are converted into one serial signal line. This is a mechanism for transmitting by time division multiplexing. For this reason, the number of signal lines between the main body side device 10 and the display side device 20 can be reduced, and wiring can be easily routed. In addition, defects such as poor connections are reduced, and the number of parts is reduced, so that manufacturing costs can be reduced.

  Further, a period other than the output period of the low-speed processing signal in time division multiplexing, that is, the output period of the high-speed processing signal by digital through can be used as a period for data input from the controller 11 to the input interface 221. Specifically, for example, this period can be used as an input period of display data from the controller 11 to the input interface 221, thereby efficiently inputting display data from the main body side apparatus 10 to the display side apparatus 20. be able to.

  In the output period of the low speed processing signal, when there is no request for the output of the low speed processing signal from the main body side device 10, the high speed processing signal may be output also in the output period of the low speed processing signal. In such a mechanism, for example, when an output request for a low-speed processing signal is not made, address data (adrs1) for changing the setting of an output period of time-division multiplexing is input from the controller 11 to the display-side device 20, and the multiplexer 226 This can be done by changing the time division multiplexing output period. By adopting such a mechanism, it becomes possible to output a high-speed processing signal to the controller 11 efficiently.

<< Example 2 >>
Since the high speed processing signal from the remote control receiver 25 is input to the multiplexer 226 only when the remote control operation is performed, it is not necessary to output the high speed processing signal when there is no input of the high speed processing signal. Therefore, in this case, it is preferable to stop the output of the high-speed processing signal by digital through from the viewpoint of reducing the processing load of the multiplexer 226 and reducing the power consumption.

  Therefore, for example, by the mechanism described below, the high-speed processing signal is output from the multiplexer 226 only when a signal is input from the remote control receiver 25. FIG. 6 shows the configuration of the data input processing system 1 having the above mechanism.

  As shown in the figure, in this data input processing system 1, the remote control signal output from the remote control receiver 25 is input not only to the multiplexer 226 but also to the signal selection circuit 225. Here, when the remote control signal is output from the remote control receiver 25, a low speed processing signal (hereinafter referred to as a synchronization signal) that can be synchronized in the signal selection circuit 225 is output. The low-speed processing signal is, for example, a signal in which “High” and “Low” change in a cycle that can be sampled in the signal selection circuit 225 or a signal in which “High” continues for a predetermined period.

  A specific operation of the data input processing system 1 in this case will be described with reference to the timing chart shown in FIG. As shown in FIG. 6, the signal selection circuit 225 also receives a remote control signal output from the remote control receiver 25.

  As shown in FIG. 7, the controller 11 inputs address data (adrs2) instructing the signal selection circuit 225 to output a remote control signal input from the remote control receiver 25 to the input interface 221 at a predetermined timing. (T0 → t1). In the output period corresponding to the address data (adrs2), when a synchronization signal is output when the remote control signal is output, the synchronization signal is output from the multiplexer 226 to the controller 11 as output data DO (data2).

  When the synchronization signal is input, the controller 11 inputs address data (adrs1) instructing the multiplexer 226 to start outputting the remote control signal by digital through by time division multiplexing to the input interface 221 (t3 → t4). ). Thereby, the multiplexer 226 starts to output the low-speed processing signal and the high-speed processing signal by digital through by time division multiplexing.

  In a period from t5 to t6, address data (adrs2) designating a low-speed processing signal to be output is inputted as the data input signal DI, and the main body side device is supplied from the multiplexer 226 in correspondence with the address data (adrs2). A low-speed processing signal is output as output data DO at 10.

  When there is no input of the high-speed processing signal, the controller 11 inputs address data (adrs1) instructing the multiplexer 226 to stop the output of the remote control signal by digital through by time division multiplexing to the input interface 221 (t8 → t9). ). Thereby, the multiplexer 226 stops the output of the low-speed processing signal and the high-speed processing signal by digital through by time division multiplexing (t9 →).

  According to the above mechanism, the high-speed processing signal is output from the multiplexer 226 only when a signal is input from the remote control receiver 25. As a result, the processing load on the multiplexer 226 can be reduced and the power consumption can be suppressed.

<< Example 3 >>
For example, depending on the configuration of the data input processing system 1, a plurality of high-speed processing signals may be output to the main body side device 10 when a plurality of remote control signals are input or when other high-speed processing signals such as USB signals exist. Sometimes you have to. In such a case, for example, by the following mechanism, a plurality of high-speed processing signals are output to the main body side device 10 only by one signal line for output data DO.

  FIG. 8 shows the configuration of the data input processing system 1 for explaining the above mechanism. As shown in the figure, in this data input processing system 1, two remote control signals output from the two remote control receivers 25 and 26 are input to the multiplexer 226. As in the second embodiment, these remote control signals are also input to the signal selection circuit 225.

  FIG. 9 is a timing chart for explaining the operation of the data input processing system 1 in this case. As shown in the figure, the controller 11 inputs address data (adrs2) instructing the signal selection circuit 225 to output a signal from the remote control receiver 25 at a predetermined timing to the input interface 221 (t0). → t1). Further, the controller 11 inputs address data (adrs2) instructing the signal selection circuit 225 to output a signal from the remote control receiver 26 at a predetermined timing to the input interface 221 (t3 → t4). Similarly to the second embodiment, the controller 11 determines whether or not a synchronization signal is output from each of the remote control receivers 25 and 26. Since the controller 11 designates one of the high-speed processing signals by the address data (adrs2), it can distinguish which remote control receiver the synchronization signal is from.

  When the synchronization signal has been output, the controller 11 inputs address data (adrs1) instructing to start the digital through output of the remote control signal from the remote control receiver from which the synchronization signal has been output to the input interface 221. (T6 → t7). As a result, the multiplexer 226 starts to output the low-speed processing signal and the high-speed processing signal by digital through by time division multiplexing from the remote control receiver from which the synchronization signal is output.

  When there is no input of the high-speed processing signal, the controller 11 inputs address data (adrs1) instructing the multiplexer 226 to stop the output of the remote control signal by digital through by time division multiplexing to the input interface 221 (t11 → t12). ). Thereby, the multiplexer 226 stops the output of the low-speed processing signal and the high-speed processing signal by digital through by time division multiplexing (t12 →).

  According to the above mechanism, when a plurality of remote control signals are input or when other high-speed processing signals such as USB signals exist, a plurality of high-speed processing signals must be output to the main body side device 10. Even in such a case, it is possible to output a plurality of high-speed processing signals to the main body side device 10 using only one signal line for the output data DO.

  In the above embodiments, the number of high-speed processing signals is not limited to the above-described number, and more high-speed processing signals may exist.

  By the way, description of the above embodiment is for making an understanding of this invention easy, and does not limit this invention. It goes without saying that the present invention can be changed and improved without departing from the gist thereof, and that the present invention includes equivalents thereof. For example, the number of low-speed processing signals is not limited to that shown above, and more low-speed processing signals may exist.

It is a figure which shows the structure of the data input processing system 1 demonstrated as one Embodiment of this invention. It is a timing chart which shows an example of the low-speed processing signal and high-speed processing signal which are demonstrated as one Embodiment of this invention. It is a timing chart explaining operation | movement of the input interface 221 when input data is input from the main body side apparatus 10 demonstrated as one Embodiment of this invention. It is a timing chart explaining operation | movement of the input interface 221 when the output request | requirement of the data demonstrated as one Embodiment of this invention is performed. It is a timing chart which shows the temporal relationship of the chip enable signal CE input from the main body side apparatus 10 demonstrated as one Embodiment of this invention, the data input signal DI, and the output data DO output from the multiplexer 226. It is a figure which shows the structure of the data input processing system 1 demonstrated as one Embodiment of this invention. It is a timing chart explaining the specific operation | movement of the data input processing system 1 demonstrated as one Embodiment of this invention. It is a figure which shows the structure of the data input processing system 1 demonstrated as one Embodiment of this invention. It is a timing chart explaining operation | movement of the data input processing system 1 demonstrated as one Embodiment of this invention. It is a figure which shows the structure of the data input processing system 1 applied to a car audio system etc.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data input processing system 10 Main body side apparatus 11 Controller 111 Synchronous data processing part 112 Asynchronous data processing part 20 Display side apparatus 21 Display panel 22 Data input processing circuit 221 Input interface 222 Control register 223 Display control part 224 Signal generation part 225 Signal selection Circuit 226 Multiplexer 23 Key scan circuit 24 Rotary encoder 25 Remote control receiver

Claims (6)

A first digital signal is an external signal synchronized with the clock signal input from the controller, the time division multiplexing and a second digital signal Ru asynchronous signal der to said clock signal and outputs to the controller,
In response to a request from the controller, a synchronization signal that is a signal that can be synchronized with the clock signal that is output when the second digital signal is output is output to the controller as the first digital signal,
A data input processing circuit that outputs the signal by the time division multiplexing to the controller in response to the controller detecting the synchronization signal . The controller outputs the second digital signal even in the output period of the first digital signal in the time division multiplexing when the first digital signal is not output from the data input processing circuit. The data input processing circuit according to claim 1, wherein: A signal selection circuit for selecting and outputting one of the plurality of first digital signals;
A multiplexer that outputs the first digital signal selected by the signal selection circuit and the second digital signal that is in a state asynchronous to the clock signal to the controller by time division multiplexing;
The data input processing circuit according to claim 1, comprising: The data input processing circuit according to claim 1, wherein the first digital signal is at least one of a key scan circuit and a signal output from a rotary encoder . The data input processing circuit according to claim 1, wherein the second digital signal is at least one of a signal output from a remote control receiver or a USB device . The data input processing circuit according to claim 1, further comprising: a display control unit that controls a display panel based on display data input from the controller .

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