JP4326100B2 - Clock switching circuit for hot plug - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock switching circuit that switches an internal clock corresponding to an interface having a hot plug function such as IEEE1394 or USB, and in particular, prevents occurrence of a hazard at the time of switching and enables stable clock generation. The present invention relates to a clock switching circuit that prevents malfunction of the clock.
[0002]
[Prior art]
In recent years, personal computers connect to peripheral devices through an interface with a hot plug function. The hot plug function is a function that activates the connection even if an interface cable is connected after the computer or peripheral device is powered on. For example, after starting up a personal computer, if an interface cable with a hot plug function is connected to the connected device connected to it, the connection with the connected device is activated and the interface cable is disconnected. Then, the connection with the connected device is deactivated.
[0003]
As the connection is activated, the internal circuit of the connected device is also activated, and a predetermined high-speed process controlled by the synchronous clock is executed. Further, after the cable is disconnected, the connection is deactivated, and the internal circuit of the connected device is also deactivated. However, the internal circuit continues the minimum operation in preparation for the subsequent cable disconnection.
[0004]
[Problems to be solved by the invention]
IEEE1394, which is an interface with a hot plug function, has a high transfer rate of 400 Mbps and is suitable for image data transfer. In order to cope with this interface, the connected device has a PLL circuit that speeds up the oscillation clock of the crystal oscillator. While the connected device is activated, the internal circuit performs a certain process in synchronization with the high-speed clock of the PLL circuit. While the connected device is inactive, the internal circuit is connected to the low-speed crystal oscillator. It is desirable to maintain a minimum operation in synchronization with the oscillation clock.
[0005]
For this reason, the internal circuit of the connected device needs to switch between the high-speed clock and the low-speed clock in response to the connection and disconnection of the interface cable. In that case, it is necessary to switch between two clocks that are asynchronous and not in phase, and a conventional general clock switching circuit cannot sufficiently prevent the occurrence of a hazard at the time of switching.
[0006]
FIG. 1 is a circuit diagram of a conventional clock switching circuit. This clock switching circuit is used for asynchronous clock switching in a communication device or the like as described in, for example, Japanese Patent Laid-Open No. 6-209309. According to the switching circuit of FIG. 1, the output clock X′tal of the crystal oscillator and the output clock PLL of the PLL circuit are switched by the selection signal Select. In order to prevent the occurrence of hazards that cause malfunction when switching between the asynchronous clock X'tal and PLL, the crystal oscillation clock X'tal side has flip-flops F / F (1), F / F (2) and AND gate AND1 are switched in synchronization with the clock X'tal, and the PLL side also has flip-flops F / F (3), F / F (4) and AND gate AND2. And switching is performed in synchronization with the clock PLL.
[0007]
FIG. 2 is an operation timing chart of the clock switching circuit of FIG. The selection signal Select is a signal that becomes H level when the interface cable is disconnected and L level when the interface cable is connected. FIG. 2 shows an operation when the interface cable is changed from the connected state to the disconnected state and then returned to the connected state.
[0008]
As shown in FIG. 2, when the selection signal Select is in the L level connection state, the clock output COUT of the switching circuit outputs the high-speed clock PLL of the PLL circuit. Therefore, when the cable is disconnected and the selection signal Select becomes H level, the flip-flop F / F (1) takes in the H level of the selection signal Select in response to the fall of the clock X'tal at time t1. Thereafter, in response to the fall of the clock PLL at time t2, the flip-flops F / F (3) (4) take in the inverted signal (L level) of the selection signal Select. As a result, the AND gate AND2 prohibits the output of the clock PLL, and the clock output COUT stops. Further, in response to the fall of the clock X'tal at time t3, the flip-flop F / F (2) transfers the selection signal Select, and the AND gate AND1 passes the clock X'tal. As a result, the clock output COUT is switched to the crystal oscillator clock X'tal.
[0009]
As described above, in response to switching of the selection signal Select, the clock to be invalidated is cut by one clock operation, and the clock to be activated is validated by two clock operations, and the hazard at the time of switching Preventing the occurrence of Furthermore, since the clock to be activated is activated in synchronization with the phase of the clock, there is no occurrence of a hazard that causes a malfunction.
[0010]
FIG. 3 is another operation timing chart of the clock switching circuit of FIG. In this case, the clock PLL is very fast compared to the clock X'tal. In this example, the frequency of the clock PLL is greater than twice the frequency of the crystal clock X'tal. At time t11, the H level of the selection signal Select is taken into the flip-flop F / F (3) (4), and the output of the high-speed clock PLL is prohibited. At time t12, the H level of the selection signal Select is flip-flop F / F. (1), and at the falling edge of crystal clock X'tal at time t13, the output of flip-flop F / F (1) is taken into the next flip-flop F / F (2) and gate AND1 Is opened, and the low-speed crystal clock X'tal is output to the output clock COUT.
[0011]
When the interface cable is connected, the selection signal Select becomes L level. This state is captured by the flip-flop F / F (3) at time t14, and is captured by the next flip-flop F / F (4) at time t15 of the next falling edge. However, as described above, since the crystal clock X'tal is less than half the frequency of the high-speed flip-flop PLL, the clock X'tal falls for the first time at the time t16 after the time t15, and the flip-flop F / F (1 ) (2) takes in the L level select signal, and the output of the low-speed crystal clock X'tal is prohibited. Therefore, a hazard may occur in the output clock COUT when switching is indicated by a circle in the figure.
[0012]
Since the IEEE1394 interface is very fast, 400 Mpbs, there is a possibility that the relationship between the clock of the PLL circuit and the crystal clock is as shown in FIG. In that case, in the conventional clock switching circuit of FIG. 1, a malfunction may occur in the subsequent logic circuit to which the output clock COUT is supplied.
[0013]
Furthermore, when the interface cable is connected, the low-speed crystal clock is switched to the high-speed PLL clock. However, if the PLL circuit that starts operation is switched in an unstable state due to the switching, an unstable clock is generated in the subsequent circuit. Is supplied, causing malfunction.
[0014]
SUMMARY OF THE INVENTION An object of the present invention is to provide a clock switching circuit that can normally switch asynchronously greatly different clocks when an interface cable with a hot plug function is disconnected or connected.
[0015]
Furthermore, another object of the present invention is to provide a clock switching circuit capable of switching normally after waiting for the clock of the PLL circuit that has started operation to a stable state when an interface cable with a hot plug function is connected. is there.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, according to one aspect of the present invention, there is provided a clock switching circuit that switches between an asynchronous first clock and a second clock according to disconnection and connection of an interface cable having a hot plug function. And a first flip-flop group that captures an interface disconnection signal corresponding to the disconnection and connection of the interface cable in response to the first clock, and a second flip-flop group that captures in response to the second clock. . Further, according to the present invention, when the interface cable is disconnected, the first flip-flop group outputs the first selection signal at the clock edge of several stages and the interface cable is connected. When this is done, the final flip-flop outputs the first non-selection signal at one clock edge. In response to the first selection signal, the first clock is selected and output, and in response to the first non-selection signal, the output of the first clock is prohibited. The second flip-flop group is configured such that when the interface cable is connected, the final stage flip-flop outputs the second selection signal at several clock edges, and when the interface cable is disconnected. The flip-flop at the final stage outputs the second non-selection signal at one clock edge. In response to the second selection signal, the second clock is selected and output, and in response to the second non-selection signal, the output of the second clock is prohibited. The present invention is characterized in that the number of stages of the second flip-flop group is larger than that of the first flip-flop group by an amount corresponding to the relationship between the frequencies of the first and second clocks.
[0017]
According to the above invention, since the switching to the high-speed second clock is performed via the second flip-flop group having a larger number of stages, it is possible to prevent the occurrence of a hazard as in the conventional example.
[0018]
According to another aspect of the present invention, when an interface cable is connected, the PLL circuit starts to operate in response to the interface disconnection signal, and the interface disconnection signal is taken into the second flip-flop group after a predetermined time. It is characterized by. Further, when the interface cable is cut, the operation of the PLL circuit is stopped in response to the interface cut signal.
[0019]
According to the present invention, when switching to the high-speed second clock, a stable PLL output clock can be output as the second clock after a predetermined time has elapsed. Further, when the interface cable is disconnected, the PLL circuit is stopped, so that wasteful current consumption can be prevented.
[0020]
Another aspect of the present invention is characterized in that the number of stages of the second flip-flop group is variably set according to a frequency setting signal from the outside. Thereby, a clock switching circuit corresponding to a plurality of types of interface cables can be provided.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.
[0022]
FIG. 4 is a diagram illustrating an interface cable and a connected device to which the present embodiment is applied. The interface cable 20 is an interface having a hot plug function such as IEEE1394 or USB. The connected device 30 to which the interface cable 20 is connected or disconnected has a connector 32 to which the cable is connected. In the connected device 30, an LSI device 34 that processes a data signal supplied from the interface cable 20 is provided.
[0023]
The LSI device 34 has a pull-up resistor R that generates a disconnect signal Select indicating connection and disconnection of the interface cable 20. The pull-up resistor R has one end connected to the power supply Vcc and the other end connected to one pin of the cable. The corresponding cable side signal line is connected to the ground GND, and when the interface cable 20 is connected, the disconnect signal Select becomes L level, and when the interface cable 20 is disconnected, the disconnect signal Select becomes H level. become. This disconnection signal Select is supplied to the clock switching circuit 36.
[0024]
A crystal oscillator 33 that generates a low-speed crystal clock (first clock) X′tal is provided in the connected device 30, and the first clock X′tal is supplied to the clock switching circuit 36 and the PLL circuit 38. Supplied. During the active state, the PLL circuit 38 generates a higher-speed second clock PLL based on the first clock X′tal.
[0025]
The clock switching circuit 36 selects either the crystal clock X′tal or the clock PLL of the PLL circuit in response to the interface cable disconnection signal Select, and supplies it to the subsequent circuits 40 and 42 as the output clock COUT. The subsequent circuit is, for example, a FIFO buffer 40 that temporarily stores data supplied from the interface cable 20 and supplies the data to the subsequent stage, and a logic circuit 42 that processes the data supplied from the FIFO buffer 40. The operation is performed using the clock COUT supplied from the circuit 36 as an operation clock.
[0026]
FIG. 5 is a circuit diagram of the clock switching circuit in the present embodiment. 6 and 7 are operation timing charts when the interface cable changes from connection to disconnection and when the interface cable changes from disconnection to connection.
[0027]
The clock switching circuit 36 shown in FIG. 5 includes a first flip-flop group 43 that selects and deselects the low-speed crystal clock X'tal, and a second flip-flop that selects and deselects the high-speed clock PLL. And a counter 44 that counts a certain time until the PLL circuit is stabilized when the interface cable 20 is connected. FIG. 5 also shows a PLL circuit 38 for convenience.
[0028]
The first flip-flop group 43 has two-stage flip-flops F / F (1) and (2), as in the conventional example, and the AND gate 12 is provided between the flip-flops. Further, the first flip-flop group 43 has an AND gate AND1 that passes or stops the first clock X′tal according to the output of the final flip-flop F / F (2). The two-stage flip-flops F / F (1) and (2) respond to the falling edge of the first clock X'tal with the internal disconnect signal CLKSEL of H level when the interface cable is disconnected. In response to the next falling edge, the final flip-flop F / F (2) outputs the first selection signal (H level) S1.
In response to the first selection signal S1, the AND gate AND1 passes the first clock X'tal.
[0029]
When the interface cable is connected, the L-level internal disconnect signal CLKSEL is taken in by the final flip-flop F / F (2) via the AND gate 12, and the first non-select signal (L level) S1 is output. In response to the first non-select signal S1, the AND gate AND1 prohibits the passage of the first clock X'tal.
[0030]
As described above, the first flip-flop group 43 generates the first selection signal S1 with two more clock edges when the interface cable is disconnected, and when the interface cable is connected, The first non-select signal S1 is generated with a smaller number of clock edges. Therefore, the first flip-flop group 43 is not necessarily limited to two flip-flops.
[0031]
The second flip-flop group 45 has more flip-flops F / F than the first flip-flop group 43. The difference in the number of stages is set according to the difference in frequency between the first clock X′tal and the second clock PLL. In the example of FIG. 5, the second flip-flop group 45 includes 2N-stage flip-flops F / F (1a) (1b) to F / F (Na) (Nb). And there are AND gates 181 to 18N between the flip-flops, and the AND gate AND2 passes or stops the second clock PLL according to the output of the flip-flop F / F (Nb) at the final stage.
[0032]
The internal disconnect signal CLKSEL is taken into the flip-flop F / F (1a) via the inverter 15. Therefore, when the inverter cable is disconnected, the inverted signal (L level) of the internal disconnect signal CLKSEL is taken into the final flip-flop F / F (Nb) via the AND gate 18N, and the second non-selected The AND gate AND2 prohibits the passage of the second clock PLL by the signal S2 (L level). On the other hand, when the inverter cable is connected, the inverted signal (H level) of the internal disconnect signal CLKSEL is taken into the first stage flip-flop F / F (1a), and in response to the rising edge of the clock PLL, the next stage Forwarded to Then, after the falling edge of the clock PLL 2N times, the final flip-flop F / F (Nb) outputs the second selection signal S2 (H level), and the AND gate AND2 outputs the second clock PLL. Let it pass.
[0033]
When the interface cable is connected, the disconnect signal Select becomes L level, the PLL circuit 38 is activated, the counter 44 counts the rising edge of the crystal clock X'tal, and the output CO is output after a predetermined number of times. The internal connection signal CLKSEL is set to H level. At that time, the PLL circuit 38 outputs a stable high-speed second clock PLL. On the other hand, when the interface is disconnected, the disconnect signal Select becomes H level, the PLL circuit 38 is deactivated, and the generation of the second clock PLL is stopped. Then, the counter 44 is preset via the NOR gate 46, the output CO becomes H level, and the internal disconnect signal also becomes H level.
[0034]
As described above, when the interface cable is connected, the PLL circuit 38 is activated and the counter 44 counts up until the PLL circuit becomes stable. After the PLL circuit 38 becomes stable, the internal disconnect signal CLKSEL is connected. The state becomes the L level. When the interface cable is disconnected, the internal disconnect signal CLKSEL immediately goes to the disconnected H level, and the PLL circuit is deactivated in response to the fall of the first clock X′tal.
[0035]
The operation when the interface cable changes from the connected state to the disconnected state will be described with reference to FIG. At time t21, the interface cable changes from the connected state to the disconnected state. Accordingly, the connection signal Select changes to H level. In response to this, the internal disconnect signal CLKSEL becomes H level. Along with this change, in response to the falling edge of the second clock PLL at time t22, the flip-flop F / F (Nb) at the final stage outputs the second non-select signal S2 at L level, and the AND gate AND2 inhibits the output of the second clock PLL.
[0036]
In response to the fall of the first clock X'tal at time t23, the first flip-flop F / F (1) takes in the H level internal disconnect signal CLKSEL, and the fall of the first clock at time t24 In response to the edge, the flip-flop F / F (2) at the final stage takes in the internal disconnect signal CLKSEL and sets the first selection signal S1 to the H level. Accordingly, the first clock X′tal is passed through the AND gate AND1, and the output clock COUT outputs the first clock. Further, in response to the H level of the first selection signal S1, the output of the AND gate 50 becomes H level, and the PLL circuit 38 becomes inactive and stops.
[0037]
Next, the operation when the interface cable changes from disconnection to connection will be described with reference to FIG. When the interface cable changes to the connected state at time t31, the disconnect signal Select becomes L level. Due to this L level, the counter 44 changes from the preset state to the count state, and starts counting the subsequent first clock X'tal. Then, the rising edge of the first clock X′tal is counted, and at time t32, the counter 44 outputs an output CO of L level. Along with this, the internal disconnection signal CLKSEL becomes the L level of the connected state. Further, the PLL circuit 38 is activated by the L level of the disconnection signal Select (non-power down state), and the generation of the second clock PLL is started. That is, a high-speed second clock PLL is generated based on the crystal clock X′tal.
[0038]
When the internal connection signal CLKSEL becomes L level, the inverted signal is taken into the first flip-flop F / F (1a) in response to the falling edge of the second clock PLL at time t33. Further, in response to the falling edge at time t34, the signal is transferred to the second flip-flop F / F (2a), and in response to the falling edge at time t36, the final flip-flop F / F (Nb ) And the second selection signal S2 (H level) is output.
[0039]
Before the final stage flip-flop outputs the second selection signal S2, in response to the falling edge of the first clock X'tal, the first stage flip-flop F / F (1) (2 ) Takes in the internal connection signal CLKSEL, outputs the first non-selection signal S1 (L level), and the output of the first clock X'tal is prohibited. Then, after a predetermined dead zone, at time t36, the second clock PLL passes through the AND gate AND2 and is output as the output clock COUT.
[0040]
As described above, when the interface cable is disconnected, the inactive PLL circuit is activated, and when a stable second clock PLL is output after a predetermined time, the internal disconnect signal CLKSEL is connected (H Level). In response to the internal disconnect signal CLKSEL, the first flip-flop group 43 first stops the output of the first clock X'tal, and then the second flip-flop group 45 having a large number of stages is the second high-speed second. The output of the clock PLL starts. Therefore, switching to the stable second clock can be reliably performed without causing a hazard.
[0041]
FIG. 8 is a circuit diagram of the clock switching circuit in the second embodiment. The same reference numbers as in FIG. 5 are given. The clock switching circuit 36 of FIG. 8 differs from the circuit of FIG. 5 in that the number of stages of the second flip-flop group 45 can be switched according to the frequency selection signals Freq1,2. Accordingly, a stage number selection circuit 52 is provided in the clock switching circuit of FIG.
[0042]
FIG. 9 is a diagram illustrating a relationship between the interface cable and the connected device in the second embodiment. In this example, the interface cable 20 is provided with a switch 21 according to the operating frequency of the interface. In the example of FIG. 9, since the switch is provided on the upper side, the frequency selection signal Freq1 is selected. Therefore, the selection circuit 52 selects a signal after a larger number of stages and supplies it to the AND gate 18N. Therefore, the operation at that time is the same as that in the first embodiment.
[0043]
On the other hand, when the interface cable 20 has a switch on the lower side, the frequency selection signal Freq2 is selected, and the selection circuit 52 selects the output of the second-stage flip-flop F / F (1b) and the NAD gate 18N. To supply. Therefore, the second flip-flop group 45 is a three-stage flip-flop, and operates in the same manner as in the conventional example.
[0044]
Therefore, in the second embodiment, the number of stages of the second flip-flop group can be selected according to the difference in frequency between the first clock X'tal and the second clock PLL, and the clock switching The time dead zone can be set to an optimum length.
[0045]
As described above, the protection scope of the present invention is not limited to the above-described embodiment, but extends to the invention described in the claims and equivalents thereof.
[0046]
【The invention's effect】
As described above, according to the present invention, it is possible to reliably switch between the low-speed clock and the high-speed clock without causing a hazard in response to the disconnection and connection of the interface cable. In addition, when an interface cable is connected, switching is performed after a stable high-speed clock is generated, so that malfunction of a circuit supplied with the clock is prevented.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a conventional clock switching circuit.
FIG. 2 is an operation timing chart of the clock switching circuit of FIG.
FIG. 3 is another operation timing chart of the clock switching circuit of FIG. 1;
FIG. 4 is a diagram illustrating an interface cable and a connected device to which the present embodiment is applied.
FIG. 5 is a circuit diagram of a clock switching circuit in the present embodiment.
6 is an operation timing chart of FIG. 5 when the interface cable changes from connection to disconnection.
7 is an operation timing chart of FIG. 5 when the interface cable changes from disconnection to connection. FIG.
FIG. 8 is a circuit diagram of a clock switching circuit according to a second embodiment.
FIG. 9 is a diagram illustrating a relationship between an interface cable and a connected device in the second embodiment.
[Explanation of symbols]
20 interface cable 30 connected device 33 crystal oscillator 36 clock switching circuit 38 PLL circuit 43 first flip-flop group 44 counter 45 second flip-flop group

Claims (4)

In a clock switching circuit that switches between an asynchronous first clock and a second clock according to disconnection and connection of an interface cable having a hot plug function,
An interface disconnection signal corresponding to the disconnection and connection of the interface cable is captured in response to the first clock, and when the interface cable is disconnected, the flip-flop at the final stage is set to the first flip-flop at several clock edges. When a selection signal is output and the interface cable is connected, the flip-flop at the final stage outputs a first non-selection signal at one clock edge, and the first selection signal is output in response to the first selection signal. A first flip-flop group that outputs one clock and inhibits the output of the first clock in response to the first non-selection signal;
The interface disconnection signal is taken in response to the second clock, and when the interface cable is connected, the flip-flop at the final stage outputs the second selection signal at several clock edges, and the interface cable Is disconnected, the last flip-flop outputs a second non-selection signal at one clock edge, outputs the second clock in response to the second selection signal, and And a second flip-flop group that inhibits the output of the second clock in response to two non-selection signals,
The clock switching circuit according to claim 1, wherein the number of stages of the second flip-flop group is larger than that of the first flip-flop group in accordance with a frequency relationship between the first and second clocks. In claim 1,
The second clock is supplied from a PLL circuit that generates the second clock from the first clock,
When the interface cable is connected, the operation of the PLL circuit is started in response to the interface disconnection signal, and the interface disconnection signal is taken into the second flip-flop group after a predetermined time. Switching circuit. In claim 2,
The clock switching circuit, wherein when the interface cable is disconnected, the operation of the PLL circuit is stopped in response to the interface disconnection signal. In claim 1,
The clock switching circuit, wherein the number of stages of the second flip-flop group is changed and set according to the frequency of the operation clock of the interface cable to be connected.

Images