JP4321076B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a semiconductor device in which a nonvolatile semiconductor memory element and a high-voltage element having a higher breakdown voltage than the nonvolatile semiconductor memory element are mixedly mounted on the same semiconductor substrate, and the semiconductor device It relates to a manufacturing method.
[0002]
[Prior art]
Conventionally, there is an EEPROM as a nonvolatile semiconductor memory element (see, for example, Patent Document 1). In the EEPROM, electrons are tunneled between a thin insulating film of about 10 nm called a tunnel film between a BN layer and a floating gate, and 1 and 0 of data are discriminated by electron injection and emission. The determination of 1 or 0 is made based on whether the memory cell is higher or lower than a predetermined threshold voltage (determination Vt).
[0003]
Normally, at the time of reading for discriminating 1 and 0, voltages of 1 to 2 V and 5 V or less are applied to the drain region and the gate electrode of the selection transistor, respectively, and the substrate, the control gate, and the source region are fixed to 0 V. The reason why the control gate is fixed at 0V is to prevent a decrease in reliability of the interlayer insulating film or the like. Therefore, the concentration of the channel region of the memory transistor is usually 1 × 10¹⁵~ 5x10¹⁶cm^-3The concentration is about.
[0004]
On the other hand, when forming a high breakdown voltage element having a higher breakdown voltage than a selection transistor of a general EEPROM, the impurity concentration is, for example, 1 × 10.¹⁵cm^-3The following low-concentration semiconductor substrate is used.
[0005]
Therefore, when forming a semiconductor device in which an EEPROM and a high breakdown voltage element are mixedly mounted on the same semiconductor substrate, it is necessary to use a low concentration semiconductor substrate. In this case, if a part of the semiconductor substrate having a low concentration is used as a channel region of an EEPROM memory transistor, 1 × 10¹⁵cm^-3Since the concentration of the channel region is lower than that of a general EEPROM having a higher concentration, the extension of the depletion layer at the PN junction between the channel region and the drain region becomes large.
[0006]
Therefore, in a semiconductor device in which an EEPROM and a high breakdown voltage element are mixedly mounted on the same semiconductor substrate, when the cell size of the memory transistor is reduced, the source region and the drain region of the EEPROM are compared with a general EEPROM. Punch-through is likely to occur in the area between.
[0007]
For this reason, in a semiconductor device in which an EEPROM and a high breakdown voltage element are mixedly mounted on the same semiconductor substrate, it is more difficult to reduce the memory transistor of the EEPROM than a general EEPROM.
[0008]
As a method for avoiding this, a method in which the semiconductor device is structured as shown in FIG. 12 by implanting ions into the channel region of the memory transistor can be considered. FIG. 12 is a cross-sectional view of the semiconductor device.
[0009]
The semiconductor device shown in FIG. 12 has an impurity concentration of 1 × 10.¹⁵cm^-3P which is^-An EEPROM and a high breakdown voltage transistor are formed on the mold silicon substrate 1. The EEPROM has a memory transistor and a selection transistor. An N-type drain region 2 (BN layer 2) and an N-type source region 3 (BN layer 3) are formed in the memory transistor region where the memory transistor is formed. A tunnel film 4 is formed on the surface of the drain region 2, and a floating gate 5 is formed on the tunnel film 4 and on a region between the drain region 2 and the source region 3. A control gate 7 is formed on the floating gate 5 via an interlayer insulating film 6.
[0010]
Then, in the channel region 8 between the drain region 2 and the source region 3, P^-A P-type layer 29 having a higher concentration than the type silicon substrate 1 is formed.
[0011]
In the selection transistor region where the selection transistor is formed, P^-N serving as a source region on the silicon substrate 1^-N type region 10 and N which becomes a drain region^-Mold region 11 and N⁺A mold region 12 is formed. N^-Mold region 10 and N^-A gate electrode 14 is formed on a region between the mold region 11 via a gate insulating film 13.
[0012]
An N-channel transistor as a high breakdown voltage transistor is formed in the high breakdown voltage transistor region. The N-channel transistor is separated from the selection transistor and the field insulating film 15, and becomes the source region N⁺N type region 16 and N to be a drain region⁺Mold region 17 and N^-And a mold region 18. N⁺Mold region 16 and N^-A gate electrode 20 is formed on a region between the mold region 18 via a gate insulating film 19.
[0013]
This semiconductor device can be manufactured as follows. FIGS. 13A to 13C and FIGS. 14A to 14C are views for explaining a manufacturing process of the semiconductor device of FIG.
[0014]
[Step shown in FIG. 13 (a)]
N of field insulating film 15 and high voltage transistor^-P in which the mold region 18 is formed^-An oxide film 21 is formed on the surface of the mold silicon substrate 1. The oxide film 21 is for avoiding contamination during ion implantation.
[0015]
[Step shown in FIG. 13B]
In this step, a photolithography step and ion implantation are performed.
[0016]
That is, a photoresist 22 is formed on the oxide film 21 and patterned to open an EEPROM memory transistor region in the photoresist 22. Then, ion implantation for forming the P-type layer 9 is performed using the photoresist 22 as a mask. In this ion implantation, for example, a P-type impurity such as B (boron) is used. Note that a region 29a in the figure indicates a region into which impurities are implanted. Thereafter, the photoresist 22 is removed.
[0017]
[Step shown in FIG. 13 (c)]
In this process, a photolithography process and ion implantation are performed again.
[0018]
That is, a photoresist 23 is formed on the oxide film 21 and patterned to open a portion of the photoresist 23 that faces the regions where the drain region 2 and the source region 3 of the memory transistor are to be formed. Then, ion implantation for forming the drain region 2 and the source region 3 is performed using the photoresist 23 as a mask. In this ion implantation, for example, an N-type impurity such as As (arsenic) is used. Note that regions 2a and 3a in the figure indicate regions into which impurities have been implanted. Thereafter, the photoresist 23 is removed.
[0019]
[Step shown in FIG. 14A]
In this process, P^-The previous P-type impurity and N-type impurity introduced into the type silicon substrate 1 are activated and diffused. In this way, the drain region 2, the source region 3, and the P-type layer 29 are formed.
[0020]
[Step shown in FIG. 14B]
In this step, a region of the oxide film 21 above the drain region 2 is removed, and P^-The surface of the mold silicon substrate 1 is exposed. Then, a tunnel film 4 is formed on the surface. Thereafter, a floating gate 5 made of polySi is formed on the tunnel film 4 and on the region between the drain region 2 and the source region 3.
[0021]
[Step shown in FIG. 14C]
A control gate 7 made of polySi is formed on the floating gate 5 with an interlayer insulating film 6 interposed therebetween, and a gate electrode 14 of a selection transistor and a gate electrode 20 of a high breakdown voltage transistor are formed. Thereafter, P ions are implanted by using the gate electrodes 14 and 20 as a mask.^-N in the select transistor region of the silicon substrate 1^-Mold region 10, N^-Mold region 11 and N⁺A mold region 12 is formed. P^-In the high voltage transistor region of the silicon substrate 1⁺Mold region 16 and N⁺A mold region 17 is formed. In this way, the semiconductor device having the structure shown in FIG. 12 is manufactured.
[0022]
Conventionally, the impurity concentration is simply 1 × 10¹⁵cm^-3P which is^-When the EEPROM and the high breakdown voltage transistor are formed on the mold silicon substrate 1, the process shown in FIG. 13B is not performed in the manufacturing process described above.
[0023]
  That is, this method adds the process shown in FIG. 13B to the normal manufacturing process. By performing ion implantation on the entire surface layer of the memory transistor region, a P-type layer is formed in the region between the drain region 2 and the source region 3.29Is forming.
[0024]
  As a result, the P-type layer29Compared with the case where it is not formed, the extension of the depletion layer from the drain region 2 can be reduced. For this reason, occurrence of punch-through can be suppressed when the cell size of the memory transistor is reduced.
[0025]
[Patent Document 1]
U.S. Pat. No. 4,823,175
[0026]
[Problems to be solved by the invention]
  However, in the above-described method, the P-type layer is compared with the conventional manufacturing process.29Therefore, it is necessary to add an expensive photolithography process. For this reason, the above-described method is not preferable from the viewpoint of manufacturing cost.
[0027]
  In view of the above, the present invention provides a semiconductor device capable of suppressing the occurrence of punch-through when a memory cell is reduced without adding a photolithography process to a conventional manufacturing process.ofAn object is to provide a manufacturing method.
[0028]
[Means for Solving the Problems]
  In order to achieve the above object, in the invention described in claim 1,The diffusion region is deeper than the source region (3) and the drain region (2) of the nonvolatile semiconductor memory element and the source region (10) and the drain region (11) of the selection transistor. First, the second conductivity type impurity region (18) of the high breakdown voltage transistor is formed in the semiconductor substrate (1).
  And non-volatile semiconductor memory elementsWhen forming the source region (3) and the drain region (2), a photoresist (23) is formed on the semiconductor substrate (1) by photolithography, and the semiconductor substrate (1) of the photoresist (23) is formed. After opening a portion facing the formation region of the drain region (2) and the source region (3), the photoresist (23) is used as a mask and impurity ions of the first conductivity type are used. The first ion is implanted under an implantation condition in which the lateral spread is larger than the implantation range of impurity ions when ion implantation for forming the source region (3) and the drain region (2) is performed. Make an injection.
[0029]
  Subsequently, a second ion implantation for forming the drain region (2) and the source region (3) is performed with the photoresist (23) left, and then the impurity implanted into the semiconductor substrate (1). The source region of the source region (3), the drain region (2), and the drain region (2) is formed in the region of the semiconductor substrate (1) where the nonvolatile semiconductor memory element is to be formed. (3) a high concentration layer (9) having a higher impurity concentration than the semiconductor substrate (1) adjacent to the side surface on the side;A region having the same impurity concentration as the semiconductor substrate (1) adjacent to the high concentration layer (9);Form.
  Thereafter, the source region (10) and the drain region (11) of the selection transistor and the source region of the high breakdown voltage transistor are ion-implanted using the gate electrode (14) of the selection transistor and the gate electrode (20) of the high breakdown voltage transistor as a mask. (16) and the drain region (17);It is characterized by forming.
[0030]
As described above, in the present invention, the drain region and the high concentration layer are formed by using the mask used in the ion implantation for forming the drain region at the time of ion implantation for forming the high concentration layer. Therefore, the photolithography process necessary for this can be performed once. Therefore, according to the present invention, a high concentration layer can be formed without adding a photolithography process to the conventional manufacturing process. Thereby, it can suppress that manufacturing cost increases.
[0031]
As shown in claim 2, the first ion implantation can be performed by oblique ion implantation. In this case, compared with the case where ion implantation is performed in a direction perpendicular to the substrate surface, the impurity concentration is more in contact with the side surface of the drain region 2 in the region between the drain region 2 and the source region 3. A high concentration layer can be formed.
[0032]
Further, as shown in claim 3, in the first ion implantation, the impurity ions are so arranged that the high concentration layer (9) is disposed adjacent to only the side surface of the side surface and the bottom surface of the drain region (2). It is also possible to set the injection range.
[0033]
By performing the first ion implantation in this manner, the impurity concentration below the bottom surface of the drain region can be made the same as that of the semiconductor substrate. Thereby, parasitic capacitance can be reduced and high-speed reading can be performed.
[0039]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
In this embodiment, the impurity concentration is 1 × 10.¹⁵cm^-3A semiconductor device in which an EEPROM as a nonvolatile semiconductor memory element and a high breakdown voltage transistor are mixedly mounted on a semiconductor substrate as described below will be described as an example. FIG. 1 is a cross-sectional view of the semiconductor device according to this embodiment. Note that the same reference numerals as those in FIG. 12 are given to the same structural portions as those in FIG.
[0041]
  In the semiconductor device shown in FIG. 12 described in the section of the prior art, a P-type layer is formed over the entire region (channel region 8) between the drain region 2 and the source region 3.29In contrast, the semiconductor device according to the present embodiment has a structure in which P is provided only in the vicinity of each of the drain region 2 and the source region 3 in the region between them.⁻In this structure, a P-type layer 9 having an impurity concentration higher than that of the silicon substrate 1 is disposed. Hereinafter, the P-type layer 9 is referred to as a punch-through stop layer 9. The P-type layer corresponds to the high concentration layer described in the claims.
[0042]
That is, in the present embodiment, as shown in FIG. 1, in the memory transistor region of the EEPROM, the punch-through stop layer 9b around the drain region 2 and the source region 3 so as to cover the drain region 2 and the source region 3, respectively. 9c is arranged. The punch-through stop layer 9b on the drain region 2 side and the punch-through stop layer 9c on the source region 3 side are separated from each other by P^-It is arranged on the mold silicon substrate 1.
[0043]
That is, punch-through stop layers 9b and 9c are formed adjacent to the drain region 2 and the source region 3, respectively. Then, from the drain region 2 toward the source region 3, the drain region 2, the punch-through stop layer 9b, P^-A low concentration region having the same impurity concentration as the type silicon substrate 1, a punch-through stop layer 9c, and a source region 3 are arranged.
[0044]
The high breakdown voltage transistor is an n-channel MOSFET, which is the same as that described in the section of the prior art.^-The breakdown voltage is determined by the impurity concentration of the type silicon substrate 1. The breakdown voltage of the high breakdown voltage transistor in this embodiment is, for example, 40 V, which is higher than the breakdown voltage (for example, 20 V) of a normal EEPROM selection transistor.
[0045]
In the present embodiment, in the region between the drain region 2 and the source region 3 in this way, the drain region 2 and P^-Since the PN junction is formed by the punch-through stop layer 9 having a higher concentration than the silicon substrate 1, the depletion layer from the drain region 2 is compared with a semiconductor device in which the punch-through stop layer 9 is not formed. Can be reduced.
[0046]
Here, in a semiconductor device that does not have the punch-through stop layer 9, P^-The impurity concentration of the silicon substrate 1 is, for example, 1 × 10¹⁴cm^-3In this case, the extension of the depletion layer from the drain region 2 when a voltage of about 1.5 V is applied to the drain region 2 during reading is about 5.5 μm. Accordingly, when the channel length is 5.5 μm in the case where the punch-through stop layer 9 is not provided, punch-through occurs, and therefore the channel length cannot be shortened.
[0047]
On the other hand, in this embodiment, P^-Type silicon substrate 1 has an impurity concentration of 1 × 10¹⁴cm^-3And the impurity concentration of the punch-through stop layer 9 is, for example, 2 × 10¹⁵m^-3In this case, the extension of the depletion layer from the drain region 2 during reading is about 1.25 μm. Thus, since the extension of the depletion layer from the drain region 2 can be reduced, the channel length of the memory transistor can be shortened as compared with the structure without the punch-through stop layer 9.
[0048]
P^-Type silicon substrate 1 has an impurity concentration of 1 × 10¹⁵cm^-3Other concentrations can be used as long as it is below. In particular, from the viewpoint of ensuring the breakdown voltage of the high breakdown voltage transistor, P^-Type silicon substrate 1 has an impurity concentration of 1-2 × 10¹⁴cm^-3It is preferable that The impurity concentration of the punch-through stop layer 9 is 1 × 10¹⁵cm^-3If the concentration is higher than that, other concentrations can be used. Thereby, even if the channel length is set to 2 μm, for example, the occurrence of punch-through can be prevented.
[0049]
In the present embodiment, the region to be the channel region 8 is the punch-through stop layer 9 and P^-It is constituted by a region having the same impurity concentration as the type silicon substrate 1. Generally, in an inversion type MOSFET, the channel region has a higher current capability as the impurity concentration is lower. This is because when the voltage is applied to the gate electrode, the conductivity type is more easily reversed in the region where the impurity concentration is lower, that is, the channel region is more likely to be generated.
[0050]
Therefore, in this embodiment, since the impurity concentration of the channel region 8 is lower than that of the semiconductor device shown in FIG. 12, the current capability is higher than that of the semiconductor device shown in FIG.
[0051]
Next, FIGS. 2A to 2B and FIGS. 3A to 3C show a manufacturing process of the semiconductor device according to the present embodiment. This embodiment is mainly shown in FIG. 12B among the manufacturing steps shown in FIGS. 13A to 13C and FIGS. 14A to 14C described in the section of the prior art. The process shown is changed.
[0052]
[Step shown in FIG. 2 (a)]
In this step, as in the step shown in FIG.^-An oxide film 21 is formed on the surface of the mold silicon substrate 1.
[0053]
[Step shown in FIG. 2 (b)]
In this process, a photolithography process and ion implantation are performed as follows. First, in the photolithography process, as in FIG. 13C, a photoresist 23 is formed on the oxide film 21, and the drain region 2 and the source region 3 of the memory transistor to be formed in the photoresist 23. The part opposite to is opened.
[0054]
Thereafter, the first ion implantation for forming the punch-through stop layer 9 is performed using the photoresist 23 as a mask. At this time, for example, ion implantation is performed in a direction perpendicular to the substrate surface using a P-type impurity such as B (boron). Also, the P-type impurity implantation range (Rp) is such that the lateral spread and the depth spread are larger than Rp during N-type impurity ion implantation for forming the drain region 2 described later. Set. A region 9a in the figure indicates a region into which an N-type impurity has been implanted.
[0055]
[Step shown in FIG. 2 (c)]
In this step, the second ion implantation for forming the drain region 2 and the source region 3 is performed using the photoresist 23 as a mask while leaving the photoresist 23 used in the previous ion implantation. At this time, for example, ion implantation using an N-type impurity such as As is performed. Thereafter, the photoresist 23 is removed.
[0056]
[Step shown in FIG. 3 (a)]
In this process, P^-P-type impurities and N-type impurities introduced into the type silicon substrate 1 are activated and diffused. Thereby, the drain region 2, the source region 3, and the punch-through stop layer 9 are formed. At this time, the punch-through stop layer 9 is shaped to cover the bottom and side surfaces of the drain region 2 because the P-type impurity ions are implanted at a larger Rp than the N-type impurity as described above. Also on the source region 3 side, the punch-through stop layer 9 is similarly shaped to cover the bottom and side surfaces of the source region 3.
[0057]
[Step shown in FIG. 3B]
In this step, the tunnel film 4 and the floating gate 5 are formed as in the step shown in FIG.
[0058]
[Step shown in FIG. 3 (c)]
In this step, as in the step shown in FIG. 14C, the control gate 7, the gate electrode 14 of the selection transistor, and the gate electrode 20 of the high breakdown voltage transistor are formed. P^-N in the select transistor region of the silicon substrate 1^-Mold region 10, N^-Mold region 11 and N⁺A mold region 12 is formed. P^-In the high voltage transistor region of the silicon substrate 1⁺Mold region 16 and N⁺A mold region 17 is formed. In this way, the semiconductor device having the structure shown in FIG. 1 is manufactured.
[0059]
In the manufacturing method of the present embodiment, a photolithography process is not performed for each ion implantation process, and a mask in which only a portion facing a region where the drain region 2 and the source region 3 are to be formed is opened as shown in FIG. Are formed by a photolithography process. Then, the first and second ion implantations are continuously performed using the mask.
[0060]
Thereby, in this embodiment, since the photolithography process required for forming the drain region 2 and the punch-through stop layer 9 is only required once as in the prior art, the punch-through can be performed without adding a photolithography process. A stop layer 9 can be formed. For this reason, it can suppress that a manufacturing cost increases.
[0061]
(Second Embodiment)
In the first embodiment, in the step shown in FIG. 2B, when performing ion implantation for forming the punch-through stop layer 9, ion implantation is performed in a direction perpendicular to the substrate surface. As shown in FIG. 4, oblique ion implantation can also be performed.
[0062]
In this case, in the step shown in FIG. 2B, after opening the photoresist 23, as shown in FIG. 4, ion implantation is performed at a desired angle and acceleration voltage with respect to the substrate surface. The desired angle and acceleration voltage satisfy the conditions described below.
[0063]
FIG. 5 is a diagram for explaining angles when performing oblique ion implantation. FIG. 5 shows P^-4 is a cross-sectional view when an oxide film 21 and a photoresist 23 are formed on the surface of the mold silicon substrate 1. FIG. A region 2a in FIG. 5 indicates a region where impurities are present when the second ion implantation for forming the drain region 2 is performed.
[0064]
Here, θ is the ion implantation angle with respect to the normal of the substrate surface. Further, in the second ion implantation, when the N-type impurity is ion-implanted perpendicularly to the substrate surface, the photoresist when the N-type impurity diffuses from the end of the photoresist 23 to the lower side of the photoresist 23. Let ΔRpy be the size of the lateral spread from the end portion of 23. Further, the implantation depth of the N-type impurity including the oxide film 21 is Rpz. Then, P of the P-type impurity when the first ion implantation is performed^-P from the surface of the silicon substrate 1^-Assuming that the penetration range into the silicon substrate 1 is PTSRp, the ion implantation conditions are an implantation angle and an acceleration voltage at which PTSRp is larger than ΔRpy. That is, the ion implantation conditions are set so that PTSRp · sin θ> ΔRpy.
[0065]
More specifically, the injection angle θ is set so that tan θ ≧ ΔRpy / Rpz, and PTSRp ≧ √ {(Rpz)²⁺(ΔRpy)²}, The acceleration voltage is set.
[0066]
For example, when the thickness of the oxide film 21 is 35 nm, As as an N-type impurity is passed through the oxide film 21 at 90 keV, and P^-When ions are implanted into the silicon substrate 1, ΔRpy is 0.0193 μm. In this case, B as a P-type impurity can be ion-implanted at an implantation angle of 24 ° and an acceleration voltage of 16 keV or higher.
[0067]
Thus, the punch-through stop layer 9 can also be formed by oblique ion implantation. According to the present embodiment, a higher concentration punch is formed near the side surface on the region side between the drain region 2 and the source region 3 in the drain region 2 in the drain region 2 than in the method of the first embodiment. The through stop layer 9 can be formed. As a result, the channel length can be shortened more effectively than in the first embodiment, and miniaturization of the memory cell can be realized.
[0068]
Also, as shown in FIG. 6, when ion implantation for forming the punch-through stop layer 9 is performed, ion implantation in a direction perpendicular to the substrate surface and oblique ion implantation as described above may be performed in combination. it can.
[0069]
(Third embodiment)
FIG. 7 is a cross-sectional view of the semiconductor device according to the third embodiment. The semiconductor device shown in FIG. 7 has a structure in which the punch-through stop layer 9 is disposed so as to be in contact with only the side surface of the side surface and the bottom surface of the drain region 2 and the source region 3. The other parts are the same as those of the semiconductor device of FIG. 1, and the same parts as those of FIG.
[0070]
In the semiconductor device of FIG. 1, the punch-through stop layer 9 b is disposed so as to cover the bottom surface and the side surface of the drain region 2. On the other hand, in the present embodiment, the punch-through stop layer 9 is not disposed below the bottom surface of the drain region 2 and is in contact with the side surface on the source region 3 side among the bottom surface and side surface of the drain region 2. A punch-through stop layer 9b is disposed.
[0071]
That is, even in this embodiment, P^-In the region from the drain region 2 to the source region 3 of the type silicon substrate 1, in order from the drain region 2 side, the drain region 2, the punch-through stop layer 9b, P^-A region having the same impurity concentration as the type silicon substrate 1, a punch-through stop layer 9c, and a source region 3 are arranged.
[0072]
Next, FIGS. 8A to 8C and FIGS. 9A to 9C show a manufacturing process of the semiconductor device of this embodiment. In the manufacturing process of this embodiment, the process shown in FIG. 8B is different from the process shown in FIG.
[0073]
[Step shown in FIG. 8 (a)]
In this step, as in the step shown in FIG.^-An oxide film 21 is formed on the surface of the mold silicon substrate 1.
[0074]
[Step shown in FIG. 8B]
Similar to the step shown in FIG. 2B, a photoresist 23 is formed and opened. Thereafter, the first ion implantation for forming the punch-through stop layer 9 is performed using the photoresist 23 as a mask. At this time, in this embodiment, ion implantation is performed at a larger implantation angle than the oblique ion implantation of the second embodiment. P^-The range in the depth direction of the P-type impurity implanted into the silicon substrate 1 is approximately the same as the range in the depth direction of the N-type impurity when ions are implanted to form the drain region 2 to be formed later. Ion implantation.
[0075]
[Step shown in FIG. 8C]
In this step, as in the step shown in FIG. 2C, the second ion implantation for forming the drain region 2 and the source region 3 is performed using the photoresist 23 as a mask with the photoresist 23 left. Do. Thereafter, the photoresist 23 is removed.
[0076]
[Steps shown in FIGS. 9A to 9C]
The steps shown in FIGS. 9A, 9B, and 9C are performed in the same manner as the steps shown in FIGS. 3A, 3B, and 3C, respectively. That is, in the process shown in FIG. 9A, the drain region 2, the source region 3, and the punch-through stop layer 9 are formed by heat treatment. In the step shown in FIG. 9B, the tunnel film 4 and the floating gate 5 are formed. In the step shown in FIG. 9C, the control gate 7, the gate electrode 14 of the selection transistor, and the gate electrode 20 of the high breakdown voltage transistor are formed. P^-N in the select transistor region of the silicon substrate 1^-Mold region 10, N^-Mold region 11 and N⁺A mold region 12 is formed. P^-In the high voltage transistor region of the silicon substrate 1⁺Mold region 16 and N⁺A mold region 17 is formed. In this way, the semiconductor device having the structure shown in FIG. 7 can be manufactured.
[0077]
In the present embodiment, as described above, the punch-through stop layer 9 is formed so as to contact only the side surfaces of the drain region 2 and the source region 3. Punch-through occurs when a depletion layer extends from the drain region 2 to the source region 3 side. Therefore, as in the present embodiment, at least the region between the drain region 2 and the source region 3 and if the punch-through stop layer 9 is disposed in contact with the drain region 2, the same as in the first embodiment. It has the effect of.
[0078]
Furthermore, in the present embodiment, P below the bottom surfaces of the drain region 2 and the source region 3 is P.^-The type silicon substrate 1 is located. That is, the bottom surfaces of the drain region 2 and the source region 3 are in contact with a region having a low impurity concentration. For this reason, parasitic capacitance is reduced and high-speed reading is possible.
[0079]
(Other embodiments)
FIG. 10 is a cross-sectional view of a semiconductor device as a first example of this embodiment. In addition, the same code | symbol is attached | subjected to the structure part same as FIG.
[0080]
In each of the above-described embodiments, the case where a lateral n-channel MOSFET is used as the high breakdown voltage transistor has been described as an example. However, a lateral p-channel MOSFET or a vertical p-channel MOSFET as shown in FIG. Can also be used.
[0081]
The semiconductor device shown in FIG.⁺Type silicon substrate 31 and P⁺P formed on the silicon substrate 31^-And a mold layer 1. P^-The mold layer 1 is P in each of the above embodiments.^-This corresponds to a silicon substrate 1 and the impurity concentration is 1 × 10¹⁵cm^-3It is as follows.
[0082]
P⁺On the silicon substrate 31, an EEPROM and a vertical p-channel MOSFET are formed. Since the EEPROM is the same as the semiconductor device shown in FIG. 7, the description thereof is omitted here. Vertical p-channel MOSFET is P^-An N-type region 32 as a base region formed in the surface layer of the mold layer 1 and a P as a source region formed in the surface layer of the N-type region 32⁺The structure includes a mold region 33 and a gate electrode 34 formed on the surface of the N-type region 32 via a gate insulating film. And although not shown, P⁺The mold region 33 is electrically connected to the source electrode, and P⁺The mold silicon substrate 31 is electrically connected to the drain electrode.
[0083]
A vertical p-channel MOSFET having such a configuration is a P-type MOSFET.^-Since the mold layer 1 has a low concentration as described above, the breakdown voltage is higher than that of a general EEPROM selection transistor.
[0084]
In each of the above-described embodiments, a case where a so-called two-layer poly structure is used as the EEPROM has been described. However, a so-called one-layer EEPROM can also be used. FIG. 11 is a cross-sectional view of a semiconductor device as a second example of this embodiment. Since the same reference numerals are given to the same structural portions as those in FIG. 7, the following description will mainly focus on the portions different from those in FIG.
[0085]
The semiconductor device shown in FIG. 11 has an impurity concentration of 1 × 10.¹⁵cm^-3P which is^-A single-layer EEPROM and a high breakdown voltage transistor are formed on the silicon substrate 1.
[0086]
The memory transistor area of the EEPROM has P^-A control gate 7 composed of an impurity diffusion layer (BN layer) is formed on the surface layer of the silicon substrate 1 and adjacent to the source region 3 (on the opposite side of the drain region 2 side) via a field insulating film 15. Has been. A floating gate 5 made of polySi is formed on the control gate 7, the source region 3, and the tunnel film 4.
[0087]
The punch-through stop layer 9 is disposed in contact with the side surfaces of the drain region 2 and the source region 3 as in FIG. In the present embodiment, the punch-through stop layer 9 is also formed on the side surface of the control gate 7.
[0088]
The semiconductor device of this embodiment can also be manufactured by the steps shown in FIGS. In this case, the control gate 7 is formed by ion implantation simultaneously with the drain region 2 and the source region 3. Therefore, in the step shown in FIG. 8B, the portion of the photoresist 23 that faces the region where the control gate 7 is to be formed is also opened, so that the side surface of the control gate 7 is also punched as shown in FIG. A through stop layer 9 is formed.
[0089]
Even in such a case, the same effect as in the third embodiment is obtained.
[0090]
In each of the above embodiments, the punch-through stop layer 9 adjacent to the drain region 2 of the memory transistor region and the punch-through stop layer 9 adjacent to the source region 3 are separated from each other. As described above, as shown in FIG. 12, the punch-through stop layer 9 can be formed in the entire region between the drain region 2 and the source region 3.
[0091]
For example, when an EEPROM with a short channel length is formed or when oblique ion implantation is performed, the implantation angle is set to a larger angle so that the punch-through stop layer 9 is formed in the entire region between the drain region 2 and the source region 3. can do.
[0092]
In each of the above-described embodiments, the case where an EEPROM is used as the nonvolatile semiconductor memory element has been described as an example. However, the present invention is not limited to the EEPROM. The present invention can also be applied to the case of using an element having a structure in which the movement occurs.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
2 is a diagram for explaining a manufacturing step for the semiconductor device shown in FIG. 1; FIG.
FIG. 3 is a drawing for explaining a manufacturing process subsequent to FIG. 2;
FIG. 4 is a diagram showing a part of the manufacturing process of the semiconductor device in the first example of the second embodiment;
FIG. 5 is a diagram for explaining ion implantation conditions in the first example of the second embodiment;
FIG. 6 is a diagram showing a part of the manufacturing process of the semiconductor device in the second example of the second embodiment;
FIG. 7 is a cross-sectional view of a semiconductor device according to a second embodiment.
8 is a diagram for explaining a manufacturing process for the semiconductor device shown in FIG. 7; FIG.
FIG. 9 is a drawing for explaining a manufacturing process subsequent to FIG. 8;
FIG. 10 is a cross-sectional view of a semiconductor device as a first example of another embodiment.
FIG. 11 is a cross-sectional view of a semiconductor device as a second example of another embodiment.
FIG. 12 is a cross-sectional view of a semiconductor device having a structure studied by the present inventors.
13 is a diagram for explaining a manufacturing step for the semiconductor device shown in FIG. 12; FIG.
14 is a diagram for explaining a manufacturing process subsequent to FIG. 13; FIG.
[Explanation of symbols]
1 ... P^-Type silicon substrate, 2 ... drain region, 3 ... source region,
4 ... tunnel film, 5 ... floating gate, 6 ... interlayer insulating film,
7 ... Control gate, 8 ... Channel region,
9 ... punch through stop layer, 10 ... source side N^-Mold area,
11 ... Drain side N^-Mold region, 12 ... N⁺Mold area,
13, 19 ... gate insulating film, 14, 20 ... gate electrode,
15 ... Field insulating film, 16 ... N⁺Mold area (source area),
17 ... N⁺Type region (drain region), 18... N^-Mold region, 21 ... oxide film,
22, 23 ... Photoresist, 29 ... P⁺Mold area,
31 ... P⁺Type silicon substrate, 32... N type region (base region),
33 ... P⁺Type region (source region), 34... Gate insulating film,
35: Gate electrode.

Claims (3)

A first semiconductor substrate (1) having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ or less, a nonvolatile semiconductor memory element, a selection transistor for selecting the nonvolatile semiconductor memory element, and a selection transistor A high breakdown voltage transistor having a high breakdown voltage and a breakdown voltage determined by the impurity concentration of the semiconductor substrate ,
The nonvolatile semiconductor memory element includes a second conductivity type source region (3), a second conductivity type drain region (2), a tunnel film (4) formed on the drain region (2), A floating gate (5) formed on the tunnel film (4),
The selection transistor includes a second conductivity type source region (10), a second conductivity type drain region (11), and between the source region (10) and the drain region (11) of the selection transistor. A gate electrode (14) formed on the region;
The high breakdown voltage transistor includes a second conductivity type source region (16), a second conductivity type drain region (17), and a second conductivity type formed around the drain region (17) of the high breakdown voltage transistor. Semiconductor device having a type impurity region (18) and a gate electrode (20) formed on a region between the source region (16) of the high breakdown voltage transistor and the second conductivity type impurity region (18) A manufacturing method of
The diffusion depth is deeper than the source region (3) and the drain region (2) of the nonvolatile semiconductor memory element and the source region (10) and the drain region (11) of the selection transistor. Prior to these regions, the second conductivity type impurity region (18) of the high breakdown voltage transistor is formed in the semiconductor substrate (1),
When the source region (3) and the drain region (2) of the nonvolatile semiconductor memory element are formed, a photoresist (23) is formed on the semiconductor substrate (1) by photolithography, and the photoresist (23), after opening a portion of the semiconductor substrate (1) facing the region to be formed of the drain region (2) and the source region (3), the photoresist (23) is used as a mask. Using impurity ions of one conductivity type, the range of impurity ions is larger than the range of impurity ions implanted when ion implantation is performed to form the source region (3) and the drain region (2). The first ion implantation is performed under the implantation conditions in which the lateral spread becomes large,
With the photoresist (23) left, a second ion implantation for forming the drain region (2) and the source region (3) is performed,
By performing a heat treatment for diffusing the impurities implanted into the semiconductor substrate (1), the source region (3) and the non-volatile semiconductor memory element formation planned region of the semiconductor substrate (1) A drain region (2) and a high-concentration layer (1st conductivity type) having a higher impurity concentration than the semiconductor substrate (1) adjacent to the side surface on the source region (3) side of the drain region (2) 9) and a region having the same impurity concentration as the semiconductor substrate (1) adjacent to the high concentration layer (9) ,
Forming the tunnel film (4) and the floating gate (5) of the nonvolatile semiconductor memory element, the gate electrode (14) of the selection transistor and the gate electrode (20) of the high breakdown voltage transistor;
Thereafter, the source region (10) and the drain region (11) of the selection transistor are ion-implanted using the gate electrode (14) of the selection transistor and the gate electrode (20) of the high breakdown voltage transistor as a mask. A method of manufacturing a semiconductor device, comprising forming the source region (16) and the drain region (17) of the high breakdown voltage transistor .   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first ion implantation, oblique ion implantation is performed.   In the first ion implantation, an impurity ion implantation range is set so that the high-concentration layer (9) is disposed adjacent to only the side surface of the drain region (2). The method of manufacturing a semiconductor device according to claim 2, wherein:

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