JP4317715B2 - Self-diagnosis logic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a self-diagnostic logic circuit that performs a dynamic fault test on a logic circuit designed for full scan using a scan test, particularly a built-in self test, in a logic circuit test technique The present invention relates to a dynamic fault test method.
[0002]
[Prior art]
As the logic circuit scales up, the number of patterns for testing the logic circuit increases, and there are cases where the limit value that can be stored in the tester is exceeded. As means for coping with this problem, for example, as described in Non-Patent Document 1, a random number pattern generator (hereinafter referred to as RPG) and a multi-input code compressor (hereinafter referred to as Rultom Input Signature Register) are included in a logic circuit. There is a built-in self-diagnosis system (Built In Self Test) (hereinafter abbreviated as BIST).
[0003]
FIG. 14 shows a circuit example of a conventional BIST. The LSI 100 includes an inspected circuit 101 that has been scan-designed, an RPG 300, and a MISR 400. The circuit under test 101 is operated by a clock signal applied from the clock pin 801. The flip-flops (hereinafter abbreviated as FFs) of the circuit under test 101 are shift registers (scan chains) based on the scan design, and are generated in the RPG 300 through the scan chain group 102 to the FFs of the circuit under test 101. The test pattern can be input (hereinafter referred to as scan-in), and the logical values of the FF groups of the circuit under test 101 can be extracted (hereinafter referred to as scan-out). The logical value scanned out from the FF group is encoded by the MISR 400 and can be taken out from the output pin 410 of the compression code. RPG and MISR are usually composed of a linear feedback shift register (hereinafter abbreviated as LFSR). RPG generates all patterns except for 0 in a pseudo-random manner. MISR is the number of bits of LFSR. If n is n bits, code compression can be performed at a failure overlook rate of 1 / (2 to the power of n-1).
[0004]
The BIST procedure is as follows. Since the pattern is generated inside the LSI and the expected value is encoded inside the LSI, the data amount of the test pattern input to the tester can be greatly reduced.
[0005]
(1) The RPG 300, MISR 400, and FF group in the circuit under test 101 are initialized.
(2) A test pattern is generated by the RPG 300.
(3) The test pattern is scanned into the FF group of the circuit under test 101 through the scan chain group 102.
(4) After completion of scan-in, the response result of the circuit under test is held in the FF group as a test result.
(5) The test result is scanned out through the scan chain group 102.
[0006]
(6) The scan-out test result is input to the MISR 400 and compressed.
(7) After performing (2) to (5) a predetermined number of times, the code of the test result is read from the compression code output pin 410.
(8) Compare the sign of the read test result with the expected value sign obtained in advance by simulation to determine whether the test result is acceptable or not.
[0007]
As a special remark of the above BIST procedure, it is mentioned that procedures 2, 3, 5, and 6 are performed simultaneously on the circuit configuration. Further, as a special note of the BIST procedure 3, it is mentioned that all the logical values of the FF group in the circuit to be inspected become the input pattern of the test step at the last step of the scan-in.
[0008]
Hereinafter, the last step of scan-in is referred to as release, and is distinguished from scan-in steps other than release. In the BIST procedure 4, the action of holding the test result in the FF is hereinafter referred to as capture.
[0009]
When BIST is used, the data capacity of the test pattern can be reduced as described above, so that a large amount of test patterns can be input. For this reason, BIST is advantageous for detecting many faults that cannot be modeled with a single stuck-at fault.
[0010]
Next, the speeding up of the logic circuit will be described. As logic circuits increase in speed, logic circuit dynamic tests have become important. A dynamic fault is a fault in which signal propagation does not fit within a predetermined time. When a dynamic failure occurs in a logic circuit, the speed performance of the logic circuit may be reduced, or the logic circuit itself may not operate normally. The dynamic failure test is a test for confirming the presence or absence of a dynamic failure. For example, as described in Non-Patent Document 2, a method for performing a functional test at an actual operation speed, or a scan test at an actual operation speed. The method implemented in is adopted.
[0011]
By the way, the logic circuit of the MOS device is characterized by consuming power and generating power noise when the logic value level of the circuit changes. Since BIST generates and uses a pseudo-random pattern with an RPG configured with LSFR, the average rate of change in the scan mode is as high as 50%. The higher the rate of change of the circuit, the higher the power consumption, the greater the influence of power supply noise, and hinder normal circuit operation.
[0012]
As a conventional technique for solving this problem, there is a self-diagnosis type logic integrated circuit diagnosis method and a self-diagnosis type logic integrated circuit described in Patent Document 1. The technique described in Patent Document 1 is a technique for eliminating an excessive random number change rate of an LSI using BIST. A random number change rate reducing circuit is inserted into the output of the RPG, or a clock signal supplied to the RPG is controlled. Is appropriately cut off to reduce the rate of change of the test pattern scanned into the circuit to be inspected and to reduce power supply noise.
[0013]
Another conventional technique is disclosed in Patent Document 2. The technique disclosed in FIG. 4 of Patent Document 2 adds a clock supply enable / disable enable circuit to the clock supply circuit of the logic circuit, thins out the clock signal supplied during the scan-in operation, and relatively slows down the scan-in speed. By doing so, average power consumption and power supply noise are reduced.
[Patent Document 1]
JP 2001-174515 A
[Patent Document 2]
USP 6,330,681 publication
[Non-Patent Document 1]
Paul H. Bardell et al. “BUILT-IN-TEST FOR VLSI Pseudorandom Techniques” published by WILEY-INTERSCIENCE, 1987, p. 38-39
[Non-Patent Document 2]
Design Wave MAGAZINE March 2001 issue CQ publisher p. 63-64 FIG. 11)
[0014]
[Problems to be solved by the invention]
The prior arts described in Patent Documents 1 and 2 are inventions that reduce BIST power supply noise. Both are aimed at reducing the average power supply noise during the test by measures in the scan mode. . However, in the dynamic failure test, a normal test cannot be performed unless the power supply noise from release to capture is also reduced.
[0015]
In the above prior art, the influence of power supply noise from release to capture becomes noticeable during dynamic failure testing because the clock interval is shortened and the effects of voltage drop overlap, resulting in a larger voltage drop. Because. The voltage drop increases as the number of circuits whose logic values change increases.
[0016]
In the dynamic fault test, it is necessary to apply the capture clock at the same test timing as the actual operation speed. Therefore, in principle, the clock interval is short, and as a result, the logical value change interval of the circuit is also shortened. The effects overlap, causing a larger voltage drop and increasing power supply noise.
[0017]
It is an object of the present invention to reduce the influence of power supply noise that occurs due to a short clock interval and thus a short time interval between a release clock and a capture clock in a dynamic fault test in a self-diagnostic logic circuit. It is to reduce the power supply noise during the process.
[0018]
[Means for Solving the Problems]
The present invention includes a circuit configuration and a test method using the circuit configuration. First, a circuit under test is divided into a plurality of groups according to a supplied clock signal by using a clock control circuit that divides one clock signal source into a plurality of clock signals and controls the allowance and cutoff of the propagation of each clock signal. A circuit configuration is realized.
[0019]
That is, the present invention includes a combination circuit and a plurality of storage elements, and includes an operation mode in which the storage elements are configured in a shift register-like scan chain and a control signal line for setting the operation mode. A plurality of phases of clock signal sources are distributed to each of the storage elements, and the clock signal is used to shift data on the scan chain, to capture signal values from the combinational circuit, and to store the contents of the storage elements. A self-diagnostic logic circuit that performs a release operation to a combinational circuit, wherein at least one of the clock signal sources includes a plurality of storage elements to which a clock pulse from one signal source is distributed; Allowed and blocked clock propagation from the clock signal source divided into groups and provided for each group of the storage elements A control circuit for controlling the control circuit, and a signal line for each group for setting each control circuit to a cutoff mode, each control circuit, after one propagation of the clock pulse is cut off by the mode setting, The self-diagnostic logic circuit is characterized in that it shifts to a mode allowing the propagation of the next clock pulse from the clock signal source in synchronization with the clock pulse itself.
[0020]
According to another aspect of the present invention, a dynamic fault test in one test step is limited to a part of a group of circuits to be inspected using the above circuit configuration, and a plurality of times In the test step, a dynamic fault test is performed on all the circuits to be inspected.
According to the present invention, it is possible to reduce power supply noise by reducing the number of dynamic failure test target circuits per test.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the concept of the overall configuration of a self-diagnostic logic circuit according to an embodiment of the present invention. 1, 100 is a logic integrated circuit (LSI) having a self-diagnosis function, 101 is a circuit to be tested designed for scan, 300 is a random number pattern generator (RPG), 400 is a multi-input code compressor (MISR), 102 is It is a scan campus. The RPG 300, the circuit to be inspected, and the MISR 400 are connected by the scan path 102, and a compression code output pin 410 for outputting the contents of the MISR 400 to the outside of the LSI 100 is provided. The internal FF of the circuit under test 101 is divided into two groups A and B. A clock control circuit 800 divides the clock signal input from the clock pin 801 into two systems of clocks A and B. The clock A is supplied to the group A FFs of the circuit under test 101, and the clock B is supplied to the group B FFs. In the figure, the internal FF of the circuit 101 to be inspected is shown to be divided into fine groups in which two of A and B are alternately arranged. This is to make the inventive concept easy to understand. In order to avoid complication of the circuit configuration, the internal FF of the circuit under test 101 is divided into a group A and a group B having an area of an appropriate size. For example, the entire circuit under test 101 is divided into four areas (as shown in FIG. 2), two of these areas are separated by a group A composed of a plurality of A, and the two separated areas are divided into a plurality of areas. The group B is configured to occupy the group B.
[0022]
Hereinafter, in this embodiment, the internal FF of the circuit under test 101 is divided into two groups, A and B. First, a dynamic fault test is performed on the group A and static on the group B in the first test step. A method of performing a failure test, performing a static failure test for group A in another test step, and performing a dynamic failure test for group B will be described. Although the case where the order of group A and B is reversed is also considered, since it is essentially the same, it does not explain.
[0023]
In this embodiment, the number of divided groups is two, but it may be divided into three or more. In any case, the circuit under test is divided into a plurality of groups by using a clock control circuit that controls the propagation and blocking of each clock signal by dividing one clock source into a plurality of groups, and at the time of one test The dynamic failure test target circuit may be limited to only some groups, and the dynamic failure tests of all groups may be performed by a plurality of tests.
[0024]
FIG. 2 is an excerpt of a part of the connection relationship between the circuit under test 101 and the clock control circuit 800 in the self-diagnostic logic circuit 100 of FIG. In FIG. 2, reference numerals 711 to 714 denote FFs in the circuit to be inspected. FF711 and FF714 belong to group A and are supplied with clock A, and FF712 and FF713 belong to group B and are supplied with clock B. A combinational circuit 701 is connected to the previous stage of FF711, and a combinational circuit 702 is connected to the previous stage of FF712. Similarly, a combinational circuit 703 is connected to the previous stage of FF713, and a combinational circuit 704 is connected to the previous stage of FF714. It is connected.
[0025]
FIG. 3 shows a circuit configuration example of the RPG 300, and FIG. 4 shows a circuit configuration example of the MISR 400.
[0026]
A circuit example of the clock control circuit 800 will be described with reference to FIG. This figure shows an example of the clock control circuit when the number of clock divisions is 2, as described above. The clock control circuit 800 includes a clock input terminal 801 and clock A (802) and clock B (803) which are clock output terminals. As a control terminal for controlling the output of the clock, the group A dynamic fault test mode signal (805) for controlling the output of the clocks A and B during the group A dynamic fault test and the clock A during the group B dynamic fault test , A group B dynamic fault test mode signal (806) for controlling the output of B, a test mode (807) and a reset signal (808). Reference numerals 810 and 811 denote edge trigger type flip-flops.
[0027]
The operation of the clock control circuit 800 will be described with reference to FIG. FIG. 6 is a time chart for explaining the operation of the clock control circuit 800. These time charts include clock input 801, output clock A (802), clock B (803), group A dynamic failure test mode signal (805), group B dynamic failure test mode signal (806), and The relationship between the test mode (807) and the clock timing (clocks 821 to 836) is shown.
[0028]
(1) in FIG. 6 shows the time realized by shifting the clock timing on the capture side in the clock control method for performing the dynamic fault test on the group A and performing the static fault test on the group B. This is an extracted area near the chart capture. The interval between the clocks 823 and 824 is the test timing of the dynamic fault test, and the interval between the clocks 823 and 825 is the test timing of the static fault test. Clocks 821 to 823 are scan-in clocks, clock 824 is a group A capture clock, clock 825 is a group B capture clock, and clock 826 is a scan-out clock.
[0029]
The clock-in 823 completes the scan-in of both the group A and B FFs, the next clock 824 captures the group A dynamic fault test, and the next clock 825 captures the group B static fault test. The scans out of groups A and B are started simultaneously from the next clock 826.
[0030]
Similarly, when a static fault test is performed on group A and a dynamic fault is performed on group B by shifting the clock timing on the capture side, the group A dynamic fault test mode signal and This can be realized by switching the group B dynamic fault test mode signal.
[0031]
(2) in FIG. 6 is realized by shifting the clock timing on the release side in the clock control method for performing the dynamic fault test on the group A and performing the static fault test on the group B. This is an extracted part of the time chart. The interval between the clocks 833 and 834 is the test timing of the dynamic fault test, and the interval between the clocks 833 and 835 is the test timing of the dynamic fault test. Clock 831 is a scan-in clock for groups A and B, clock 832 is a scan-in clock for group B, clock 833 is a scan-in clock for group A, and clock 834 is a capture clock for groups A and B. , Clocks 835 to 836 are group A and B scan-out clocks. Group B scan-in is completed at clock 832, group A scan-in is completed at next clock 833, and group B static fault test is captured at the next clock 834 along with a capture of group A dynamic fault test. Is captured, and the scan-out of groups A and B is started simultaneously from the next clock 835.
[0032]
Similarly, when a static fault test is performed for group A and a dynamic fault is performed for group B by shifting the clock timing on the release side, the clock A suppression signal and the clock B suppression signal are interchanged. This is possible.
[0033]
Next, referring to FIGS. 7 and 8, a general configuration and procedure for performing a dynamic fault test and a static fault test will be described.
[0034]
FIG. 7 shows a configuration example for performing a dynamic fault test by a scan test. A logic circuit 500 (corresponding to the logic circuit 100 in FIG. 2) designed for Multiplexed Scan (hereinafter abbreviated as MUX-SCAN) 501 is a circuit to be tested (corresponding to the combinational circuits 701 to 704 in FIG. 2). . Here, for simplification, the BUF element is a circuit to be inspected. Reference numerals 510 and 511 denote Multiplexed Flip-Flops (hereinafter abbreviated as MUX-FF) corresponding to the combinational circuits 701 to 704 in FIG. 2, and either normal data input or scan data is captured by applying a clock 520. The input data of the MUX-FF is switched by the value of a scan enable signal (hereinafter abbreviated as SEN signal) 530. When the SEN signal is 0, the normal data side is taken in, and when it is 1, the scan data side is taken in. Hereinafter, a state in which the SEN signal is 1 is referred to as a scan mode, and a state in which the SEN signal is 0 is referred to as a normal mode. 540 is a scan-in data pin (hereinafter abbreviated as SID pin), 541 is a scan-out data pin (hereinafter abbreviated as SOD pin), and 542 is a scan chain.
[0035]
In the scan mode, the data applied from the SID pin is applied to the MUX-FFs 510 and 511 through the scan chain (scan-in), and the logical value held by the MUX-FFs 510 and 511 is output from the SOD pin ( Scan out). Note that the normal data input of the MUX-FF 510 is fixed to 0.
[0036]
FIG. 8 is a time chart example of a dynamic fault test corresponding to the configuration of FIG. 7 are all initialized to 0 at time t0. Tsys indicates test timing. First, the SEN signal is set to the scan mode at time t0, a clock is applied at time t1 while 1 is applied to the SID pin, and 1 is scanned in (released) to the MUX-FF 510. At this time, a 0 → 1 transition occurs at the q terminal of the MUX-FF 510 (550). Next, after setting the SEN signal to the normal mode at time t2, a clock is applied at time t3, and the output signal of the circuit under test 501 is held in the MUX-FF 511 (551). If the circuit under test is normal, the 0 → 1 transition generated in the MUX-FF 510 reaches the MUX-FF 511 after d1 from the time t1 (d1 <Tsys), so the logical value of the MUX-FF 511 is 1. (552). Conversely, if there is a dynamic failure in the circuit under test 501, the transition of 0 → 1 occurring in the MUX-FF 510 reaches the MUX-FF 511 after d2 (d2> Tsys) from the time t1, so that the MUX-FF 511 The logical value is 0 before the transition, and it can be determined that the circuit under test has failed.
[0037]
Next, a test circuit according to an embodiment of the present invention will be described with reference to FIGS.
[0038]
First, an example of the operation of the test circuit when all FFs are subjected to a dynamic fault test will be described with reference to FIG. When a test pattern is generated from the RPG 300 of FIG. 2 and the original clock 801 is applied with the FFs 711 to 714 as a scan mode, the test pattern is scanned into the FFs 711 to FF 714. Next, when the original clock 801 is applied with the FFs 711 to 714 in the normal mode, the test results are captured by the FFs 711 to FF714 according to the combinational circuit in the previous stage of the FF. In this case, all FF clocks are applied at the timing of the dynamic fault test.
[0039]
Next, an example of the operation of the test circuit to which the means for shifting the clock on the capture side among the power supply noise reduction means that is a feature of the present invention is described with reference to FIG.
[0040]
First, (1) in FIG. 10 is a case where only the group A is subjected to a dynamic fault test. When a test pattern is generated from the RPG 300 of FIG. 2 and the original clock 801 is applied with the FFs 711 to 714 as a scan mode, the test pattern is scanned into the FFs 711 to FF 714. Next, when the FFs 711 to 714 are set to the normal mode and the control signal of the clock control circuit 800 is controlled to suppress the propagation of only the clock B and the original clock is applied, the FF 711 and the FF 714 are tested according to the combinational circuit in the previous stage of the FF. Capture the results. At this time, since the clock B is suppressed, the FF 712 and the FF 713 do not change with the scanned-in values.
[0041]
Next, by controlling the control signal of the clock control circuit 800 while keeping the FFs 711 to 714 in the normal mode and suppressing the propagation of only the clock A and applying the original clock, the FF 712 and the FF 713 according to the combinational circuit in the preceding stage of the FF. Captures test results. At this time, since the clock A is suppressed, the FF 711 and the FF 714 do not change with the captured values. In this case, among the four FFs 711 to 714, only the two FFs in group A are applied with the dynamic failure test timing.
[0042]
As described above, according to the present invention, at the time of the dynamic fault test of the logic circuit using the BIST, the dynamic fault test is performed only on one of the two groups of FFs out of the four FFs 711 to 714. A clock is applied at the timing, and clocks for other groups are suppressed. As a result, the target logic of the dynamic fault test to be performed at one time is limited, so that power noise from release to capture can be reduced, and problems caused by power noise in the dynamic fault test can be eliminated.
[0043]
(2) in FIG. 10 is intended for the dynamic fault test only for group B, but is not particularly described because it can be realized by reversing the control of clocks A and B in (1) of FIG.
[0044]
Next, with reference to FIG. 11, an operation example in which means for shifting the release-side clock among the power supply noise reducing means described above is applied will be described.
[0045]
(1) in FIG. 11 is a case where only group A is subjected to a dynamic fault test. When a test pattern is generated from the RPG 300 of FIG. 2, the FFs 711 to 714 are set to the scan mode, the clock control circuit 800 is controlled, propagation of only the clock A is suppressed, and the original clock 801 is applied once, the test patterns are applied to the FF712 and FF713. Is scanned in. At this time, since the clock A is suppressed, the logical values of the FF 711 and the FF 714 do not change. Next, when the clock control circuit 800 is controlled while the FFs 711 to 714 are in the scan mode, the propagation of the clock B is suppressed and the original clock is applied, the RPG 300 generates a test pattern, and the test pattern is scanned to the FF 711 and the FF 714. In. At this time, since the clock B is suppressed, the logical values of the FF 712 and the FF 713 do not change with the scanned values.
[0046]
Next, when the FFs 711 to 714 are set in the normal mode, the control signal of the clock control circuit 800 is controlled and the original clock is applied without suppressing the propagation of the clocks A and B, the FF 711 according to the combinational circuit in the preceding stage of the FF. ~ 714 captures test results. In this case, among all four FFs, only two FFs in group A are applied with the clock at the timing of the dynamic fault test.
(2) in FIG. 11 is intended for dynamic failure test only for group B, but is not particularly described because it can be realized by reversing the control of clocks A and B in (1) of FIG. .
[0047]
An example of a test procedure using the above test circuit is shown in FIG. The test procedure is roughly divided into two flows. In the first flow 1, a dynamic fault test is performed on group A, and a static fault test is performed on group B. In the next flow 2, a dynamic fault test is performed on the group B, and a static fault test is performed on the group A.
[0048]
First, the flow 1 of FIG. 12 will be described in detail. In the first step 1, the RPG 300, MISR 400, and FF group in the circuit under test 101 are initialized. In BIST, if the internal logic value of the circuit is indefinite, the simulation result for obtaining the expected value becomes indefinite, so initialization is necessary. When all the logical values of RPG are 0, random numbers cannot be generated inside the LFSR, so RPG is initialized with a value other than 0.
[0049]
In the next step 2, the test pattern is scanned in and the test result is scanned out. Since the RPG, the scan chain, and the MISR are directly connected, the scan-in is performed as the pattern is generated, the scan-out is performed simultaneously with the scan-in, and the test result is encoded together with the scan-out.
[0050]
In the next step 3, the clock control circuit 800 is controlled to set the group A as the dynamic fault test target, the group B as the static fault test target, and hold the response result of the circuit under test as the test result in the FF group. The clock control method for carrying out the dynamic fault test for group A and the static fault test for group B is as described above with reference to FIG.
[0051]
Steps 2 and 3 are repeated until a predetermined number of times +1 test is performed. Here, the reason why the predetermined number of times is added is that the test results for the predetermined number of times cannot be encoded unless +1 scan-out and encoding are performed.
When the predetermined number of tests +1 is completed, the test result of flow 1 is read from the code output pin 410 in step 5 and compared with the expected value code obtained in advance by the test simulation in step 6 to determine whether the LSI is acceptable or not.
[0052]
The flow 2 is different from the flow 1 only in that the dynamic failure test target group is set to B and the static failure test target group is set to A in step 8, and will not be described in particular. The initialization of the RPG 300, the MISR 400, and the FF group in the circuit under test 101 does not exist in the flow 2, but may be entered at the beginning of the flow 2.
[0053]
According to the above procedure, by limiting the target logic of the dynamic fault test performed at one time during the dynamic fault test of the logic circuit using BIST, it is possible to reduce power supply noise from release to capture. That is, it is possible to eliminate a problem caused by power supply noise in the dynamic failure test.
[0054]
Here, the reason why the influence of the power supply noise during the period from release to capture becomes significant during the dynamic fault test will be described with reference to FIG.
[0055]
(1) in FIG. 13 shows a power supply voltage waveform due to a change in the logic value of the logic circuit. A power supply voltage drop due to power consumption occurs from the time when the logic value of the logic circuit changes in synchronization with the application of the clock, and a phenomenon of gradual recovery occurs (610).
[0056]
(2) of FIG. 13 shows the power supply waveform at the time of static failure test. A power supply voltage drop occurs with the application of the release clock 620, and the voltage drop is eliminated as time passes. Even when the clock interval is short, the normal state is restored before the capture clock 622 is applied (621). 623).
[0057]
(3) of FIG. 13 shows the power supply waveform at the time of the dynamic fault test when the clock interval is short. The process is the same as the static fault test until a voltage drop occurs with the application of the release clock 630 (631), but the capture clock 632 is applied before the power supply waveform returns to the normal state. The clock interval is shortened and the influence of the voltage drop overlaps, resulting in a larger voltage drop (633). The voltage drop increases as the number of circuits whose logic values change increases. As described above, in the dynamic fault test, it is necessary to apply the capture clock at the same test timing as the actual operation speed. Therefore, in principle, the clock interval is short, and as a result, the logical value change interval of the circuit is also shortened. The effects of the drops overlap and are superimposed, creating a larger voltage drop.
[0058]
According to the embodiment of the present invention, the target logic of the dynamic fault test performed at a time is limited. That is, in the first step, a dynamic fault test is performed on the FF 711 and FF 714 in the group A, and a static fault test is performed on the FF 712 and the FF 713 in the group B. In the next step, the dynamic failure test target group is B, and the static failure test target group is A.
[0059]
In this way, by limiting the target logic of the dynamic fault test to be performed at one time at the time of the dynamic fault test of the logic circuit using BIST, even if the clock interval is shortened, the logic shown in FIG. The number of circuits having a larger voltage drop (633) shown in (3) is limited. For example, the number of circuits becomes ½ of the whole, and power supply noise accompanying the voltage drop can be reduced. Can be eliminated, and problems caused by power supply noise in dynamic fault testing can be eliminated.
[0060]
Next, another embodiment of the present invention will be described. In this embodiment, the internal FF of the circuit under test 101 is divided into three groups A, B, and C. First, a dynamic fault test is performed on the group A in the first test step, and the groups B, C A static fault test is performed on the group A, a static fault test is performed on the groups A and C in another test step, and a dynamic fault test is performed on the group B. Further, in another test step, a dynamic fault test is performed on the group C and a static fault test is performed on the groups A and B. The method of the dynamic fault test and the static fault test is the same as the embodiment described above. Also in this example, since the target logic of the dynamic fault test performed at a time can be limited, the influence of power supply noise can be reduced.
[0061]
【The invention's effect】
According to the present invention, from the release to the capture even when the clock interval is short, by limiting the target logic of the dynamic fault test to be performed at one time during the dynamic fault test of the logic circuit using the BIST. Power supply noise can be reduced, and problems caused by power supply noise in dynamic fault testing can be eliminated.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.
FIG. 2 is a diagram illustrating a circuit example illustrating a specific example of an embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration example of a random number pattern generator (Random Pattern Generator) used during BIST.
FIG. 4 is a diagram illustrating a configuration example of a multi-input code compressor (Multi Input Signature Register) used at the time of BIST.
FIG. 5 is an example of a clock control circuit for explaining a specific example of an embodiment of the present invention;
FIG. 6 is a time chart of a clock control circuit for explaining a specific example of an embodiment of the present invention.
FIG. 7 is a diagram illustrating a configuration example for performing a dynamic fault test by a scan test.
FIG. 8 is a time chart for explaining the operation of a dynamic fault test.
FIG. 9 is a time chart for explaining the operation of one embodiment of the present invention.
FIG. 10 is a circuit example illustrating an operation of a dynamic fault test.
FIG. 11 is an operation example of a test circuit in which only group A or group B is a dynamic fault test target;
FIG. 12 is a diagram showing a test procedure according to an embodiment of the present invention.
FIG. 13 is a time chart for explaining power supply noise in a dynamic fault test.
FIG. 14 is a circuit example of a conventional self test (Built In Self Test).
[Explanation of symbols]
100--Logic Integrated Circuit (LSI)
101--scanned circuit to be tested
102--scan chain
300--Random Pattern Generator
400--Multi-Input Code Compressor
410--Test result sign output pin
500--small logic circuit
501--Circuit under test
510--Multiplexed flip-flop
511--Multiplexed flip-flop
520--clock pin
530--Scan enable pin
540--Scan-in data pin
541--Scanout Data Pin
542-Scan chain
701-704--combination circuit
711-714-Multiplexed flip-flop
800--clock control circuit
801-803--clock pins
806-808--control pins of the clock control circuit
810-811--edge trigger type flip-flop.

Claims (1)

One or a plurality of phase clock signals, each having a combinational circuit and a plurality of storage elements, comprising an operation mode in which the storage elements are configured in a shift register-like scan chain and a control signal line for setting the operation mode A source is distributed to each storage element, and a shift operation of data on the scan chain, a capture operation of a signal value from the combination circuit, and a release operation of contents held by the storage element to the combination circuit by the clock signal A self-diagnostic logic circuit,
The plurality of storage elements are divided into first and second groups;
For each of the first and second groups, the control circuit and the signal before Kigu each loop to set the pre-SL control circuit to the blocking mode for controlling the blocking and tolerance of the clock propagation from said clock signal source With a line,
Each of the control circuits, after the propagation of the first clock pulse to the first group by the mode setting is cut off, synchronizes with the first clock pulse itself and receives the next from the clock signal source. The second clock pulse is allowed to propagate to the first group and is not allowed to propagate to the second group, and the second group of the first clock pulses is changed according to the mode setting. After the propagation to is interrupted, the next second clock pulse from the clock signal source is allowed to propagate to the second group in synchronization with the first clock pulse itself and the first clock pulse is allowed. A self-diagnostic logic circuit configured to transition to a mode that blocks propagation to the group .

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