JP4311862B2 - Chip mounting method - Google Patents

Chip mounting method Download PDF

Info

Publication number
JP4311862B2
JP4311862B2 JP2000158878A JP2000158878A JP4311862B2 JP 4311862 B2 JP4311862 B2 JP 4311862B2 JP 2000158878 A JP2000158878 A JP 2000158878A JP 2000158878 A JP2000158878 A JP 2000158878A JP 4311862 B2 JP4311862 B2 JP 4311862B2
Authority
JP
Japan
Prior art keywords
substrate
chip
head
heating
heater
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000158878A
Other languages
Japanese (ja)
Other versions
JP2001338946A (en
Inventor
朗 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toray Engineering Co Ltd
Original Assignee
Toray Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toray Engineering Co Ltd filed Critical Toray Engineering Co Ltd
Priority to JP2000158878A priority Critical patent/JP4311862B2/en
Publication of JP2001338946A publication Critical patent/JP2001338946A/en
Application granted granted Critical
Publication of JP4311862B2 publication Critical patent/JP4311862B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75251Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75252Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75723Electrostatic holding means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75733Magnetic holding means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75743Suction holding means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/83095Temperature settings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/83095Temperature settings
    • H01L2224/83096Transient conditions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Description

【0001】
【発明の属する技術分野】
本発明は、チップ実装方法に関するものである。
【0002】
【従来の技術】
従来、周知のように、ACF(Anisotropic Conductive Film)、NCF(Non−Conductive Film)、ACP(Anisotropic Conductive Paste)又はNCP(Non−Conductive Paste)等の熱硬化性接着材を塗布又は貼着(以下、単に付着という。)した基板にチップを仮圧着し、次いで、それを本圧着することが広く実施されている。
【0003】
すなわち、チップを上方のヘッドで保持すると共に熱硬化性接着材が付着された基板を下方の基板保持ステージで支持又は保持(以下、単に保持という。)し、そして、チップと基板とを位置合わした(以下、単にアライメントという。)後、ヘッドを降下させて仮圧着し、次いで、それを次工程へ搬送し、かつ、他のヘッドを降下させて本圧着している。このように、仮圧着、本圧着といった二段階の圧着工程を経て実装している。
【0004】
【発明が解決しようとする課題】
ところが、仮圧着は、一般に例えば、熱硬化性接着材の硬化を目的としない範囲の加熱温度が約60℃、加圧力が約0.2MPa、加圧時間が約0.5秒といった条件下で行われるのに対し、本圧着は、例えば、熱硬化性接着材の硬化を目的とする範囲の加熱温度が約220℃、加圧力が約1MPa、加圧時間が約20秒といった条件下で行われる為に、アライメントした後で所定位置に仮圧着しても、本圧着時の高温加熱・高加圧力といった過酷な条件下においては、チップ及び/又は基板が伸縮してチップと基板との位置ずれが発生し易く、かつ、このような位置ずれの発生は、チップと基板との電気的接続を不安定にするから、品質上好ましくない。また、本圧着時にチップが伸縮するが、その伸縮方向がチップの中心に対して均一に伸縮するとは限らない。
【0005】
なお、仮圧着に比して本圧着に要する時間が数十倍長い為に、アイドル時間を省いて生産性の向上を図る観点からして仮圧着、本圧着といった二段階の圧着工程を経て実装するようにしているが、たとえ、仮圧着をしないで直接、本圧着するようにしても、上述の位置ずれが発生するから、これでは問題解決にならない。
【0006】
本発明は、このようなことに鑑みて発明されたものであって、その目的は、本圧着に際し、チップと基板との位置ずれが発生するのを防止して高品質の実装製品を得ることができるようにすることである。
【0007】
【課題を解決するための手段】
上記目的を達成する為に、本発明においては、請求項1,2に記載するように、アライメントに先立ってチップのみ又はチップ及び基板を所定に加熱して伸縮させ、かつ、その後においてアライメントした上で熱硬化性接着材をチップのみ又はチップ及び基板の復元を阻止可能な半硬化状態にさせるように本圧着時の加熱温度と同じ加熱温度で加熱し、本圧着時の加圧力と同じ加圧力で加圧し、より具体的には、硬化率が約30%〜50%になるように加熱して仮圧着している。
【0008】
【発明の実施の形態】
図1において示されているチップ実装装置は、上方のヘッド1と、下方の基板保持ステージ2と、二視野の認識手段3とを備え、そして、ヘッド1は、ブロック4にツール5を装着して構成される。
【0009】
なお、ブロック4は、図示されていない上方のヘッド昇降装置に装着されている。また、ツール5は、ヒータ6を備えていると共にその下端面に開口されている吸気孔(図示されていない)でチップ7を吸着、すなわち、真空吸着によって保持し得るように設けられている。
【0010】
一方、基板保持ステージ2は、図示されていない可動テーブル装置に装着されてX軸方向、Y軸方向又はXY両軸方向へ移動(以下、単に平行移動という。)し得ると共に回転し得るように設けられている。また、ヒータ8を備えていると共にその上端面に開口されている吸気孔(図示されていない)で基板9を吸着、すなわち、真空吸着によって保持し得るように設けられている。
【0011】
更に、二視野の認識手段3は、ヘッド1のツール5に保持されているチップ7に設けられている認識マークA1,A2(図2参照)を認識する第1認識手段10と、基板保持ステージ2に保持されている基板9に設けられている認識マークB1,B2(図3参照)を認識する第2認識手段11とで構成され、かつ、図示されていない可動テーブルに装着されて平行移動及び昇降(Z軸方向へ移動)し得るように設けられている。なお、基板9に、ACF、NCF、ACP又はNCP等の熱硬化性接着材12が付着されている。
【0012】
よって、上方のヘッド1でチップ7を保持すると共に下方の基板保持ステージ2で基板9を保持し、そして、チップ7と基板9とを位置合わせ、すなわち、アライメントし、次いで、ヘッド1を降下させて基板9にチップ7を仮圧着することができる。
【0013】
その際、基板9を保持している基板保持ステージ2がチップ7を保持したヘッド1の下方へ移動されると、二視野の認識手段3が右側の退避位置からチップ7と基板9との間へ移動し、上側の第1認識手段10の光軸10aがチップ認識マークA1,A2を認識すると共に下側の第2認識手段10の光軸11aが基板認識マークB1,B2を認識する。
【0014】
そして、全てのマークの認識を終えると、二視野の認識手段3がそこから元の退避位置へ移動されると共に全てのマークの位置情報を演算して、認識マークA1は認識マークB1と、また、認識マークA2は認識マークB2と夫々合致させるように基板保持ステージ2が移動する。
【0015】
このようにしてチップ7と基板9とのアライメントを行うことができる。そして、かかるアライメントに引き続いて仮圧着が行われるが、この仮圧着においては、熱硬化性接着材12を半硬化、すなわち、硬化率が約30%〜50%になるように加熱する。
【0016】
なお、この加熱制御は、ヘッド1のヒータ6(ヘッド側のヒータ)のみを作動させて行われるが、熱硬化性接着材12を半硬化させる為には、例えば、加熱温度が約220℃、加圧力が約1MPa、加圧時間が約1秒の条件下で仮圧着すればよい。
【0017】
すなわち、加熱温度(約220℃)及び加圧力(約1MPa)は、次工程の本圧着のそれらと同一であるが、加圧時間を所定時間に短縮することによって熱硬化性接着材12の硬化率を約30%〜50%にすることができる。
【0018】
以下、熱硬化性接着材12の硬化率が約30%〜50%にせしめられた仮圧着実装体は、次工程において本圧着されるが、ここにおいては、図示されていない基板保持ステージに保持されている仮圧着実装体の上方からヘッドを降下させて熱圧着する。例えば、加熱温度が約220℃、加圧力が約1MPa、加圧時間が約20秒といった条件下で行えばよい。これにより、熱硬化性接着材12の硬化率を100%、すなわち、完全に硬化させることができる。
【0019】
このように、本発明においては、仮圧着時に熱硬化性接着材を、チップの復元を阻止可能な半硬化状態にさせるように加熱する。その為、仮圧着実装体のチップは、伸縮し難い状態に仮固着されている。本圧着と同じ温度でチップを伸縮させた後、アライメントしている。
【0020】
従って、本圧着時の高温加熱・高加圧力といった過酷な条件下においても、チップが伸縮して基板との位置ずれが発生するのを防止することができて高品質の実装製品を得ることができる。
【0021】
なお、本発明においては、仮圧着時における熱硬化性接着材の半硬化加熱を、上述の例のようにヘッド1のヒータ6(ヘッド側のヒータ)のみを作動させて行うこと以外に、基板保持ステージ2のヒータ8(基板側のヒータ)のみを作動させて行ってもよく、更に、ヘッド1のヒータ6(ヘッド側のヒータ)及び基板保持ステージ2のヒータ8(基板側のヒータ)の両方を作動させて行ってもよい。
【0022】
また、本発明においては、チップ7が熱影響によって伸縮し易い特性を有しているもの、例えば、フィルム(FPC)やフィルムテープキャリアパッケージ(TCP)などの場合においては、仮圧着に先立ってのアライメント(チップ7と基板9との位置合わせ)は、ヘッド1のヒータ6(ヘッド側のヒータ)を作動させて保持しているチップ7を加熱して伸縮させた後で行うのが好ましい。
【0023】
また、基板9は、一般には、熱影響を受け難い基板、例えば、ガラス基板やセラミック基板等が選択されるが、そのような基板と異なり熱影響を受け易い特性を有している場合においては、仮圧着に先立ってのアライメントは、基板保持ステージ2のヒータ8(基板側のヒータ)を作動させて保持している基板9を加熱して伸縮させた後で行うのが好ましい。
【0024】
また、チップ7及び基板9の両方が熱影響を受け易い特性を有している場合においては、ヘッド1のヒータ6(ヘッド側のヒータ)及び基板保持ステージ2のヒータ8(基板側のヒータ)の両方を作動させて保持しているチップ7及び基板9を加熱して伸縮させた後でアライメントを行うのが好ましい。
【0025】
このように、チップ7及び/又は基板9を伸縮をさせた後においてアライメントを行うことによって、一段と高精度にアライメントすることができ、しかも、本圧着と略同一の加熱条件によってチップ7及び/又は基板9を予め伸縮させている為に、次工程の本圧着時における高温加熱・高加圧といった過酷条件の影響を緩和することができ、従って、高精度に本圧着することができて高品質化を図ることができる。
【0026】
なお、図4に基づいて、ヘッド1のヒータ6(ヘッド側のヒータ)及び基板保持ステージ2のヒータ8(基板側のヒータ)の両方を作動させて保持しているチップ7及び基板9を加熱して伸縮させる例について述べると、ヘッド1がチップ7を吸着保持した時点においては、チップ7はLの長さ(図5参照)になっているが、ヒータ6が作動して加熱すると±αだけ伸縮する。このような伸縮は、一般に、加熱温度が220℃、加熱時間が約0.5〜1秒で惹起される。
【0027】
一方、基板9についても、これが基板保持ステージ2に保持された時点においては、Mの長さ(図6参照)になっているが、ヒータ8が作動して加熱すると±βだけ伸縮する。これは、一般に、加熱温度が220℃、加熱時間が約1〜3秒で惹起される。
【0028】
その為、このよう伸縮を無視したのでは、高精度にアライメントすることができない、すなわち、基板9のパッド9a,9bとチップ7のバンプ7a,7bとを位置ずれしていないように正確に整合させることが困難になる。
【0029】
しかし、本発明においては、上述のように、伸縮をさせた後でアライメントするようにしているので、そのような問題が発生するのを防止することができる。
【0030】
加えて、その際、ヘッド1のヒータ6(ヘッド側のヒータ)及び基板保持ステージ2のヒータ8(基板側のヒータ)の加熱制御を、二視野の認識手段3で認識マークA1,A2及び認識マークB1,B2を認識し、その認識結果に基づいてチップ7及び基板9の伸縮量又は伸縮率を一定に保つようにしている。
【0031】
すなわち、上記認識に基づいてチップ7及び基板9の伸縮量又は伸縮率を演算してヒータ6,8を制御することによってチップ7及び基板9の伸縮量又は伸縮率を一定に保つようにしている。その為、より正確にアライメントすることができる。
【0032】
なお、その場合における両ヒータ6,8のフィードバック制御は、毎回行ってもよいと共に、チップ7や基板9のアライメント回数に対して数個に1回、数十個に1回など間欠的に行ってもよい。また、間欠的にフィードバック制御を行う場合、装置は前回(現在)のフィードバック制御データを記憶しておき、次のフィードバック制御にてデータを更新する。
【0033】
以上において、本発明においていう「チップ」とは、例えば、フィルム(FPC)、フィルムテープキャリアパッケージ(TCP)、ICチップ、半導体チップ、光素子、表面実装部品、チップ、ウエハなど、その種類や大きさに関係なく、基板に対して接合せしめる方の物(ワーク)をいう。
【0034】
また、「基板」とは、例えば、樹脂基板、ガラス基板、フィルム基板、チップ、ウエハなど、その種類や大きさに関係なく、チップが接合せしめる方の物(ワーク)をいう。
【0035】
また、「認識手段」とは、例えば、CCDカメラ、赤外線カメラ、X線カメラ、センサーなどであって、そのその種類や大きさに関係なく、認識マークを認識し得るものであれば、いかなる形態の手段であってもよい。
【0036】
また、「認識マーク」とは、孔、溝、印刷マークなどであって、その大きさや種類及びキャリブレーションやアライメントなどの特定の目的だけに利用されるものに限定されず、兼用のものであってもよい。
【0037】
また、「チップ保持手段」とは、吸気孔による吸着保持手段、静電気による静電保持手段、磁石や磁気などによる磁気保持手段、複数又は単数の可動ツメによってチップを掴む又は押さえる機械的手段などであって、いかなる形態の保持手段であってもよい。
【0038】
また、「基板保持手段」とは、同様に、吸気孔による吸着保持手段、静電気による静電保持手段、磁石や磁気などによる磁気保持手段、複数又は単数の可動ツメによってチップを掴む又は押さえる機械的手段などであって、いかなる形態の保持手段であってもよい。
【0039】
また、「ヘッド」は、昇降制御し得るように装着することだけに限定されず、固定、平行移動制御、回転制御、昇降制御及び平行移動制御、昇降制御及び回転制御、昇降制御及び平行移動制御及び回転制御、平行移動制御及び回転制御など、各種態様に制御可能に装着することができる。
【0040】
また、「基板保持ステージ」は、平行移動制御及び回転制御し得るように装着することに限定されず、固定、回転制御、昇降制御、平行移動制御、昇降制御及び平行移動制御、昇降制御及び平行移動制御及び回転制御、回転制御及び昇降制御など、各種態様に制御可能に装着することができる。
【0041】
また、「認識手段」は、平行移動制御及び昇降制御し得るように装着することに限定されず、固定、平行移動制御、回転制御、昇降制御、平行移動制御及び回転制御、平行移動制御及び回転制御及び昇降制御、回転制御及び昇降制御など、各種態様に制御可能に装着することができる。
【0042】
また、二視野の認識手段を構成している第1認識手段と第2認識手段を分離して各々が別々に動作又は同時同方向に動作させるように設けてもよい。更に、アライメント時、認識手段の光軸が透過可能な基板を用いる場合、認識手段は基板の下側から基板認識マークとチップ認識マークを認識する構成に設けてもよい。
【0043】
また、チップに設けられた「バンプ」とは、例えば、ハンダバンプ、スタッドバンプなど、基板に設けられているパッドと接合される方の手段をいう。
【0044】
また、基板に設けられた「パッド」とは、例えば、電気配線された電極、電気配線がされていないダミー電極など、チップに設けられているバンプと接合合される方の手段をいう。
【0045】
【発明の効果】
上述のように、本発明によると、本圧着に際し、チップと基板との位置ずれが発生するのを防止し得て高品質の実装製品を得ることができる。
【図面の簡単な説明】
【図1】チップ実装態様を示す図である。
【図2】チップの平面図である。
【図3】基板の平面図である。
【図4】チップ及び基板を伸縮させる為の加熱制御態様を示す図である。
【図5】ヘッドがチップを保持している姿を示す拡大図である。
【図6】基板保持ステージが基板を保持している姿を示す拡大図である。
【符号の説明】
1:ヘッド
2:基板保持ステージ
3:二視野の認識手段
6:ヒータ(ヘッド側ヒータ)
7:チップ
7a,7b:バンプ
8:ヒータ(基板側ヒータ)
9:基板
9a,9b:パッド
12:熱硬化性接着材
A1,A2,B1,B2:認識マーク
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip mounting method.
[0002]
[Prior art]
Conventionally, as is well known, an ACF (Anisotropic Conductive Film), NCF (Non-Conductive Film), ACP (Anisotropic Conductive Paste), NCP (Non-Conductive Paste) or other hardening material such as NCP (Non-Conductive Paste) is used. It is widely practiced that a chip is temporarily pressure-bonded to a substrate that is simply attached), and then main-bonded to the chip.
[0003]
That is, the chip is held by the upper head, and the substrate to which the thermosetting adhesive is attached is supported or held (hereinafter simply referred to as holding) by the lower substrate holding stage, and the chip and the substrate are aligned. was allowed (hereinafter, simply. as alignment) after it lowers the head temporary pressure bonding, it is then conveyed to the next step, and are pressure bonding by lowering the other heads. In this way, mounting is performed through a two-stage crimping process such as temporary crimping and main crimping.
[0004]
[Problems to be solved by the invention]
However, provisional pressure bonding is generally performed under conditions such as a heating temperature of about 60 ° C., a pressing force of about 0.2 MPa, and a pressing time of about 0.5 seconds, which are not intended to cure a thermosetting adhesive. On the other hand, the main pressure bonding is performed under the conditions such that the heating temperature in the range for curing the thermosetting adhesive is about 220 ° C., the applied pressure is about 1 MPa, and the pressing time is about 20 seconds. Therefore, even if it is temporarily crimped in place after alignment, the chip and / or substrate will expand and contract under severe conditions such as high-temperature heating and high pressure during final crimping. Deviation is likely to occur, and the occurrence of such a positional deviation is not preferable in terms of quality because the electrical connection between the chip and the substrate becomes unstable. In addition, the chip expands and contracts during the main press bonding, but the expansion and contraction direction does not always expand and contract uniformly with respect to the center of the chip.
[0005]
In addition, since the time required for the main pressure bonding is tens of times longer than the temporary pressure bonding, it is mounted through a two-step pressure bonding process such as temporary pressure bonding and main pressure bonding from the viewpoint of improving productivity by omitting idle time. However, even if the main pressure bonding is performed directly without performing the temporary pressure bonding, the above-described positional deviation occurs, so this does not solve the problem.
[0006]
The present invention has been invented in view of the above, and an object of the present invention is to obtain a high-quality mounting product by preventing occurrence of misalignment between the chip and the substrate at the time of final press bonding. Is to be able to.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, as described in claims 1 and 2, prior to alignment, only the chip or the chip and the substrate are heated and expanded to a predetermined extent, and then aligned. in the thermosetting adhesive is heated at the same heating temperature and heating temperature during the crimping so as to tip only or chips and restoration of the substrate to the semi-cured state can be prevented, the same pressure as the pressure applied during the bonding in pressurized, more specifically, curing rate is temporarily pressure bonded by heating to be about 30% to 50%.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The chip mounting apparatus shown in FIG. 1 includes an upper head 1, a lower substrate holding stage 2, and a two-field recognition means 3, and the head 1 mounts a tool 5 on a block 4. Configured.
[0009]
The block 4 is mounted on an upper head lifting device (not shown). The tool 5 includes a heater 6 and is provided so that the chip 7 can be held by suction, that is, by vacuum suction, through an intake hole (not shown) opened at the lower end surface thereof.
[0010]
On the other hand, the substrate holding stage 2 is mounted on a movable table device (not shown) so that it can move in the X-axis direction, the Y-axis direction, or both XY-axis directions (hereinafter simply referred to as parallel movement) and rotate. Is provided. In addition, the heater 9 is provided and is provided so that the substrate 9 can be held by suction, that is, by vacuum suction, through an intake hole (not shown) opened at the upper end surface thereof.
[0011]
Further, the two-field recognition means 3 includes a first recognition means 10 for recognizing recognition marks A1 and A2 (see FIG. 2) provided on the chip 7 held by the tool 5 of the head 1, and a substrate holding stage. 2 and second recognition means 11 for recognizing the recognition marks B1 and B2 (see FIG. 3) provided on the substrate 9 held by 2 and mounted on a movable table (not shown) for translation. And can be moved up and down (moved in the Z-axis direction). A thermosetting adhesive material 12 such as ACF, NCF, ACP or NCP is attached to the substrate 9.
[0012]
Accordingly, the chip 7 is held by the upper head 1 and the substrate 9 is held by the lower substrate holding stage 2, and the chip 7 and the substrate 9 are aligned, that is, aligned , and then the head 1 is lowered. Thus, the chip 7 can be temporarily bonded to the substrate 9.
[0013]
At that time, when the substrate holding stage 2 holding the substrate 9 is moved below the head 1 holding the chip 7, the two-field recognition means 3 moves between the chip 7 and the substrate 9 from the retreat position on the right side. The optical axis 10a of the upper first recognition means 10 recognizes the chip recognition marks A1, A2, and the optical axis 11a of the lower second recognition means 10 recognizes the substrate recognition marks B1, B2.
[0014]
When the recognition of all the marks is completed, the recognition means 3 for the two fields of view is moved from there to the original retracted position and the position information of all the marks is calculated so that the recognition mark A1 becomes the recognition mark B1. The substrate holding stage 2 moves so that the recognition mark A2 and the recognition mark B2 respectively match.
[0015]
In this way, alignment between the chip 7 and the substrate 9 can be performed. Subsequent to this alignment, temporary pressure bonding is performed. In this temporary pressure bonding, the thermosetting adhesive 12 is semi-cured, that is, heated so that the curing rate is about 30% to 50%.
[0016]
This heating control is performed by operating only the heater 6 of the head 1 (the heater on the head side). In order to semi-cure the thermosetting adhesive 12, for example, the heating temperature is about 220 ° C., What is necessary is just to temporarily press-bond on the conditions whose pressurization pressure is about 1 MPa and pressurization time is about 1 second.
[0017]
That is, the heating temperature (about 220 ° C.) and the applied pressure (about 1 MPa) are the same as those of the main press bonding in the next step, but the thermosetting adhesive 12 is cured by shortening the pressing time to a predetermined time. The rate can be about 30% to 50%.
[0018]
Hereinafter, the temporary press-bonded mounting body in which the curing rate of the thermosetting adhesive 12 is set to about 30% to 50% is finally pressed in the next step, but here, it is held on a substrate holding stage (not shown). The head is lowered from above the pre-bonded mounting body, and thermocompression bonding is performed. For example, the heating temperature is about 220 ° C., the applied pressure is about 1 MPa, and the pressurization time is about 20 seconds. Thereby, the cure rate of the thermosetting adhesive 12 can be 100%, that is, completely cured.
[0019]
Thus, in this invention, it heats so that a thermosetting adhesive material may be made into the semi-hardened state which can prevent the decompression | restoration of a chip | tip at the time of temporary pressing. For this reason, the chip of the temporary press-bonded mounting body is temporarily fixed in a state where it is difficult to expand and contract. After the chip is expanded and contracted at the same temperature as the main press bonding, alignment is performed.
[0020]
Therefore, even under harsh conditions such as high-temperature heating and high pressurizing force during main bonding, it is possible to prevent the chip from expanding and contracting and generating a positional deviation from the substrate, and to obtain a high-quality mounting product. it can.
[0021]
In the present invention, in addition to performing the semi-curing heating of the thermosetting adhesive at the time of pre-bonding by operating only the heater 6 (head heater) of the head 1 as in the above example, the substrate Only the heater 8 (substrate side heater) of the holding stage 2 may be operated, and further, the heater 6 (head side heater) of the head 1 and the heater 8 (substrate side heater) of the substrate holding stage 2 may be operated. Both may be activated.
[0022]
Further, in the present invention, in the case where the chip 7 has a characteristic that easily expands and contracts due to the influence of heat, for example, a film (FPC) or a film tape carrier package (TCP), it is necessary to perform prior to the temporary pressure bonding. The alignment (positioning of the chip 7 and the substrate 9) is preferably performed after the chip 7 held by operating the heater 6 (head side heater) of the head 1 is heated and expanded.
[0023]
The substrate 9 is generally a substrate that is not easily affected by heat, such as a glass substrate or a ceramic substrate. However, unlike such a substrate, the substrate 9 has characteristics that are easily affected by heat. The alignment prior to the temporary pressure bonding is preferably performed after the substrate 9 held by operating the heater 8 (substrate side heater) of the substrate holding stage 2 is heated and stretched.
[0024]
When both the chip 7 and the substrate 9 are susceptible to thermal influence, the heater 6 of the head 1 (head heater) and the heater 8 of the substrate holding stage 2 (substrate heater) It is preferable to perform alignment after the chip 7 and the substrate 9 that are held by operating both are heated and stretched.
[0025]
Thus, by performing alignment after expanding and contracting the chip 7 and / or the substrate 9, alignment can be performed with higher accuracy, and the chip 7 and / or under the heating conditions substantially the same as the main pressure bonding. Since the substrate 9 is expanded and contracted in advance, the influence of severe conditions such as high temperature heating and high pressurization at the time of the final press bonding in the next process can be mitigated, so that the main press bonding can be performed with high accuracy and high quality. Can be achieved.
[0026]
In addition, based on FIG. 4, the chip | tip 7 and the board | substrate 9 which hold | maintain by operating both the heater 6 (head side heater) of the head 1 and the heater 8 (substrate side heater) of the board | substrate holding | maintenance stage 2 are heated. When an example of expanding and contracting is described, when the head 1 sucks and holds the chip 7, the chip 7 is L length (see FIG. 5), but when the heater 6 is activated and heated, ± α Only stretches. Such expansion and contraction is generally caused when the heating temperature is 220 ° C. and the heating time is about 0.5 to 1 second.
[0027]
On the other hand, when the substrate 9 is held on the substrate holding stage 2, the length is M (see FIG. 6), but when the heater 8 is activated and heated, it expands and contracts by ± β. This is generally caused when the heating temperature is 220 ° C. and the heating time is about 1 to 3 seconds.
[0028]
Therefore, if the expansion and contraction is ignored in this way , alignment cannot be performed with high accuracy, that is, the pads 9a and 9b of the substrate 9 and the bumps 7a and 7b of the chip 7 are not misaligned. It becomes difficult to align.
[0029]
However, in the present invention, as described above, alignment is performed after the expansion and contraction, so that such a problem can be prevented from occurring.
[0030]
In addition, at this time, the heating control of the heater 6 of the head 1 (head heater) and the heater 8 of the substrate holding stage 2 (substrate heater) is performed by the recognition means 3 with two fields of view and the recognition marks A1, A2 and recognition. The marks B1 and B2 are recognized, and the expansion amount or expansion ratio of the chip 7 and the substrate 9 is kept constant based on the recognition result.
[0031]
That is, the expansion amount or expansion ratio of the chip 7 and the substrate 9 is calculated based on the above recognition and the heaters 6 and 8 are controlled to keep the expansion amount or expansion ratio of the chip 7 and the substrate 9 constant. . Therefore, alignment can be performed more accurately.
[0032]
In this case, the feedback control of the heaters 6 and 8 may be performed every time, and is performed intermittently, such as once every several times or once every several tens of times with respect to the number of alignments of the chip 7 and the substrate 9. May be. When performing feedback control intermittently, the apparatus stores the previous (current) feedback control data and updates the data in the next feedback control.
[0033]
In the above, the “chip” in the present invention refers to, for example, the type and size of a film (FPC), a film tape carrier package (TCP), an IC chip, a semiconductor chip, an optical element, a surface mount component, a chip, a wafer, and the like. Regardless of the size, it refers to the object (work) to be bonded to the substrate.
[0034]
The “substrate” refers to an object (work) to which the chip can be bonded regardless of its type and size, such as a resin substrate, a glass substrate, a film substrate, a chip, and a wafer.
[0035]
Further, the “recognition means” is, for example, a CCD camera, an infrared camera, an X-ray camera, a sensor, etc., and can take any form as long as it can recognize a recognition mark regardless of its type and size. It may be the means.
[0036]
The “recognition mark” is a hole, a groove, a print mark, etc., and is not limited to a size and type, and used only for a specific purpose such as calibration or alignment. May be.
[0037]
“Chip holding means” means suction holding means by suction holes, electrostatic holding means by static electricity, magnetic holding means by magnets or magnetism, mechanical means for gripping or holding the chip by a plurality or a single movable claw, etc. Any holding means may be used.
[0038]
Similarly, the “substrate holding means” is a mechanical means for holding or holding a chip by means of suction holding means by suction holes, electrostatic holding means by static electricity, magnetic holding means by magnets or magnetism, or a plurality or a single movable claw. Any form of holding means may be used.
[0039]
In addition, the “head” is not limited to being mounted so as to be able to perform elevation control, but is fixed, parallel movement control, rotation control, elevation control and parallel movement control, elevation control and rotation control, elevation control and parallel movement control. In addition, it can be controllably mounted in various modes such as rotation control, parallel movement control, and rotation control.
[0040]
Further, the “substrate holding stage” is not limited to be mounted so as to be able to perform parallel movement control and rotation control, but is fixed, rotation control, lift control, parallel movement control, lift control and parallel movement control, lift control and parallel control. It can be mounted controllably in various modes such as movement control, rotation control, rotation control, and elevation control.
[0041]
Further, the “recognition means” is not limited to be mounted so as to be able to perform parallel movement control and elevation control, but is fixed, parallel movement control, rotation control, elevation control, parallel movement control and rotation control, parallel movement control and rotation. It can be controllably mounted in various modes such as control and lift control, rotation control and lift control.
[0042]
Further, the first recognition means and the second recognition means constituting the two-field recognition means may be separated so that each operates separately or simultaneously in the same direction. Further, when using a substrate through which the optical axis of the recognition means can be transmitted during alignment, the recognition means may be provided to recognize the substrate recognition mark and the chip recognition mark from the lower side of the substrate.
[0043]
The “bump” provided on the chip refers to a means to be bonded to a pad provided on the substrate, such as a solder bump or a stud bump.
[0044]
In addition, the “pad” provided on the substrate refers to a means to be bonded to a bump provided on the chip, such as an electrically wired electrode or a dummy electrode not electrically wired.
[0045]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the positional deviation between the chip and the substrate from occurring during the main press bonding, and to obtain a high-quality mounting product.
[Brief description of the drawings]
FIG. 1 is a diagram showing a chip mounting mode.
FIG. 2 is a plan view of a chip.
FIG. 3 is a plan view of a substrate.
FIG. 4 is a diagram showing a heating control mode for expanding and contracting a chip and a substrate.
FIG. 5 is an enlarged view showing a state in which a head holds a chip.
FIG. 6 is an enlarged view showing a state in which the substrate holding stage holds the substrate.
[Explanation of symbols]
1: Head 2: Substrate holding stage 3: Two-field recognition means 6: Heater (head heater)
7: Chips 7a, 7b: Bump 8: Heater (substrate side heater)
9: Substrate 9a, 9b: Pad 12: Thermosetting adhesive A1, A2, B1, B2: Recognition mark

Claims (3)

チップを上方のヘッドで保持すると共に熱硬化性接着材が付着された基板を下方の基板保持ステージで保持し、前記チップと前記基板とを位置合わした後、前記ヘッドを降下させて前記チップを前記基板に仮圧着し、次いで、本圧着するチップ実装方法において、前記チップと前記基板との位置合わせを、前記ヘッドに装着されたヘッド側ヒータで前記チップを加熱して伸縮させた後において行うと共に前記仮圧着時に、前記チップの復元を阻止可能な半硬化状態にさせるように前記ヘッド側ヒータで前記熱硬化性接着材を本圧着時の加熱温度と同じ加熱温度で加熱し、本圧着時の加圧力と同じ加圧力で加圧することを特徴とするチップ実装方法。The substrate thermosetting adhesive material is deposited and held below the substrate holding stage, after the Align position and the said chip substrate, said lowered the head chip holds the chip above the head In the chip mounting method in which the chip is temporarily bonded to the substrate and then finally bonded, the alignment between the chip and the substrate is performed by heating and expanding and contracting the chip with a head-side heater mounted on the head. During the temporary pressing, the thermosetting adhesive is heated at the same heating temperature as the main pressing by the head side heater so that the chip is prevented from being restored in a semi-cured state. chip mounting method which is characterized in that the pressure at the same pressure as the pressure of time. チップを上方のヘッドで保持すると共に熱硬化性接着材が付着された基板を下方の基板保持ステージで保持し、前記チップと前記基板とを位置合わした後、前記ヘッドを降下させて前記チップを前記基板に仮圧着し、次いで、本圧着するチップ実装方法において、前記チップと前記基板との位置合わせを、前記ヘッドに装着されたヘッド側ヒータで前記チップを加熱して伸縮させると共に基板保持ステージに装着された基板側ヒータで前記基板を加熱して伸縮させた後において行い、かつ、前記仮圧着時に、前記チップ及び前記基板の復元を阻止可能な半硬化状態にさせるように前記ヘッド側ヒータ及び前記基板側ヒータの両方で前記熱硬化性接着材を本圧着時の加熱温度と同じ加熱温度で加熱し、本圧着時の加圧力と同じ加圧力で加圧することを特徴とするチップ実装方法。The substrate thermosetting adhesive material is deposited and held below the substrate holding stage, after the Align position and the said chip substrate, said lowered the head chip holds the chip above the head In the chip mounting method in which the chip is temporarily bonded to the substrate and then finally bonded, the alignment between the chip and the substrate is performed by heating and expanding and contracting the chip with a head-side heater mounted on the head and holding the substrate. Performing after heating and expanding / contracting the substrate with a substrate-side heater mounted on a stage, and at the time of temporary bonding, the head side is set to a semi-cured state capable of preventing restoration of the chip and the substrate heating said thermosetting adhesive material at the same heating temperature and the heating temperature during the crimping at both the heater and the substrate-side heater, to pressure at the same pressure as the pressure applied during the bonding Chip mounting wherein the. 前記ヘッド側ヒータ及び前記基板側ヒータの加熱制御を、前記チップに設けられている認識マークと前記基板に設けられている認識マークとを認識手段で認識し、その認識結果に基づいて前記チップ及び前記基板の伸縮量又は伸縮率を一定に保つように行うことを特徴とする請求項2に記載のチップ実装方法。  Recognizing the recognition mark provided on the chip and the recognition mark provided on the substrate is recognized by a recognition means for heating control of the head side heater and the substrate side heater, and based on the recognition result, the chip and 3. The chip mounting method according to claim 2, wherein the expansion and contraction rate or expansion ratio of the substrate is kept constant.
JP2000158878A 2000-05-29 2000-05-29 Chip mounting method Expired - Fee Related JP4311862B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000158878A JP4311862B2 (en) 2000-05-29 2000-05-29 Chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000158878A JP4311862B2 (en) 2000-05-29 2000-05-29 Chip mounting method

Publications (2)

Publication Number Publication Date
JP2001338946A JP2001338946A (en) 2001-12-07
JP4311862B2 true JP4311862B2 (en) 2009-08-12

Family

ID=18663279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000158878A Expired - Fee Related JP4311862B2 (en) 2000-05-29 2000-05-29 Chip mounting method

Country Status (1)

Country Link
JP (1) JP4311862B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102048902B1 (en) * 2019-07-26 2019-11-26 성우테크론 주식회사 manufacturing apparatus for micro light emitting diode module

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3966516B2 (en) * 2001-06-20 2007-08-29 東レエンジニアリング株式会社 Mounting method and apparatus
EP2221866B1 (en) * 2004-01-07 2020-08-12 Nikon Corporation Stacking apparatus and method for stacking integrated circuit elements
JP4982318B2 (en) * 2006-10-30 2012-07-25 セイコーインスツル株式会社 Electronic device manufacturing method and manufacturing apparatus thereof
JP2008177350A (en) * 2007-01-18 2008-07-31 Fujitsu Ltd Manufacturing method and manufacturing apparatus of electronic device
JP2008209961A (en) * 2007-02-23 2008-09-11 Fujitsu Ltd Production method of electronic apparatus, production method of electronic equipment mounted with electronic apparatus, and production method of article mounted with electronic apparatus
JP5854375B2 (en) * 2010-12-24 2016-02-09 ボンドテック株式会社 Joining apparatus and joining method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102048902B1 (en) * 2019-07-26 2019-11-26 성우테크론 주식회사 manufacturing apparatus for micro light emitting diode module

Also Published As

Publication number Publication date
JP2001338946A (en) 2001-12-07

Similar Documents

Publication Publication Date Title
CN109103117B (en) Apparatus for bonding semiconductor chips and method of bonding semiconductor chips
US20060016562A1 (en) Heating and pressurizing apparatus for use in mounting electronic components, and apparatus and method for mounting electronic components
JP2004031885A (en) Bonding method and apparatus therefor
JP3030201B2 (en) Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JP4311862B2 (en) Chip mounting method
JP6234277B2 (en) Crimping head, mounting apparatus and mounting method using the same
JPH07240435A (en) Manufacture of semiconductor package, mounting of semiconductor, and semiconductor mounting equipment
US6966964B2 (en) Method and apparatus for manufacturing semiconductor device
KR102221588B1 (en) Apparatus for Bonding Semiconductor Chip and Method for Bonding Semiconductor Chip
JP2004047670A (en) Flip-chip packaging method and flip-chip packaging apparatus
KR20210052774A (en) System for flip chip bonding and method for flip chip bonding using the same
JP2731383B2 (en) Component mounting structure and component mounting method
JP2794847B2 (en) Flip chip bonding apparatus and bonding method
JP3997838B2 (en) Driver IC crimping apparatus and crimping method
JP5098939B2 (en) Bonding apparatus and bonding method
JP4024458B2 (en) Method for mounting semiconductor device and method for manufacturing semiconductor device package
JP2004039802A (en) Method of manufacturing semiconductor device, and semiconductor manufacturing apparatus
JP6461822B2 (en) Semiconductor device mounting method and mounting apparatus
JP2002141373A (en) Method and apparatus for mounting semiconductor
JP2002009111A (en) Method for mounting semiconductor flip chip
JP2602389B2 (en) Component mounting method
JP2006229106A (en) Semiconductor device and method and apparatus for mounting the same
JP2002299376A (en) Bonding apparatus and bonding method
JP2015192104A (en) Semiconductor chip mounting method and semiconductor chip mounting device
JP2004259917A (en) Bonding method and device thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070308

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090312

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090414

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090512

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090512

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130522

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140522

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees