JP4310974B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

Info

Publication number
JP4310974B2
JP4310974B2 JP2002213498A JP2002213498A JP4310974B2 JP 4310974 B2 JP4310974 B2 JP 4310974B2 JP 2002213498 A JP2002213498 A JP 2002213498A JP 2002213498 A JP2002213498 A JP 2002213498A JP 4310974 B2 JP4310974 B2 JP 4310974B2
Authority
JP
Japan
Prior art keywords
wiring board
wiring
manufacturing
pattern
solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002213498A
Other languages
Japanese (ja)
Other versions
JP2004055952A (en
Inventor
健人 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP2002213498A priority Critical patent/JP4310974B2/en
Publication of JP2004055952A publication Critical patent/JP2004055952A/en
Application granted granted Critical
Publication of JP4310974B2 publication Critical patent/JP4310974B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、絶縁層上に電気配線を形成された配線基板の製造方法に関し、特に、半導体素子搭載用インターポーザ、プリント配線基板に用いられる配線基板の製造方法に関する。
【0002】
【従来の技術】
近年、半導体大規模集積回路(LSI)等の半導体素子ではトランジスターの集積度が高まり、その動作速度はクロック周波数で2GHzに達するものが、また、入出力端子数では2000を越えるものが出現するに至っている。
【0003】
半導体素子の入出力端子数増加の要求に対し、半導体素子の微細加工技術は年々進歩してきいるが、インターポーザあるいはプリント配線基板の微細化技術が追いついていないのが現状である。
【0004】
半導体素子の入出力端子数の増加にともない、インターポーザとの接続方法には、格子配列のフリップチップ接続が必要となってくる。
【0005】
インターポーザの接続端子が格子配列になると、格子の内側の端子から外側に配線を引き回す際、格子の外側の端子間に配線を通す必要がある。微細配線が形成できないと入出力端子数の増加に対応できなくなる。ひとつの手段として、端子径を小さくすることが考えられるが、ソルダーレジストの解像度並びにアライメント精度の制限から端子径を小さくするには限界が出てくる。このため、端子間により多くの配線を通すための微細化技術が要求される。
【0006】
一方、プリント配線基板においても、インターポーザ等搭載部品の高密度実装の要求が高まっている。はんだボールが格子状に配置されたBGA(Ball Grid Array)型やCSP(Chip Size Package)型インターポーザではインターポーザサイズの小型化の要求にともない、はんだボールの狭ピッチ化の方向にある。したがって、プリント配線基板上の接続パッド周辺部の配線にも、同様に微細化技術の要求が高まっている。
【0007】
現在、一般的に配線形成には、エッチングでパターンを形成するサブトラクティブ工法が採用されている。それに使われるエッチングレジストは、アルカリ水溶液で現像を行なうアルカリ現像タイプのフォトレジストが主流となっている。アルカリ現像タイプのレジストは溶剤現像タイプに比べ、防爆対策の必要もなく、非常に、扱い易い反面、親水性が高く、図2(a)に示すようにエッチング時に導体層とレジスト界面からエッチング液が浸透しやすくなり、配線上面の平坦幅が確保できず、微細なパターンが形成できないという問題点がある。すなわち、図2(b)に示す配線パターンの上部の幅(寸法A)が配線パターンの下部の幅(寸法B)より極めて小さい断面形状になってしまう。これでは、配線ピッチを狭くすることが困難となる。
【0008】
配線の微細化のために、セミアディティブ工法が用いられる場合がある。本工法では、絶縁層上の電気めっきの給電層を形成し、フォトレジストパターンを形成し、めっき液中でパターン開口部にめっきパターンを形成し、フォトレジストパターンを除去した後、エッチング液にて給電層を除去して配線パターンを形成する。しかし、本工法では給電層を薄く形成しないと、エッチング液にてパターン幅が制御できないこと、また、薄膜の給電層を形成するには、無電解めっきやスパッタによる成膜方法が一般的であるが、両方法とも配線の密着性がとれないという問題がある。さらに、サブトラクティブ工法に比べ、プロセスが長くなりコストが高くなるという問題がある。
【0009】
【発明が解決しようとする課題】
本発明は係る従来技術の問題点に鑑みてなされたもので、サブトラクティブ工法で微細配線の形成が可能な配線基板の製造方法を提供することを課題とする。
【0010】
【課題を解決するための手段】
本発明において上記課題を達成するために、請求項1の発明では絶縁層上の導体層にレジストパターンを形成し、ウエットエッチングにより配線を形成する配線基板の製造方法において、
アクリル樹脂系フォトレジストを用いて該レジストパターンを形成し、パターン形成後にカルボン酸をブロックするアルコール又は有機酸のアンモニウム塩を該レジストパターンの皮膜中に取り込ませることにより、パターン形成された該レジストの表面自由エネルギーを調整することを特徴とする配線基板の製造方法としたものである。
【0012】
また、請求項の発明では、該導体層が銅、または、銅合金からなることを特徴とする請求項に記載の配線基板の製造方法としたものである。
【0013】
また、請求項の発明では導体層を溶解する酸化剤溶液が水溶液であることを特徴とする請求項1又は2に記載の配線基板の製造方法としたものである。
【0014】
また、請求項の発明では該酸化剤溶液が塩化第2鉄あるいは塩化第2銅溶液であることを特徴とする請求項1からの何れかに記載の配線基板の製造方法としたものである。
【0015】
【発明の実施の形態】
本発明の配線基板について図1を用いて説明する。絶縁基板2上に導体層1に形成した基板(図1(a))を用い、導体層上にフォトレジスト膜3を形成する。(図1(b))。
【0016】
所定のパターンを有するフォトマスクを用い露光、現像を行ないフォトレジストパターン4を形成し(図1(c))、ポストベークを行なう。ここで用いられているフォトレジストはアルカリ水溶液で可溶なため、露光やポストベークによる架橋では、まだ、親水性成分が多く残る。
【0017】
本発明では、フォトレジストパターン形成後ポストベークした被膜の表面自由エネルギーが
0.1<γp<5.0 mN/m、
あるいは、
0.1<γh<10.0 mN/m
であるものであれば良い。ここで、γpは表面自由エネルギーの双極子相互作用成分、γhは水素結合成分を示す。
【0018】
フォトレジストの表面自由エネルギーは疎水成分であるγd、双極子相互作用成分γp、水素結合成分γhの合計で示される。このうち、親水性に関するγpとγhの値が上記の範囲以上にあると導体層とフォトレジスト膜の界面からエッチング液が浸透しやすくなり、寸法Aは寸法Bより小さくなり微細配線が形成できなくなる。一方、γpとγhの値が上記の範囲以下になるとフォトレジスト自体の塗工ができなくなる。
【0019】
さらには、
0.2<γp<1.0 mN/m、
あるいは、
0.2<γh<5.0 mN/m
であるとその作用は大きい。
【0020】
レジストの種類は上記γpやγhの値の範囲内であれば、感光性を有するフォトレジストでも印刷タイプのレジストでも構わない。また、アルカリ現像タイプのフォトレジストパターンのうち上記γpやγhの範囲以上である場合、ポストベーク温度をあげたり、ベーク時間を長くすることにより上記γpやγhの値の範囲に調整することも可能である。特に、ノボラック樹脂にナフトキノンジアジドを配合させたノボラック系フォトレジストを用いると効果がある。また、アルカリ可溶なアクリル系樹脂をバインダーとして用いるアクリル樹脂系フォトレジストでは、パターン形成後に、カルボン酸をブロックするようなアルコールや有機酸のアンモニウム塩を被膜中に取り込ませることも効果がある。一方、ポリビニルアルコールに重クロム酸塩を配合した水溶性フォトレジストでは、パターン形成後の硬膜処理に用いるクロム酸の濃度をあげたり、ポストベーク温度を高くすることで効果が出る。
【0021】
続いて、導体層1を溶解できる酸化剤溶液でエッチングを行ない配線パターン5を形成し(図1(d))、レジストパターン4を剥離して、本発明の配線基板を形成する(図1(e))。
【0022】
導体層金属は導電性を有するものであれば、何れを用いても構わないが、導体層金属とレジスト材料との密着性が界面のエッチング液の浸透にも影響を与える。レジスト材料との密着性の高い銅や銅合金を用いた場合のほうがエッチング液の浸透が押さえられ微細配線が形成できる。一方、密着性の悪いステンレスを用いると導体層とレジストパターン界面からエッチング液が浸透しやすくなり、配線断面形状が悪くなる。
【0023】
エッチング液である酸化剤溶液は、極性の高い水溶媒を用いた系のほうが効果が大きい。溶媒の極性が低いものを用いると、レジストの表面エネルギーが上記範囲にあっても、極性が低くなるにつれて、導体層とレジスト界面からエッチング液が浸透しやすくなる。酸化剤として塩化第二鉄や塩化第二銅を用いた水溶液が液の粘度が高く、同様に浸透しにくく、微細なパターンが形成可能である。
【0024】
【実施例】
以下に実施例を説明する。
【0025】
多層配線基板の製造方法の実施の形態を、図1の(a)〜(e)の流れに従って説明する。
【0026】
ポリイミド基板2上に18μm厚の電解銅箔1を貼り合わせた基板を用い(図1(a)、アルカリ現像タイプアクリル樹脂系フォトレジストをロールコータで5μm塗布し乾燥した(図1(b))。所定のパターンを有するフォトマスクを用い露光、現像を行ないレジストパターン4を形成した(図1(c))。
【0027】
その後、ポストベークを130℃、30分行ない、さらに、2J/cm2の後露光を行なった。このとき、フォトレジスト表面の表面自由エネルギーを標準溶液の接触角から求めた。標準溶液として、水(γd=29.1、γp=1.3、γh42.4mN/m)、ジヨウドメチル(γd=46.8、γp=4.0、γh=0mN/m)、α−ブロモナフタレン(γd=44.4、γp=0.2、γh=0mN/m)を用い、22℃の恒温室にてフォトレジスト表面上の接触角を共和界面化学(株)製接触角測定装置にて測定した。得られた接触角θ並びに標準溶液のγ値を用い、以下の式から、フォトレジストの表面自由エネルギーを算出した。
【0028】
γL(1+COSθ)=2(γLd・γRd)1/2↑+2(γLp・γRp)1/2↑+2(γLh・γRh)1/2↑
【0029】
ここで、γLは標準溶液の表面自由エネルギー、γRはフォトレジストの表面自由エネルギーを示す。計算の結果、γpは0.8mN/m、γhは3.2mN/mであった。
【0030】
ボーメ度40°の塩化第二鉄水溶液を用い、50℃でスプレーエッチングを行ない、配線パターン5を形成した(図1(d))。最後に、レジストパターン4を剥離して、本発明の配線基板を得た。配線幅40μmの寸法を測定したところ、配線上部幅(寸法A)は38μm、配線下部幅(寸法B)は40μmであった。
【0031】
【発明の効果】
本発明は、レジストパターンの表面自由エネルギーのうち親水性成分に関係するγpとγhを低くすることにより導体層とレジスト界面からのエッチング液の浸透を押さえることができ、微細な配線を形成することができるという効果がある。
【0032】
【図面の簡単な説明】
【図1】本発明の配線基板の製造方法を示す断面図。
【図2】従来の配線基板を示す断面図。
【符号の説明】
1…導体層
2…絶縁層
3…レジスト膜
4…レジストパターン
5…配線パターン
6…エッチング液
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board in which electrical wiring is formed on an insulating layer, and more particularly to a method for manufacturing a wiring board used for a semiconductor element mounting interposer and a printed wiring board.
[0002]
[Prior art]
In recent years, in semiconductor elements such as semiconductor large-scale integrated circuits (LSIs), the degree of integration of transistors has increased, and the operation speed has reached 2 GHz as the clock frequency, and the number of input / output terminals has exceeded 2000. Has reached.
[0003]
In response to the demand for an increase in the number of input / output terminals of a semiconductor element, the microfabrication technology of the semiconductor element has progressed year by year, but the current situation is that the miniaturization technique of the interposer or the printed wiring board has not caught up.
[0004]
As the number of input / output terminals of a semiconductor element increases, a method for connecting to an interposer requires a flip chip connection in a lattice arrangement.
[0005]
When the connection terminals of the interposer are arranged in a grid, it is necessary to pass the wiring between terminals outside the grid when routing the wiring from the terminals inside the grid to the outside. If fine wiring cannot be formed, it will not be possible to cope with an increase in the number of input / output terminals. As one means, it is conceivable to reduce the terminal diameter. However, there is a limit in reducing the terminal diameter due to limitations of the resolution and alignment accuracy of the solder resist. For this reason, a miniaturization technique for passing more wiring between terminals is required.
[0006]
On the other hand, the demand for high-density mounting of mounted components such as an interposer is also increasing in printed wiring boards. BGA (Ball Grid Array) type and CSP (Chip Size Package) type interposers in which solder balls are arranged in a grid form are in the direction of narrowing the pitch of solder balls in accordance with the demand for miniaturization of the interposer size. Accordingly, there is an increasing demand for miniaturization technology for wiring around the connection pad on the printed wiring board.
[0007]
Currently, a subtractive method of forming a pattern by etching is generally used for wiring formation. The etching resist used for this is mainly an alkali development type photoresist that is developed with an alkaline aqueous solution. Compared with solvent development type, alkali development type resists do not require explosion-proof measures and are very easy to handle, but have high hydrophilicity, and as shown in FIG. However, there is a problem that a flat width on the upper surface of the wiring cannot be secured and a fine pattern cannot be formed. In other words, the upper width (dimension A) of the wiring pattern shown in FIG. 2B has a cross-sectional shape that is extremely smaller than the lower width (dimension B) of the wiring pattern. This makes it difficult to reduce the wiring pitch.
[0008]
A semi-additive construction method may be used for miniaturization of wiring. In this method, an electroplating power supply layer is formed on the insulating layer, a photoresist pattern is formed, a plating pattern is formed in the pattern opening in the plating solution, the photoresist pattern is removed, and then the etching solution is used. The power supply layer is removed to form a wiring pattern. However, in this method, the pattern width cannot be controlled by the etching solution unless the power feeding layer is formed thin, and the electroless plating or sputtering film forming method is generally used to form a thin power feeding layer. However, both methods have a problem that the adhesion of the wiring cannot be taken. Furthermore, there is a problem that the process becomes longer and the cost becomes higher than the subtractive method.
[0009]
[Problems to be solved by the invention]
The present invention has been made in view of the problems of the related art, and it is an object of the present invention to provide a method of manufacturing a wiring board capable of forming fine wiring by a subtractive construction method.
[0010]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, in the invention of claim 1, in the method of manufacturing a wiring board, a resist pattern is formed on the conductor layer on the insulating layer, and wiring is formed by wet etching.
The resist pattern is formed using an acrylic resin-based photoresist, and after pattern formation, an alcohol or an organic acid ammonium salt that blocks carboxylic acid is incorporated into the film of the resist pattern, whereby the patterned resist is formed. A method for manufacturing a wiring board is characterized in that the surface free energy is adjusted .
[0012]
According to a second aspect of the present invention, there is provided the method for manufacturing a wiring board according to the first aspect, wherein the conductor layer is made of copper or a copper alloy.
[0013]
According to a third aspect of the present invention, there is provided the method for manufacturing a wiring board according to the first or second aspect, wherein the oxidant solution for dissolving the conductor layer is an aqueous solution.
[0014]
According to a fourth aspect of the present invention, in the method for manufacturing a wiring board according to any one of the first to third aspects, the oxidant solution is a ferric chloride or cupric chloride solution. is there.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The wiring board of the present invention will be described with reference to FIG. Using a substrate (FIG. 1A) formed on the conductor layer 1 on the insulating substrate 2, a photoresist film 3 is formed on the conductor layer. (FIG. 1 (b)).
[0016]
Exposure and development are performed using a photomask having a predetermined pattern to form a photoresist pattern 4 (FIG. 1C), and post-baking is performed. Since the photoresist used here is soluble in an alkaline aqueous solution, many hydrophilic components still remain in the crosslinking by exposure or post-baking.
[0017]
In the present invention, the surface free energy of the film post-baked after forming the photoresist pattern is 0.1 <γp <5.0 mN / m,
Or
0.1 <γh <10.0 mN / m
If it is what is. Here, γp represents a dipole interaction component of surface free energy, and γh represents a hydrogen bond component.
[0018]
The surface free energy of the photoresist is represented by the sum of γd, which is a hydrophobic component, dipole interaction component γp, and hydrogen bond component γh. Among these, if the values of γp and γh relating to hydrophilicity are in the above range, the etching solution easily penetrates from the interface between the conductor layer and the photoresist film, and the dimension A is smaller than the dimension B, making it impossible to form fine wiring. . On the other hand, if the values of γp and γh are below the above ranges, the photoresist itself cannot be applied.
[0019]
Moreover,
0.2 <γp <1.0 mN / m,
Or
0.2 <γh <5.0 mN / m
If it is, the effect is large.
[0020]
As long as the type of resist is within the range of the values of γp and γh, a photosensitive photoresist or a printing type resist may be used. In addition, when the alkali development type photoresist pattern is in the above range of γp or γh, it can be adjusted to the range of γp or γh by increasing the post-bake temperature or increasing the baking time. It is. In particular, it is effective to use a novolac-based photoresist in which naphthoquinone diazide is blended with a novolak resin. In addition, in an acrylic resin-based photoresist using an alkali-soluble acrylic resin as a binder, it is also effective to incorporate an alcohol or an organic acid ammonium salt that blocks carboxylic acid into the film after pattern formation. On the other hand, in a water-soluble photoresist in which dichromate is blended with polyvinyl alcohol, an effect can be obtained by increasing the concentration of chromic acid used for the hardening process after pattern formation or by increasing the post-bake temperature.
[0021]
Subsequently, etching is performed with an oxidant solution capable of dissolving the conductor layer 1 to form a wiring pattern 5 (FIG. 1D), and the resist pattern 4 is peeled off to form the wiring board of the present invention (FIG. e)).
[0022]
Any conductive layer metal may be used as long as it has conductivity, but the adhesion between the conductive layer metal and the resist material also affects the penetration of the etchant at the interface. When copper or copper alloy having high adhesion to the resist material is used, the penetration of the etching solution is suppressed and fine wiring can be formed. On the other hand, when stainless steel having poor adhesion is used, the etching solution easily penetrates from the interface between the conductor layer and the resist pattern, and the wiring cross-sectional shape is deteriorated.
[0023]
The oxidizing agent solution as an etching solution is more effective in a system using a highly polar aqueous solvent. When a solvent having a low polarity is used, even if the surface energy of the resist is within the above range, the etching solution easily penetrates from the conductor layer and the resist interface as the polarity decreases. An aqueous solution using ferric chloride or cupric chloride as an oxidant has a high viscosity, and is similarly difficult to penetrate, so that a fine pattern can be formed.
[0024]
【Example】
Examples will be described below.
[0025]
An embodiment of a method for manufacturing a multilayer wiring board will be described in accordance with the flow of FIGS.
[0026]
Using a substrate obtained by laminating an electrolytic copper foil 1 having a thickness of 18 μm on a polyimide substrate 2 (FIG. 1A), 5 μm of an alkali development type acrylic resin photoresist was applied by a roll coater and dried (FIG. 1B). Exposure and development were performed using a photomask having a predetermined pattern to form a resist pattern 4 (FIG. 1C).
[0027]
Thereafter, post-baking was performed at 130 ° C. for 30 minutes, and further post-exposure was performed at 2 J / cm 2 . At this time, the surface free energy of the photoresist surface was determined from the contact angle of the standard solution. As a standard solution, water (γd = 29.1, γp = 1.3, γh42.4 mN / m), diiodomethyl (γd = 46.8, γp = 4.0, γh = 0 mN / m), α-bromonaphthalene (Γd = 44.4, γp = 0.2, γh = 0 mN / m), and the contact angle on the photoresist surface was measured with a contact angle measuring device manufactured by Kyowa Interface Chemical Co., Ltd. in a constant temperature room at 22 ° C. It was measured. Using the obtained contact angle θ and the γ value of the standard solution, the surface free energy of the photoresist was calculated from the following equation.
[0028]
γL (1 + COSθ) = 2 (γLd · γRd) 1/2 ↑ + 2 (γLp · γRp) 1/2 ↑ + 2 (γLh · γRh) 1/2 ↑
[0029]
Here, γL represents the surface free energy of the standard solution, and γR represents the surface free energy of the photoresist. As a result of calculation, γp was 0.8 mN / m, and γh was 3.2 mN / m.
[0030]
Using an aqueous ferric chloride solution having a Baume degree of 40 °, spray etching was performed at 50 ° C. to form a wiring pattern 5 (FIG. 1D). Finally, the resist pattern 4 was peeled off to obtain the wiring board of the present invention. When the dimension of the wiring width of 40 μm was measured, the wiring upper width (dimension A) was 38 μm, and the wiring lower width (dimension B) was 40 μm.
[0031]
【The invention's effect】
In the present invention, by reducing γp and γh related to the hydrophilic component of the surface free energy of the resist pattern, the penetration of the etching solution from the conductor layer and the resist interface can be suppressed, and a fine wiring is formed. There is an effect that can be.
[0032]
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a wiring board according to the present invention.
FIG. 2 is a cross-sectional view showing a conventional wiring board.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Conductor layer 2 ... Insulating layer 3 ... Resist film 4 ... Resist pattern 5 ... Wiring pattern 6 ... Etching liquid

Claims (4)

絶縁層上の導体層にレジストパターンを形成し、ウエットエッチングにより配線を形成する配線基板の製造方法において、
アクリル樹脂系フォトレジストを用いて該レジストパターンを形成し、パターン形成後にカルボン酸をブロックするアルコール又は有機酸のアンモニウム塩を該レジストパターンの皮膜中に取り込ませることにより、パターン形成された該レジストの表面自由エネルギーを調整することを特徴とする配線基板の製造方法。
In a method for manufacturing a wiring board, a resist pattern is formed on a conductor layer on an insulating layer, and wiring is formed by wet etching.
The resist pattern is formed using an acrylic resin-based photoresist, and after pattern formation, an alcohol or an organic acid ammonium salt that blocks carboxylic acid is incorporated into the film of the resist pattern, whereby the patterned resist is formed. A method for manufacturing a wiring board, comprising adjusting surface free energy.
該導体層が銅、または、銅合金からなることを特徴とする請求項に記載の配線基板の製造方法。The method for manufacturing a wiring board according to claim 1 , wherein the conductor layer is made of copper or a copper alloy. 導体層を溶解する酸化剤溶液が水溶液であることを特徴とする請求項1又は2記載の配線基板の製造方法。A method for manufacturing a wiring board according to claim 1 or 2, wherein the oxidizing agent solution for dissolving the conductive layer is an aqueous solution. 該酸化剤溶液が塩化第2鉄あるいは塩化第2銅溶液であることを特徴とする請求項1からの何れかに記載の配線基板の製造方法。A method for manufacturing a wiring board according to any one of claims 1 to 3, characterized in that the oxidizer solution is a ferric or cupric chloride chloride solution.
JP2002213498A 2002-07-23 2002-07-23 Wiring board manufacturing method Expired - Fee Related JP4310974B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002213498A JP4310974B2 (en) 2002-07-23 2002-07-23 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002213498A JP4310974B2 (en) 2002-07-23 2002-07-23 Wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP2004055952A JP2004055952A (en) 2004-02-19
JP4310974B2 true JP4310974B2 (en) 2009-08-12

Family

ID=31936078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002213498A Expired - Fee Related JP4310974B2 (en) 2002-07-23 2002-07-23 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP4310974B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007189031A (en) * 2006-01-12 2007-07-26 Allied Material Corp Semiconductor device mounting member, semiconductor device and light emitting diode using the same
JP2008139225A (en) * 2006-12-05 2008-06-19 Yokogawa Electric Corp Spectrum display device and fourier analyzer using it
JP2012039108A (en) * 2010-07-16 2012-02-23 Dainippon Printing Co Ltd Solar battery power collection sheet and manufacturing method of solar battery power collection sheet
KR102146532B1 (en) * 2017-08-18 2020-08-20 주식회사 엘지화학 Method for preparing film mask

Also Published As

Publication number Publication date
JP2004055952A (en) 2004-02-19

Similar Documents

Publication Publication Date Title
JP2005175128A (en) Semiconductor device and manufacturing method thereof
JP2007227933A (en) Flexible circuit board for flip-chip-on-flex applications
JP2003338516A (en) Semiconductor device and method of manufacturing the same
KR100777994B1 (en) Process to manufacture tight tolerance embedded elements for printed circuit boards
JP2000353760A (en) Manufacture of semiconductor device mounting relay board
US6562250B1 (en) Method for manufacturing wiring circuit boards with bumps and method for forming bumps
US20020061641A1 (en) Bump forming method, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP3226489B2 (en) Suspension board with circuit
JP2006100631A (en) Wiring board and its manufacturing method
JPH10125818A (en) Substrate for semiconductor device, semiconductor device and manufacture thereof
JP4310974B2 (en) Wiring board manufacturing method
JPH10125819A (en) Substrate for semiconductor device, semiconductor device and manufacture thereof
JPH09283925A (en) Semiconductor device and manufacture thereof
US20120148960A1 (en) Method of manufacturing printed circuit board
US20090008133A1 (en) Patterned Circuits and Method for Making Same
KR20110009790A (en) Flexible printed circuit board and method for manufacturing the same
KR20090103605A (en) Method for manufacturing printed circuit board
TWI418275B (en) Manufacturing process for printed circuit board with conductive structure of lines
KR100752016B1 (en) Method for manufacturing printed circuit board
JP2005129665A (en) Semiconductor device and manufacturing method thereof
JP2010199530A (en) Printed circuit board, and manufacturing method thereof
JP3174356B2 (en) Printed circuit board manufacturing method
JP2004274071A (en) Substrate for semiconductor apparatus, semiconductor apparatus, and manufacturing method for them
KR20050109653A (en) Preparation of semiconductor substrate by build up technology
JP4687084B2 (en) Method for manufacturing printed wiring board with built-in passive element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050621

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080129

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080924

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090421

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090504

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130522

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140522

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees