JP4310845B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a solid-state imaging device and a manufacturing method thereof.
[0002]
[Prior art]
  As a solid-state imaging device, a so-called vertical overflow drain type solid-state imaging device is known in which surplus charges in the light receiving sensor section are discharged to the substrate side. The present applicant has previously described a CCD solid-state imaging device in which a depletion region of a light receiving sensor portion is formed by a high resistance epitaxial layer having a thickness of 2 μm or more in a vertical overflow drain type solid-state imaging device, and sensitivity is also provided in the near infrared region. An image sensor was developed (see Japanese Patent Application No. 8-152494).
[0003]
  FIG. 8 shows this CCD solid-state imaging device. The CCD solid-state imaging device 1 has a low impurity concentration of the same conductivity type, that is, n on a semiconductor substrate 2 made of a first conductivity type, for example, n-type silicon.^-The first conductive well region 4 of the second conductivity type, for example, p-type, serving as an overflow barrier region is formed in the epitaxial layer 3 of the semiconductor substrate 10. A high-resistance semiconductor region having a higher specific resistance than the first p-type semiconductor well region 4, a so-called high-resistance epitaxial layer 5, is formed by epitaxial growth on the first p-type semiconductor well region 4. The high resistance epitaxial layer 5 has a thickness of 2 μm or more, preferably 5 μm or more, and is a p-type region or n-type region having a lower concentration than the first p-type semiconductor well region 4, or a non-doped (intrinsic semiconductor) region. It is formed.
[0004]
  N for configuring each light receiving sensor portion 11 in a matrix arrangement on the surface of the high resistance epitaxial layer 5.⁺Semiconductor region 6 and p thereon⁺Positive charge accumulation region 7 is formed. Further, the n-type transfer channel region 9 of the vertical transfer register 12 is formed at a position corresponding to one side of each light receiving sensor portion row of the high resistance epitaxial layer 5 with the read gate portion 13 interposed therebetween. A second p-type semiconductor well region 8 is formed under the transfer channel region 9. Further, a p-type channel stop region 14 that partitions each light receiving sensor unit 11 is formed.
[0005]
  A transfer electrode 16 made of, for example, polycrystalline silicon is formed on the transfer channel region 9, the channel stop region 14, and the readout gate portion 13 via a gate insulating film 15, and the transfer channel region 9, the gate insulating film 15, and the transfer electrode are formed. 16 constitutes a vertical transfer register 12 having a CCD structure. Further, a light shielding film 17 is formed on the entire surface other than the opening of the light receiving sensor unit 11 via an interlayer insulating film 18 covering the transfer electrode 16.
[0006]
  In this manner, the CCD solid-state imaging of the vertical overflow drain type in which the light receiving sensor unit 11, the first p-type semiconductor well region 4 serving as the overflow barrier region, and the substrate 2 serving as the overflow drain are formed in the vertical direction. Element 1 is configured.
[0007]
  In this CCD solid-state imaging device 1, the overflow barrier region 4 is formed at a depth where infrared rays are sufficiently absorbed, and the high resistance epitaxial layer 5 reaching the overflow barrier region 4 is depleted, so that the near-infrared region is also obtained. It can have sensitivity.
[0008]
[Problems to be solved by the invention]
  By the way, in the CCD solid-state imaging device 1 having sensitivity also in the near-infrared region described above, for example, the high resistance epitaxial layer 5 is made p.^-When formed into a mold, as shown in Comparative Example 1 in FIG. 9, when the solid-state imaging chip is obtained by cutting from the scribe line 21,Scribe surfaceP^-High-resistance epitaxial layer 5 and n-type semiconductor substrate 10, that is, n^-A pn junction 22 formed with the epitaxial layer 3 is exposed, and a GND potential is applied through the semiconductor substrate 10 and GND, that is, the channel stop region 14.^-There is a possibility that a leakage current may occur between the high resistance epitaxial layer 5.
[0009]
  P^-In the peripheral region of the high resistance epitaxial layer 15, a protection transistor 24 is formed for the purpose of protecting the gate insulating film and the pn junction. In Comparative Example 1 of FIG.^-A p-type base region 23 is formed in the high-resistance epitaxial layer 5, an n-type emitter region 26 is formed in the base region 23, and an n-type collector electrode extraction region 27 is formed to form a high-resistance epitaxial layer. A protection transistor (vertical npn bipolar transistor) 24 having a collector region 5 is formed. 28 is p⁺The base electrode extraction region, C is a collector terminal, B is a base terminal, and E is an emitter terminal.
[0010]
  In this protection transistor 24, the collector region is p.^-Since the high-resistance epitaxial layer 5 is used, there arises a problem that the electrostatic strength is reduced, that is, the protection capability of the protection transistor is weakened.
[0011]
  On the other hand, in the CCD solid-state imaging device 1 described above, for example, the high resistance epitaxial layer 5 is n^-When formed into a mold, as shown by the potential distribution I in FIG. 12, a potential depression is formed in the overflow barrier region 4 with respect to the hole charge h, and the hole charge h accumulated in the overflow barrier region 4 is formed. Is less likely to be discharged to the channel stop region 14, and the so-called shading is deteriorated, which is caused by a decrease in the saturation charge amount Qs and a difference between a peripheral pixel and a pixel other than the peripheral portion where hole charges h are easily discharged. Etc. becomes a problem.
[0012]
  In order to improve this point, the present applicant has changed the high resistance epitaxial layer 5 to n as shown in FIGS.^-Even in the case of the mold, the internal p-type semiconductor region 25 is formed in a portion in the high resistance epitaxial layer 5 corresponding to the lower portion of the transfer electrode 16 between the light receiving sensor portions adjacent in the vertical direction, and hence the lower portion of the p-type channel stop region 14. A CCD solid-state imaging device was proposed (see Japanese Patent Application No. 10-90175).
[0013]
  According to the CCD solid-state imaging device shown in FIGS. 10 and 11, a potential dip with respect to the hole charge h is not formed as shown by the potential distribution II in FIG. 13 and is generated by photoelectric conversion at a deep position in the high resistance epitaxial layer 5. The hole charge h is not accumulated in the overflow barrier region 4 but is discharged through the p-type channel stop region 14 through the internal p-type semiconductor region 25.
[0014]
  Further, the protection transistor 24 in the peripheral portion is n^-Since the high resistance epitaxial layer 5 is configured as a collector region, the protection capability as the protection transistor 24 can be ensured. However, the internal p-type semiconductor region 25 provided in each pixel hinders pixel miniaturization.
[0015]
  In view of the above-described points, the present invention achieves pixel miniaturization without impairing characteristics, andScribe surfaceThe present invention provides a solid-state imaging device capable of avoiding the occurrence of a leakage current at the same time and a manufacturing method thereof.
[0016]
[Means for Solving the Problems]
  The solid-state imaging device according to the present invention includes a second conductivity type impurity region serving as an overflow barrier region formed in a region corresponding to the pixel region of the first conductivity type semiconductor substrate, and a second conductivity type impurity region. A region portion of the second conductivity type formed by the high resistance epitaxial layer formed on the substrate, and a region portion of the first conductivity formed by the high resistance epitaxial layer formed on the semiconductor substrate corresponding to the region portion around the pixel region. , Solid-state imaging chip scribeThe first conductive type semiconductor substrate and the first conductive type region are exposed on the surface, and the scribe surfaceThus, the pn junction is not exposed.
[0017]
  In the method for manufacturing a solid-state imaging device according to the present invention, a second conductivity type impurity region which becomes an overflow barrier region by introducing a second conductivity type impurity into a region corresponding to the pixel region of the first conductivity type semiconductor substrate. A non-doped or first conductivity type high resistance epitaxial layer is grown on the semiconductor substrate including the second conductivity type impurity region, and at the same time, the second conductivity type impurity in the impurity region is grown to the high resistance epitaxial layer. The region corresponding to the impurity region of the high resistance epitaxial layer is diffused to the second conductivity type.The first conductivity type impurity of the semiconductor substrate is diffused into the high resistance epitaxial layer, and the region corresponding to the periphery of the pixel region of the high resistance epitaxial layer is formed into the first conductivity type.A solid-state imaging chip scribeThe first conductive type semiconductor substrate and the first conductive type region are exposed on the surface, and the scribe surfaceThe pn junction is not exposed.
[0018]
  According to the present invention, the region portion of the high resistance epitaxial layer corresponding to the impurity region serving as the overflow barrier is formed in the same conductivity type as the impurity region, and the region portion corresponding to the peripheral portion of the high resistance epitaxial layer is formed with the semiconductor substrate. Since they are formed in the same conductivity type, one charge photoelectrically converted in the vicinity of the impurity region is not accumulated in the impurity region but is discharged to the channel stop region through the high resistance epitaxial layer.
[0019]
  Further, the internal second conductivity type “semiconductor region as shown in FIG. 11 is not necessary, and the pixel can be miniaturized.
  Since the region corresponding to the periphery of the high resistance epitaxial layer is formed in the same conductivity type as the semiconductor substrate,As shown in FIG. 2, it was cut from the scribe line.Of solid-state imaging chipScribe surfaceThen, the pn junction is not exposed,Scribe surfaceThere is no generation of leakage current.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings.
[0021]
  1 and 2 show an embodiment of a vertical overflow drain type solid-state imaging device according to the present invention. This embodiment is a case where the present invention is applied to a CCD solid-state imaging device having sensitivity also in the near infrared region. FIG. 1 is a plan view of the main part of the imaging region of the solid-state imaging device, and FIG. 2 is a sectional view of the vicinity of the pixel region and the peripheral region.
[0022]
  The solid-state imaging device 31 according to the present embodiment has a low impurity concentration of the same conductivity type, that is, n on a semiconductor substrate 32 made of first conductivity type, for example, n-type silicon.^-A second conductivity type semiconductor region which is an overflow barrier region in a region corresponding to the pixel region in the epitaxial layer 33 of the semiconductor substrate 40, In the example, a p-type first semiconductor well region 34 is formed, and a specific resistance is higher than that of the first p-type semiconductor well region 34 by epitaxial growth on the first p-type semiconductor well region 34 (therefore, the first p-type semiconductor well region 34 is formed). A high-resistance semiconductor region (so-called high-resistance epitaxial layer 35) having a lower impurity concentration than the p-type semiconductor well region 34 is formed. N for forming the light receiving sensor portion 41 in the high resistance epitaxial layer 35.⁺Semiconductor region 36 and p above this⁺Positive charge accumulation region 37 is formed.
[0023]
  Further, an n-type transfer channel region 39 for forming a vertical transfer register 43 described later is formed in the high resistance epitaxial layer 35 at a position corresponding to one side of each column of the light receiving sensor unit 41. A second p-type semiconductor well region 38 is formed below. Further, a p-type channel stop region 44 is formed in the high resistance epitaxial layer 35 at a position that partitions the light receiving sensor portion 41.
[0024]
  The light receiving sensor unit 41 is a pixel, and a plurality of light receiving sensor units 41 are arranged in a matrix as shown in FIG. A read gate unit 42 is formed between the light receiving sensor unit 41 and the vertical transfer register 43.
[0025]
  On the transfer channel region 39, the channel stop region 44, and the readout gate portion 42, transfer electrodes 46 [46 a, 46 b] made of, for example, polycrystalline silicon having a two-layer structure are formed via the gate insulating film 45. A vertical transfer register 43 having a CCD structure is constituted by the gate insulating film 45 and the transfer electrode 46.
[0026]
  Further, a light shielding film 47 made of, for example, Al is formed on the entire surface excluding the opening of the light receiving sensor portion 41 through an interlayer insulating film 48 covering the transfer electrode 46.
[0027]
  The first conductivity type low impurity concentration epitaxial layer 33 is provided to reduce the so-called shutter voltage. By forming this epitaxial layer 33, the substrate voltage V_subTherefore, the shutter voltage can be easily reduced.
[0028]
  The first p-type semiconductor well region 34 serving as the overflow barrier region preferably has an impurity concentration of 10¹⁴-10¹⁶cm^-3Within the range of
[0029]
  The thickness of the high resistance epitaxial layer 35 is 2 μm or more, preferably 5 μm or more, for example, about 10 μm. The impurity concentration of the high resistance epitaxial layer 35 is 10¹⁵cm^-3Less than, for example, 10¹³cm^-3It can be.
[0030]
  In the present embodiment, in particular, the region portion 35A corresponding to the pixel region of the high-resistance epitaxial layer 35, that is, the region portion 35A corresponding to the first p-type semiconductor well region 34 serving as the overflow barrier region is provided in the first region. The p-type semiconductor well region 34 is formed with the same conductivity type, and the peripheral region portion 35B of the high resistance epitaxial layer 35 is formed with the same conductivity type as that of the n-type semiconductor substrate 40.
[0031]
  The region portion 35A of the high-resistance epitaxial layer 35 has a lower impurity concentration than the first p-type semiconductor well region 34 serving as an overflow barrier region.^-It is formed in a high resistance region. Further, the peripheral region portion 35B of the high-resistance epitaxial layer 35 is formed on the n-type semiconductor substrate 40.^-N having a lower impurity concentration than the epitaxial layer 33 of^-It is formed in a high resistance region.
[0032]
  N of the high resistance epitaxial layer 35^-A protective transistor 51 similar to that described above is formed in the peripheral region portion 35B. This protection transistor 51 has n^-A p-type base region 52 is formed in the peripheral region portion 35B, an n-type emitter region 53 is formed in the base region 52, and an n serving as a collector region is formed.^-An n-type collector electrode extraction region 54 is formed in the region portion 35B, and a p-type base electrode extraction region 55 is formed in the base region 52. C is a collector terminal, B is a base terminal, and E is an emitter terminal.
[0033]
  In the solid-state imaging device 31, a first p-type semiconductor well region 34 serving as an overflow barrier region is formed at a depth at which infrared rays are sufficiently absorbed, and the high resistance epitaxial layer 35 reaching the overflow barrier region 34 is depleted. Thus, sensitivity can be obtained in the near infrared region.
[0034]
  According to the solid-state imaging device 31 having sensitivity also in the near infrared region according to the present embodiment, the region portion 35A corresponding to the overflow barrier region 34 of the high resistance epitaxial layer 35 is formed as a p-type, that is, Since the region including the region portion 35A of the high-resistance epitaxial layer and the overflow barrier region 34, which are depleted regions of the light receiving sensor unit 31, are all formed of p-type, the pixels adjacent to each other in the vertical direction shown in FIG. Without providing the internal p-type semiconductor region 25 for eliminating the hole charge at the position corresponding to, a potential dip with respect to the hole charge h does not occur as shown by the potential distribution III in FIG.
[0035]
  That is, without providing the internal p-type semiconductor region 25, the hole charge h generated by photoelectric conversion at a deep position in the high-resistance epitaxial layer 35 is not accumulated in the overflow barrier region 34, but is accumulated in the p-layer of the high-resistance epitaxial layer 35.^-It can be discharged to the p-type channel stop region 44 on the surface through the region portion 35A. Thereby, the overflow barrier region 34 is completely depleted. Accordingly, problems such as reduction of the saturation charge amount Qs and shading do not occur, and the characteristics of each pixel can be made uniform. Further, the pixels can be further miniaturized as the internal p-type semiconductor region 25 can be omitted.
[0036]
  The peripheral region portion 35B of the high-resistance epitaxial layer 35 is n-type having the same conductivity type as the n-type semiconductor substrate 40.^-Because it is formed inAs shown in FIG. 2, it was cut from the scribe line 57.Solid-state imaging chip scribeN-type semiconductor substrate 40 and n on the surface ⁻⁻ The peripheral region portion 35B of the surface is exposed and the scribe surfaceThe pn junction is not exposed to the scribesurfaceIn this case, no leakage current is generated between the n-type semiconductor substrate and GND.
[0037]
  Further, color mixing between pixels in the vertical direction can be prevented.
[0038]
  The above-described solid-state imaging device 31 according to the present embodiment is manufactured, for example, as follows.
[0039]
  FIG. 4 shows an example of the production method of the present invention. First, as shown in FIG. 4A, an n-type silicon semiconductor substrate 32 having a low impurity concentration and the same conductivity type as that of the substrate 32, for example.^-An n-type semiconductor substrate 40 on which the epitaxial layer 33 is formed is provided. N of the n-type semiconductor substrate 40^-A p-type impurity is introduced into the surface of the region corresponding to the pixel region of the epitaxial layer 33 to form a first p-type semiconductor well region 34 serving as an overflow barrier region.
[0040]
  In the formation of the first p-type semiconductor well region 34, in this example, as the p-type impurity, plural types of the same conductivity type impurities having different diffusion coefficients, for example, aluminum (Al) impurity and boron (B) impurity are ionized. Introduce by injection. Aluminum impurities have a smaller diffusion coefficient than boron impurities. The dose ratio to be introduced can be about Al: B = 10 to 100: 1.
[0041]
  Next, as shown in FIG. 4B, an n-type or non-doped (intrinsic semiconductor) high-resistance epitaxial layer 35 is grown on the entire surface of the n-type semiconductor substrate 40. During this epitaxial growth, boron impurities having a large diffusion coefficient are mainly diffused from the first p-type semiconductor well region 33 into the epitaxial layer. The p-type semiconductor well region, that is, the region portion 35A corresponding to the overflow barrier region 33 is p^-Grows as a high resistance region.
[0042]
  The overflow barrier region 34 is mainly formed by aluminum impurities having a small diffusion coefficient.
[0043]
  Aluminum that is a p-type impurity has a small diffusion coefficient, a low solid solubility (so-called solubility), and a low activation rate in the silicon semiconductor. However, the overflow barrier region 34 has an impurity concentration of 10¹⁴-10¹⁶cm^-3Therefore, aluminum can be used as an impurity for the overflow barrier region 34.
[0044]
  On the other hand, in the peripheral region portion 35B of the high-resistance epitaxial layer 35, n-type epitaxial growth or n.^-By diffusion of n-type impurities from the epitaxial layer 33 into the epitaxial layer 35, n of the same conductivity type as the base 40 is obtained.^-It becomes a high resistance region.
[0045]
  Next, p corresponding to the pixel region of the high resistance epitaxial layer 35 is formed.^-N constituting the light receiving sensor 41 described above in the high resistance region 35A⁺Semiconductor region 36 and p⁺The positive charge accumulation region 37, the second p-type semiconductor well region 38, the n-type transfer channel region 39, and the p-type channel stop region 44 are formed by ion implantation, for example. Further, n around the high-resistance epitaxial layer 35^-The p-type base region 52, the n-type emitter region 53, and the p-type that constitute the protection transistor 51 in the region portion 35B⁺Base electrode extraction region 55 and n⁺The collector electrode extraction region 54 is formed by ion implantation, for example.
[0046]
  Next, a gate insulating film 45 is formed on the entire surface so as to cover the surface, and a transfer electrode 46 made of a polycrystalline silicon layer is selectively formed thereon. Thereafter, the transfer electrode 46 is covered with an interlayer insulating film 48, and a light shielding film 47 made of Al or the like is formed thereon. An opening is formed in the light shielding film 47 at a portion corresponding to the light receiving sensor unit 41. Further, although not shown, an interlayer insulating film and a planarizing film are stacked, and a color filter and an on-chip microlens are formed on the planarizing film. In this way, the CCD solid-state imaging device 31 shown in FIG. 7 is obtained.
[0047]
  According to the manufacturing method according to the embodiment of FIG. 4, the overflow barrier region 34 is formed by ion implantation of boron impurities having a large diffusion coefficient and aluminum impurities having a small diffusion coefficient as p-type impurities. During the growth of the non-doped high-resistance epitaxial layer 35, the region portion 35 </ b> A corresponding to the overflow barrier region 34 of the high-resistance epitaxial layer 35 is formed by p through out-diffusion of boron impurities from the overflow barrier region 34.^-It can be a high resistance region. At the same time, in the peripheral region portion 35B of the high-resistance epitaxial layer 35, n-type epitaxial growth or non-doped epitaxial growth causes n-type impurity out-diffusion from the n-type semiconductor substrate 40 to cause n^-It can be a high resistance region.
[0048]
  In addition, since the overflow barrier region 34 is mainly formed of aluminum impurities having a small diffusion coefficient, fluctuations in the thickness and impurity concentration of the overflow barrier region 34 are suppressed, and accordingly, variations in imaging element characteristics are unlikely to occur.
[0049]
  FIG. 5 shows another example of the production method of the present invention. First, as shown in FIG. 5A, for example, an n-type silicon semiconductor substrate 32 having n impurity concentration of the same conductivity type and low impurity concentration.^-An n-type semiconductor substrate 40 on which the epitaxial layer 33 is formed is provided. This n^-A first p-type semiconductor well region 34 serving as an overflow barrier region is formed on the surface of the region corresponding to the pixel region of the epitaxial layer 33 by implanting the same type of p-type impurity and implanting ions with different energy and impurity concentration. .
[0050]
  In this example, boron (B) impurity is used as an impurity, and the impurity concentration peak position R is located at a deep position with a high implantation energy, for example, an implantation energy of about 2 MeV._P1Impurity ion peak position R at a shallow position with a lower implantation energy, for example, an implantation energy of about 100 keV._P2Then, the second boron ion implanted portion 62 is implanted so that the overflow barrier region 34 is formed.
[0051]
  The first boron ion implantation part 61 has a higher impurity concentration than the second boron ion implantation part 62. For example, the ratio of the dose to be introduced may be about the first boron ion implantation part 61: the second boron ion implantation part 62 = 10 to 100: 1.
[0052]
  Next, as shown in FIG. 5B, an n-type or non-doped (intrinsic semiconductor) high-resistance epitaxial layer 35 is grown on the entire surface of the n-type semiconductor substrate 40. During this epitaxial growth, the region 35A corresponding to the overflow barrier region 34 of the high resistance epitaxial layer 35 is p by mainly out-diffusion of boron impurities from the second boron ion implanted portion 62 in the overflow barrier region 34.^-Grows as a high resistance region. The overflow barrier region 34 is formed using the boron impurity of the first boron ion implanted portion 61 as a main impurity.
[0053]
  On the other hand, the peripheral region portion 35B of the high-resistance epitaxial layer 35 is formed by n-type epitaxial growth or in the case of non-doped epitaxial growth.^-The n-type impurity out-diffusion from the epitaxial layer 33 causes n of the same conductivity type as the base 40.^-It becomes a high resistance region. Next, in the same manner as described above, the CCD solid-state imaging device 31 shown in FIG. 7 is obtained.
[0054]
  According to the manufacturing method according to the embodiment of FIG. 5, the overflow barrier region 34 is made of the same kind of impurities, in this example, boron impurities, and the first and second borons having different implantation energies and impurity concentrations. By forming the n-type or non-doped high-resistance epitaxial layer 35, the overflow barrier region 34 of the high-resistance epitaxial layer 35 is formed by out-diffusion from the second boron ion-implanted portion 62 when the n-type or non-doped high-resistance epitaxial layer 35 is grown. P corresponding to the area portion 35A corresponding to the upper side.^-It can be a high resistance region. At the same time, in the peripheral region 35B of the high-resistance epitaxial layer 35, n-type epitaxial growth or n-type impurity out-diffusion from the substrate 40 in the case of non-doped epitaxial growth is performed.^-It can be a high resistance region.
[0055]
  Further, the overflow barrier region 34 is mainly formed at the deep position R._P1Since the first boron ion implanted portion 61 is formed of boron impurities, fluctuations in the thickness and impurity concentration of the overflow barrier region 34 are suppressed, and variations in imaging element characteristics are unlikely to occur.
[0056]
  FIG. 6 shows still another example of the production method of the present invention. First, as shown in FIG. 6A, for example, on an n-type silicon semiconductor substrate 32, n of the same conductivity type and a low impurity concentration.^-An n-type semiconductor substrate 40 on which the epitaxial layer 33 is formed is provided. This n^-A first p-type semiconductor well region 34 serving as an overflow barrier region is formed on the surface of the region corresponding to the pixel region of the epitaxial layer 33 by, for example, ion implantation. In this example, boron impurities are ion-implanted to form the first p-type semiconductor well region 34.
[0057]
  Next, as shown in FIG. 6B, an n-type or non-doped (intrinsic semiconductor) high-resistance epitaxial layer 35 is grown on the entire surface of the n-type semiconductor substrate 40. During this epitaxial growth, the region portion 35A corresponding to the overflow barrier region 34 in the high-resistance epitaxial layer 35 becomes p due to impurity out-diffusion from the overflow barrier region 33.^-Grows as a high resistance region. On the other hand, in the peripheral region portion 35B of the high-resistance epitaxial layer 35, n-type epitaxial growth or n.^-An n-type impurity having the same conductivity type as that of the substrate 40 is obtained by out-diffusion of the n-type impurity from the epitaxial layer 33 to the epitaxial layer 35.^-It becomes a high resistance region.
[0058]
  Next, in the same manner as described above, the CCD solid-state imaging device 31 shown in FIG. 7 is obtained.
[0059]
  Also in the manufacturing method according to the embodiment of FIG. 6, when the high resistance epitaxial layer 35 is grown, the region portion 35A corresponding to the overflow barrier region 34 of the high resistance epitaxial layer 35 is formed by p.^-A high resistance region is used, and the peripheral region portion 35B is n^-It can be a high resistance region. However, in the example of FIG. 6, variations in the thickness and impurity concentration of the overflow barrier region 34 are likely to occur, and in this respect, the manufacturing method shown in FIGS. 4 and 5 is superior.
[0060]
  According to the manufacturing method according to each of the above-described embodiments, the peripheral portion of the chip of the high-resistance epitaxial layer is changed to the n-type region portion 35B by controlling the amount of impurity out-diffusion constituting the overflow barrier region 34, and the pixel The region portion 35A corresponding to the region can be a p-type region portion 35A.
[0061]
  Therefore, the pixel can be miniaturized without decreasing the above-described saturation charge amount Qs or increasing shading.Scribe surfaceTherefore, it is possible to easily manufacture a CCD solid-state imaging device that does not generate a leakage current between the semiconductor substrate and the ground (GND), and that has sensitivity in the near-infrared region with improved electrostatic strength of the protection transistor, that is, so-called protection capability it can.
[0062]
  In the example of FIGS. 4 and 5, a CCD solid state in which fluctuations in the thickness and impurity concentration of the overflow barrier region 34 during epitaxial growth are suppressed, variation in image pickup device characteristics is suppressed, yield is high, and sensitivity is also obtained in the near infrared region. The image sensor 31 can be manufactured.
[0063]
  In the above example, n is formed on the n-type semiconductor substrate 32.^-An epitaxial layer 33 is formed.^-The present invention can also be applied to a configuration in which the epitaxial layer 33 is omitted.
[0064]
  The solid-state imaging device of the present invention can also be applied to a solid-state imaging device other than a CCD solid-state imaging device, such as a CMOS sensor or an internal amplification sensor.
[0065]
  The solid-state imaging device of the present invention is not limited to the above-described example, and can take other various configurations without departing from the gist of the present invention.
[0066]
【The invention's effect】
  According to the solid-state imaging device according to the present invention, the region corresponding to the impurity region serving as the overflow barrier region of the high-resistance epitaxial layer is formed with the second conductivity type that is the same conductivity type as the impurity region, By forming the peripheral region portion of the first conductivity type, which is the same conductivity type as the semiconductor substrate, one charge photoelectrically converted in the vicinity of the impurity region is discharged to the channel stop region on the surface without accumulating in the impurity region. Therefore, the pixel can be miniaturized without causing a decrease in the saturation charge amount Qs and an increase in shading.
[0067]
  In addition, solid-state imaging chipScribe surfaceIn FIG. 2, there is no exposure of the pn junction, and no leakage current is generated between the semiconductor substrate and the ground (GND).
[0068]
  Color mixing between pixels in the vertical direction can be prevented.
[0069]
  Moreover, it can avoid that the electrostatic strength of the protection transistor formed in a high resistance epitaxial peripheral region part falls. Therefore, it is possible to provide a solid-state imaging device having a sensitivity in the near infrared region by the vertical overflow drain method with a high number of pixels and high reliability. In addition, it is possible to provide a solid-state image sensor that hardly causes variations in image sensor characteristics.
[0070]
  According to the method for manufacturing a solid-state imaging device according to the present invention, the solid-state imaging device can be manufactured with high yield. In addition, it is possible to manufacture a solid-state imaging device with a high yield by suppressing variations in the thickness and impurity concentration of the impurity region and thus suppressing variations in device characteristics.
[Brief description of the drawings]
FIG. 1 is a plan view of a main part of an imaging region of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a pixel portion and a peripheral region of a solid-state imaging device according to an embodiment of the present invention.
3 is a potential distribution diagram in the substrate thickness direction of AA portion of FIG. 1; FIG.
4A to 4B are manufacturing process diagrams illustrating an example of a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.
5A to 5B are manufacturing process diagrams illustrating another example of a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.
6A to 6B are manufacturing process diagrams illustrating another example of a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.
FIG. 7 is a manufacturing process diagram of a solid-state imaging element according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view of a pixel portion of a conventional solid-state image sensor.
9 is a cross-sectional view of a main part of a solid-state imaging device according to Comparative Example 1. FIG.
10 is a plan view of a main part of an imaging region of a solid-state imaging device according to Comparative Example 2. FIG.
11 is a cross-sectional view of a main part of a solid-state imaging device according to Comparative Example 2. FIG.
12 is a potential distribution diagram in the substrate thickness direction between pixels of Comparative Example 1. FIG.
13 is a potential distribution diagram in the substrate thickness direction between pixels of Comparative Example 2. FIG.
[Explanation of symbols]
1, 31... Solid imaging device, 32... N-type semiconductor substrate, 32.^-Epitaxial layer, 40 ... n-type semiconductor substrate, 34 ... Overflow barrier region (impurity region), 35 ... High-resistance epitaxial layer, 41 ... Light receiving sensor part, 42 ... Read gate part, 43 ... Vertical transfer register , 44 ... Channel stop region, 51 ... Protection transistor, 57 ... Scribe line

Claims (7)

A second conductivity type impurity region serving as an overflow barrier region formed in a region corresponding to the pixel region of the first conductivity type semiconductor substrate;
A second conductivity type region formed by a high resistance epitaxial layer formed on the second conductivity type impurity region;
A first conductivity type region portion by the high resistance epitaxial layer formed on a semiconductor substrate corresponding to a region portion around the pixel region;
A solid-state imaging device characterized in that the first conductivity type semiconductor substrate and the first conductivity type region are exposed on a scribe surface of a solid-state imaging chip , and a pn junction is not exposed on the scribe surface. element. 2. The solid-state imaging device according to claim 1, wherein the impurity region of the second conductivity type is formed of a region having boron impurities. 2. The solid-state imaging device according to claim 1, wherein the second conductivity type impurity region is formed of a region containing an aluminum impurity. Introducing a second conductivity type impurity into a region corresponding to the pixel region of the first conductivity type semiconductor substrate to form a second conductivity type impurity region serving as an overflow barrier region;
A non-doped or first conductivity type high resistance epitaxial layer is grown on the semiconductor substrate including the second conductivity type impurity region, and at the same time, the second conductivity type impurity in the impurity region is diffused into the high resistance epitaxial layer. The region corresponding to the impurity region of the high-resistance epitaxial layer is made to have the second conductivity type , and the first conductivity-type impurity of the semiconductor substrate is diffused into the high-resistance epitaxial layer to thereby form the pixel region of the high-resistance epitaxial layer. A region corresponding to the periphery of the first conductive type ,
A solid-state imaging device , wherein the first conductive type semiconductor substrate and the first conductive type region are exposed on a scribe surface of a solid-state imaging chip, and a pn junction is not exposed on the scribe surface . Production method. 5. The method of manufacturing a solid-state imaging device according to claim 4, wherein the second conductivity type impurity region is formed by implanting ions of the same type with different energies and impurity concentrations. 5. The method of manufacturing a solid-state imaging device according to claim 4, wherein a plurality of types of impurities having different diffusion coefficients are ion-implanted to form the second conductivity type impurity region. The method for manufacturing a solid-state imaging device according to claim 4, wherein the impurity region of the second conductivity type is formed by ion implantation of an aluminum impurity and a boron impurity.

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