JP4309796B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device including a memory cell array composed of nonvolatile memory cells such as a flash memory, and more particularly to a semiconductor memory device including a redundancy circuit that relieves a defect in a memory cell array.

  For example, in a flash memory, in general, in order to realize a function of replacing a defective block in units of blocks with a redundant block (redundancy block) prepared in advance when a defect occurs in an erase block which is a unit of batch erase. The redundancy circuit is installed. By mounting such a redundancy circuit, the yield of non-defective products can be improved.

  However, as the memory capacity increases, the redundancy area occupied by the chip also increases. This increases the circuit area of the chip. In addition, the number of users is diversifying, and the number of cases in which the total memory capacity of the specification is not necessarily increased is increasing.

  In order to solve such a problem, a technique is disclosed in which only a defective area is deselected when a defect still remains after replacing a defective block with a spare block (see Patent Document 1).

The semiconductor memory device of the above technique is configured to sequentially shift addresses when a defective block occurs. Therefore, when there are many defective blocks, the number of times the address is shifted increases, and the amount of addresses to be shifted increases sequentially. For this reason, time for reading data is delayed.
JP 2001-291394 A

  The present invention uses a part of a normal memory area as a redundancy area, thereby suppressing an increase in the redundancy area, and further improving a yield by relieving a product that has been treated as a defective product as a partially good product. An object of the present invention is to provide a semiconductor memory device capable of performing

A semiconductor memory device according to an aspect of the present invention includes a memory cell array including a plurality of normal blocks and a plurality of redundancy blocks. When the number of defective blocks in the block exceeds the number of redundancy blocks , a replacement circuit that replaces the defective blocks with normal blocks in the same chip and performs replacement so that the address space of the memory cell array is continuous Including.

  According to the present invention, by using a part of the normal memory area as a redundancy area, an increase in the redundancy area is suppressed, and a product that has been treated as a defective product in the past is relieved as a partially good product, thereby improving the yield. It is possible to provide a semiconductor memory device that can be used.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
Hereinafter, a flash memory having electrically rewritable nonvolatile memory cells will be described as an example of the semiconductor memory device.

  FIG. 1 is a block diagram showing a configuration of a flash memory according to the first embodiment of the present invention.

  The memory cell array 1 is composed of n banks. Each bank i (i = 1 to n) includes a predecoder 2, m blocks BLK1 to BLK, and, for example, one redundancy block RBLKi. The redundancy block RBLK is a block that is replaced with a defective block when a defective block occurs.

  For example, the flash memory of this embodiment includes n redundancy blocks RBLK1 to RBLK1. That is, when there are n or less defective blocks, the redundancy blocks RBLK1 to RBLK1 to n are used as blocks to be replaced with defective blocks. Furthermore, in this embodiment, a part or all of the last bank n is used as an excess redundancy block area.

  That is, when there are more than n defective blocks and n + m or less, excess redundancy blocks ORBLK1 to ORBLK1 to m are used as blocks that are replaced with defective blocks. The final bank n has the same configuration as the other banks 1 to n-1. The excess redundancy block ORBLK has the same configuration as the block BLK.

  In each bank, a local address line 13, a local power supply line 14, and a local data line 15 are provided in common to each block in the bank.

  The local address line 13 transfers an address signal to each block. The local power supply line 14 supplies power necessary for data reading and data writing or erasing to each block. The local data line 15 transfers read data and write data to and from each block.

  In the flash memory, an address line 10, a power line 11, and a data line 12 are provided in common for all banks. The address line 10 is connected to each local address line 13. The power supply line 11 is connected to each local power supply line 14. The data line 12 is connected to each local data line 15. The predecoder 2 connects or disconnects the local address line 13, the local power supply line 14, and the local data line 15, and the address line 10, the power supply line 11, and the data line, respectively.

  The address line 10 transfers an address signal to all banks. The power supply line 11 supplies power necessary for data reading and data writing or erasing to all banks. The data line 12 transfers read data and write data to and from all banks.

  An address buffer 3 is connected to the address line 10. A power supply circuit 4 is connected to the power supply line 11. A sense amplifier circuit SA5 is connected to the data line 12.

  The address buffer 3 outputs an address signal. The address signal output from the address buffer 3 includes a bank address signal for designating a bank, a block address signal for designating a block, a column address signal for selecting a bit line BL, and a row address signal for selecting a word line WL.

  The power supply circuit 4 supplies power necessary for data reading and data writing or erasing. SA5 detects and amplifies data read to the data line 12 by the data read operation or data read to the data line 12 by the verify operation.

  The interface circuit 6 exchanges data and address signals with an external circuit (not shown). The interface circuit 6 is connected to the address buffer 3, the power supply circuit 4, and the sense amplifier circuit SA5.

  The flash memory also includes a redundancy hit circuit 7, a bank decoder 8, and a block decoder 9. When an address signal designating a defective block is input, the redundancy hit circuit 7 generates a hit signal HITBLK for replacing the defective block with the redundancy block. Then, the hit signal HITBLK is supplied to the bank decoder 8 and the block decoder 9.

  The bank decoder 8 selects a bank based on the bank address signal input from the address buffer 3 or the hit signal HITBLK. The block decoder 9 selects a block based on a block address signal input from the address buffer 3 or a hit signal HITBLK.

  Next, the configuration of each bank will be described. FIG. 2 is a block diagram showing a configuration of the bank shown in FIG. Each block BLK is a minimum unit of data erasure, and a plurality of memory cells MC are arranged in a matrix. Each block BLK is provided with a plurality of bit lines BL and a plurality of word lines WL. Memory cells MC are arranged at positions where the bit lines BL and the word lines WL intersect.

  Each bank i includes, for example, one redundancy block RBLKi. The redundancy block RBLKi is a block that is replaced with a defective block when a defective block occurs.

  Each block BLK is provided with a row decoder 16 and a column decoder 17. Specifically, a row decoder 16 is disposed at the end of the word line WL of each block BLK. A column decoder 17 is disposed at the end of the bit line BL of each block BLK. The row decoder 16 selects the word line WL based on the row address signal. The column decoder 17 selects the bit line BL based on the column address signal.

  Further, a sub-decoder 18 is disposed in each block. A block selection signal is supplied to the sub-decoder 18 by the block decoder. The sub-decoder 18 connects or disconnects the block, the local address line 13, the local power supply line 14, and the local data line 15 based on the block selection signal. The same applies to the redundancy block RBLKi.

  Next, the configuration of the redundancy hit circuit 7 will be described. FIG. 3 is a block diagram showing a configuration of the redundancy hit circuit 7 shown in FIG. An address signal output from the address buffer 3 is input to the redundancy hit circuit 7. The redundancy hit circuit 7 includes a defective block address storage circuit 7a and a hit detection circuit 7b.

  The defective block address storage circuit 7a stores an address signal of a block determined to be defective when the operation check test of the flash memory is performed. Further, the defective block address storage circuit 7a receives address signals of m defective blocks (which is the number of excess redundancy blocks ORBLK) in addition to address signals of n defective blocks (which is the number of redundant blocks RBLK). I remember it.

  The hit detection circuit 7b compares the address signal with the defective block address signal stored in the defective block address storage circuit 7a. If they match, the hit detection circuit 7b generates a hit signal HITBLKi (i = 1 to n + m) that specifies the replacement block. The hit signal HITBLKi is supplied to the bank decoder 8 and the block decoder 9.

  Next, the configuration of the bank decoder 8 will be described. FIG. 4 is a block diagram showing a configuration of bank decoder 8 shown in FIG. The bank decoder 8 receives the bank address signal output from the address buffer 3 and the hit signal HITBLKi. The bank decoder 8 includes a normal bank selection circuit 8a and an excess redundancy bank selection circuit 8b.

  The normal bank selection circuit 8a selects the banks 1 to n-1 based on the bank address signal and the hit signal HITBLKi. The normal bank selection circuit 8a generates a bank selection signal MBLKi (i = 1 to n−1). The bank selection signal MBLKi (i = 1 to n−1) is supplied to the corresponding predecoder 2 of the bank i.

  The excess redundancy bank selection circuit 8b selects the bank n including the excess redundancy block based on the bank address signal and the hit signal HITBLKi. The excess redundancy bank selection circuit 8b generates a bank selection signal MBLKn. The bank selection signal MBLKn is supplied to the predecoder 2 in the bank n.

  FIG. 5 is a block diagram illustrating an example of the predecoder 2. The predecoder 2 includes switch circuits SW1 to SW3. A bank selection signal MBLK is supplied to each of the switch circuits SW1 to SW3. The switch circuit SW1 is connected to the local address line 13. The switch circuit SW2 is connected to the local power line 14. The switch circuit SW3 is connected to the local data line 15. The switch circuit SW1 connects the local address line 13 and the address line 10 when the bank selection signal MBLK is activated. The same applies to the switch circuits SW2 and SW3.

  FIG. 6 is a circuit diagram showing an example of the normal bank selection circuit 8a. Note that the circuit shown in FIG. 6 is a circuit that selects one bank i (i = 1 to n−1). That is, the normal bank selection circuit 8a includes a number of circuits shown in FIG. 6 corresponding to the banks 1 to n-1.

  Hit signals HITBLK1 to HITBLKn + m are input to the NOR circuit 30, respectively. That is, the NOR circuit 30 detects whether any one of the hit signals HITBLK1 to HITBLKn + m is activated. The signal output from the NOR circuit 30 is input to the NAND circuit 33 via the inverter circuits 31 and 32. A bank address signal is input to the NAND circuit 33.

  The signal output from the NAND circuit 33 is input to the NOR circuit 35 via the inverter circuit 34. In addition, the hit signal HITBLKi (i = 1 to n−1) is input to the NOR circuit 35. The signal output from the NOR circuit 35 is output as the bank selection signal MBLKi via the inverter circuit 36. The bank selection signal MBLKi is supplied to the predecoder 2 of the bank i.

  In FIG. 6, when the hit signals HITBLK1 to HITBLKn + m are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLK1 to HITBLKn + m are activated, the bank address signal is forcibly made non-selected by the NAND circuit 33. In this case, the bank is selected based on the hit signal HITBLKi (i = 1 to n−1).

  FIG. 7 is a circuit diagram showing an example of the excess redundancy bank selection circuit 8b. Hit signals HITBLKn to HITBLKn + m are input to the NOR circuit 37, respectively. The signal output from the NOR circuit 37 is input to the NOR circuit 35 via the inverter circuit 38. The signal output from the NOR circuit 35 is output as a bank selection signal MBLKn via the inverter circuit 36. The bank selection signal MBLKn is supplied to the predecoder 2 in the bank n. Other configurations are the same as those in FIG.

  In FIG. 7, when the hit signals HITBLK1 to HITBLKn + m are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLK1 to HITBLKn + m are activated, the bank address signal is forcibly made non-selected by the NAND circuit 33. In this case, the bank is selected based on the hit signals HITBLKn to n + m. That is, when any one of hit signals HITBLKn to HITBLKn + m is activated, bank n is selected.

  Next, the configuration of the block decoder 9 will be described. FIG. 8 is a block diagram showing a configuration of the block decoder 9 shown in FIG. The block decoder 9 receives the block address signal output from the address buffer 3, the hit signal HITBLKi, and the bank selection signal MBLKi. The block decoder 9 includes a normal block selection circuit 9a, a redundancy block selection circuit 9b, and an excess redundancy block selection circuit 9c.

  The normal block selection circuit 9a selects the blocks BLK1 to BLm based on the block address signal and the bank selection signal MBLKi (i = 1 to n). The normal block selection circuit 9a generates a block selection signal SBLKi (i = 1 to m). The block selection signal SBLKi is supplied to a sub-decoder 18 of a normal block that is not used as a redundancy block.

  The redundancy block selection circuit 9b selects the redundancy blocks RBLK1 to RBLK1 to n based on the bank selection signal MBLKi (i = 1 to n) and the hit signal HITBLKi (i = 1 to n). The redundancy block selection circuit 9b generates a block selection signal SRBLKi (i = 1 to n). The block selection signal SRBLKi is supplied to the sub decoders 18 of the redundancy blocks RBLK1 to n.

  The excess redundancy block selection circuit 9c selects the excess redundancy block ORBLK based on the block address signal, the bank selection signal MBLKi (i = 1 to n), and the hit signal HITBLKi (i = n + 1 to n + m). The excess redundancy block selection circuit 9c generates a block selection signal SORBLKi (i = 1 to m). The block selection signal SORBLKi is supplied to the sub-decoder 18 of the excess redundancy block ORBLKi.

  Specifically, each block selection signal is supplied to a sub-decoder 18 disposed in each block. Each sub-decoder 18 connects or disconnects the local address line 13, the local power supply line 14, the local data line 15 and the block based on the block selection signal. Each sub-decoder 18 has, for example, an address switch, a power switch, and a data line switch, and these switches are connected or disconnected.

  FIG. 9 is a circuit diagram showing an example of the normal block selection circuit 9a. The circuit shown in FIG. 9 is a circuit that selects one normal block BLKi (i = 1 to m). That is, the normal block selection circuit 9a includes a number of circuits shown in FIG. 9 corresponding to the number of normal blocks BLK.

  Hit signals HITBLK1 to HITBLKn + m are input to the NOR circuit 47, respectively. The signal output from the NOR circuit 47 is input to the address non-select terminal Add_dis via the inverter circuit 48. The address non-selection terminal Add_dis is input to the NAND circuit 41 via the inverter circuit 40. The block address signal is input to the NAND circuit 41. Further, the bank selection signal MBLKi (i = 1 to n) is input to the NAND circuit 41. The signal output from the NAND circuit 41 is input to the NOR circuit 45 via the inverter circuit 42.

  The bank selection signal MBLKi (i = 1 to n) is input to one input part of the NAND circuit 43. The other input portion of the NAND circuit 43 is supplied with a ground voltage Vss (low level). The signal output from the NAND circuit 43 is input to the NOR circuit 45 via the inverter circuit 44. The signal output from the NOR circuit 45 is output as a block selection signal SBLKi via the inverter circuit 46.

  In FIG. 9, the normal block selection circuit 9a is configured to be controlled by a block address signal. That is, the selection of the normal block is performed based on the block address signal.

  FIG. 10 is a circuit diagram showing an example of the redundancy block selection circuit 9b. Note that the circuit shown in FIG. 10 is a circuit that selects one redundancy block RBLKi (i = 1 to n). That is, the redundancy block selection circuit 9b includes a number of circuits shown in FIG. 10 corresponding to the number of redundancy blocks RBLK.

  A power supply voltage Vdd (high level) is supplied to the address non-selection terminal Add_dis. The NAND circuit 43 receives a hit signal HITBLKi (i = 1 to n). The signal output from the NOR circuit 45 is output as a block selection signal SRBLKi via the inverter circuit 46. Other configurations are the same as those in FIG.

  In FIG. 10, the block address signal is forcibly made non-selected by the NAND circuit 41. In this case, the redundancy block RBLK is selected based on the hit signal HITBLKi (i = 1 to n).

  FIG. 11 is a circuit diagram showing an example of the excess redundancy block selection circuit 9c. Note that the circuit shown in FIG. 11 is a circuit that selects one excess redundancy block. In other words, the excess redundancy block selection circuit 9c includes a number of circuits shown in FIG. 11 corresponding to the excess redundancy block.

  Hit signals HITBLK1 to HITBLKn + m are input to the NOR circuit 47, respectively. The signal output from the NOR circuit 47 is input to the address non-select terminal Add_dis via the inverter circuit 48. Further, the hit signal HITBLKi (i = n + 1 to n + m) is input to the NAND circuit 43. The signal output from the NOR circuit 45 is output as a block selection signal SORBLKi through the inverter circuit 46. Other configurations are the same as those in FIG.

  In FIG. 11, when the hit signals HITBLK1 to HITBLKn + m are not activated, the selection of the excess redundancy block is performed based on the block address signal. On the other hand, when the hit signals HITBLK1 to HITBLKn + m are activated, the block address signal is forcibly made non-selected by the NAND circuit 41. In this case, the selection of the excess redundancy block is performed based on the hit signal HITBLKi (i = n + 1 to n + m).

  The operation of the flash memory configured as described above will be described. Here, for example, an operation check test of the flash memory is performed, and it is assumed that defects for replacement in units of blocks have occurred for s blocks.

  When s is n or less, the defective block can be replaced with the redundancy blocks RBLK1 to RBLK1. Therefore, it is not necessary to use the excess redundancy blocks ORBLK1 to ORBLK1 for redundancy, and it is possible to use them as normal blocks. Thereby, the flash memory can be relieved as a non-defective product. Specifically, a storage area for n × m blocks can be secured.

  On the other hand, when s is larger than n and equal to or smaller than (n + m), n defective blocks can be replaced with redundancy blocks RBLK1 to RBLK1. In addition, (s−n) defective blocks can be replaced by excess redundancy blocks ORBLK1 to ORBLK1 to m. Therefore, even when the defective block exceeds the redundancy blocks RBLK1 to RBLKn, it can be remedied as a non-defective product. Specifically, a storage area for (n × m− (s−n)) blocks can be secured.

  Further, when s is larger than (n + m), the defective block cannot be replaced with the redundancy blocks RBLK1 to RBLK1 to n and the excess redundancy blocks ORBLK1 to m. In this case, the flash memory is a defective product.

  In the above embodiment, the number of banks used for the excess redundancy block area is not limited to one. When two redundant blocks from the final core are used as an excess redundancy block area, address signals of (n + 2m) defective blocks are stored in the redundancy hit circuit 7. By configuring in this way, if s is n or less, all non-defective products (n × m block non-defective products), and if s is larger than n and (n + 2 m) or less, partial products ((n × m− (s−n) Flash memory can be relieved as a good block). If s is larger than (n + 2m), the flash memory becomes a defective product.

  Thus, there is a degree of freedom in the number of blocks used as the excess redundancy block area. Therefore, the criteria for determining the storage capacity of the product can be arbitrarily set.

  In addition, the flash memory according to the present embodiment is configured to allocate excess redundancy block areas in order from the bank corresponding to the higher address as the address space. As a result, only the address capacity is reduced while maintaining the continuity of the address space.

  FIG. 12 is a schematic diagram of the memory cell array 1 for explaining the redundancy block replacement operation of the present embodiment. In the flash memory according to the present embodiment, when redundancy block replacement is performed, the failure block RBLK is replaced with the redundancy block RBLK with priority over the defective block whose address space is lower in the defective block. Further, when the defective block exceeds the redundancy block RBLK, the defective block whose address space is lower in the defective block is sequentially replaced from the excess redundancy block ORBLK whose address space is higher in the last bank n.

  In FIG. 12, for example, the configuration of the memory cell array 1 includes four banks 1 to 4, four redundancy blocks RBLK 1 to 4, and seven defective blocks 1 to 7. In this case, the defective blocks 1 to 4 are replaced with redundancy blocks RBLK1 to RBLK4, respectively. In addition, the defective block 5 is replaced with the excess redundancy block ORBLKm. Further, the defective block 6 is replaced with an excess redundancy block ORBLKm-1, and the defective block 7 is replaced with an excess redundancy block ORBLKm-3.

  By doing so, it is possible to configure the flash memory so that the address capacity decreases in order from the top of the address signal while maintaining the continuity of the address space. Further, redundancy block replacement across banks can be performed.

  Note that the address space of the excess redundancy block replaced with the defective block is disabled. This is managed by the user who uses the partially acceptable flash memory.

  As described above in detail, in the present embodiment, when the number of defective blocks exceeds the number of redundancy blocks RBLK, normal blocks are used as excess redundancy blocks. Further, an excess redundancy block is allocated so as to maintain the continuity of the address space.

  Therefore, according to the present embodiment, a product that has been treated as a defective product can be remedied as a non-defective product. Thereby, the yield of good products can be improved.

  Moreover, it is not always necessary to secure a large number of redundancy blocks whose use is unknown. Thereby, an increase in the redundancy area prepared in advance can be suppressed. As a result, the chip area can be reduced.

  Further, since the continuity of the address space can be maintained, the burden on the user who uses the flash memory does not increase.

  The normal bank selection circuit 8a and the excess redundancy bank selection circuit 8b constituting the bank decoder 8 may be provided in the corresponding predecoder 2 respectively. Even if it comprises in this way, it can implement similarly to the above.

  Further, the normal block selection circuit 9a, the redundancy block selection circuit 9b, and the excess redundancy block selection circuit 9c constituting the block decoder 9 may be provided in the corresponding sub decoders 18, respectively. Even if it comprises in this way, it can implement similarly to the above.

  Further, the excess redundancy block area may be allocated in order from the bank corresponding to the lower address as the address space. Even with this configuration, it is possible to maintain the continuity of the address space.

(Second Embodiment)
In the second embodiment, the present invention is applied to a flash memory that can perform data reading (simultaneous execution) from another bank while writing or erasing data in a certain bank.

  FIG. 13 is a block diagram showing a configuration of a flash memory according to the second embodiment of the present invention. The redundancy block RBLK of the flash memory shown in FIG. 13 is provided with a predecoder 2a independently in the redundancy block and can be freely replaced with a defective block without being restricted by the bank. It is a configuration to be arranged (independent redundancy block).

  The memory cell array 1 is composed of n banks. Each bank i (i = 1 to n) includes a predecoder 2a and m blocks BLK1 to m. Each bank is provided with a predecoder 2a. Further, each block BLK is provided with a row decoder 16, a column decoder 17, and a sub-decoder 18.

  In addition, the memory cell array 1 includes redundancy blocks RBLK1 to RBLK1 to t independently of the banks. That is, when there are t or less defective blocks, the redundancy blocks RBLK1 to RBLK1 to t are used as blocks that are replaced with defective blocks. Each redundancy block RBLK is provided with a predecoder 2a, a row decoder 16, a column decoder 17, and a subdecoder 18.

  Further, in the present embodiment, o out of n banks are used as excess redundancy bank areas. In other words, when there are t + o defective blocks, the maximum (n− (o−1)) th to nth banks are used as excess redundancy bank regions. Then, a bank including o defective blocks is replaced with a maximum of o banks.

  In each bank, the read local address line 13a, the automatic local address line 13b, the read local power line 14a, the automatic local power line 14b, and the read common to each block in the bank A local data line 15a and an automatic local data line 15b are provided. Each of the sub-decoders 18 connects or disconnects the local address lines 13a and 13b, the local power supply lines 14a and 14b, and the local data lines 15a and 15b based on the block selection signal.

  Note that the data writing operation of the flash memory is an operation of automatically writing data for a plurality of addresses inside the memory when data for a plurality of addresses is continuously input from the outside. Specifically, write data for a plurality of addresses is held in a data register (not shown) provided in the memory, and the write data is automatically written into the memory cell array 1 inside the apparatus.

  Further, the data write operation includes a verify operation for verifying whether or not predetermined data is correctly programmed in the selected memory cell. Hereinafter, an operation from when a plurality of data is input from the outside until the verification is completed is referred to as an automatic operation. A local address line or the like used for the automatic operation is referred to as an automatic local address line or the like.

  Each redundancy block RBLK includes a read local address line 13a, an automatic local address line 13b, a read local power line 14a, an automatic local power line 14b, a read local data line 15a, and an automatic local data. It is connected to the line 15b.

  In the flash memory, the read address line 10a, the automatic address line 10b, the read power supply line 11a, the automatic power supply line 11b, the read data line 12a, and the automatic use are common to all banks. A data line 12b is provided. The read address line 10a is connected to each read local address line 13a. The automatic address line 10b is connected to each automatic local address line 13b. The read power supply line 11a is connected to each read local power supply line 14a. The automatic power supply line 11b is connected to each automatic local power supply line 14b. The read data line 12a is connected to each read local data line 15a. The automatic data line 12b is connected to each automatic local data line 15b.

  Each predecoder 2a connects or disconnects the read address line 10a and the read local address line 13a based on the bank selection signal. Each predecoder 2a connects or disconnects the other lines in the same manner.

  The address buffer 3 is connected to the read address line 10a and the automatic address line 10b. A read power supply circuit 4a is connected to the read local power supply line 14a. The automatic power supply circuit 4b is connected to the automatic local power supply line 14b. A read sense amplifier circuit SA5a is connected to the read local data line 15a. An automatic sense amplifier circuit SA5b is connected to the automatic local data line 15b.

  The read power circuit 4a supplies power necessary for data reading. The automatic power supply circuit 4b supplies power necessary for data writing or erasing. The read sense amplifier circuit SA5a detects and amplifies data read to the read data line 12a. The automatic sense amplifier circuit SA5b detects and amplifies data read to the automatic data line 12b by the verify operation.

  The flash memory also includes a redundancy hit circuit 7, a bank decoder 19, and a block decoder 20. When an address signal designating a defective block is input, the redundancy hit circuit 7 generates a hit signal HITBLK for replacing the defective block with the redundancy block. The hit signal HITBLK is supplied to the bank decoder 19 and the block decoder 20.

  The address signal output from the address buffer 3 is input to the redundancy hit circuit 7. The redundancy hit circuit 7 includes a defective block address storage circuit 7a and a hit detection circuit 7b.

  The defective block address storage circuit 7a stores an address signal of a block determined to be defective when the operation check test of the flash memory is performed. Further, the defective block address storage circuit 7a stores an address signal of a bank including o defective blocks in addition to address signals of t defective blocks (which is the number of redundancy blocks RBLK).

  The hit detection circuit 7b compares the address signal with the defective block address signal stored in the defective block address storage circuit 7a. If they match, the hit detection circuit 7b generates hit signals HITBLKi (i = 1 to t) and HITBANKi (i = 1 to o) for specifying the replacement redundancy block or excess redundancy bank.

  Next, the bank decoder 19 will be described. The bank decoder 19 selects a bank based on a bank address signal, a hit signal HITBLK, and the like input from the address buffer 3.

  FIG. 14 is a block diagram showing a configuration of bank decoder 19 shown in FIG. The bank decoder 19 receives a bank address signal output from the address buffer 3 and hit signals HITBLKi (i = 1 to t) and HITBANKi (i = 1 to o). The bank decoder 19 includes a normal bank selection circuit 19a, a redundancy block selection circuit 19b, and an excess redundancy bank selection circuit 19c.

  The normal bank selection circuit 19a selects the banks 1 to no based on the bank address signal or the hit signal HITBLKi. The normal bank selection circuit 19a generates a bank selection signal MBLKi (i = 1 to no). The bank selection signal MBLKi (i = 1 to no) is supplied to the predecoder 2a of the bank i corresponding to each of the banks 1 to no.

  The redundancy block selection circuit 19b selects a redundancy block (consisting of the redundancy block RBLK and the predecoder 2a) based on the bank address signal or the hit signal HITBLKi. The redundancy block selection circuit 19b generates a bank selection signal MRBLKi (i = 1 to t). The bank selection signal MRBLKi is supplied to the predecoder 2a of the corresponding redundancy block RBLKi among the redundancy blocks RBLK1 to RBLKi.

  The excess redundancy bank selection circuit 19c selects the excess redundancy banks n- (o-1) to n based on the bank address signal or the hit signal HITBLKi. The excess redundancy bank selection circuit 19c generates a bank selection signal MBLKi (i = n− (o−1) to n). The bank selection signal MBLKn is supplied to the predecoder 2a of the corresponding bank among the excess redundancy banks n- (o-1) to n.

  FIG. 15 is a circuit diagram showing an example of the normal bank selection circuit 19a. Note that the circuit shown in FIG. 15 is a circuit that selects one bank i (i = 1 to no). That is, the normal bank selection circuit 19a includes a number of circuits shown in FIG. 15 corresponding to the banks 1 to no.

  The NOR circuit 50 is input with hit signals HITBLKi (i = 1 to t) and HITBANKi (i = 1 to o). That is, the NOR circuit 50 detects whether one of the hit signals HITBLKi (i = 1 to t) or HITBANKi (i = 1 to o) is activated. The signal output from the NOR circuit 50 is input to the NAND circuit 53 via the inverter circuits 51 and 52. A bank address signal is input to the NAND circuit 53.

  A signal output from the NAND circuit 53 is output as a bank selection signal MBLKi (i = 1 to no) via the inverter circuit 54. The bank selection signal MBLKi is supplied to the predecoder 2a of the bank i.

  In FIG. 15, when the hit signals HITBLKi and HITBANKi are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLKi and HITBANKi are activated, the banks 1 to no are not selected.

  FIG. 16 is a circuit diagram showing an example of the redundancy block selection circuit 19b. Note that the circuit shown in FIG. 16 is a circuit that selects one redundancy block i (i = 1 to t). That is, the redundancy block selection circuit 19b includes a number of circuits shown in FIG. 16 corresponding to the redundancy blocks RBLK1 to RBLK1 to t.

  The power supply voltage Vdd (high level) is input to the NAND circuit 53 via the inverter circuit 52. A bank address signal is input to the NAND circuit 53.

  The signal output from the NAND circuit 53 is input to the NOR circuit 55 via the inverter circuit 54. Further, the hit signal HITBLKi (i = 1 to t) is input to the NOR circuit 55. The signal output from the NOR circuit 55 is output as a bank selection signal MRBLKi (i = 1 to t) via the inverter circuit 56. The bank selection signal MRBLKi is supplied to the predecoder 2a of the redundancy block RBLKi.

  In FIG. 16, the bank address signal is forcibly made non-selected by the NAND circuit 53. In this case, the redundancy block RBLKi is selected based on the hit signal HITBLKi (i = 1 to t).

  FIG. 17 is a circuit diagram showing an example of the excess redundancy bank selection circuit 19c. Note that the circuit shown in FIG. 17 is a circuit that selects one excess redundancy bank i (i = n− (o−1) to n). That is, the excess redundancy bank selection circuit 19c includes a number of circuits shown in FIG. 17 corresponding to the banks n- (o-1) to n.

  Hit signals HITBLKi and HITBANKi are input to the NOR circuit 50, respectively. That is, the NOR circuit 50 detects whether one of the hit signals HITBLKi and HITBANKi is activated. The signal output from the NOR circuit 50 is input to the NAND circuit 53 via the inverter circuits 51 and 52. A bank address signal is input to the NAND circuit 53.

  The signal output from the NAND circuit 53 is input to the NOR circuit 55 via the inverter circuit 54. The NOR circuit 55 receives a hit signal HITBANKi (i = 1 to o). The signal output from the NOR circuit 55 is output as a bank selection signal MBLKi (i = n− (o−1) to n) via the inverter circuit 56. The bank selection signal MBLKi is supplied to the predecoder 2a of the bank i.

  In FIG. 17, when the hit signals HITBLKi and HITBANKi are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLKi and HITBANKi are activated, the selection of the banks n- (o-1) to n is performed based on the hit signals HITBANKi (i = 1 to o).

  Next, the block decoder 20 will be described. The block decoder 20 selects a block based on a block address signal input from the address buffer 3, a hit signal HITBLK, and the like. FIG. 18 is a block diagram showing a configuration of the block decoder 20 shown in FIG. The block decoder 20 receives the block address signal output from the address buffer 3, the hit signal HITBLKi, and the bank selection signals MBLKi and MRBLKi. The block decoder 20 includes a normal block selection circuit 20a, a redundancy block selection circuit 20b, and an excess redundancy block selection circuit 20c.

  The normal block selection circuit 20a selects the blocks BLK1 to BLm based on the block address signal and the bank selection signal MBLKi (i = 1 to no). The normal block selection circuit 20a generates a block selection signal SBLKi (i = 1 to m). The block selection signal SBLKi is supplied to the sub-decoder 18 of the block BLK in the normal bank that is not used as the excess redundancy bank.

  The redundancy block selection circuit 20b selects the redundancy blocks RBLK1 to RBLK1 to t based on the bank selection signal MRBLKi (i = 1 to t) and the hit signal HITBLKi (i = 1 to t). The redundancy block selection circuit 20b generates a block selection signal SRBLKi (i = 1 to t). The block selection signal SRBLKi is supplied to the sub-decoder 18 of the redundancy block RBLKi.

  The excess redundancy block selection circuit 20c selects an excess redundancy block based on the block address signal and the bank selection signal MBLKi (i = n− (o−1) to n). The excess redundancy block selection circuit 20c generates a block selection signal SORBLKi (i = 1 to m). The block selection signal SORBLKi is supplied to the sub-decoder 18 of the excess redundancy block ORBLKi.

  Specifically, each block selection signal is supplied to a sub-decoder 18 disposed in each block. Each sub-decoder 18 connects or disconnects the local address lines 13a and 13b, the local power supply lines 14a and 14b, and the local data lines 15a and 15b based on the block selection signal. Each sub-decoder 18 has, for example, an address switch, a power switch, and a data line switch, and these switches are connected or disconnected.

  FIG. 19 is a circuit diagram showing an example of the normal block selection circuit 20a. The circuit shown in FIG. 19 is a circuit for selecting one normal block BLKi (i = 1 to m). That is, the normal block selection circuit 20a includes a number of circuits shown in FIG. 19 corresponding to the number of normal blocks BLK.

  A ground voltage Vss (low level) is supplied to the address non-selection terminal Add_dis. The address non-selection terminal Add_dis is input to the NAND circuit 61 via the inverter circuit 60. The block address signal is input to the NAND circuit 61. Further, the bank selection signal MBLKi (i = 1 to no) is input to the NAND circuit 61. The signal output from the NAND circuit 61 is input to the NOR circuit 65 via the inverter circuit 62.

  The bank selection signal MBLKi (i = 1 to no) is input to one input part of the NAND circuit 63. Further, the ground voltage Vss (low level) is supplied to the other input portion of the NAND circuit 63. A signal output from the NAND circuit 63 is input to the NOR circuit 65 via the inverter circuit 64. A signal output from the NOR circuit 65 is output as a block selection signal SBLKi (i = 1 to m) via the inverter circuit 66.

  In FIG. 19, the normal block selection circuit 20a is configured to be controlled only by a block address signal. That is, the selection of the normal block is performed based on the block address signal.

  FIG. 20 is a circuit diagram showing an example of the redundancy block selection circuit 20b. Note that the circuit shown in FIG. 20 is a circuit that selects one redundancy block RBLKi (i = 1 to t). That is, the redundancy block selection circuit 20b includes a number of circuits shown in FIG. 20 corresponding to the number of redundancy blocks RBLK.

  A power supply voltage Vdd (high level) is supplied to the address non-selection terminal Add_dis. The address non-selection terminal Add_dis is input to the NAND circuit 61 via the inverter circuit 60. The block address signal is input to the NAND circuit 61. Further, the power supply voltage Vdd (high level) is input to the NAND circuit 61. The signal output from the NAND circuit 61 is input to the NOR circuit 65 via the inverter circuit 62.

  The power supply voltage Vdd (high level) is input to the NAND circuit 63. The NAND circuit 63 receives the hit signal HITBLKi (i = 1 to t). A signal output from the NAND circuit 63 is input to the NOR circuit 65 via the inverter circuit 64. The signal output from the NOR circuit 65 is output as a block selection signal SRBLKi (i = 1 to t) via the inverter circuit 66.

  In FIG. 20, the block address signal is forcibly made non-selected by the NAND circuit 61. In this case, the redundancy block RBLK is selected based on the hit signal HITBLKi (i = 1 to t).

  FIG. 21 is a circuit diagram showing an example of the excess redundancy block selection circuit 20c. Note that the circuit shown in FIG. 21 is a circuit that selects one excess redundancy block. That is, the excess redundancy block selection circuit 20c includes a number of circuits shown in FIG. 21 corresponding to the excess redundancy block.

  The block address signal is input to the NAND circuit 61. The bank selection signal MBLKi (i = n− (o−1) to n) is input to the NAND circuit 61. The signal output from the NAND circuit 61 is input to the NOR circuit 65 via the inverter circuit 62.

  The signal output from the NOR circuit 65 is output as a block selection signal SORBLKi (i = 1 to m) via the inverter circuit 62.

  In FIG. 21, when the bank selection signal MBLKi (i = n− (o−1) to n) is not activated, the selection of the excess redundancy block is not performed. On the other hand, when the bank selection signal MBLKi (i = n− (o−1) to n) is activated, the selection of the excess redundancy block is performed based on the block address signal.

  Here, the description has been made on the premise that the design amount is reduced by using a common circuit, but the circuit may be optimized and the number of elements may be reduced within a range in which the function is realized.

  The operation of the flash memory configured as described above will be described.

  When the number of defective blocks is t or less, the defective blocks can be replaced with redundancy blocks RBLK1 to RBLK1. Therefore, it is not necessary to use the banks 1 to n as the redundancy area, and it can be used as a normal bank. Thereby, the flash memory can be relieved as a non-defective product. Specifically, a storage area for n × m blocks can be secured.

  On the other hand, when (t + o) defective blocks are generated, t defective blocks can be replaced with redundancy blocks RBLK1 to RBLK1. In addition, o defective blocks can be replaced with banks n- (o-1) to n at the maximum. Therefore, even when the defective block exceeds the redundancy blocks RBLK1 to RBLKn, it can be relieved as a partial good product. Specifically, a storage area of ((no) × m) blocks can be secured at least.

  Here, in this embodiment, unlike the first embodiment, defective blocks exceeding the number of redundancy blocks are replaced in units of banks. This is because the blocks BLK1 to m share the predecoder 2a and the data lines 15a and 15b in the bank. Therefore, if the block replacement is performed as in the first embodiment, the above-described excess redundancy blocks ORBLK may be connected to each other. This is because simultaneous execution is impossible.

  Further, an excess redundancy block area is allocated in order from the bank corresponding to the higher address as the address space. Therefore, only the address capacity is reduced while maintaining the continuity of the address space.

  FIG. 22 is a schematic diagram of the memory cell array 1 for explaining the redundancy block replacement operation of the present embodiment. In the flash memory according to the present embodiment, when redundancy block replacement is performed, the failure block RBLK is replaced with the redundancy block RBLK with priority over the defective block whose address space is lower in the defective block. Further, when the defective block exceeds the redundancy block RBLK, the bank including the defective block whose address space is lower in the defective block is replaced in order from the last bank n.

  In FIG. 22, for example, the configuration of the memory cell array 1 includes five banks 1 to 5, three redundancy blocks RBLK 1 to 3, and five defective blocks 1 to 5. In this case, the defective blocks 1 to 3 are replaced with the redundancy blocks RBLK 1 to 3 respectively. Also, the bank 2 including the defective block 4 is replaced with the excess redundancy bank 5. Further, the bank 3 including the defective block 5 is replaced with the excess redundancy bank 4.

  By doing so, it is possible to configure the flash memory so that the address capacity decreases in order from the top of the address signal while maintaining the continuity of the address space. In this case, the memory capacity is 3 banks.

  As another replacement operation, the repair method can be optimized so that the memory capacity after the repair is maximized. FIG. 23 is a schematic diagram of the memory cell array 1 for explaining another replacement operation of the present embodiment.

  The configuration of the defective block shown in FIG. 23 is the same as that in FIG. In FIG. 23, bank 1 including defective blocks 1 to 3 is replaced with bank 5. The defective block 4 is replaced with the redundancy block RBLK1. The defective block 5 is replaced with the redundancy block RBLK2.

  By doing so, it is possible to configure the flash memory so that the address capacity decreases in order from the top of the address signal while maintaining the continuity of the address space. Furthermore, by preferentially replacing a bank including a plurality of defective blocks with bank replacement, the memory capacity after repair can be maximized. In this case, the memory capacity is 4 banks.

  As described above in detail, according to this embodiment, a product that has been treated as a defective product can be remedied as a non-defective product. Thereby, a yield can be improved.

  In addition, the yield can be improved also in a flash memory that can read data from another bank (simultaneous execution) while writing or erasing data in a certain bank. Other effects are the same as those in the first embodiment.

  The normal bank selection circuit 19a, the redundancy block selection circuit 19b, and the excess redundancy bank selection circuit 19c constituting the bank decoder 19 may be provided in the corresponding predecoder 2a. Even if it comprises in this way, it can implement similarly to the above.

  In addition, the normal block selection circuit 20a, the redundancy block selection circuit 20b, and the excess redundancy block selection circuit 20c constituting the block decoder 20 may be provided in the corresponding sub-decoders 18 respectively. Even if it comprises in this way, it can implement similarly to the above.

  Further, the excess redundancy block area may be allocated in order from the bank corresponding to the lower address as the address space. Even with this configuration, it is possible to maintain the continuity of the address space.

(Third embodiment)
The third embodiment is a flash memory that can read data from other banks while writing or erasing data in a certain bank (simultaneous execution), and includes, for example, one redundancy block in each bank. The present invention is applied to.

  FIG. 24 is a block diagram showing a configuration of a flash memory according to the third embodiment of the present invention. In the flash memory having such a configuration, the redundancy block to be replaced with the defective block is limited within the bank. Further, when the number of defective blocks generated in the same bank exceeds the number of redundancy blocks, the bank is replaced with another bank.

  Each bank i includes, for example, one redundancy block RBLKi. The flash memory according to the present embodiment includes, for example, n redundancy blocks RBLK1 to RBLK1. That is, when there is one defective block in each block, the redundancy blocks RBLK1 to RBLK1 to n are used as blocks that are replaced with defective blocks.

  The address signal output from the address buffer 3 is input to the redundancy hit circuit 7. The redundancy hit circuit 7 includes a defective block address storage circuit 7a and a hit detection circuit 7b.

  The defective block address storage circuit 7a stores an address signal of a block determined to be defective when the operation check test of the flash memory is performed. The defective block address storage circuit 7a stores address signals of o defective banks in addition to address signals of n defective blocks.

  The hit detection circuit 7b compares the address signal with the defective address signal stored in the defective block address storage circuit 7a. If they match, the hit detection circuit 7b generates a hit signal HITBLKi (i = 1 to n) designating a replacement redundancy block or a hit signal HITBANKi (i = 1 to o) designating an excess redundancy bank. .

  The flash memory includes a bank decoder 21 and a block decoder 22. The bank decoder 21 selects a bank based on a bank address signal input from the address buffer 3 or a hit signal HITBLK. The block decoder 22 selects a block based on a block address signal input from the address buffer 3 or a hit signal HITBLK.

  Next, the configuration of the bank decoder 21 will be described. FIG. 25 is a block diagram showing a configuration of bank decoder 21 shown in FIG.

  The bank decoder 21 receives the bank address signal output from the address buffer 3 and hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o). The bank decoder 21 includes a normal bank selection circuit 21a and an excess redundancy bank selection circuit 21b.

  The normal bank selection circuit 21a selects the bank i based on the bank address signal and the hit signal HITBLKi. The normal bank selection circuit 21a generates a bank selection signal MBLKi (i = 1 to no). The bank selection signal MBLKi (i = 1 to no) is supplied to the predecoder 2a of the corresponding bank i (i = 1 to no).

  The excess redundancy bank selection circuit 21b selects an excess redundancy bank to be replaced with a bank having two or more defective blocks based on the bank address signal and the hit signal HITBLKi. The excess redundancy bank selection circuit 21b generates a bank selection signal MRBLKi (i = no + 1 to n). The bank selection signal MRBLKi is supplied to the predecoder 2a of the corresponding bank i.

  When the bank selection signal MBLKi or the bank selection signal MRBLKi is input, the predecoder 2a connects the read local address line 13a and the read address line 10a. The same applies to the other lines.

  FIG. 26 is a circuit diagram showing an example of the normal bank selection circuit 21a. The circuit shown in FIG. 26 is a circuit that selects one bank i. That is, the normal bank selection circuit 21a includes the circuit shown in FIG. 26 for the corresponding number of banks.

  The NOR circuit 70 is input with hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o). That is, the NOR circuit 70 detects whether one of the hit signals HITBLKi (i = 1 to n) or HITBANKi (i = 1 to o) is activated. The signal output from the NOR circuit 70 is input to the NAND circuit 73 via the inverter circuits 71 and 72. A bank address signal is input to the NAND circuit 73.

  The signal output from the NAND circuit 73 is input to the NOR circuit 75 via the inverter circuit 74. The NOR circuit 75 receives a hit signal HITBLKi (i = 1 to no). The signal output from the NOR circuit 75 is output as a bank selection signal MBLKi (i = 1 to no) via the inverter circuit 76. The bank selection signal MBLKi is supplied to the predecoder 2a of the bank i.

  In FIG. 26, when the hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o) are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o) are activated, the bank address signal is forcibly made non-selected by the NAND circuit 73. In this case, the bank is selected based on the hit signal HITBLKi (i = 1 to no).

  FIG. 27 is a circuit diagram showing an example of the excess redundancy bank selection circuit 21b. The NOR circuit 77 is supplied with a hit signal HITBLKp and HITANKp (p = the bank number). The signal output from the NOR circuit 77 is input to the NOR circuit 75 via the inverter circuit 78. The signal output from the NOR circuit 75 is output as a bank selection signal MRBLKi (i = no−1 to n) via the inverter circuit 76. The bank selection signal MRBLKi is supplied to the pre-decoder 2a of the excess redundancy bank. Other configurations are the same as those in FIG.

  In FIG. 27, when the hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o) are not activated, the bank is selected based on the bank address signal. On the other hand, when the hit signals HITBLKi (i = 1 to n) and HITBANKi (i = 1 to o) are activated, the bank address signal is forcibly made non-selected by the NAND circuit 73. In this case, the selection of the bank is performed based on the hit signal HITBLKp or HITBANKp (p = the bank number).

  Next, the configuration of the block decoder 22 will be described. FIG. 28 is a block diagram showing a configuration of the block decoder 22 shown in FIG. The block decoder 22 receives a block address signal output from the address buffer 3, a hit signal HITBLKi, and bank selection signals MBLKi and MRBLKi. The block decoder 22 includes a normal block selection circuit 22a and a redundancy block selection circuit 22b.

  The normal block selection circuit 22a selects the blocks BLK1 to m based on the block address signal, the hit signal HITBLKi (i = 1 to n), and the bank selection signal MBLKi (i = 1 to no). The normal block selection circuit 9a generates a block selection signal SBLKi (i = 1 to m). The block selection signal SBLKi is supplied to a sub-decoder 18 of a normal block that is not used as a redundancy block.

  The redundancy block selection circuit 22b selects the redundancy blocks RBLK1 to RBLK1 to n based on the block address signal, the bank selection signal MBLKi (i = 1 to no), and the hit signal HITBLKi (i = 1 to n). The redundancy block selection circuit 22b generates a block selection signal SRBLKi (i = 1 to n). The block selection signal SRBLKi is supplied to the sub decoders 18 of the corresponding redundancy blocks RBLK1-n.

  FIG. 29 is a circuit diagram showing an example of the normal block selection circuit 22a. Note that the circuit shown in FIG. 29 is a circuit that selects one normal block BLKi (i = 1 to m). That is, the normal block selection circuit 9a includes a number of circuits shown in FIG. 29 corresponding to the number of normal blocks BLK.

  The hit signals HITBLK1 to n are input to the NOR circuit 80, respectively. The signal output from the NOR circuit 80 is input to the address non-select terminal Add_dis via the inverter circuit 81. The address non-selection terminal Add_dis is input to the NAND circuit 83 via the inverter circuit 82. The block address signal is input to the NAND circuit 83. Further, the bank selection signal MBLKi (i = 1 to no) is input to the NAND circuit 83. The signal output from the NAND circuit 83 is input to the NOR circuit 87 via the inverter circuit 84.

  The bank selection signal MBLKi (i = 1 to no) is input to the NAND circuit 85. A ground voltage Vss (low level) is supplied to the input portion of the NAND circuit 85. The signal output from the NAND circuit 85 is input to the NOR circuit 87 via the inverter circuit 86. A signal output from the NOR circuit 87 is output as a block selection signal SBLKi (i = 1 to m) via the inverter circuit 88.

  In FIG. 29, the normal block selection circuit 22a is configured to be controlled only by the block address signal when the hit signals HITBLK1-n are not activated. That is, the selection of the normal block is performed based on the block address signal. When the hit signals HITBLK1 to n are activated, the block selection signal SBLKi is not activated.

  FIG. 30 is a circuit diagram showing an example of the redundancy block selection circuit 22b. Note that the circuit shown in FIG. 30 is a circuit that selects one redundancy block RBLKi (i = 1 to n). That is, the redundancy block selection circuit 22b includes a number of circuits shown in FIG. 30 corresponding to the redundancy block RBLK.

  A power supply voltage Vdd (high level) is supplied to the address non-selection terminal Add_dis. The NAND circuit 85 receives a hit signal HITBLKi (i = 1 to n). The signal output from the NOR circuit 87 is output as a block selection signal SRBLKi (i = 1 to n) via the inverter circuit 88. Other configurations are the same as those in FIG.

  In FIG. 30, the block address signal is forcibly made non-selected by the NAND circuit 83. In this case, the redundancy block RBLK is selected based on the hit signal HITBLKi (i = 1 to n).

  The block selection circuit in the excess redundancy bank is different from that shown in FIG. 29 except that the bank selection signal MRBLKi (i = no + 1 to n) is supplied instead of the bank selection signal MBLKi (i = 1 to no). It is the same structure as FIG.

  The operation of the flash memory configured as described above will be described. When one or less defective blocks are generated in one bank i, the defective blocks are replaced with the redundancy block RBLKi. That is, the normal bank selection circuit 21a generates the bank selection signal MBLKi. The bank selection signal MBLKi is supplied to the predecoder 2a of the bank i where the defective block has occurred. Further, the redundancy block selection circuit 22b generates a block selection signal SRBLKi. The block selection signal SRBLKi is input to the subdecoder 18 of the redundancy block RBLKi.

  When there are two bad blocks in the bank i, the redundancy block RBLKi is already used. In this case, the excess redundancy bank selection circuit 21b replaces the second defective block with the excess redundancy bank n. That is, the excess redundancy bank selection circuit 21b generates the bank selection signal MRBLKn. The bank selection signal MRBLKn is supplied to the predecoder 2a of the last bank n. Further, the block selection in the excess redundancy bank n is performed by a block address signal.

  When the number of defective blocks in the bank i exceeds two or there are a plurality of banks having two defective blocks, the replacement is performed in order from the bank n-1. In this case, for example, a defective block with a lower address is replaced with a bank with an upper address.

  FIG. 31 is a schematic diagram of the memory cell array 1 for explaining the redundancy block replacement operation of the present embodiment. In FIG. 31, for example, the configuration of the memory cell array 1 includes four banks 1 to 4, four redundancy blocks RBLK 1 to 4, and three defective blocks 1 to 5.

  In this case, the defective block 1 is replaced with the redundancy block RBLK1 in the same bank 1. Similarly, the defective block 2 is replaced with a redundancy block RBLK3 in the same bank 3. The defective block 3 is replaced with the bank 4 because there is no redundancy block RBLK that can be replaced in the same bank 3.

  By doing so, it is possible to configure the flash memory so that the address capacity decreases in order from the top of the address signal while maintaining the continuity of the address space. In this case, the memory capacity is 3 banks.

  As described above in detail, according to this embodiment, a product that has been treated as a defective product can be remedied as a non-defective product. Thereby, a yield can be improved. In addition, the yield can be improved also in a flash memory that can read data from another bank (simultaneous execution) while writing or erasing data in a certain bank.

  In addition, the yield can be improved even in a flash memory that does not have a redundancy block independently outside the bank.

  The normal bank selection circuit 21a and the excess redundancy bank selection circuit 21b constituting the bank decoder 21 may be provided in the corresponding predecoder 2a. Even if it comprises in this way, it can implement similarly to the above.

  Further, the normal block selection circuit 22a and the redundancy block selection circuit 22b constituting the block decoder 22 may be provided in the corresponding sub-decoders 18 respectively. Even if it comprises in this way, it can implement similarly to the above.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

1 is a block diagram showing a configuration of a flash memory according to a first embodiment of the present invention. The block diagram which shows the structure of the bank shown in FIG. The block diagram which shows the structure of the redundancy hit circuit 7 shown in FIG. FIG. 2 is a block diagram showing a configuration of a bank decoder 8 shown in FIG. FIG. 2 is a block diagram showing an example of a predecoder 2 shown in FIG. FIG. 5 is a circuit diagram showing an example of a normal bank selection circuit 8a shown in FIG. FIG. 5 is a circuit diagram showing an example of an excess redundancy bank selection circuit 8b shown in FIG. The block diagram which shows the structure of the block decoder 9 shown in FIG. FIG. 9 is a circuit diagram showing an example of a normal block selection circuit 9a shown in FIG. FIG. 9 is a circuit diagram showing an example of a redundancy block selection circuit 9b shown in FIG. FIG. 9 is a circuit diagram showing an example of an excess redundancy block selection circuit 9c shown in FIG. FIG. 3 is a schematic diagram of a memory cell array 1 for explaining an operation of redundancy block replacement. The block diagram which shows the structure of the flash memory which concerns on the 2nd Embodiment of this invention. FIG. 14 is a block diagram showing a configuration of a bank decoder 19 shown in FIG. 13. FIG. 15 is a circuit diagram showing an example of a normal bank selection circuit 19a shown in FIG. The circuit diagram which shows an example of the redundancy block selection circuit 19b shown in FIG. FIG. 15 is a circuit diagram showing an example of an excess redundancy bank selection circuit 19c shown in FIG. FIG. 14 is a block diagram showing a configuration of the block decoder 20 shown in FIG. 13. FIG. 19 is a circuit diagram showing an example of a normal block selection circuit 20a shown in FIG. FIG. 19 is a circuit diagram showing an example of a redundancy block selection circuit 20b shown in FIG. FIG. 19 is a circuit diagram showing an example of an excess redundancy block selection circuit 20c shown in FIG. FIG. 3 is a schematic diagram of a memory cell array 1 for explaining an example of a redundancy block replacement operation. FIG. 5 is a schematic diagram of a memory cell array 1 for explaining another example of a redundancy block replacement operation. FIG. 5 is a block diagram showing a configuration of a flash memory according to a third embodiment of the present invention. The block diagram which shows the structure of the bank decoder 21 shown in FIG. FIG. 26 is a circuit diagram showing an example of a normal bank selection circuit 21a shown in FIG. FIG. 26 is a circuit diagram showing an example of an excess redundancy bank selection circuit 21b shown in FIG. The block diagram which shows the structure of the block decoder 22 shown in FIG. FIG. 29 is a circuit diagram showing an example of a normal block selection circuit 22a shown in FIG. FIG. 29 is a circuit diagram showing an example of a redundancy block selection circuit 22b shown in FIG. 28. FIG. 3 is a schematic diagram of a memory cell array 1 for explaining an example of a redundancy block replacement operation.

Explanation of symbols

  BL ... bit line, WL ... word line, MC ... memory cell, 1 ... memory cell array, 2, 2a ... predecoder, 3 ... address buffer, 4, 4a, 4b ... power supply circuit, 5, 5a, 5b ... SA, 6 ... interface circuit, 7 ... redundancy hit circuit, 7a ... defective block address storage circuit, 7b ... hit detection circuit, 8, 19, 21 ... bank decoder, 8a, 19a, 21a ... normal bank selection circuit, 8b, 19c, 21b ... Excess redundancy bank selection circuit, 9, 20, 22 ... block decoder, 9a, 20a, 22a ... normal block selection circuit, 9b, 19b, 20b, 22b ... redundancy block selection circuit, 9c, 20c ... excess redundancy block selection circuit, 10 , 10a, 10b ... address lines, 11, 11a, 11b ... power supply lines, 1 , 12a, 12b ... data lines, 13, 13a, 13b ... local address lines, 14, 14a, 14b ... local power supply lines, 15, 15a, 15b ... local data lines, 16 ... row decoder, 17 ... column decoder, 18 ... Sub-decoder, 30, 35, 37, 45, 47, 50, 55, 65, 70, 75, 77, 80, 87 ... NOR circuit, 33, 41, 43, 53, 61, 63, 73, 83, 85 ... NAND circuit 31, 32, 34, 36, 38, 40, 42, 44, 46, 48, 51, 52, 54, 56, 60, 62, 64, 66, 71, 72, 74, 76, 78, 81 , 82, 84, 86, 88... Inverter circuit.

Claims (5)

A memory cell array including a plurality of normal blocks and a plurality of redundancy blocks, each of which includes a block composed of one or a plurality of memory cells serving as a data erasing unit;
When the number of defective blocks in the normal block exceeds the number of redundancy blocks, the defective block is replaced with a normal block in the same chip , and replacement is performed so that the address space of the memory cell array is continuous. A semiconductor memory device comprising a replacement circuit. 2. The semiconductor memory device according to claim 1 , wherein the replacement circuit uses normal blocks that are replaced with the defective blocks in order from the end of the address space . The memory cell array is composed of a plurality of banks having a plurality of said normal block respectively, and at least one of the bank semiconductor memory according to claim 1 or 2, characterized in that it has the redundancy block apparatus. The replacement circuit includes a storage circuit that stores a first address of the defective block;
4. The semiconductor memory device according to claim 1, further comprising: a detection circuit that detects that the defective block is designated based on the first address. 5.   5. The semiconductor memory device according to claim 1, further comprising a selection circuit that selects the normal block to be replaced with the defective block.

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