JP4309379B2 - Circuit board and manufacturing method thereof - Google Patents

Circuit board and manufacturing method thereof Download PDF

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JP4309379B2
JP4309379B2 JP2005186357A JP2005186357A JP4309379B2 JP 4309379 B2 JP4309379 B2 JP 4309379B2 JP 2005186357 A JP2005186357 A JP 2005186357A JP 2005186357 A JP2005186357 A JP 2005186357A JP 4309379 B2 JP4309379 B2 JP 4309379B2
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insulating layer
plating
pattern
conductor
recess
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克郎 青島
要吾 高橋
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Meiko Co Ltd
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Description

本発明は回路基板とその製造方法に関し、更に詳しくは、中空状態で各種の受動部品、とりわけ空心コイル部品が内蔵されている回路基板と、その受動部品を回路パターンを形成する過程で同時に形成することができる回路基板の製造方法に関する。   The present invention relates to a circuit board and a method of manufacturing the circuit board. More specifically, the present invention relates to a circuit board in which various passive components, particularly air core coil components, are formed in a hollow state, and the passive components are simultaneously formed in the process of forming a circuit pattern. The present invention relates to a method for manufacturing a circuit board.

携帯電話に代表される各種の電子機器の小型化、多機能化、高速化などが急速に進んでいるが、そのことに伴って、機器に組み込まれる回路基板に関しては、回路パターンのファイン化、多層構造化、部品実装密度の高密度化などの検討と並んで、実装される各種の受動部品の機能を回路基板に内蔵させる研究も進められている。
例えば、コンデンサの場合、回路基板の製造過程で、絶縁基材の内部に平行配置されてそれぞれは電極として機能する２層の導電層と、それら導電層の間に挟まれている誘電体材料の層によって、平行平板型のコンデンサ構造体を同時に組み込むことにより、このコンデンサ構造体が絶縁基板の厚み方向に内蔵されている構造の多層回路基板が知られている（特許文献１を参照）。 Various electronic devices represented by mobile phones are rapidly becoming smaller, multifunctional, and faster, but along with that, circuit boards incorporated in devices are becoming finer. Along with studies on multi-layered structures and increased component mounting density, research is underway to incorporate the functions of various passive components to be mounted in the circuit board.
For example, in the case of a capacitor, in the process of manufacturing a circuit board, two conductive layers that are arranged in parallel inside the insulating base and each function as an electrode, and a dielectric material sandwiched between the conductive layers A multilayer circuit board having a structure in which a capacitor structure is built in the thickness direction of an insulating substrate by incorporating parallel plate type capacitor structures by layers simultaneously is known (see Patent Document 1).

しかしながら、細い導体をコイリングして製造された３次元構造体であるコイル部品の場合は、各層に回路パターンを形成しながら単位基板を積層していく多層回路基板の製造過程で、同時にこのようなコイル部品をある層に組み込むことは事実上不可能である。
そのため、コイル部品の場合は、回路基板の製造過程で内蔵されるのではなく、別工程で既に製作されているコイル部品を、完成した回路基板の表面に外付けで実装されているのが通例である。
特表平５−５００１３６号公報 However, in the case of a coil component that is a three-dimensional structure manufactured by coiling thin conductors, such a process is simultaneously performed in the manufacturing process of a multilayer circuit board in which unit substrates are stacked while forming a circuit pattern on each layer. It is virtually impossible to incorporate coil components into a layer.
For this reason, in the case of coil components, it is not usually built in the circuit board manufacturing process, but coil components already manufactured in a separate process are externally mounted on the surface of the completed circuit board. It is.
Japanese translation of PCT publication No. 5-500136

本発明は、受動部品、とくに３次元構造体のコイル部品が組み込まれている新規な構造の回路基板と、回路基板を製造していく過程で、同時に、受動部品を当該回路基板に組み込むことができる回路基板の製造方法の提供を目的とする。   The present invention provides a circuit board having a novel structure in which a passive component, particularly a coil component of a three-dimensional structure, and a process of manufacturing the circuit board. At the same time, the passive component can be incorporated into the circuit board. An object of the present invention is to provide a method for manufacturing a circuit board.

上記した目的を達成するために、本発明においては、基板表面に形成された有底凹部と、前記有底凹部の空間内に一部または全部が中空状態で形成されている受動部品とを備え、
前記受動部品は、めっき材料を用いた電気めっき法で形成され、断面が四角形の線状導体から成り、その上面が前記基板表面と面一状態になっていることを特徴とする回路基板が提供される。
受動部品としては、前記有底凹部の空間内に完全中空状態で前記有底凹部を横断する導体回路部品と、断面四角形状に巻回された空心コイル部品であって、前記空心コイル部品の下辺導体部分は前記有底凹部の底部に埋設され、上辺導体部分と両側導体部分は前記凹部の空間内に裸出しているものが例示される。 In order to achieve the above object, the present invention includes a bottomed recess formed on a substrate surface and a passive component partly or entirely formed in a hollow state in the space of the bottomed recess. ,
The passive component is formed by an electroplating method using a plating material, is formed of a linear conductor having a square cross section, and an upper surface thereof is flush with the substrate surface. Is done.
The passive component includes a conductor circuit component that traverses the bottomed recess in a completely hollow state in the space of the bottomed recess, and an air core coil component that is wound in a square cross-section, and a lower side of the air core coil component The conductor part is embedded in the bottom part of the bottomed recessed part, and the upper side conductor part and both side conductor parts are exposed in the space of the recessed part.

また、本発明においては、平滑基板の片面に成膜された導体薄膜の表面に、第一めっき材料から成り、形成すべき受動部品と同一形状を有する第一めっき部と、前記第一めっき部を埋設し、かつ前記第一めっき材料とは異質の第２めっき材料から成り、形成すべき有底凹部と同一形状を有する第２めっき部とを有する中間材Ａを製造する工程Ａ；
前記中間材Ａの前記第２めっき部側の表面に絶縁基材を熱圧プレスして一体化構造物Ｂを製造する工程Ｂ；および、
前記一体化構造物Ｂから前記平滑基板と前記導体薄膜を順次除去して前記第２めっき部の一部表面と前記受動部品の一部表面を表出させたのち、前記第２めっき部のみを選択的にエッチング除去して前記有底凹部を形成する工程Ｃ；
を備えていることを特徴をする回路基板の製造方法が提供される。 Further, in the present invention, the surface of the conductive thin film formed on one surface of the smooth substrate is made of the first plating material, and has the same shape as the passive component to be formed, and the first plating portion And manufacturing an intermediate material A having a second plated portion having the same shape as the bottomed recess to be formed, which is made of a second plated material different from the first plated material;
A step B of manufacturing an integrated structure B by hot-pressing an insulating base material on the surface of the intermediate material A on the second plating part side; and
After removing the smooth substrate and the conductive thin film sequentially from the integrated structure B to expose a partial surface of the second plated portion and a partial surface of the passive component, only the second plated portion is exposed. A step C of selectively removing by etching to form the bottomed recess;
A circuit board manufacturing method is provided.

そして、上記した導体回路部品を有する中間材Ａを製造する場合には、上記した工程Ａが、
平滑基板の片面に成膜された導体薄膜の表面を被覆して絶縁層ａを形成し、前記絶縁層ａに露光・現像処理を行なって、少なくとも前記導体回路部品を形成すべき箇所の前記絶縁層ａを除去することにより、前記導体回路部品の平面パターンと同じ平面パターンを有し、かつ前記導体薄膜の表面が表出している凹部パターンａを形成し、ついで、電気めっき法で、前記凹部パターンａの中に、残置する前記絶縁層ａの表面と面一状態になるまで第１めっき材料を充填して第１めっき部を形成する工程Ａ1；
前記第１めっき部を含む表面全部を被覆して絶縁層ｂを形成し、前記絶縁層ｂに露光・現像処理を行なって、有底凹部を形成すべき箇所の前記絶縁層ｂを除去することにより、形成すべき有底凹部と同一形状を有し、かつ前記第１めっき部の表面と前記導体薄膜の表面が表出している凹部パターンｂを形成し、ついで、電気めっき法で、前記凹部パターンｂの中に、残置する前記絶縁層ｂの表面と面一状態になるまで、前記第１めっき材料とは異質な第２めっき材料を充填して第２めっき部を形成する工程Ａ2；および、
前記第２めっき部を含む表面全部を被覆して絶縁層ｃを形成し、前記絶縁層ｃに露光・現像処理を行なって、前記第２めっき部９の一部表面と前記第１めっき部の両端部分の表面が表出する凹部パターンｃを形成し、ついで、電気めっき法で、前記凹部パターンｃの中に、残置する前記絶縁層ｃの表面と面一状態になるまで前記第１めっき材料を充填したのち、前記絶縁層ｃを除去する工程Ａ3；
を備えている。 And when manufacturing the intermediate material A which has an above-described conductor circuit component, the above-mentioned process A includes
An insulating layer a is formed by covering the surface of the conductive thin film formed on one surface of the smooth substrate, and the insulating layer a is exposed and developed, so that at least the insulating portion where the conductor circuit component is to be formed is formed. By removing the layer a, a concave pattern a having the same planar pattern as that of the conductor circuit component and exposed on the surface of the conductive thin film is formed, and then the concave portion is formed by electroplating. Step A 1 of filling the first plating material in the pattern a until the surface of the insulating layer a to be left is flush with the surface of the pattern a to form the first plating portion;
Covering the entire surface including the first plating portion to form an insulating layer b, exposing and developing the insulating layer b, and removing the insulating layer b where a bottomed recess is to be formed To form a recess pattern b having the same shape as the bottomed recess to be formed and the surface of the first plating portion and the surface of the conductor thin film exposed, and then by electroplating, Step A 2 in which a second plating material different from the first plating material is filled in the pattern b until the surface of the insulating layer b to be left is flush with the pattern b to form a second plating portion; and,
An insulating layer c is formed by covering the entire surface including the second plating part, and an exposure / development treatment is performed on the insulating layer c, so that a part of the surface of the second plating part 9 and the first plating part are formed. A concave pattern c is formed so that the surfaces of both end portions are exposed, and then the first plating material is in a state flush with the surface of the insulating layer c to be left in the concave pattern c by electroplating. Step A 3 of removing the insulating layer c after filling
It has.

また、受動部品が上記した空心コイル部品を有する中間材Ａである場合には、上記した工程Ａが、
平滑基板の片面に成膜された導体薄膜の表面を被覆して絶縁層ｄを形成し、前記絶縁層ｄに露光・現像処理を行なって、前記空心コイル部品の上辺導体部分を形成すべき箇所の前記絶縁層ｄを除去することにより、そこに前記上辺導体部分と同一の平面パターンを有し、かつ前記導体薄膜の表面が表出している凹部パターンｄを形成し、ついで、電気めっき法で、前記凹部パターンｄの中に、残置する前記絶縁層ｄの表面と面一状態になるまで第１めっき材料を充填して前記空心コイル部品の上辺導体部分を形成する工程Ａ4；
前記上辺導体部を含む表面全部を被覆して絶縁層ｅを形成し、前記絶縁層ｅに露光・現像処理を行なって、コイルの両側導体部分を形成すべき箇所の前記絶縁層ｅを除去することにより、そこに前記上辺導体部分の端部表面が表出している凹孔パターンｅを形成し、ついで、電気めっき法で、前記凹孔パターンｅの中に、残置する前記絶縁層ｅの表面と面一状態になるまで前記第１めっき材料を充填して前記空心コイル部品の両側導体部分を形成する工程Ａ5；
前記両側導体部分の表面を含む表面全部を被覆して絶縁層ｆを形成し、前記絶縁層ｆに露光・現像処理を行なって、有底凹部を形成すべき箇所の前記絶縁層ｆを除去することにより、形成すべき前期有底凹部と同一形状を有し、かつ前記上辺導体部分と前記両側導体部分と前記導体薄膜の表面が表出している凹部パターンｆを形成し、ついで、電気めっき法で、前期凹部パターンｆの中に、前記両側導体部分の下部端面と面一状態になるまで第２めっき材料を充填して第２めっき部を形成する工程Ａ6；および
前記第２めっき部の表面を含む表面全部を被覆して絶縁層ｇを形成し、前記絶縁層ｇに露光・現像処理を行なって、前記空心コイル部品の下辺導体部分を形成すべき箇所の前記絶縁層ｇを除去することにより、前記両側導体部分の下部端面と前記第２めっき部の表面が表出している凹部パターンｇを形成し、ついで、電気めっき法で、前記凹部パターンｇの中に、残置する前記絶縁層ｇの表面と面一状態になるまで前記第１めっき材料を充填してコイルの下辺導体部分を形成したのち、前記絶縁層ｄ，ｅ，ｆ，ｇの全てを除去する工程Ａ7；
を備えている。 Further, when the passive component is the intermediate material A having the above-described air-core coil component, the above-described step A is
A portion where the surface of the conductive thin film formed on one surface of the smooth substrate is covered to form an insulating layer d, and the insulating layer d is exposed and developed to form an upper conductor portion of the air-core coil component. By removing the insulating layer d, a recess pattern d having the same plane pattern as the upper side conductor portion and exposing the surface of the conductive thin film is formed, and then electroplating is used. Step A 4 of filling the first plating material in the concave pattern d until the surface of the insulating layer d to be left is flush with the surface of the insulating layer d to form the upper conductor portion of the air-core coil component;
An insulating layer e is formed so as to cover the entire surface including the upper conductor portion, and the insulating layer e is exposed and developed to remove the insulating layer e where the both-side conductor portions of the coil are to be formed. Then, a concave hole pattern e in which the end surface of the upper side conductor portion is exposed is formed thereon, and then the surface of the insulating layer e to be left in the concave hole pattern e by electroplating. Filling the first plating material until it is flush with the first plating material to form both side conductor portions of the air-core coil component A 5 ;
An insulating layer f is formed so as to cover the entire surface including the surfaces of the both-side conductor portions, and the insulating layer f is exposed and developed to remove the insulating layer f where a bottomed recess is to be formed. Thus, a concave pattern f having the same shape as the first bottomed concave portion to be formed and the surface of the upper side conductor portion, the both side conductor portions, and the conductive thin film is exposed, and then electroplating is performed. And the step A 6 of filling the second plating material into the recess pattern f in the previous period until it is flush with the lower end faces of the both side conductor portions to form the second plating portion; and An insulating layer g is formed so as to cover the entire surface including the surface, and the insulating layer g is exposed and developed to remove the insulating layer g where the lower conductor portion of the air-core coil component is to be formed. Under the conductor parts on both sides A recess pattern g in which the end face of the part and the surface of the second plating part are exposed is formed, and then the surface of the insulating layer g to be left is flush with the surface of the recess pattern g by electroplating. Step A 7 in which the first plating material is filled until the bottom conductor portion of the coil is formed, and then all of the insulating layers d, e, f, and g are removed.
It has.

本発明の回路基板の場合、例えば空心コイル部品は有底凹部の空間内に空心状態で形成され、誘電率が１の空気に取り囲まれているので、高効率のリアクタンス素子として機能する。
また、本発明の受動部品は、フォトリソグラフィーとエッチング技術および電気めっき法を組み合わせて形成されるので、例えばその線幅や厚み、各線間距離などの寸法精度は高くなる。 In the case of the circuit board of the present invention, for example, the air-core coil component is formed in the air-core state in the space of the bottomed recess, and is surrounded by air having a dielectric constant of 1, and thus functions as a highly efficient reactance element.
In addition, since the passive component of the present invention is formed by combining photolithography, an etching technique, and an electroplating method, for example, the dimensional accuracy such as the line width and thickness, and the distance between each line is increased.

最初に、本発明の回路基板の概略斜視図を図１、図２に示す。図１は、受動部品が例えば抵抗素子のような導体回路部品である場合の回路基板（Ｉ）を示す。
図２は、受動図品がコイル部品である場合の回路基板（II）を示す。
いずれの回路基板においても、基板１の表面１ａには平面視形状が四角形である有底の凹部２が形成されている。そして、この凹部２の空間の中には、導体回路部品３Ａ（回路基板（Ｉ）の場合）や、コイル部品３Ｂ（回路基板（II）の場合）が形成されている。 First, schematic perspective views of a circuit board of the present invention are shown in FIGS. FIG. 1 shows a circuit board (I) when the passive component is a conductor circuit component such as a resistance element.
FIG. 2 shows the circuit board (II) when the passive component is a coil component.
In any circuit board, a bottomed recess 2 having a square shape in plan view is formed on the surface 1a of the board 1. In the space of the recess 2, a conductor circuit component 3A (in the case of the circuit board (I)) and a coil component 3B (in the case of the circuit board (II)) are formed.

導体回路部品３Ａとコイル部３Ｂの両端は、いずれも、これらが後述する工程を経て形成されるときに同時に形成される端子部４、４と一体構造になっている。
回路基板（Ｉ）の導体回路部品３Ａは、断面が四角形の線状導体が凹部２の空間内において完全な中空状態で同一平面内を延びて、全体として当該凹部２を横断する扁平形状になっている。その場合、導体回路部３Ａの上面３ａと基板１の表面１ａは面一状態になっている。また、凹部２の底面には、端子部４，４と接続する回路パターン（図示しない）が形成されている。 Both ends of the conductor circuit component 3A and the coil portion 3B have an integral structure with the terminal portions 4 and 4 that are formed simultaneously when they are formed through the steps described later.
The conductor circuit component 3A of the circuit board (I) has a flat shape in which a linear conductor having a square cross section extends in the same plane in a completely hollow state in the space of the recess 2 and crosses the recess 2 as a whole. ing. In that case, the upper surface 3a of the conductor circuit portion 3A and the surface 1a of the substrate 1 are flush with each other. A circuit pattern (not shown) connected to the terminal portions 4 and 4 is formed on the bottom surface of the recess 2.

一方、回路基板（II）のコイル部品３Ｂの場合は、断面四角形の線状導体が凹部２の上下方向→斜横方向に順次巻回されて、全体として３次元構造体になっている。
このコイル部品３Ｂの個々の巻回部を端子部４，４の方から見ると（凹部２の長手方向から見ると）、その形状は、図３で示したように、大略、環状の四角形に見える。
そこで、以後、このコイル部品３Ｂの環状四角形において、上辺に位置する部分を上位導体部分３Ｂ1、下辺に位置する部分を下辺導体部分３Ｂ2、両側に位置する部分を両側導体部分３Ｂ3という。 On the other hand, in the case of the coil component 3B of the circuit board (II), a linear conductor having a square cross section is wound in order from the vertical direction of the concave portion 2 to the oblique horizontal direction to form a three-dimensional structure as a whole.
When the individual winding portions of the coil component 3B are viewed from the terminal portions 4 and 4 (viewed from the longitudinal direction of the concave portion 2), the shape thereof is generally an annular quadrangle as shown in FIG. appear.
Therefore, hereinafter, in the annular quadrilateral of the coil component 3B, a portion located on the upper side is referred to as an upper conductor portion 3B 1 , a portion located on the lower side is referred to as a lower conductor portion 3B 2 , and portions located on both sides are referred to as both-side conductor portions 3B 3 .

これらの各導体部分は、後述するように、いずれも同一のめっき材料を用いた電気めっき法で一体的に形成され、それぞれの境界部では互いに直角をなして方向転換をしている。
そして、凹部２の空間内に形成されるこのコイル部品３Ｂの場合、下辺導体部分３Ｂ2は凹部２の底部になっている基板１の中に埋設されている。しかし、両側導体部分３Ｂ3と上辺導体部分３Ｂ1は、いずれも、凹部２の空間内に裸出している。 As will be described later, each of these conductor portions is integrally formed by electroplating using the same plating material, and the direction is changed at right angles to each other at each boundary portion.
In the case of this coil component 3 </ b > B formed in the space of the recess 2, the lower-side conductor portion 3 </ b > B 2 is embedded in the substrate 1 that is the bottom of the recess 2. However, both the side conductor portions 3B 3 and the upper side conductor portion 3B 1 are bare in the space of the recess 2.

したがって、このコイル部品３Ｂでは、磁力線は誘電率１の空気中を通過できる。すなわち、このコイル部品３Ｂは、空心コイル部品として機能することができる。
次に、本発明の回路基板の製造方法を詳細に説明する。
本発明の製造方法は、まず、平滑基板の片面に成膜された導体薄膜の表面に、受動部品になる第１めっき部とそれを収容する有底凹部になる第２めっき部を備えた中間材Ａを製造する工程Ａと、この中間材Ａと絶縁基材を熱圧プレスして一体化構造物Ｂを製造する工程Ｂと、この一体化構造物Ｂから第２めっき部のみを除去して前記有底凹部を形成する工程Ｃで構成されている。 Therefore, in this coil component 3B, the magnetic lines of force can pass through the air having a dielectric constant of 1. That is, this coil component 3B can function as an air-core coil component.
Next, the method for manufacturing a circuit board according to the present invention will be described in detail.
In the manufacturing method of the present invention, first, an intermediate provided with a first plating portion that becomes a passive component and a second plating portion that becomes a bottomed recess that accommodates it on the surface of a conductive thin film formed on one surface of a smooth substrate. Step A for manufacturing the material A, Step B for manufacturing the integrated structure B by hot pressing the intermediate material A and the insulating base material, and removing only the second plating portion from the integrated structure B The step C is formed to form the bottomed recess.

その場合、回路基板（Ｉ）と回路基板（II）の場合では、上記した工程Ａの態様が異なってくる。
そこで、最初に、回路基板（Ｉ）の製造方法について説明する。
まず、工程Ａ1について説明する。
図４で示したように、表面が平滑で、比較的厚く、剛性を有する平滑基板５を用意し、その片面に、電気めっき法やスパッタ法のような公知の薄膜形成法で導体薄膜６を成膜する。 In that case, the aspect of the above-mentioned process A differs in the case of circuit board (I) and circuit board (II).
First, a method for manufacturing the circuit board (I) will be described.
First, the process A 1 will be described.
As shown in FIG. 4, a smooth substrate 5 having a smooth surface, a relatively thick and rigid surface is prepared, and a conductive thin film 6 is formed on one surface thereof by a known thin film forming method such as electroplating or sputtering. Form a film.

平滑基材５としては、表面が平滑であればその材質は問わないが、例えばステンレス鋼板、ガラス板などをあげることができる。また導体薄膜の材料としては例えばＮｉやＣｕをあげることができ、その厚みは３〜８μｍとピンホールが発生しない程度の厚みであればよい。
ついで、図５で示したように、導体薄膜６の表面６ａを被覆して所定厚み（ｔ1とする）の絶縁層７（絶縁層ａ）を形成する。具体的には、例えば厚みｔ1のドライフィルムを貼着したり、液体レジストを厚みｔ1となるように印刷して形成する。 The material of the smooth base 5 is not limited as long as the surface is smooth, and examples thereof include a stainless steel plate and a glass plate. Examples of the material for the conductor thin film include Ni and Cu. The thickness of the conductor thin film may be 3 to 8 μm so long as no pinhole is generated.
Next, as shown in FIG. 5, an insulating layer 7 (insulating layer a) having a predetermined thickness (t 1 ) is formed by covering the surface 6 a of the conductor thin film 6. Specifically, for example, a dry film having a thickness of t 1 is attached, or a liquid resist is printed so as to have a thickness of t 1 .

なお、上記した厚みｔ1は、図１で示した導体回路部品３Ａの厚みと等値にする。
ついで、この絶縁層ａに露光・現像処理を行なって、導体回路部品３Ａを形成すべき箇所の絶縁層ａを除去し、図６で示したように、導体薄膜６の表面６ａが表出している凹部パターン８（凹部パターンａ）を形成する。
なお、この凹部パターン８は、図７で示したように、形成すべき導体回路部品３Ａの平面パターンと同じ平面パターンになっている。 The thickness t 1 is equal to the thickness of the conductor circuit component 3A shown in FIG.
Next, the insulating layer a is exposed and developed to remove the insulating layer a where the conductor circuit component 3A is to be formed, and as shown in FIG. 6, the surface 6a of the conductor thin film 6 is exposed. The recessed pattern 8 (recessed pattern a) is formed.
As shown in FIG. 7, the recess pattern 8 has the same planar pattern as the planar pattern of the conductor circuit component 3A to be formed.

ついで、導体薄膜６（または平滑基板５が導電材である場合は平滑基板５）をマイナス極にして電気めっきを行ない、凹部パターン８の中に第１めっき材料を充填して第１めっき部９を形成し、図８で示したような中間材Ａ1を製造する。
その場合、図８で示したように、第１めっき部９の表面９ａと絶縁層７の表面７ａは面一状態となるように電気めっきが行なわれる。 Next, electroplating is performed with the conductor thin film 6 (or the smooth substrate 5 when the smooth substrate 5 is a conductive material) as a negative electrode, and the first plating material 9 is filled in the concave pattern 8 by filling the first plating material. And an intermediate material A 1 as shown in FIG. 8 is manufactured.
In that case, as shown in FIG. 8, the electroplating is performed so that the surface 9a of the first plating portion 9 and the surface 7a of the insulating layer 7 are flush with each other.

ついで、工程Ａ2について説明する。
工程Ａ2では、まず、図８で示した中間材Ａ1の第１めっき部９も含めた全体の表面を被覆して所定厚み（ｔ2とする）の絶縁層１０（絶縁層ｂ）を形成する（図９）。
ここで、絶縁層１０の厚みｔ2と絶縁層７の厚みｔ1の合計が、図１で示した凹部２の深さと等値になるように、上記した厚みｔ2が決められる。 Next, the step A 2 will be described.
In step A 2 , first, an insulating layer 10 (insulating layer b) having a predetermined thickness (t 2 ) covering the entire surface including the first plating portion 9 of the intermediate material A 1 shown in FIG. Form (FIG. 9).
Here, a total thickness t 1 of the thickness t 2 and the insulating layer 7 of insulating layer 10 is such that the depth and equality recess 2 shown in FIG. 1, the thickness t 2 as described above is determined.

ついで、この絶縁層１０に露光・現像処理を行なって、凹部２を形成すべき箇所の絶縁層１０を除去し、更に対応する箇所の絶縁層７も除去する。
このとき、導体回路部品３Ａと接続する端子部４，４（図１）を形成するために、第１めっき部９における両端部では、絶縁層７と絶縁層１０を残しておく。
その結果、図１０で示したように、絶縁層１０の表面からの深さが（ｔ1＋ｔ2）であり、内部には導体薄膜６の表面６ａと第１めっき部９の表面が表出している凹部パターン１１（凹部パターンｂ）が形成される。 Next, the insulating layer 10 is exposed and developed to remove the insulating layer 10 where the recesses 2 are to be formed, and further remove the corresponding insulating layer 7.
At this time, in order to form the terminal portions 4 and 4 (FIG. 1) connected to the conductor circuit component 3A, the insulating layer 7 and the insulating layer 10 are left at both ends of the first plating portion 9.
As a result, as shown in FIG. 10, the depth from the surface of the insulating layer 10 is (t 1 + t 2 ), and the surface 6 a of the conductor thin film 6 and the surface of the first plating portion 9 are exposed inside. The recessed pattern 11 (recessed pattern b) is formed.

ついで、導体薄膜６（または平滑基板５）をマイナス極にして電気めっきを行ない、凹部パターン１１の中に第２めっき材料を充填して第２めっき部１２を形成して中間材Ａ2を製造する。
その場合、図１１で示したように、第２めっき部１２の表面１２ａと絶縁層１０の表面１０ａは面一状態となるように電気めっきが行なわれる。 Then, subjected to electroplating with the conductive thin film 6 (or smooth substrate 5) to the negative pole, producing an intermediate material A 2 to form a second plating section 12 is filled with a second plating material in the recess pattern 11 To do.
In that case, as shown in FIG. 11, the electroplating is performed so that the surface 12a of the second plating portion 12 and the surface 10a of the insulating layer 10 are in a flush state.

次に工程Ａ3について説明する。
この工程Ａ3では、図１２で示したように、まず、中間材Ａ2の全体表面を所望する厚み（ｔ3とする）の絶縁層１３（絶縁層ｃ）で被覆したのち、露光・現像処理を行なって、端子部４，４（図１）になるべき第１めっき部９の表面と第２めっき部１２の一部表面が所定のパターンで表出している凹部パターン１４（凹部パターンｃ）を形成する。したがって、このときの絶縁層の全体の厚み（ｔ1＋ｔ2＋ｔ3）は、中間材Ａ2の絶縁層全体の厚み（ｔ1＋ｔ2）よりも厚くなっていて、第２めっき材１２の表面は全体の表面から深さｔ3だけ凹没した状態になっている。 Next, Step A 3 will be described.
In this step A 3 , as shown in FIG. 12, first, the entire surface of the intermediate material A 2 is covered with an insulating layer 13 (insulating layer c) having a desired thickness (t 3 ), and then exposed and developed. By performing the processing, the surface of the first plating part 9 and the partial surface of the second plating part 12 to be the terminal parts 4 and 4 (FIG. 1) are exposed in a predetermined pattern (recess pattern c). ). Therefore, the total thickness (t 1 + t 2 + t 3 ) of the insulating layer at this time is thicker than the total thickness (t 1 + t 2 ) of the entire insulating layer of the intermediate material A 2 . The surface is recessed from the entire surface by a depth t 3 .

ついで、導電薄膜６（または平滑基板５）をマイナス極にして電気めっきを行ない、凹部パターン１４の中に第１めっき材料を充填する。
その結果、図１３で示したように、形成すべき凹部２と同一形状をした第２めっき部１２の側部は第１めっき材料のめっき層１５で被覆され、かつめっき層１５が端子部になるべき第１めっき部９と一体化しており、また第２めっき部１２の表面には、厚みｔ3で第１めっき材料から成る回路パターン１５が形成される。 Next, electroplating is performed with the conductive thin film 6 (or the smooth substrate 5) as the negative electrode, and the concave plating pattern 14 is filled with the first plating material.
As a result, as shown in FIG. 13, the side portion of the second plating portion 12 having the same shape as the recess 2 to be formed is covered with the plating layer 15 of the first plating material, and the plating layer 15 is formed on the terminal portion. A circuit pattern 15 made of the first plating material with a thickness t 3 is formed on the surface of the second plating part 12, which is integrated with the first plating part 9 to be formed.

ついで、絶縁層１３を除去する。その結果、図１４で示したように、第２めっき部１２の表面には第１めっき材料から成り、第１めっき部９の両端箇所と接続している厚みｔ3の回路パターン１５を有する中間材Ａが製造される。
また、上記した工程Ａ1〜工程Ａ3において、第１めっき材料と第２めっき材料は互いに異質な材料が使用される。そして、第２めっき材料は後述するエッチング処理時に除去されるのであるが、第１めっき材料としては、このエッチング処理時にあってもエッチング除去されることのない材料であることが必要である。具体的には、第１めっき材料にはＮｉ，第２めっき材料にはＣｕが使用される。 Next, the insulating layer 13 is removed. As a result, as shown in FIG. 14, the surface of the second plating part 12 is made of the first plating material and has an intermediate circuit pattern 15 having a thickness t 3 connected to both end portions of the first plating part 9. Material A is manufactured.
Further, in the above-described steps A 1 to A 3 , different materials are used for the first plating material and the second plating material. The second plating material is removed during the etching process described later, but the first plating material needs to be a material that is not etched away even during the etching process. Specifically, Ni is used for the first plating material and Cu is used for the second plating material.

本発明では、工程Ａで製造された上記中間材Ａに対し、次に工程Ｂが行なわれる。
工程Ｂでは、中間材Ａのめっき層１５側の表面に絶縁基材１６を対向配置したのち、両者を熱圧プレスすることにより、図１５で示した一体化構造物Ｂが製造される。
なお、このとき、中間材Ａにおける絶縁層７，１０を除去してから熱圧プレスしてもよく、また除去することなく熱圧プレスしてもよい。 In the present invention, the process B is then performed on the intermediate material A produced in the process A.
In Step B, the insulating base material 16 is disposed opposite to the surface of the intermediate material A on the plating layer 15 side, and then both are hot-pressed to produce the integrated structure B shown in FIG.
At this time, the insulating layers 7 and 10 in the intermediate material A may be removed and then hot-pressed or may be hot-pressed without being removed.

また、絶縁基材１６としては、プレプレグ材であってもよいが、既に回路形成されている単層または多層回路基板の表面に例えば樹脂塗膜が形成されている回路基板それ自体であってもよい。
次の工程Ｃでは、まず、工程Ｂで製造された一体化構造物Ｂから、図１６で示したように、平滑基板５と導体薄膜６を順次除去する。その結果、表面には、第１めっき部９、第２めっき部１２の表面が面一状態で表出する。 The insulating base material 16 may be a prepreg material, or may be a circuit board itself in which, for example, a resin coating is formed on the surface of a single-layer or multilayer circuit board on which a circuit is already formed. Good.
In the next step C, first, the smooth substrate 5 and the conductive thin film 6 are sequentially removed from the integrated structure B manufactured in the step B as shown in FIG. As a result, the surface of the 1st plating part 9 and the 2nd plating part 12 appears on the surface in a flush state.

ついで、第２めっき材料のみを選択的にエッチングするエッチャントを用いたエッチング処理を行ない、第２めっき部１２を除去する。
第１めっき材料から成る第１めっき部９とめっき層１５は、この過程でエッチング除去されることはないので、結局、図１７で示したように、得られた基板の表面には、空間を有する凹部２が形成され、この凹部２の空間内には、第１めっき部９から成り、基板の表面１ａと面一状態をなして中空状態で配線されている導体回路部品が形成され、そして凹部２の底部に埋設された状態で表出している回路パターン１５が形成される。すなわち、図１で示した回路基板（Ｉ）が製造される。 Next, an etching process using an etchant that selectively etches only the second plating material is performed to remove the second plating portion 12.
Since the first plating portion 9 and the plating layer 15 made of the first plating material are not etched away in this process, as shown in FIG. 17, a space is finally formed on the surface of the obtained substrate. A concave portion 2 is formed, and in the space of the concave portion 2 is formed a conductor circuit component which is composed of the first plating portion 9 and is wired in a hollow state in a state of being flush with the surface 1a of the substrate, and A circuit pattern 15 exposed in a state of being embedded in the bottom of the recess 2 is formed. That is, the circuit board (I) shown in FIG. 1 is manufactured.

次に、図２で示した回路基板（II）の製造方法について説明する。
この場合の製造方法は、回路基板（Ｉ）の場合に比べて、工程Ａが異なっている。
以下に、各工程を順次説明する。
工程Ａ4では、まず、図１８で示したように、平滑基板５の片面に成膜した導体薄膜６の表面を被覆して絶縁層１７（絶縁層ｄ）を形成したのち、この絶縁層１７に露光・現像処理を行なうことにより、図３で示した空心コイル部品の上辺導体部分３Ｂ1を形成すべき箇所の絶縁層１７を除去して、そこに、導体薄膜６の表面６ａが表出している凹部パターン１８（凹部パターンｄ）を形成する。 Next, a method for manufacturing the circuit board (II) shown in FIG. 2 will be described.
The manufacturing method in this case is different in the process A compared to the case of the circuit board (I).
Below, each process is demonstrated one by one.
In step A 4 , first, as shown in FIG. 18, an insulating layer 17 (insulating layer d) is formed by covering the surface of the conductive thin film 6 formed on one surface of the smooth substrate 5, and then the insulating layer 17. the by performing exposure and development process, to remove the air-core coil component of the upper side conductor portions 3B 1 position of the insulating layer 17 to form the shown in FIG. 3, there, out surface 6a of the conductive thin film 6 is Table The recessed pattern 18 (recessed pattern d) is formed.

なお、この凹部パターン１８は、図１９で示したように、上辺導体部分３Ｂ1と同一形状の複数の凹溝が互いに等間隔で直線状に配列した平面パターンになっている。各凹溝の底面からは導体薄膜の表面６ａが表出し、またこの平面パターンの両側には、端子部４，４（図２）になるべき凹溝も形成されている。
ついで、導体薄膜６（または平滑基板５）をマイナス極にして電気めっきを行ない、図２０で示したように、凹部パターン１８の中に第１めっき材料を充填して、コイルの上辺導体部分３Ｂ1を形成し、中間材Ａ4を製造する。このとき、残置している絶縁層１７の表面１７ａと上辺導体部分３Ｂ1の表面は面一状態となるように電気めっきを行なう。 As shown in FIG. 19, the concave pattern 18 is a planar pattern in which a plurality of concave grooves having the same shape as the upper conductor portion 3B 1 are linearly arranged at equal intervals. The surface 6a of the conductive thin film is exposed from the bottom surface of each concave groove, and concave grooves to be the terminal portions 4 and 4 (FIG. 2) are also formed on both sides of the planar pattern.
Next, electroplating is performed with the conductor thin film 6 (or the smooth substrate 5) as the negative electrode, and as shown in FIG. 20, the first plating material is filled in the recess pattern 18, and the upper conductor portion 3B of the coil is filled. 1 is formed, to produce the intermediate material a 4. In this case, the surface 17a and the upper conductor portion 3B 1 of the surface of the insulating layer 17 that is leaving performs electroplating so as to flush with.

工程Ａ5では、図２１で示したように、最初に上記した中間材Ａ4の上辺導体部分３Ｂ1を含む全体の表面を被覆して所定厚みの絶縁層１９（絶縁層ｅ）を形成する。このときの絶縁層１９の厚みは、図３で示した空心コイル部品における両側導体部分３Ｂ3の高さと等値に設定される。
ついで、絶縁層１９に露光・現像処理を行ない、両側導体部分３Ｂ3を形成すべき箇所の絶縁層１９を除去し、そこに、図２２で示したように、それぞれの上辺導体部分３Ｂ1の端部表面が表出している凹孔パターン２０（凹孔パターンｅ）を形成する。 In step A 5, as shown in FIG. 21, an insulating layer 19 of the first to cover the entire surface including the upper conductive portion 3B 1 intermediate members A 4 that the predetermined thickness (insulating layer e) . The thickness of the insulating layer 19 at this time is set to the height and equality of both side conductor portions 3B 3 in an air-core coil component shown in FIG.
Then, subjected to exposure and development in the insulating layer 19, an insulating layer 19 of the portion to be formed on both sides conductor portion 3B 3 is removed, there, as shown in FIG. 22, the respective upper conductor portions 3B 1 A concave hole pattern 20 (concave hole pattern e) whose end surface is exposed is formed.

ついで、導体薄膜６（または平滑基板５）をマイナス極にして電気めっきを行い、凹孔パターン２０に第１めっき材料を充填して、図２３で示したように、コイルの両側導体部分３Ｂ3を形成する。このとき、残置している絶縁層１９の表面１９ａと両側導体部分３Ｂ3の下部端面は面一状態となるように電気めっきが行われる。
このようにして、第１めっき材料から成る上辺導体部分３Ｂ1の端部と、同一材料から成る両側導体部分３Ｂ3の上端とが一体化しためっき充填部を有する中間材Ａ5が得られる。 Next, electroplating is performed with the conductive thin film 6 (or the smooth substrate 5) as the negative electrode, and the first plating material is filled into the concave hole pattern 20, and as shown in FIG. 23, both side conductor portions 3B 3 of the coil. Form. At this time, the lower end face of the surface 19a and both side conductive portion 3B 3 of insulating layer 19 that is leaving the electroplating is performed so that the flush state.
In this way, an intermediate material A 5 having a plating filling portion in which the end portion of the upper conductor portion 3B 1 made of the first plating material and the upper ends of both side conductor portions 3B 3 made of the same material are integrated is obtained.

工程Ａ6では、まず、両側導体部分３Ｂ3の下部端面を含む全体の表面に所定の厚みの絶縁層２１（絶縁層ｆ）を形成し、ついでこの絶縁層２１と絶縁層１９と絶縁層１７に順次露光・現像処理を行い、形成すべき凹部２（図２）と同一形状をした凹部パターン２２（凹部パターンｆ）を形成する。
このときの絶縁層２１の厚みは、図３で示したコイル部品における下辺導体部分３Ｂ2の厚みと等値となるように設定する。また、絶縁層２１の露光・現像処理に際しては、両側導体部分３Ｂ3の下部端面を被覆する部分は除去しないで残置させる。 In step A 6 , first, an insulating layer 21 (insulating layer f) having a predetermined thickness is formed on the entire surface including the lower end faces of the both-side conductor portions 3 B 3 , and then the insulating layer 21, insulating layer 19, and insulating layer 17 are formed. Then, exposure / development processes are sequentially performed to form a recess pattern 22 (recess pattern f) having the same shape as the recess 2 (FIG. 2) to be formed.
The thickness of the insulating layer 21 at this time is set to be lower conductor portion 3B 2 of thickness and equality in the coil component shown in FIG. Further, when exposure and development of the insulating layer 21, the portion covering the lower end face of each side conductor portions 3B 3 causes leaving without removing.

その結果、図２４で示したように、底面には導体薄膜６の表面６ａが表出し、また上辺導体部分３Ｂ1と両側導体部分３Ｂ3の表面も表出し、しかし両側導体部分３Ｂ3の下部端面は絶縁層２１で被覆されている凹部パターン２２（凹部パターンｆ）が形成される。
ついで、導体薄膜６（または平滑基板５）をマイナス極にして電気めっきを行い、凹部パターン２２の中に第２めっき材料（例えばＣｕ）を充填することにより、図２５で示したように、第２めっき部２３を形成して中間材Ａ6を製造する。 As a result, as shown in FIG. 24, the surface 6a of the conductor thin film 6 is exposed on the bottom surface, and the surfaces of the upper conductor portion 3B 1 and the both side conductor portions 3B 3 are also exposed, but the lower portions of the both side conductor portions 3B 3 are exposed. A concave pattern 22 (concave pattern f) covered with the insulating layer 21 is formed on the end surface.
Next, electroplating is performed with the conductive thin film 6 (or the smooth substrate 5) as the negative electrode, and the second plating material (for example, Cu) is filled in the concave pattern 22 to obtain the first as shown in FIG. forming a second plating section 23 to produce the intermediate material a 6 in.

このとき、第２めっき部２３の表面２３ａと両側導体部分３Ｂ3の下部端面とは面一状態になるように電気めっきの条件が設定される。
工程Ａ7では、まず、第２めっき部２３の表面２３ａを被覆して、図２６で示したように、所定厚みの絶縁層２４（絶縁層ｇ）を形成する。具体的には、中間材Ａ6における絶縁層２１の凹没部に絶縁材を充填して絶縁層２４にする。このときの絶縁層２４の厚みは、形成すべき下辺導体部分３Ｂ2の厚みと等値になるように、絶縁材の充填後、例えば研磨処理を行なって調製すればよい。 At this time, the conditions of the electroplating to be flush with the surface 23a and the lower end face of each side conductor portions 3B 3 of the second plating section 23 is set.
In Step A 7, first, by coating the surface 23a of the second plating section 23, as shown in FIG. 26, an insulating layer 24 (insulating layer g) of predetermined thickness. Specifically, the insulating layer 24 is filled with an insulating material in the recessed portion of the insulating layer 21 in the intermediate material A 6 . The thickness of the insulating layer 24 at this time may be adjusted by, for example, performing a polishing process after filling with an insulating material so as to be equal to the thickness of the lower conductor portion 3B 2 to be formed.

ついで、絶縁層２４に露光・現像処理を行い、下辺導体部分３Ｂ2を形成すべき箇所の絶縁層２４を除去して、図２７で示したように、第２めっき部２３の表面２３ａと両側導体部分３Ｂ3の下部端面が表出している凹部パターン２５（凹部パターンｇ）を形成する。
ついで、導体薄膜６（または平滑基板５）をマイナス極にして電気めっきを行い、凹部パターン２５の中に第１めっき材料を充填して、図２８で示したように、コイルの下辺導体部分３Ｂ2を形成する。 Next, the insulating layer 24 is exposed and developed to remove the insulating layer 24 where the lower conductor portion 3B 2 is to be formed, and as shown in FIG. 27, the surface 23a and both sides of the second plating portion 23 are removed. A concave pattern 25 (concave pattern g) is formed in which the lower end face of the conductor portion 3B 3 is exposed.
Next, electroplating is performed with the conductor thin film 6 (or the smooth substrate 5) as the negative electrode, and the first plating material is filled in the recess pattern 25, and as shown in FIG. 28, the lower conductor portion 3B of the coil. Form two .

このとき、下辺導体部分３Ｂ2の表面と残置する絶縁層２４の表面は面一状態となるように電気めっきを行う。
ついで、絶縁層２４（２１）、絶縁層１９、絶縁層１７を全てエッチング除去して、図２９で示した中間材Ａ7を製造する。
この中間材Ａ7は、導体薄膜６の表面６ａに、第２めっき材料から成り、図２の凹部２と同一形状をした第２めっき部２３と、いずれも第１めっき材料からなり、互いの端面で一体的に接続している上辺導体部分３Ｂ1、両側導体部分３Ｂ3、下辺導体部分３Ｂ2で構成された第１めっき部が形成されている。 At this time, the surface of the insulating layer 24 leaving the lower conductor portion 3B 2 surfaces Electroplating is done so that the flush state.
Then, an insulating layer 24 (21), an insulating layer 19, all of the insulating layer 17 is removed by etching, to produce the intermediate material A 7 shown in FIG. 29.
The intermediate member A 7 is a surface 6a of the conductive thin film 6 made of the second plating material, the recess 2 and the second plating unit 23 in which the same shape of FIG. 2, both made of the first plating material, the mutual A first plating portion is formed which is composed of an upper side conductor portion 3B 1 , two side conductor portions 3B 3 , and a lower side conductor portion 3B 2 that are integrally connected at the end face.

工程Ｂにおいては、中間材Ａ7の第１めっき部と第２めっき部側に絶縁基材２６を対向配置し、両者を熱圧プレスして一体化し、図３０で示したような一体化構造物Ｂが製造される。
絶縁基材２６としては、前記した回路基板（I）の場合と同様に、プリプレグ材であってもよいが、既に回路形成されている単層または多層回路基材の表面に例えば樹脂塗膜が形成されている回路基板それ自体であってもよい。 In step B, the first plating section and the insulating substrate 26 to the second plating unit side of the intermediate member A 7 placed opposite, both integrated and hot pressing, integrated as shown in FIG. 30 structure Product B is manufactured.
The insulating base material 26 may be a prepreg material as in the case of the circuit board (I) described above. For example, a resin coating film is formed on the surface of a single-layer or multi-layer circuit base material on which a circuit is already formed. The formed circuit board itself may be used.

工程Ｃでは、一体化構造物Ｂから平滑基板５と導体薄膜６を順次除去して、上辺導体部分３Ｂ1（第１めっき部）の表面と第２めっき部２３の表面を表出させる。
ついで、第２めっき材料のみを選択的にエッチングするエッチャントでエッチング処理を行って第２めっき部を除去する。
その結果、図３１で示したように、得られた基板には、空間を有する凹部２と、その凹部内に上辺導体部分３Ｂ1と両側導体部分３Ｂ3と下辺導体部分３Ｂ2とから成る空心コイル部分3Ｂが形成されている。 In step C, the smooth substrate 5 and the conductive thin film 6 are sequentially removed from the integrated structure B to expose the surface of the upper side conductor portion 3B 1 (first plating portion) and the surface of the second plating portion 23.
Next, an etching process is performed with an etchant that selectively etches only the second plating material to remove the second plating portion.
As a result, as shown in FIG. 31, the obtained substrate has a concave portion 2 having a space, and an air core comprising an upper side conductor portion 3B 1 , both side conductor portions 3B 3 and a lower side conductor portion 3B 2 in the concave portion. A coil portion 3B is formed.

このようにして上辺導体部分３Ｂ1の表面は絶縁基材２６の表面と面一状態で配線され、下辺導体部分３Ｂ2は絶縁基材２６に埋設されている空心コイル部分を有する回路基板（II）が製造される。 In this way, the surface of the upper side conductor portion 3B 1 is wired so as to be flush with the surface of the insulating base material 26, and the lower side conductor portion 3B 2 is a circuit board (II) having an air-core coil portion embedded in the insulating base material 26. ) Is manufactured.

本発明の回路基板は、基板表面に形成した凹部の中に中空状態で受動部品が実装されている。とくに受動部品がコイル部品である場合、そのコイル部品は空心コイルになっているので、良好なコイル特性を発揮することができる。
また、受動部品はいずれも電気めっき法で製造されているので、導体の寸法や断面積、導体間のギャップなどを高精度で作製可能である。 In the circuit board of the present invention, a passive component is mounted in a hollow state in a recess formed on the substrate surface. In particular, when the passive component is a coil component, the coil component is an air-core coil, so that good coil characteristics can be exhibited.
In addition, since all passive components are manufactured by electroplating, it is possible to manufacture conductor dimensions and cross-sectional areas, gaps between conductors, and the like with high accuracy.

本発明の回路基板（I）の１例を示す斜視図である。It is a perspective view which shows one example of the circuit board (I) of this invention. 本発明の回路基板（II）の１例を示す斜視図である。It is a perspective view which shows one example of the circuit board (II) of this invention. 回路基板（II）におけるコイル部品３Ｂを示す斜視図である。It is a perspective view which shows the coil components 3B in a circuit board (II). 導体薄膜で平滑基板の片面が被覆された状態を示す断面図である。It is sectional drawing which shows the state by which the single side | surface of the smooth substrate was coat | covered with the conductor thin film. 絶縁層ａを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the insulating layer a was formed. 絶縁層ａに凹部パターンａを形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the recessed part pattern a in the insulating layer a. 図６の凹部パターンａの平面視形状を示す平面図である。It is a top view which shows the planar view shape of the recessed part pattern a of FIG. 中間材Ａ1を示す断面図である。Is a sectional view showing an intermediate material A 1. 中間材Ａ1に絶縁層ｂを形成した状態を示す断面図である。The intermediate material A 1 is a sectional view showing a state of forming an insulating layer b. 凹部パターンｂを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the recessed part pattern b was formed. 中間材Ａ2を示す断面図である。Is a sectional view showing an intermediate material A 2. 中間材Ａ2に、絶縁層ｃを形成した状態を示す断面図である。The intermediate material A 2, is a cross-sectional view showing a state of forming an insulating layer c. 第２めっき部に第１めっき材料のめっき層を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the plating layer of the 1st plating material in the 2nd plating part. 中間材Ａを示す断面図である。3 is a cross-sectional view showing an intermediate material A. FIG. 一体化構造物Ｂを示す断面図である。It is sectional drawing which shows the integrated structure B. FIG. 一体化構造物Ｂから平滑基板と導体薄膜を除去した状態を示す断面図である。It is sectional drawing which shows the state which removed the smooth substrate and the conductor thin film from the integrated structure B. 回路基板（I）を示す断面図である。It is sectional drawing which shows a circuit board (I). 導体薄膜の表面にコイルの上辺導体部分の凹部パターンｄを形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the recessed part pattern d of the upper-side conductor part of a coil on the surface of a conductor thin film. 形成した凹部パターンｄの平面視形状の１例を示す平面図である。It is a top view which shows an example of the planar view shape of the formed recessed part pattern d. 中間材Ａ4を示す断面図である。It is a cross-sectional view showing the intermediate member A 4. 中間材Ａ4に絶縁層ｅを形成した状態を示す断面図である。The intermediate member A 4 is a sectional view showing a state of forming an insulating layer e. 凹孔パターンｅを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the concave hole pattern e was formed. 中間材Ａ5を示す断面図である。Is a sectional view showing an intermediate member A 5. 凹部パターンｆを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the recessed part pattern f was formed. 中間材Ａ6を示す断面図である。Is a sectional view showing an intermediate member A 6. 絶縁層ｇを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the insulating layer g was formed. 凹部パターンｇを形成した状態を示す断面図である。It is sectional drawing which shows the state in which the recessed part pattern g was formed. 下辺導体部分を形成した状態をを示す断面図である。It is sectional drawing which shows the state in which the lower-side conductor part was formed. 中間材Ａ7を示す断面図である。Is a sectional view showing an intermediate member A 7. 一体化構造物Ｂを示す断面図である。It is sectional drawing which shows the integrated structure B. FIG. 回路基板（II）を示す断面図である。It is sectional drawing which shows a circuit board (II).

符号の説明Explanation of symbols

１ 基板
１ａ 基板１の表面
２ 有底凹部
３Ａ 導体回路部品
３ａ 導体回路部品３Ａの上面
３Ｂ 空心コイル部品
３Ｂ1 上辺導体部分
３Ｂ3 両側導体部分
３Ｂ2 下辺導体部分
４ 端子部
５ 平滑基板
６ 導体薄膜
６ａ 導体薄膜６の表面
７ 絶縁層ａ
８ 凹部パターンａ
９ 第１めっき部
９ａ 第１めっき部９の表面
１０ 絶縁層ｂ
１１ 凹部パターンｂ
１２ 第２めっき部
１２ａ 第２めっき部１２の表面
１３ 絶縁層ｃ
１４ 凹部パターンｃ
１５ 第１めっき材料のめっき層（回路パターン）
１６ 絶縁基材
１７ 絶縁層ｄ
１８ 凹部パターンｄ
１９ 絶縁層ｅ
２０ 凹部パターンｅ
２１ 絶縁層ｆ
２２ 凹部パターンｆ
２３ 第２めっき部
２３ａ 第２めっき部２３の表面
２４ 絶縁層ｇ
２５ 凹部パターンｇ
２６ 絶縁基材 DESCRIPTION OF SYMBOLS 1 Board | substrate 1a The surface of the board | substrate 2 Bottomed recessed part 3A Conductor circuit component 3a Upper surface of the conductor circuit component 3A 3B Air core coil component 3B 1 Upper side conductor part 3B 3 Both-side conductor part 3B 2 Lower side conductor part 4 Terminal part 5 Smooth substrate 6 Conductor thin film 6a Surface of the conductive thin film 6 7 Insulating layer a
8 Concave pattern a
9 First plating portion 9a Surface of first plating portion 9 10 Insulating layer b
11 Recess pattern b
12 Second plating portion 12a Surface of second plating portion 12 13 Insulating layer c
14 Recess pattern c
15 Plating layer (circuit pattern) of the first plating material
16 Insulating base material 17 Insulating layer d
18 Concave pattern d
19 Insulating layer e
20 Concave pattern e
21 Insulating layer f
22 Recess pattern f
23 2nd plating part 23a Surface of 2nd plating part 23 24 Insulating layer g
25 Concave pattern g
26 Insulating substrate

Claims (7)

基板表面に形成された有底凹部と、前記有底凹部の空間内に一部または全部が中空状態で形成されている受動部品とを備え、
前記受動部品は、めっき材料を用いた電気めっき法で形成され、断面が四角形の線状導体から成り、その上面が前記基板表面と面一状態になっていることを特徴とする回路基板。 A bottomed recess formed on the substrate surface, and a passive component partly or entirely formed in a hollow state in the space of the bottomed recess ,
The circuit board , wherein the passive component is formed by an electroplating method using a plating material, is composed of a linear conductor having a square cross section, and an upper surface thereof is flush with the substrate surface . 前記受動部品が、前記有底凹部の空間内に完全中空状態で前記有底凹部を横断する導体回路部品である請求項１の回路基板。   The circuit board according to claim 1, wherein the passive component is a conductor circuit component that traverses the bottomed recess in a completely hollow state in the space of the bottomed recess. 前記受動部品が、断面四角形状に巻回された構造の空心コイル部品であって、前記空心コイル部品の下辺導体部分は前記有底凹部の底部に埋設され、上辺導体部分と両側導体部分は前記有底凹部の空間内に裸出している請求項１の回路基板。   The passive component is an air core coil component having a structure wound in a quadrangular cross section, wherein the lower side conductor portion of the air core coil component is embedded in the bottom of the bottomed recess, and the upper side conductor portion and both side conductor portions are The circuit board according to claim 1, wherein the circuit board is bare in the space of the bottomed recess. 平滑基板の片面に成膜された導体薄膜の表面に、第一めっき材料から成り、形成すべき受動部品と同一形状を有する第一めっき部と、前記第一めっき部を埋設し、かつ前記第一めっき材料とは異質の第２めっき材料から成り、形成すべき有底凹部と同一形状を有する第２めっき部とを有する中間材Ａを製造する工程Ａ；
前記中間材Ａの前記第２めっき部側の表面に絶縁基材を熱圧プレスして一体化構造物Ｂを製造する工程Ｂ；および、
前記一体化構造物Ｂから前記平滑基板と前記導体薄膜を順次除去して前記第２めっき部の一部表面と前記受動部品の一部表面を表出させたのち、前記第２めっき部のみを選択的にエッチング除去して前記有底凹部を形成する工程Ｃ；
を備えていることを特徴とする回路基板の製造方法。 A first plating part made of a first plating material and having the same shape as the passive component to be formed, and the first plating part are embedded on the surface of the conductive thin film formed on one side of the smooth substrate, and the first Step A for producing an intermediate material A comprising a second plated material that is different from the one plated material and has a bottomed concave portion to be formed and a second plated portion having the same shape;
A step B of manufacturing an integrated structure B by hot-pressing an insulating base material on the surface of the intermediate material A on the second plating part side; and
After removing the smooth substrate and the conductive thin film sequentially from the integrated structure B to expose a partial surface of the second plated portion and a partial surface of the passive component, only the second plated portion is exposed. A step C of selectively removing by etching to form the bottomed recess;
A method for manufacturing a circuit board, comprising: 前記第１めっき材料がＮｉであり、前記第２めっき材料がＣｕである請求項４の回路基板の製造方法。   The method for manufacturing a circuit board according to claim 4, wherein the first plating material is Ni and the second plating material is Cu. 前記工程Ａが、請求項２における前記導体回路部品と同一形状の第１めっき部および前記有底凹部と同一形状の第２めっき部を有する前記中間材Ａを製造する工程であって、
その工程Ａが、
平滑基板の片面に成膜された導体薄膜の表面を被覆して絶縁層ａを形成し、前記絶縁層ａに露光・現像処理を行なって、少なくとも前記導体回路部品を形成すべき箇所の前記絶縁層ａを除去することにより、前記導体回路部品の平面パターンと同じ平面パターンを有し、かつ前記導体薄膜の表面が表出している凹部パターンａを形成し、ついで、電気めっき法で、前記凹部パターンａの中に、残置する前記絶縁層ａの表面と面一状態になるまで第１めっき材料を充填して第１めっき部を形成する工程Ａ1；
前記第１めっき部を含む表面全部を被覆して絶縁層ｂを形成し、前記絶縁層ｂに露光・現像処理を行なって、有底凹部を形成すべき箇所の前記絶縁層ｂを除去することにより、形成すべき有底凹部と同一形状を有し、かつ前記第１めっき部の表面と前記導体薄膜の表面が表出している凹部パターンｂを形成し、ついで、電気めっき法で、前記凹部パターンｂの中に、残置する前記絶縁層ｂの表面と面一状態になるまで、前記第１めっき材料とは異質な第２めっき材料を充填して第２めっき部を形成する工程Ａ2；および、
前記第２めっき部を含む表面全部を被覆して絶縁層ｃを形成し、前記絶縁層ｃに露光・現像処理を行なって、前記第２めっき部９の一部表面と前記第１めっき部の両端部分の表面が表出する凹部パターンｃを形成し、ついで、電気めっき法で、前記凹部パターンｃの中に、残置する前記絶縁層ｃの表面と面一状態になるまで前記第１めっき材料を充填したのち、前期絶縁層ｃを除去する工程Ａ3；
を備えている請求項４の回路基板の製造方法。 The step A is a step of manufacturing the intermediate material A having a first plating portion having the same shape as the conductor circuit component in claim 2 and a second plating portion having the same shape as the bottomed recess,
The process A is
An insulating layer a is formed by covering the surface of the conductive thin film formed on one surface of the smooth substrate, and the insulating layer a is exposed and developed, so that at least the insulating portion where the conductor circuit component is to be formed is formed. By removing the layer a, a concave pattern a having the same planar pattern as that of the conductor circuit component and exposed on the surface of the conductive thin film is formed, and then the concave portion is formed by electroplating. Step A 1 of filling the first plating material in the pattern a until the surface of the insulating layer a to be left is flush with the surface of the pattern a to form the first plating portion;
Covering the entire surface including the first plating portion to form an insulating layer b, exposing and developing the insulating layer b, and removing the insulating layer b where a bottomed recess is to be formed To form a recess pattern b having the same shape as the bottomed recess to be formed and the surface of the first plating portion and the surface of the conductor thin film exposed, and then by electroplating, Step A 2 in which a second plating material different from the first plating material is filled in the pattern b until the surface of the insulating layer b to be left is flush with the pattern b to form a second plating portion; and,
An insulating layer c is formed by covering the entire surface including the second plating part, and an exposure / development treatment is performed on the insulating layer c, so that a part of the surface of the second plating part 9 and the first plating part are formed. A concave pattern c is formed so that the surfaces of both end portions are exposed, and then the first plating material is in a state flush with the surface of the insulating layer c to be left in the concave pattern c by electroplating. Step A 3 of removing the previous insulating layer c after filling
A method for manufacturing a circuit board according to claim 4. 前記工程Ａが、請求項３における前記空心コイル部品と同一形状の第１めっき部および前記有底凹部と同一形状の第２めっき部を有する前記中間材Ａを製造する工程であって、
その工程Ａが、
平滑基板の片面に成膜された導体薄膜の表面を被覆して絶縁層ｄを形成し、前記絶縁層ｄに露光・現像処理を行なって、前記空心コイル部品の上辺導体部分を形成すべき箇所の前記絶縁層ｄを除去することにより、そこに前記上辺導体部分と同一の平面パターンを有し、かつ前記導体薄膜の表面が表出している凹部パターンｄを形成し、ついで、電気めっき法で、前記凹部パターンｄの中に、残置する前記絶縁層ｄの表面と面一状態になるまで第１めっき材料を充填して前記空心コイル部品の上辺導体部分を形成する工程Ａ4；
前記上辺導体部を含む表面全部を被覆して絶縁層ｅを形成し、前記絶縁層ｅに露光・現像処理を行なって、前記空心コイル部品の両側導体部分を形成すべき箇所の前記絶縁層ｅを除去することにより、そこに前記上辺導体部分の端部表面が表出している凹孔パターンｅを形成し、ついで、電気めっき法で、前記凹孔パターンｅの中に、残置する前記絶縁層ｅの表面と面一状態になるまで前記第１めっき材料を充填して前記空心コイル部品の両側導体部分を形成する工程Ａ5；
前記両側導体部分の表面を含む表面全部を被覆して絶縁層ｆを形成し、前記絶縁層ｆに露光・現像処理を行なって、有底凹部を形成すべき箇所の前記絶縁層ｆを除去することにより、形成すべき前記有底凹部と同一形状を有し、かつ前記上辺導体部分と前記両側導体部分と前記導体薄膜の表面が表出している凹部パターンｆを形成し、ついで、電気めっき法で、前期凹部パターンｆの中に、前記両側導体部分の下部端面と面一状態になるまで第２めっき材料を充填して第２めっき部を形成する工程Ａ6；および
前記第２めっき部の表面を含む表面全部を被覆して絶縁層ｇを形成し、前記絶縁層ｇに露光・現像処理を行なって、前記空心コイル部品の下辺導体部分を形成すべき箇所の前記絶縁層ｇを除去することにより、前記両側導体部分の下部端面と前記第２めっき部の表面が表出している凹部パターンｇを形成し、ついで、電気めっき法で、前記凹部パターンｇの中に、残置する前記絶縁層ｇの表面と面一状態になるまで前記第１めっき材料を充填して前記空心コイル部品の下辺導体部分を形成したのち、前記絶縁層ｄ，ｅ，ｆ，ｇの全てを除去する工程Ａ7；
を備えている請求項４の回路基板の製造方法。 The step A is a step of manufacturing the intermediate material A having a first plating part having the same shape as the air-core coil component in claim 3 and a second plating part having the same shape as the bottomed recess,
The process A is
A portion where the surface of the conductive thin film formed on one surface of the smooth substrate is covered to form an insulating layer d, and the insulating layer d is exposed and developed to form an upper conductor portion of the air-core coil component. By removing the insulating layer d, a recess pattern d having the same plane pattern as the upper side conductor portion and exposing the surface of the conductive thin film is formed, and then electroplating is used. Step A 4 of filling the first plating material in the concave pattern d until the surface of the insulating layer d to be left is flush with the surface of the insulating layer d to form the upper conductor portion of the air-core coil component;
An insulating layer e is formed by covering the entire surface including the upper side conductor portion, and the insulating layer e is subjected to exposure / development processing, and the insulating layer e at a position where both side conductor portions of the air-core coil component are to be formed. Is removed to form a concave hole pattern e in which the end surface of the upper side conductor portion is exposed, and then the insulating layer is left in the concave hole pattern e by electroplating. filling the first plating material until it is flush with the surface of e to form both side conductor portions of the air-core coil component A 5 ;
An insulating layer f is formed so as to cover the entire surface including the surfaces of the both-side conductor portions, and the insulating layer f is exposed and developed to remove the insulating layer f where a bottomed recess is to be formed. Thereby forming a concave pattern f having the same shape as the bottomed concave portion to be formed, and exposing the surface of the upper side conductor portion, the both side conductor portions, and the conductive thin film, and then electroplating And the step A 6 of filling the second plating material into the recess pattern f in the previous period until it is flush with the lower end faces of the both side conductor portions to form the second plating portion; and An insulating layer g is formed so as to cover the entire surface including the surface, and the insulating layer g is exposed and developed to remove the insulating layer g where the lower conductor portion of the air-core coil component is to be formed. Under the conductor parts on both sides A recess pattern g in which the end face of the part and the surface of the second plating part are exposed is formed, and then the surface of the insulating layer g to be left is flush with the surface of the recess pattern g by electroplating. Filling the first plating material until forming the lower conductor portion of the air-core coil component, and then removing all of the insulating layers d, e, f, g; A 7 ;
A method for manufacturing a circuit board according to claim 4.
JP2005186357A 2005-06-27 2005-06-27 Circuit board and manufacturing method thereof Expired - Fee Related JP4309379B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804878B2 (en) 2016-02-18 2020-10-13 Samsung Electro-Mechanics Co., Ltd. Acoustic resonator module and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804878B2 (en) 2016-02-18 2020-10-13 Samsung Electro-Mechanics Co., Ltd. Acoustic resonator module and method of manufacturing the same

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