JP4306161B2 - Electronic clock - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic timepiece including a power generation device.
[0002]
[Prior art]
As an electronic timepiece, for example, an electronic timepiece with a solar battery is widely used. This electronic timepiece charges a secondary battery built in advance by a power generation action by the solar battery and uses an output voltage of the secondary battery as a power source. Driving the internal circuit of the watch.
[0003]
In such an electronic timepiece, in order to secure a voltage necessary for charging the secondary battery, solar cells are usually used in a series connection of several stages. When the secondary battery becomes insufficiently charged and the output voltage decreases, the internal circuit stops. As a result, the hands of the analog timepiece are stopped, and the digital display of the digital timepiece is turned off. When the secondary battery is charged again, the internal circuit operates and the time measurement process returns.
[0004]
There is also known an electronic timepiece in which a voltage detection circuit for a secondary battery is installed in an internal circuit and displays a power supply voltage level meter. This electronic timepiece detects the current output voltage of the secondary battery with respect to the state of the secondary battery in which all the operations of the internal circuit can be realized, and displays a power supply voltage level meter according to the detection result.
[0005]
[Problems to be solved by the invention]
However, when the voltage of the secondary battery drops and the internal circuit stops, the analog timepiece stops while displaying the time at the time of stoppage, which may cause the user to recognize the wrong time. In addition, when all the pointers are concentrated and stopped at the upper part of one cell among the plurality of solar cells on the dial, the light receiving area of the cell is reduced and the charging efficiency is deteriorated.
[0006]
When the internal circuit starts operating again due to charging, the hand position detection circuit is installed and the hand position before stopping is stored in RAM (Random Access Memory) in advance in order to accurately restore the analog timepiece. For example, a complicated circuit configuration is required.
[0007]
Further, when the voltage at which the internal circuit stops is set at a low temperature when the discharge characteristics of the secondary battery deteriorate, the internal circuit stops when the secondary battery drops to the set voltage. However, there is a possibility that the capacity for driving a circuit with a small load is actually remaining in the secondary battery at room temperature. In this case, there arises a problem that the capacity of the secondary battery cannot be used sufficiently effectively.
[0008]
An object of the present invention is to realize a state transition with good power supply efficiency from a drop in power supply voltage to a stop of an internal circuit and a return to operation by charging, thereby enabling the capacity of the secondary battery and improving the charging efficiency. .
[0009]
[Means for Solving the Problems]
  In order to solve the above problems, a pointer for displaying time, a power supply circuit having a power generation unit and a power storage unit, a pointer driving unit that operates with the output voltage of the power supply circuit and drives the pointer, Based on the obtained time information, the current time counting means which operates with the output voltage and counts the current time, operates with the output voltage of the power supply circuit, receives the radio wave including the time code and obtains the time information. A radio wave correcting unit that corrects the current time of the current time counting unit, a voltage detecting unit that detects an output voltage of the power supply circuit, and a voltage detected by the voltage detecting unit is equal to or lower than a first voltage. When the pointer is moved to a predetermined position by the pointer driving means and the operation of the radio wave correcting means is stopped, and it is continuously detected for a certain time that the voltage detecting means has become the second voltage or higher. Wherein to initiate operation of the radio-corrected means, and control means for moving the current time position in the pointer drive means the pointer based on the time information obtained by the radio correction means,The power generation means includes a plurality of solar cells arranged on a dial, and a predetermined interval is provided in all or a part between the plurality of battery cells, and the predetermined position is an upper portion of the predetermined interval. is thereIt is characterized by that.
[0010]
  According to the first aspect of the present invention, when the voltage detected by the voltage detecting means becomes equal to or lower than the first voltage, the pointer is moved to a predetermined position by the pointer driving means and the operation of the radio wave correcting means is stopped. The operation of the radio wave correcting unit is started when the voltage detecting unit continuously detects that the voltage has become equal to or higher than the second voltage for a certain period of time, and the pointer is set based on the time information obtained by the radio wave correcting unit. Since it is moved to the position, it is possible to suppress a decrease in the power of the power storage means, and it is possible to control the pointer driving means without requiring a complicated circuit such as a needle position detection circuit. Also,A predetermined interval is provided in all or a part between the plurality of battery cells, and the predetermined position is an upper portion of the predetermined interval, so that a power generation means with good charging efficiency can be realized.
[0011]
  The invention according to claim 2 is the electronic timepiece according to claim 1,The control means obtains the movement amount of the pointer based on the predetermined position and the current time of the current time counting means, and moves the pointer by the movement amount obtained by the pointer driving means.It is characterized by that.
[0013]
  The invention according to claim 3 is the electronic timepiece according to claim 1 or 2,The predetermined position is a position of 12:00:00It is characterized by that.
[0017]
  Claim4The invention described is from claim 13The electronic timepiece according to any one of the above, wherein the plurality of solar cells are electronic timepieces arranged in a circumferential direction with a predetermined interval between all or a part of the solar cells. Yes.
[0018]
  This claim4According to the described invention, from claim 13In the electronic timepiece according to any one of the above, in the plurality of solar cells, for example, as shown in FIG. 13B, a predetermined interval is provided between all or a part of the solar cells, and the solar cells are arranged in the circumferential direction. By setting the predetermined position of the pointer at a predetermined interval, it is possible to realize a power generation means with good charging efficiency.
[0019]
  Claim5The invention described is from claim 14In the electronic timepiece according to any one of the above, the heavy load control means for controlling the driving of the heavy load, and the output voltage of the power supply circuit when the heavy load is applied are monitored. The electronic timepiece is further provided with a heavy load voltage monitoring means for prohibiting the heavy load control (for example, the heavy load monitoring voltage detection circuit 15 of FIG. 1).
[0020]
  This claim5According to the described invention, from claim 14In any of the electronic timepieces described above, when the output voltage of the power supply circuit decreases, the heavy load voltage monitoring means stops the heavy load control, whereby the charge capacity of the power storage means can be used effectively.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of an electronic timepiece to which the present invention is applied will be described in detail with reference to FIGS.
[0022]
[overall structure]
FIG. 1 is a block diagram showing a circuit configuration of an electronic timepiece according to the present invention. First, the configuration will be described.
[0023]
The clock circuit unit 10 includes a CPU (Central Processing Unit) 101, an oscillation circuit 102, a clock circuit 103, a display unit 104, a buzzer unit 105, a switch unit 106, a ROM (Read Only Memory) 107, a RAM 108, a fast-forward pulse supply circuit 109, The driving circuit 110 is configured.
[0024]
The CPU 101 executes various programs stored in advance in the ROM 107 and controls the operation of connected circuits. The CPU 101 includes a clock circuit 103, a display unit 104, a buzzer unit 105, a switch unit 106, a ROM 107, a RAM 108, a voltage detection circuit 14, a heavy load monitoring voltage detection circuit 15, a standard radio wave reception circuit 17, a tilt switch 21, and an EL driver 22. Is connected.
[0025]
The oscillation circuit 102 is a circuit that always outputs a signal having a constant frequency. The clock circuit 103 receives the signal of the oscillation circuit 102, counts the signal, and outputs a signal when the count value becomes a value corresponding to 1 minute. When C1 reaches a value corresponding to 20 seconds, a signal C2 is output to the CPU 101.
[0026]
The display unit 104 includes a liquid crystal screen and displays data sent from the CPU 101, such as current time data, date data, and a power supply voltage level meter.
[0027]
The buzzer unit 105 generates an alarm sound according to a signal sent from the CPU 101 by a timer function set by the user.
[0028]
The switch unit 106 outputs a corresponding switch input signal to the CPU 101 when any of various switches is operated by the user.
[0029]
The ROM 107 stores various programs for controlling the entire circuit in advance, and stores data for realizing the functions of the electronic timepiece.
[0030]
The RAM 108 is used as a work area for the CPU 101 such as temporarily storing programs and data when the CPU 101 executes various programs stored in the ROM 107.
[0031]
The fast-forward pulse supply circuit 109 is a circuit that inputs a signal sent from the CPU 101 and transfers it to the drive circuit 110 when fast-forwarding the hands of the analog timepiece.
[0032]
The drive circuit 110 is a circuit for inputting a signal sent from the CPU 101 or the fast-forward pulse supply circuit 109 and controlling the step motor 18 that drives the hands of the analog timepiece.
[0033]
The solar cell 11 is an energy exchanger that absorbs solar light energy and converts it into electricity, and the secondary battery 12 charges the electricity generated by the solar cell 11 to realize a power circuit for the entire circuit.
[0034]
A voltage detection (Battery Level Detector: hereinafter referred to as “BLD”) circuit 14 receives an AS-1 signal corresponding to a set voltage from the CPU 101 and detects the voltage of the secondary battery 12. The detected voltage is compared with the set voltage, and the result is output to the CPU 101 as a BLD-1 signal.
[0035]
In addition to the voltage detection function of the BLD circuit 14, the heavy load monitoring voltage detection circuit (hereinafter referred to as "strong load monitoring BLD circuit") 15 is used when the voltage of the secondary battery drops below the set voltage when the heavy load circuit is driven. A signal for stopping the driving of the heavy load circuit is output to the CPU 101 and the heavy load circuit.
[0036]
The standard radio wave receiving circuit 16 is a circuit that converts a radio wave received by the antenna 17 into an electric signal and outputs a signal including data necessary for a clock function such as a current time code, an integrated date code, and a day code to the CPU 101. .
[0037]
The step motor 18 is a circuit that drives the hands of the analog timepiece in accordance with a signal sent from the drive circuit 110, and drives the hands 20 through the wheel train mechanism 19.
[0038]
The tilt switch 21 outputs a signal to the CPU 101 when the electronic timepiece is tilted at a predetermined angle or more. In response to the signal sent from the tilt switch 21, the CPU 101 sends a signal to an electroluminescence (hereinafter referred to as “EL”) driver 22, and the EL driver 22 drives the EL element 23. As a result, the EL element 23 emits light.
[0039]
FIG. 2 is a diagram showing the data configuration of the ROM 107. The ROM 107 mainly stores a system program 21, a voltage detection processing program 22, a pointer current time return processing program 23, a pointer 12 o'clock position movement processing program 24, and a radio wave reception and time correction processing program 25.
[0040]
The system program 21 is a program that controls basic operations of the electronic timepiece. The voltage detection processing program 22 is a program in which the BLD circuit 14 detects the output voltage of the secondary battery 12 and performs control corresponding to the detection result. The pointer current time return processing program 23 is a program that is executed when the pointer 20 is moved from the position where the pointer 20 is stopped to the position of the current time. The pointer 12:00 position movement processing program 24 is a program that is executed when the pointer 20 is moved to the position of 12:00:00 when the output voltage of the secondary battery 12 falls below a certain set voltage. The radio wave reception and time correction processing program 25 is a program that is executed to extract the current time, day of the week, and integrated date from the signal sent from the standard radio wave reception circuit 16 and correct the internal timekeeping time.
[0041]
FIG. 3 is a diagram illustrating a data configuration of the RAM 108. The RAM 108 mainly includes a voltage level storage area 31, a heavy load drive flag storage area 32, a time counter storage area 33, an alarm time storage area 34, a moving pulse number storage area 35, a correction pulse number storage area 36, and a current time data storage area. 37, a day data storage area 38 and a date data storage area 39.
[0042]
The voltage level storage area 31 is an area in which a voltage level corresponding to the detected voltage is stored when the voltage detection processing program 22 is executed. The heavy load drive flag storage area 32 is an area for storing a normal operation state or an operation stop state of a circuit having a heavy load. The time counter storage area 33 is an area used to measure time when the CPU 101 executes the voltage detection processing program 22. The alarm time storage area 34 is an area for storing the alarm time set by the user. The movement pulse number storage area 35 is an area for storing the calculated movement pulse number when the CPU 101 executes the pointer current time return processing program 23 and the pointer 12:00 position movement processing program 24. The correction pulse number storage area 36 is an area for storing the calculated correction pulse number when the CPU 101 executes the pointer current time return processing program 23. The current time data storage area 37, day of the week data storage area 38, and date data storage area 39 are time data from data sent from the standard radio wave receiving circuit 16 when the CPU 101 executes the radio wave reception and time correction processing program 25. This is an area for extracting day of the week data and date data and storing each data.
[0043]
FIG. 4 is a diagram showing an example of the appearance of the electronic timepiece. The electronic timepiece mainly includes a pointer 20, a switch unit 105, and a display unit 104.
[0044]
The pointer 20 includes an hour hand and a minute hand, and displays the current time as an analog type clock. For example, in the case of an electronic timepiece with a 20-second hand movement, the minute hand moves one step every 20 seconds. The switch unit 105 is operated when executing various modes such as time adjustment and alarm setting.
[0045]
FIG. 5 is an enlarged view of the display unit 104. The display unit 104 includes a liquid crystal screen and the like, and includes a current time or date display unit 301, a radio wave reception mark 302, a day of week display unit 303, and a power supply voltage level meter 304.
[0046]
The current time or date display unit 301 displays either the current time or the date by operating the switch unit 105. The radio wave reception mark 302 is lit while the analog timepiece and the digital timepiece indicate an accurate time. That is, the light is turned off when the hand movement is stopped due to the voltage drop of the secondary battery 12 or while the time is corrected by receiving the radio wave.
[0047]
The day of the week display unit 303 mainly displays the day of the week, but also displays characters and marks corresponding to various modes. The power supply voltage level meter 304 lights a, b, and c according to the detection voltage of the secondary battery 12 by the BLD circuit 14, and displays the remaining battery level.
[0048]
[Operation]
Next, the operation of the electronic timepiece to which the present invention is applied will be described. FIG. 6 is a diagram showing the charge / discharge characteristics of the secondary battery 12 in the electronic timepiece, the setting range of the voltage level, and the display method of the power supply voltage level meter 304 corresponding to each level.
[0049]
Assuming that the output voltage of the secondary battery 12 detected by the BLD circuit 14 is V, when the voltage V is AS2 or higher (V ≧ AS2), the level is 1, and when AS3 is lower than AS2 (AS2> V ≧ AS3) Level 2 is lower than AS4 and lower than AS3 (AS3> V ≧ AS4). When the voltage drops due to discharging (the voltage V decreases from AS3 to AS4), level 3D is increased. The CPU 101 determines the level 3U when it is increasing from AS4 to AS3, and the level 4 when it is less than AS4 (V <AS4), and stores it in the voltage level storage area 31 of the RAM 108.
[0050]
In FIG. 6, when the voltage V becomes less than AS4 due to the voltage drop, the CPU 101 turns off the heavy load drive flag, moves the pointer to a predetermined position (for example, 12:00), and stops the heavy load circuit. That is, the hand movement is also stopped.
[0051]
After that, when the voltage V rises due to charging and becomes AS3 or more, the CPU 101 turns on the heavy load drive flag, identifies the current time by receiving radio waves, moves the hands to the current time position, etc. Return the operation. The above is the basic operation when the voltage of the secondary battery 12 is lowered.
[0052]
However, when the voltage V rises from AS4 due to charging, if the voltage V fluctuates in the vicinity of AS3, there arises a problem that the operation of turning on or off the heavy load drive flag is repeated. In order to solve this, the time counter storage area 33 is provided in the RAM 108, and when the voltage V increases from AS4 to AS3, the CPU 101 counts the time in the state of AS3 or higher, for example, continuously for 30 minutes. If it is in the state, the heavy load drive flag is turned ON, and processing for restoring the operation of the clock function is performed.
[0053]
A display method of the power supply voltage level meter 304 will be described. When the voltage level is level 1, the CPU 101 lights a and b of the power supply voltage level meter 304. When the voltage level is 2 or 3D, the CPU 101 turns on b of the power supply voltage level meter 304. When the voltage level is level 3U or 4, the CPU 101 turns on the power supply voltage level meter 304 c.
[0054]
FIG. 7 is a diagram showing the operation status of each function corresponding to the display method of the power supply voltage level meter 304. When the output voltage of the secondary battery 12 detected by the BLD circuit 14 is any one of level 1, level 2 and level 3D, the main functions of the electronic timepiece are display, reception, report sound, light and normal hand movement. Works normally. On the other hand, at level 3U or level 4, the display is turned on when the voltage rises and turned off when the voltage drops. In addition, the operations of receiving, reporting sound, light, and normal hand movement are stopped.
[0055]
FIG. 8 is a flowchart showing the operation of the system program 21. First, when the electronic timepiece is turned on, the CPU 101 determines whether or not a one-minute carry signal C1 is input from the timepiece circuit 103 (step S601). When the one-minute carry signal C1 is input to the CPU 101 (step S601; Yes), the BLD circuit 14 detects the output voltage of the secondary battery 12, and performs voltage detection processing for executing each operation according to the voltage level (step S602). : FIG. 9). On the other hand, when the carry signal C1 for 1 minute is not input to the CPU 101 (step S601; No), the voltage of the secondary battery 12 is not detected, and the process proceeds to step S603.
[0056]
Next, the CPU 101 determines whether the data in the heavy load drive flag storage area 32 is “ON” or “OFF” (step S603). When the data in the heavy load drive flag storage area 32 is “ON” (step S603; Yes), it indicates that the heavy load circuit can be operated, and the CPU 101 performs the process of the next step. On the other hand, when the data in the heavy load flag storage area 32 is “OFF” (step S603; No), the driving of the heavy load circuit is prohibited due to the voltage drop of the secondary battery 12, and thus processing such as hand movement and radio wave reception is performed. The process proceeds to step S613.
[0057]
Next, the CPU 101 determines whether there is a switch input signal due to the operation of the switch unit 105. If there is an input signal, the CPU 101 executes a corresponding switch process (step S604).
[0058]
Next, the CPU 101 determines whether a 20-second carry signal C2 is input from the clock circuit 103 (step S605). When the 20-second carry signal C2 is input to the CPU 101 (step S605; Yes), the CPU 101 sends a signal to the drive circuit 110 to drive the pointer one step (step S606). On the other hand, when the 20-second carry signal C2 is not input to the CPU 101 (step S605; No), the pointer driving process is not performed and the process proceeds to step S607.
[0059]
Next, the CPU 101 compares the internal clock time, that is, whether the current time data held by the clock circuit 103 is 2:00 am (step S607). If the internal time is 2:00 am (step S607; Yes), the CPU 101 determines whether the radio wave reception mark 302 is lit (step S608). When the radio wave reception mark 302 is lit (step S608; Yes), the radio wave reception mark 302 is turned off. On the other hand, when the radio wave reception mark 302 is not lit (step S608; No), the extinguishing process is not performed and the process proceeds to step S611.
[0060]
In step S607, if the internal time is not 2:00 am (step S607; No), the CPU 101 compares whether the internal time is 4:00 am (step S610). If the internal time is 4 am (step S610; Yes), the process proceeds to step S611. On the other hand, if the internal timekeeping time is not 4 am (step S610; No), the process proceeds to step S612 without performing time correction processing by radio wave reception.
[0061]
Then, the CPU 101 performs time correction processing by radio wave reception when the internal clock time is 2:00 am or 4:00 am, and corrects the deviation of the internal clock time (step S611: FIG. 12).
[0062]
Next, the CPU 101 compares the internal clock time with the data in the alarm time storage area 34, and if they are equal, outputs a signal to the buzzer unit 105 to generate an alarm (step S612).
[0063]
Next, the CPU 101 determines whether digital display is being performed on the display unit 104 (step S613). When the digital display is being performed (step S613; Yes), the CPU 101 outputs the internal clock time to the display unit 104 and displays the current time on the digital clock (step S614).
[0064]
On the other hand, when the digital display is not performed on the display unit 104 (step S613; No), and when the display process of step S614 ends, the CPU 101 shifts the process to step S601.
[0065]
FIG. 9 is a flowchart showing the operation of the voltage detection processing program 22. First, the CPU 101 determines whether or not the output voltage V of the secondary battery 12 is greater than or equal to AS2 in FIG. 6 (V ≧ AS2) (step S701). If the voltage V is greater than or equal to AS2 (step S701; Yes), the CPU 101 determines whether the data in the voltage level storage area 31 is “1” (step S702). If the data in the voltage level storage area 31 is not “1” (step S702; No), the CPU 101 stores “1” in the voltage level storage area 31 and lights a and b of the power supply voltage level meter 304 (step S702). S704). Then, this process ends. On the other hand, if the data in the voltage level storage area 31 is already “1” in step S702 (step S702; Yes), this process ends without executing the subsequent processes.
[0066]
In step S701, when the voltage V is less than AS2 (step S701; No), the CPU 101 determines whether the voltage V is greater than or equal to AS3 and less than AS2 (AS2> V ≧ AS3) (step S705). When the voltage V is greater than or equal to AS3 and less than AS2 (step S705; Yes), the CPU 101 determines whether or not the data in the voltage level storage area 31 is “2” (step S706). When the data in the voltage level storage area 31 is not “2” (step S706; No), the CPU 101 stores “2” in the voltage level storage area 31 (step S707), and turns on b of the power supply voltage level meter 304. (Step S708). On the other hand, if the data in the voltage level storage area 31 is already “2” in step S706 (step S706; Yes), the CPU 101 proceeds to step S709.
[0067]
Next, the CPU 101 determines whether the data in the heavy load drive flag storage area 32 is “ON” or “OFF” (step S709). When the data in the heavy load drive flag storage area 32 is “OFF” (step S709; Yes), the CPU 101 determines whether the voltage level of the secondary battery 12 is AS3 or more continuously for 30 minutes (step S710). When the voltage level of the secondary battery 12 is AS3 or higher continuously for 30 minutes (step S710; Yes), the data in the heavy load drive flag storage area 32 is set to “ON” (step S711), and the pointer current time return processing is performed. This is performed (step S712: FIG. 10).
[0068]
If the data in the heavy load drive flag storage area 32 is “ON” in step S709 (step S709; No), or if the voltage V is not more than AS3 continuously for 30 minutes or more in step S710 (step S710). ; No), or when the current pointer time return processing is completed, this processing is terminated.
[0069]
If it is determined in step S705 that the voltage V is not greater than AS3 and less than AS2 (step S705; No), the CPU 101 determines whether the voltage V is greater than or equal to AS4 and less than AS3 (AS3> V ≧ AS4) (step S713). When the voltage V is greater than or equal to AS4 and less than AS3 (step S713; Yes), the CPU 101 determines whether the data in the voltage level storage area 31 is either “3D” or “3U” (step S714). If the data in the voltage level storage area 31 is not “3D” or “3U” (step S714; No), then the CPU 101 determines whether the data in the voltage level storage area 31 is “2” or “1” (step S714; No). Step S715). If the data in the voltage level storage area 31 is “2” or “1” (step S715; Yes), the CPU 101 determines that the voltage V has dropped from level 2 or 1, and sets “3D” in the voltage level storage area 31. Store (step S716), and b of the power supply voltage level meter 304 is turned on (step S717). Then, this process ends. In step S714, if the data in the voltage level storage area 31 is already “3D” or “3U” (step S714; Yes), this process is terminated without performing the subsequent processes.
[0070]
On the other hand, if the data in the voltage level storage area 31 is not “2” or “1” in step S715 (step S715; No), that is, if the data in the voltage level storage area 31 is “4”, the CPU 101 It is determined that V has risen from level 4, and “3U” is stored in the voltage level storage area 31 (step S718), and c of the power supply voltage level meter 304 is turned on (step S719). Subsequently, the CPU 101 turns on the digital display on the display unit 104 (step S720), and ends this process.
[0071]
If it is determined in step S713 that the voltage V is not greater than or equal to AS4 and less than AS3 (step S713; No), the CPU 101 determines whether the data in the voltage level storage area 31 is “4” (step S721). When the data in the voltage level storage area 31 is “4” (step S721; Yes), this process is terminated.
[0072]
On the other hand, when the data in the voltage level storage area 31 is not “4” (step S721; No), the CPU 101 stores “4” in the voltage level storage area 31 (step S722), and c of the power supply voltage level meter 304 is stored. Lights up (step S723). Subsequently, the CPU 101 turns off the digital display on the display unit 104 (step S724), and stores OFF in the heavy load drive flag storage area 32 (step S725). This stops the operation of the heavy load circuit.
[0073]
Next, the CPU 101 performs a pointer 12:00 position movement process (step S726: FIG. 11), and moves the pointer to the position of 12:00:00. Then, the CPU 101 determines whether or not the radio wave reception mark 302 is lit (step S727). If the radio wave reception mark 302 is lit (step S727; Yes), the CPU 101 turns off the radio wave reception mark 302 (step S728) and ends this process. Similarly, when the radio wave reception mark is not lit (step S727; No), the present process is terminated.
[0074]
FIG. 10 is a flowchart showing the operation of the pointer current time return processing program 23. First, the CPU 101 extracts the current time data from the input signal from the standard radio wave receiving circuit 16, calculates the number of steps of the pointer from the 12 o'clock position to the current time, that is, the number of pulses, and uses the number of pulses as the number of moving pulses. Store in the storage area 35 (step S801).
[0075]
Here, as a numerical value indicating the position of the pointer, for example, when the position of 12:00:00 is 0 memory, and this electronic timepiece has a 20-second hand movement, the pointer has one step in 20 seconds, that is, 12:01:00. At that time, the pointer advances three steps. Thus, when the current time is 1:00:00 in step S801, the CPU 101 stores the number of movement pulses (= step number) as “180” for forward rotation and “1980” for reverse rotation. Store in area 35.
[0076]
Next, the CPU 101 fast-forwards 180 steps from the position of 12:00:00 to the position of 1:00:00, the number of pulses that elapse while the pointer is fast-forwarded to the current time position. If the time required for this is 20 seconds, the number of pulses for the time elapsed during fast-forwarding is 1 pulse), and the number of pulses is stored in the correction pulse number storage area 36 (step S802).
[0077]
Subsequently, the CPU 101 outputs the sum of the data in the movement pulse number storage area 35 and the correction pulse number storage area 36 as a signal to the fast-forward pulse supply circuit 109 (step S803), and ends this process. As a result, the fast-forward pulse supply circuit 109 outputs a pulse to the drive circuit 110, and the pointer is moved to the current time position by the step motor 18 and the gear train mechanism 19.
[0078]
FIG. 11 is a flowchart showing the operation of the pointer 12:00 position movement processing program 24. Here, the pointer stop position due to the decrease in the output voltage of the secondary battery 12 is set to 12:00:00, but it is of course possible to set it to, for example, 1:00:00.
[0079]
First, the CPU 101 calculates the number of pulses from the time when the clock function stops to the position of 12:00:00 and stores it in the moving pulse number storage area 35 (step S901). For example, when the time when the clock function stops is 11:00:00, the number of steps to be moved to the position of 12:00:00 is “180” in normal rotation, that is, the number of pulses is also “180”. Become.
[0080]
Next, the CPU 101 outputs the data in the moving pulse number storage area 35 as a signal (step S902), and ends this process. As a result, the fast feed pulse supply circuit 109 outputs a pulse to the drive circuit 110, and the pointer is moved to the position of 12:00 by the step motor 18 and the gear train mechanism 19.
[0081]
FIG. 12 is a flowchart showing the operation of the radio wave reception and time correction processing program 25. First, the antenna 17 receives a radio wave (step S1001), converts the radio wave received by the standard radio wave receiving circuit 16 into a signal, and outputs the signal to the CPU 101. The CPU 101 extracts the current time, day of the week, and integrated date data from the signal (step S1002), converts the integrated date data into date data, and stores each data in the RAM 108.
[0082]
Next, the CPU 101 matches the internal timekeeping time, day-of-week data and date data held by the clock circuit 103 with each data in the current time data storage area 37, day-of-week data storage area 38 and date data storage area 39 in the RAM 108. When it is determined that there is consistency (step S1004; Yes), the process proceeds to step S1006.
[0083]
On the other hand, when it is determined that there is no consistency (step S1004; No), the CPU 101 corrects the internal timekeeping time, day of the week data, and date data held by the clock circuit 103 to each data in the RAM 108 (step S1005), and displays it. The radio wave reception mark 302 of the unit 104 is turned on (step S1006), and this process is terminated.
[0084]
As described above, when the output voltage of the secondary battery 12 decreases, the CPU 101 stops the operation of the heavy load circuit by setting the state of the heavy load drive flag storage area 32 to “OFF”. The pointer is moved to a predetermined position and stopped. When the output voltage of the secondary battery 12 rises due to charging, and the voltage is higher than AS3 for a certain period, the CPU 101 restores the timepiece function of the electronic timepiece.
[0085]
Thus, when the pointer stopped at a predetermined position is moved to an accurate time by charging the secondary battery 12, for example, the position of the pointer is determined without requiring a complicated circuit such as a needle position detection circuit. And can move.
[0086]
[Method for arranging power generation devices]
In an electronic timepiece to which the present invention is applied, solar cells (hereinafter simply referred to as “cells”) are arranged on the dial as power generation means, and in order to secure a voltage necessary for charging the secondary battery 12, When operating by connecting cells in series, if the power generation efficiency of a certain cell is poor, the charging efficiency deteriorates.
[0087]
Therefore, in order to perform charging in a short time, for example, when the hand movement is stopped due to a decrease in the output voltage of the secondary battery 12, it is necessary to examine the cell placement method with the best charging efficiency and the stop position of the pointer. is there.
[0088]
FIGS. 13A, 13B, and 13C show that the operation voltage is changed when the output voltage V of the secondary battery 12 is lowered to AS4 or less and the state of the heavy load drive flag storage area 32 is “OFF”. It is the figure which showed arrangement | positioning of the pointer position in the state which stopped, and the photovoltaic cell.
[0089]
In FIG. 13 (a), four cells 1101a, 1102a, 1103a and 1104a are arranged on the dial, and an hour hand 1110a and a minute hand 1111a are present thereon. The dial configurations in FIGS. 13B and 13C are also described with the same numerical symbols, and are distinguished by the subscripts b and c.
[0090]
In FIG. 13A, for example, when the dial of the electronic timepiece is circular, the cells 1101a to 1104a have a sector shape with a central angle at the center of the dial and are arranged in the circumferential direction. FIGS. 13B and 13C have the same configuration.
[0091]
FIG. 13A is a diagram in which the stop positions of the hour hand 1110a and the minute hand 1111a are set at the top of different cells, such as 10:10:00, when the pointer is stopped. When the pointer is concentrated on the upper part of one cell (for example, 1:10: 00), the light reception of the cell is blocked by the pointer, so that the power generation efficiency is deteriorated and the charging efficiency is decreased. Accordingly, the time when the hour hand 1110a and the minute hand 1111a are not located on the same cell is set as the stop position.
[0092]
In this case, in the pointer 12:00 position movement process of FIG. 11, for example, the pointer stop position is set to 12:00:00, but this pointer stop position is set to 10:10:00. In step S901, the number of pulses required to move the pointer to the position of 10:10:00 from the time when the hand movement stopped due to the decrease in the output voltage of the secondary battery 12 is calculated, and the hour hand 1110a and the minute hand Move 1111a.
[0093]
Thereby, power generation efficiency can be equalized in all cells, and charging efficiency can be improved.
[0094]
FIG. 13B is a diagram in which a predetermined interval is provided in all or a part between the cells, and the stop positions of the hour hand 1110b and the minute hand 1111b are set above the predetermined interval. For example, a predetermined interval is provided between the cells b1 and b4, and the time at which the hour hand 1110b and the minute hand 1111b are positioned above the predetermined interval, that is, 12:00:00 is set as the pointer stop position. Here, the cells b1, b2, b3 and b4 are arranged with the same area.
[0095]
As a result, since the pointer that blocks light reception does not stop above the cells 1101b, 1102b, 1103b, and 1104b, the power generation efficiency can be made the same in all the cells, and the charging efficiency can be improved.
[0096]
FIG. 13C is a diagram in which the area of one cell is made larger than the other cells, and the stop positions of the hour hand 1110c and the minute hand 1111c are set above the large cell when the pointer is stopped. For example, the cell c1 has a sector shape with a central angle of 120 °, and the cells c2, c3, and c4 have a sector shape with a central angle of 80 °. Then, the pointer stop position is set at a position of 12:00:00 where the hour hand 1110c and the minute hand 1111c are located above the cell c1.
[0097]
Thereby, power generation efficiency can be made comparable in all the cells, and charging efficiency can be improved.
[0098]
[Strong load monitoring BLD circuit]
Next, the heavy load monitoring BLD circuit 15 will be described. In order to effectively use the charging capacity of the secondary battery 12, the heavy load monitoring BLD circuit 15 has a strong load circuit such as an EL driver 22, a buzzer before the output voltage of the secondary battery 12 falls below the operating voltage of the CPU 101. This is a circuit having a function of outputting a signal for inhibiting the circuit operation of the unit 105 and the like.
[0099]
FIG. 14 is a circuit diagram for explaining the heavy load monitoring BLD circuit 15 and devices connected thereto, and the connection of the CPU 101, the secondary battery 12, the heavy load monitoring BLD circuit 15, the capacitor 1201, and the heavy load circuit 1202. Represents a relationship.
[0100]
The heavy load monitoring BLD circuit 15 receives the AS-2 signal corresponding to the detected voltage from the CPU 101, detects the output voltage of the secondary battery 12, and outputs the result to the CPU 101 as the signal b-2. A detection function and a heavy load monitoring function for outputting a signal b-1 that is a heavy load prohibition signal to the CPU 101 and the heavy load circuit 1202 before the output voltage of the secondary battery 12 falls below the operating voltage of the CPU 101 are provided. .
[0101]
The heavy load circuit 1202 indicates a circuit with a large load, such as the EL driver 22, the buzzer unit 105, and the drive circuit 110, for example. When the signal b-1 is input from the heavy load monitoring BLD circuit 15 or the signal b-2 which is a heavy load control signal is input from the CPU 101, the operation stops.
[0102]
FIG. 15 shows a circuit operation when the output voltage of the secondary battery 12 is lowered. Here, the description of the normal voltage detection function is omitted, and the operation voltage guarantee method of the CPU 101 and the operation timing of the signal BLD-2 and the heavy load prohibition signal b-1 will be described.
[0103]
First, referring to FIG. 15, the waveform of the graph and the set voltage for controlling the heavy load monitoring BLD circuit 15 will be described. The curve (a) shows the waveform of the output voltage V of the secondary battery 12. (B) shows the signal BLD-1, and (c) shows the signal b-1.
[0104]
Here, the minimum operating voltage of the CPU 101 is 1.3 [V], and the voltage that guarantees the operation of the CPU 101 is 1.6 [V]. Therefore, the voltage for performing the control to stop the operation of the heavy load circuit 1202 is set to 1.6 [V].
[0105]
The time ta is a time taken for the heavy load monitoring BLD circuit 15 to recognize that the voltage V is 1.6 [V], and is a time depending on hardware such as a propagation time.
[0106]
The time tb is 1 slightly higher than 1.3 [V] which is the lowest operating voltage of the CPU 101 after the strong load monitoring BLD circuit 15 recognizes that the voltage V is 1.6 [V]. This is the time required for the voltage to drop to 4 [V]. That is, t = ta + tb, and the time t is the time required for the voltage V to drop from 1.6 [V] to 1.4 [V] due to the discharge of the capacitor 1201. In the present embodiment, since the minimum operating voltage of the CPU 101 is 1.3 [V], the minimum guaranteed operating voltage is considered to be 1.4 [V].
[0107]
Next, the operation timing will be described. The voltage V drops to 1.6 [V], and then after a time ta, the heavy load monitoring BLD circuit 15 outputs the L level to the CPU 101 as the signal BLD-2. Thereafter, it takes time tb until the voltage V reaches 1.4 [V], and within this time, the heavy load monitoring BLD circuit 15 outputs the H level as the signal b-1. As a result, the heavy load circuit 1202 stops operating before falling below the minimum operating voltage of the CPU 101. When the operation of the heavy load circuit 1202 stops, the voltage V increases due to charging.
[0108]
Therefore, when the voltage V decreases to 1.6 [V] or less, the heavy load circuit 1202 stops, but the circuit continues to operate in a circuit with a small load, so the charge capacity of the secondary battery 12 should be used effectively. Can do.
[0109]
【The invention's effect】
  According to the first aspect of the present invention, when the voltage detected by the voltage detecting means becomes equal to or lower than the first voltage, the pointer is moved to a predetermined position by the pointer driving means and the operation of the radio wave correcting means is stopped. The operation of the radio wave correcting means is started when the detection means continuously detects that the voltage exceeds the second voltage for a certain period of time, and the pointer is set to the current time position based on the time information obtained by the radio wave correcting means. Since it is made to move, the reduction | decrease in the electric power of an electrical storage means can be suppressed, For example, a pointer drive means can be controlled, without requiring complicated circuits, such as a hand position detection circuit.In addition, a predetermined interval is provided in all or part of the plurality of battery cells, and the predetermined position is an upper portion of the predetermined interval, so that it is possible to realize a power generation unit with good charging efficiency.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration of an electronic timepiece to which the present invention is applied.
FIG. 2 is a diagram showing a data structure of a ROM in an electronic timepiece.
FIG. 3 is a diagram showing a data structure of a RAM in an electronic timepiece.
FIG. 4 is a diagram showing an example of the appearance of an electronic timepiece.
FIG. 5 shows a display unit of an electronic timepiece.
FIG. 6 is a diagram showing a discharge characteristic of a secondary battery, a setting range of a voltage level thereof, and a display method of a power supply voltage level meter corresponding to each level in the electronic timepiece.
FIG. 7 is a diagram showing an operation state of each function corresponding to a display method of a power supply voltage level meter in the electronic timepiece.
FIG. 8 is a flowchart showing a basic operation in the electronic timepiece.
FIG. 9 is a flowchart showing each operation corresponding to the voltage level of the output voltage of the secondary battery in the electronic timepiece.
FIG. 10 is a flowchart showing the operation of a pointer current time return process in the electronic timepiece.
FIG. 11 is a flowchart showing an operation of a hand 12 o'clock position movement process in the electronic timepiece.
FIG. 12 is a flowchart showing operations of radio wave reception and time correction processing in the electronic timepiece.
FIG. 13 is a diagram showing a pointer position and an arrangement of solar cells in a state where the hand movement is stopped in the electronic timepiece.
FIG. 14 is a circuit diagram showing a heavy load monitoring BLD circuit and devices connected thereto in an electronic timepiece.
FIG. 15 is a timing chart showing a circuit operation when the output voltage of the secondary battery is lowered in the electronic timepiece.
[Explanation of symbols]
10 Clock circuit
101 CPU
102 Oscillator circuit
103 Clock circuit
104 Display section
105 Buzzer
106 Switch part
107 ROM
108 RAM
109 Rapid feed pulse supply circuit
110 Drive circuit
11 Solar cell
12 Secondary battery
13 Capacitor
14 Voltage detection circuit
15 Heavy load monitoring voltage detection circuit
16 Standard radio wave receiver
17 Antenna
18 Step motor
19 Wheel train mechanism
20 Guidelines
21 Tilt switch
22 EL driver
23 EL element

Claims (5)

A pointer to display the time,
A power supply circuit having a power generation means and a power storage means;
Pointer driving means that operates at the output voltage of the power supply circuit and drives the pointer;
A current time counting means that operates at the output voltage of the power supply circuit and counts the current time;
A radio wave correcting means that operates at the output voltage of the power supply circuit, receives radio waves including a time code, obtains time information, and corrects the current time of the current time counting means based on the obtained time information;
Voltage detection means for detecting an output voltage of the power supply circuit;
When the voltage detected by the voltage detecting means becomes equal to or lower than the first voltage, the pointer is moved to a predetermined position by the pointer driving means and the operation of the radio wave correcting means is stopped, and the voltage detecting means When the voltage of 2 or more is continuously detected for a predetermined time, the operation of the radio wave correction means is started, and the pointer is moved by the pointer drive means based on the time information obtained by the radio wave correction means. Control means for moving to the current time position,
The power generation means has a plurality of solar cells arranged on a dial,
A predetermined interval is provided in all or a part between the plurality of battery cells, and the predetermined position is an upper portion of the predetermined interval. The electronic timepiece according to claim 1,
The control means obtains a movement amount of the pointer based on the predetermined position and a current time of the current time counting means, and moves the pointer by a movement amount obtained by the pointer driving means. Electronic clock. The electronic timepiece according to claim 1 or 2,
The electronic timepiece according to claim 1, wherein the predetermined position is a position of 12:00:00. The electronic timepiece according to any one of claims 1 to 3,
The electronic timepiece is characterized in that the plurality of solar cells are arranged in a circumferential direction with a predetermined interval between all or part of the solar cells. The electronic timepiece according to any one of claims 1 to 4,
A heavy load control means for controlling the driving of the heavy load;
Monitoring the output voltage of the power supply circuit at the time of heavy load driving, and when it becomes a predetermined voltage, a strong load voltage monitoring means for prohibiting the control of the heavy load by the heavy load control means;
An electronic timepiece characterized by further comprising:

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