JP4305424B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP4305424B2
JP4305424B2 JP2005202967A JP2005202967A JP4305424B2 JP 4305424 B2 JP4305424 B2 JP 4305424B2 JP 2005202967 A JP2005202967 A JP 2005202967A JP 2005202967 A JP2005202967 A JP 2005202967A JP 4305424 B2 JP4305424 B2 JP 4305424B2
Authority
JP
Japan
Prior art keywords
control pad
semiconductor element
metal layer
wiring
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005202967A
Other languages
Japanese (ja)
Other versions
JP2007027183A (en
Inventor
知巳 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2005202967A priority Critical patent/JP4305424B2/en
Publication of JP2007027183A publication Critical patent/JP2007027183A/en
Application granted granted Critical
Publication of JP4305424B2 publication Critical patent/JP4305424B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、半導体素子の両面に金属体を半田付けして構成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device configured by soldering metal bodies on both sides of a semiconductor element and a method for manufacturing the same.

高耐圧・大電流用のパワーＩＣ（ＩＧＢＴやＭＯＳＦＥＴ等）の半導体チップ（半導体素子）は、使用時の発熱が大きいため、半導体チップからの放熱性を向上させるための構成が必要である。この構成の一例として、半導体チップの両面にヒートシンク（金属体）を半田付けする構成が考えられており、例えば特許文献１に記載されている。
特開２００３−０６８９５９号公報 A semiconductor chip (semiconductor element) of a power IC (IGBT, MOSFET, etc.) for high withstand voltage and large current generates a large amount of heat during use, and thus requires a configuration for improving heat dissipation from the semiconductor chip. As an example of this configuration, a configuration in which a heat sink (metal body) is soldered to both surfaces of a semiconductor chip is considered, and is described in Patent Document 1, for example.
JP 2003-068959 A

上記従来構成の半導体チップ（例えばＩＧＢＴ）の上面には、半田付け用の第１の電極（例えばエミッタ電極）が設けられていると共に、その周辺部にワイヤボンディング用の制御パッド（例えばゲートパッド）が設けられている。この構成の場合、半導体チップの第１の電極上に銅ブロック（ヒートシンク）を半田付けした後、制御パッドにボンディングワイヤをボンディングしている。   A first electrode (for example, an emitter electrode) for soldering is provided on the upper surface of the semiconductor chip (for example, IGBT) having the above-described conventional configuration, and a wire bonding control pad (for example, a gate pad) is provided on the periphery thereof Is provided. In this configuration, a copper block (heat sink) is soldered on the first electrode of the semiconductor chip, and then a bonding wire is bonded to the control pad.

しかし、上記構成の場合、半導体チップの第１の電極上に銅ブロックを半田付けするとき、即ち、半田のリフロー工程において半田を融解するときに、半田が突沸することがあり、溶融した半田の小さな粒が飛散して制御パッド上に付着することがあった。そして、半田が付着した制御パッド上にワイヤボンディングすると、ボンディング強度が低下し、剥離が起こるおそれがあった。   However, in the case of the above configuration, when soldering the copper block on the first electrode of the semiconductor chip, that is, when melting the solder in the solder reflow process, the solder may bump, Small particles may scatter and adhere to the control pad. When wire bonding is performed on the control pad to which the solder is attached, the bonding strength is reduced and peeling may occur.

これに対して、制御パッドを覆う治具を半導体チップに取り付け、溶融した半田の小さな粒が飛散しても、上記治具により制御パッド上に付着することを防止する構成が考えられる。しかし、この構成の場合、半導体チップには反りがあるため、治具で制御パッドを密着して覆うことが難しく、半田の付着を防止することが困難であった。また、治具により半導体チップの割れを招くおそれもあり、この治具を用いる方法は実際には採用することができなかった。   On the other hand, a configuration is conceivable in which a jig for covering the control pad is attached to the semiconductor chip, and even if small particles of molten solder are scattered, the jig prevents the solder from adhering to the control pad. However, in this configuration, since the semiconductor chip is warped, it is difficult to closely cover the control pad with a jig and it is difficult to prevent adhesion of solder. Moreover, there is a possibility that the semiconductor chip may be cracked by the jig, and the method using this jig cannot be actually used.

尚、リフロー工程後に、ＩＰＡ（イソプロピルアルコール）を用いて洗浄することにより、リフロー時の異物を除去する方法がある。しかし、この方法では、制御パッドに付着した半田を除去することができない。   In addition, there is a method of removing foreign matters during reflow by washing with IPA (isopropyl alcohol) after the reflow step. However, this method cannot remove the solder attached to the control pad.

そこで、本発明の目的は、半田のリフロー工程時に半田の小さな粒が飛散して制御パッド上に付着することがあっても、制御パッド上にワイヤボンディングしたときに、ボンディング強度が低下することを極力防止できる半導体装置及びその製造方法を提供するにある。   Accordingly, an object of the present invention is to reduce bonding strength when wire bonding is performed on a control pad even if small particles of solder may scatter and adhere to the control pad during the solder reflow process. It is an object of the present invention to provide a semiconductor device that can be prevented as much as possible and a manufacturing method thereof.

請求項１の発明は、半導体素子の両面に金属体を半田付けして構成されたものにおいて、前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、前記金属層の上に半田レジスト材料を設けることにより複数に分割されているところに特徴を有する。 The invention of claim 1 is configured by soldering a metal body on both surfaces of a semiconductor element, and is provided on one surface of the semiconductor element, and a first electrode for soldering the metal body; A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires; and two or more bonding wires bonded to the control pad. The control pad is characterized in that it is formed by providing a metal layer on the Al wiring and is divided into a plurality of parts by providing a solder resist material on the metal layer .

請求項２の発明は、半導体素子の両面に金属体を半田付けして構成された半導体装置において、前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、前記金属層は、半田レジスト材料により複数に分割されているところに特徴を有する。 According to a second aspect of the present invention, in a semiconductor device configured by soldering a metal body on both sides of a semiconductor element, the first electrode is provided on one surface of the semiconductor element and solders the metal body A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires; and two or more bonding wires bonded to the control pad. The control pad is formed by providing a metal layer on an Al wiring, and the metal layer is divided into a plurality of parts by a solder resist material .

請求項３の発明は、半導体素子の両面に金属体を半田付けして構成された半導体装置において、前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、前記金属層及び前記Ａｌ配線は、半田レジスト材料により複数に分割されているところに特徴を有する。 According to a third aspect of the present invention, in a semiconductor device configured by soldering a metal body to both surfaces of a semiconductor element, the first electrode is provided on one surface of the semiconductor element and is used to solder the metal body A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires; and two or more bonding wires bonded to the control pad. The control pad is formed by providing a metal layer on an Al wiring, and the metal layer and the Al wiring are divided into a plurality of parts by a solder resist material .

請求項４の発明は、半導体素子の一方の面に設けられ半田付け用の第１の電極と、前記半導体素子の一方の面における周辺部に設けられワイヤボンディング用の制御パッドとを備えた半導体装置の製造方法において、前記制御パッドを形成するためのＡｌ配線の上に、前記制御パッドを分割するための半田レジスト材料を設ける工程と、前記Ａｌ配線の上に金属層を設ける工程とを備えたところに特徴を有する。 According to a fourth aspect of the present invention , there is provided a semiconductor comprising: a first electrode for soldering provided on one surface of a semiconductor element; and a control pad for wire bonding provided at a peripheral portion on one surface of the semiconductor element. The method for manufacturing an apparatus includes a step of providing a solder resist material for dividing the control pad on the Al wiring for forming the control pad, and a step of providing a metal layer on the Al wiring. It has features.

以下、本発明の第１の実施例について、図１ないし図４を参照しながら説明する。まず、図３は本実施例の半導体装置の概略構成を示す断面図である。この図３に示すように、本実施例の半導体装置１は、半導体素子２と、下側ヒートシンク（金属体）３と、上側ヒートシンク（金属体）４と、ヒートシンクブロック（金属体）５とを備えて構成されている。   A first embodiment of the present invention will be described below with reference to FIGS. First, FIG. 3 is a sectional view showing a schematic configuration of the semiconductor device of the present embodiment. As shown in FIG. 3, the semiconductor device 1 of the present embodiment includes a semiconductor element 2, a lower heat sink (metal body) 3, an upper heat sink (metal body) 4, and a heat sink block (metal body) 5. It is prepared for.

上記半導体素子２は、例えばＩＧＢＴやＭＯＳＦＥＴやサイリスタ等のパワー半導体素子から構成されている。この半導体素子２の形状は、本実施例の場合、例えば矩形の薄板状である。また、下側ヒートシンク３、上側ヒートシンク４及びヒートシンクブロック５は、例えばＣｕで構成されている。尚、上記Ｃｕに代えて、Ａｌ等の熱伝導性及び電気伝導性の良い金属で構成しても良い。   The semiconductor element 2 is composed of a power semiconductor element such as an IGBT, a MOSFET, or a thyristor. In the case of this embodiment, the shape of the semiconductor element 2 is, for example, a rectangular thin plate. The lower heat sink 3, the upper heat sink 4, and the heat sink block 5 are made of Cu, for example. Note that, instead of Cu, a metal having good thermal conductivity and electrical conductivity such as Al may be used.

また、上記構成の半導体装置１において、半導体素子２の下面と下側ヒートシンク３の上面との間は、接合部材である例えば半田６によって接合されている。そして、半導体素子２の上面とヒートシンクブロック５の下面との間も、半田６によって接合されている。更に、ヒートシンクブロック５の上面と上側ヒートシンク４の下面との間も、半田６によって接合されている。   In the semiconductor device 1 having the above-described configuration, the lower surface of the semiconductor element 2 and the upper surface of the lower heat sink 3 are joined by, for example, solder 6 that is a joining member. The upper surface of the semiconductor element 2 and the lower surface of the heat sink block 5 are also joined by solder 6. Further, the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 are also joined by solder 6.

上記構成においては、半導体素子２の両面からヒートシンク３、４及びヒートシンクブロック５を介して放熱される構成となっている。
また、図１及び図２に示すように、半導体素子２の一方の面である上面には、主電極である第１の電極（例えばエミッタ電極）７が設けられていると共に、上記上面における周辺部である図１中の下辺部には、制御電極である例えば５個の制御パッド８が設けられている。これら制御パッド８は、例えばゲートパッドや、電流センサ用の制御パッドや、温度センサ用の制御パッド等である。 In the above configuration, heat is radiated from both surfaces of the semiconductor element 2 through the heat sinks 3 and 4 and the heat sink block 5.
As shown in FIGS. 1 and 2, a first electrode (for example, an emitter electrode) 7 that is a main electrode is provided on the upper surface that is one surface of the semiconductor element 2, and the periphery of the upper surface is For example, five control pads 8 which are control electrodes are provided on the lower side in FIG. These control pads 8 are, for example, gate pads, control pads for current sensors, control pads for temperature sensors, and the like.

各制御パッド８は、後述するようにして、例えば４個に分割された分割パッド８ａを有している。各分割パッド８ａの面積は、ボンディングワイヤ９（図１参照）を１本ボンディングすることが可能な最小の面積である。従って、制御パッド８は、ボンディングワイヤ９を例えば４本（即ち、２本以上）ボンディングすることが可能な面積を有している。   Each control pad 8 has, for example, a divided pad 8a divided into four as will be described later. The area of each divided pad 8a is the minimum area where one bonding wire 9 (see FIG. 1) can be bonded. Therefore, the control pad 8 has an area where four bonding wires 9 (for example, two or more) can be bonded.

また、半導体素子２の他方の面である下面の全面には、主電極である第２の電極（例えばコレクタ電極）１０が設けられている。
そして、図１に示すように、第２の電極１０には、下側ヒートシンク３が半田６を介して電気的に接続されていると共に、第１の電極７には、ヒートシンクブロック５が半田６を介して電気的に接続されている。また、制御パッド８は、リードフレーム１１にボンディングワイヤ９を介してワイヤーボンディングされている。 A second electrode (for example, a collector electrode) 10 that is a main electrode is provided on the entire lower surface that is the other surface of the semiconductor element 2.
As shown in FIG. 1, the lower heat sink 3 is electrically connected to the second electrode 10 via the solder 6, and the heat sink block 5 is connected to the first electrode 7 with the solder 6. It is electrically connected via. The control pad 8 is wire bonded to the lead frame 11 via a bonding wire 9.

この構成の場合、制御パッド８の４個の分割パッド８ａすべてに対してワイヤーボンディングしても良いし、４個の分割パッド８ａのうちの適当な３個または２個または１個の分割パッド８ａに対してワイヤーボンディングするように構成しても良い。また、第１の電極７から遠い側の２個の分割パッド８ａ（またはそのうちの１個の分割パッド８ａ）だけに対してワイヤーボンディングするように構成しても良い。   In the case of this configuration, wire bonding may be performed to all four divided pads 8a of the control pad 8, or appropriate three, two, or one divided pad 8a of the four divided pads 8a. Alternatively, wire bonding may be used. Alternatively, only two divided pads 8a (or one divided pad 8a of them) on the side far from the first electrode 7 may be wire-bonded.

また、下側ヒートシンク３及び上側ヒートシンク４は、厚さ寸法が例えば約２ｍｍ程度の板材で形成されている。ヒートシンクブロック５は、厚さ寸法が例えば約１．５ｍｍ程度の板材で形成されており、その大きさは、半導体素子２の大きさよりも１回り小さい程度の大きさ（即ち、第１の電極７とほぼ同じ大きさ）である。また、半導体素子２の厚さ寸法は、例えば約０．１４ｍｍ程度であり、半田６の厚さ寸法は、例えば約０．１ｍｍ程度である。   The lower heat sink 3 and the upper heat sink 4 are formed of a plate material having a thickness dimension of, for example, about 2 mm. The heat sink block 5 is formed of a plate material having a thickness dimension of, for example, about 1.5 mm, and the size of the heat sink block 5 is slightly smaller than the size of the semiconductor element 2 (that is, the first electrode 7). About the same size). Moreover, the thickness dimension of the semiconductor element 2 is about 0.14 mm, for example, and the thickness dimension of the solder 6 is about 0.1 mm, for example.

尚、半導体装置１のほぼ全体は、図示しない樹脂（例えばエポキシ樹脂）によりモールドされている。この場合、半導体装置１を樹脂でモールドするに当たっては、上下型からなる成形型（図示しない）を使用している。尚、ヒートシンク３、４の端子部（図示しない）及びリードフレーム１１の端子部（図示しない）は、モールド成形体（図示しない）から突出するように構成されている。更に、下側ヒートシンク３の下面と上側ヒートシンク４の上面は、モールド成形体から露出するように構成されている。また、上記した構成の半導体装置１の製造方法（即ち、製造工程）の具体例は、本出願人がすでに出願した特願２００１−１２７５１６に記載されており、これに記載されている方法を適宜使用すれば良い。   Note that almost the entire semiconductor device 1 is molded with a resin (not shown) (for example, epoxy resin). In this case, when the semiconductor device 1 is molded with resin, a molding die (not shown) composed of upper and lower molds is used. In addition, the terminal part (not shown) of the heat sinks 3 and 4 and the terminal part (not shown) of the lead frame 11 are configured to protrude from a molded body (not shown). Furthermore, the lower surface of the lower heat sink 3 and the upper surface of the upper heat sink 4 are configured to be exposed from the molded body. A specific example of the manufacturing method (ie, manufacturing process) of the semiconductor device 1 having the above-described configuration is described in Japanese Patent Application No. 2001-127516 already filed by the present applicant, and the method described therein is appropriately selected. Use it.

次に、第１の電極７、第２の電極１０及び制御パッド８の具体的構成について説明する。第２の電極１０は、図２に示すように、半導体基板１２の下面に金属層１３を形成して構成されている。金属層１３は、例えばＮｉとＡｕを積層して構成されている。第１の電極７と制御パッド８は、半導体基板１２の上面に形成されたＡｌ配線１４と、このＡｌ配線１４の上に形成された金属層１５とから構成されている。金属層１５は、例えばＮｉとＡｕを積層して構成されている。尚、上記Ａｌ配線１４の代わりに、例えばＡｌＳｉ配線を形成するように構成しても良い。   Next, specific configurations of the first electrode 7, the second electrode 10, and the control pad 8 will be described. As shown in FIG. 2, the second electrode 10 is configured by forming a metal layer 13 on the lower surface of the semiconductor substrate 12. The metal layer 13 is configured by stacking, for example, Ni and Au. The first electrode 7 and the control pad 8 are composed of an Al wiring 14 formed on the upper surface of the semiconductor substrate 12 and a metal layer 15 formed on the Al wiring 14. The metal layer 15 is configured by stacking, for example, Ni and Au. In place of the Al wiring 14, for example, an AlSi wiring may be formed.

また、半導体基板１２上における外周部並びに第１の電極７と制御パッド８との間には、保護膜１６が設けられている。この保護膜１６は、例えばポリイミドで形成されている。尚、上記ポリイミド（保護膜１６）は、半田レジスト材料である。   A protective film 16 is provided between the outer peripheral portion of the semiconductor substrate 12 and between the first electrode 7 and the control pad 8. The protective film 16 is made of polyimide, for example. The polyimide (protective film 16) is a solder resist material.

そして、図１及び図２に示すように、制御パッド８の金属層１５は、保護膜１６により４個の領域に分割されており、これら４個の領域が前記分割パッド８ａを構成している。この構成の場合、金属層１５は半田レジスト材料により分割されている。   As shown in FIGS. 1 and 2, the metal layer 15 of the control pad 8 is divided into four regions by the protective film 16, and these four regions constitute the divided pad 8a. . In the case of this configuration, the metal layer 15 is divided by a solder resist material.

ここで、制御パッド８及び第１の電極７を形成する製造工程について、図４を参照して説明する。まず、図４（ａ）に示すように、半導体基板１２上に所定のパターンのＡｌ配線１４を形成する。この場合、図４（ａ）中の右側のＡｌ配線１４が制御パッド８に対応し、左側のＡｌ配線１４が第１の電極７に対応している。   Here, a manufacturing process for forming the control pad 8 and the first electrode 7 will be described with reference to FIG. First, as shown in FIG. 4A, an Al wiring 14 having a predetermined pattern is formed on a semiconductor substrate 12. In this case, the right Al wiring 14 in FIG. 4A corresponds to the control pad 8, and the left Al wiring 14 corresponds to the first electrode 7.

この後、図４（ｂ）に示すように、半導体基板１２上に保護膜１６を形成する。この場合、ポリイミドの膜を全面に形成した後、マスク等を用いて設定されたパターンの保護膜１６だけを残すようにし、残りを除去する。ここで、保護膜１６のうちの制御パッド８用のＡｌ配線１４の上に形成された部分が、制御パッド８を分割するための保護膜１６、即ち、半田レジスト材料である。   Thereafter, as shown in FIG. 4B, a protective film 16 is formed on the semiconductor substrate 12. In this case, after a polyimide film is formed on the entire surface, only the protective film 16 having a pattern set using a mask or the like is left, and the rest is removed. Here, a portion of the protective film 16 formed on the Al wiring 14 for the control pad 8 is the protective film 16 for dividing the control pad 8, that is, a solder resist material.

続いて、図４（ｃ）に示すように、Ａｌ配線１４の上に金属層１５を形成する。この金属層１５は、例えばＮｉ層とＡｕ層を積層して構成されている。これにより、第１の電極７及び制御パッド８が形成される。そして、制御パッド８においては、図１に示すように、その金属層１５が保護膜１６により４個に分割されている。   Subsequently, as shown in FIG. 4C, a metal layer 15 is formed on the Al wiring 14. The metal layer 15 is formed by stacking, for example, a Ni layer and an Au layer. Thereby, the first electrode 7 and the control pad 8 are formed. In the control pad 8, as shown in FIG. 1, the metal layer 15 is divided into four by a protective film 16.

このような構成の本実施例によれば、制御パッド８の面積を、ボンディングワイヤを４本ボンディングすることが可能な面積としたので、半導体素子２の第１の電極７にヒートシンクブロック５を半田付けするときに、即ち、半田のリフロー工程時に、半田の小さな粒が飛散して制御パッド８上に付着することがあっても、制御パッド８上に半田が付着していない部分をほぼ確実に確保することができ、制御パッド８上にワイヤボンディングしたときに、ボンディング強度が低下することを極力防止できる。   According to this embodiment having such a configuration, the area of the control pad 8 is set to an area where four bonding wires can be bonded, so that the heat sink block 5 is soldered to the first electrode 7 of the semiconductor element 2. When soldering, that is, during the solder reflow process, even if small particles of solder may scatter and adhere to the control pad 8, the portion where the solder is not attached to the control pad 8 is almost certainly ensured. It can be ensured, and it is possible to prevent the bonding strength from being lowered as much as possible when wire bonding is performed on the control pad 8.

特に、上記実施例では、制御パッド８を複数に、例えば４個に分割したので、半田のリフロー工程時に、半田の小さな粒が飛散して制御パッド８の４個の分割パッド８ａ中の１個または２個の分割パッド８ａ上に付着することがあっても、半田は、付着した分割パッド８ａ上で広がるだけであり、他の分割パッド８ａ上にまで広がらない。これにより、制御パッド８上に半田が付着していない部分をほぼ確実に確保することができる。   In particular, in the above embodiment, since the control pad 8 is divided into a plurality of, for example, four, one of the four divided pads 8a of the control pad 8 is scattered during the solder reflow process. Alternatively, even if the solder adheres on the two divided pads 8a, the solder spreads only on the adhered divided pads 8a and does not spread on the other divided pads 8a. As a result, it is possible to almost certainly ensure a portion on the control pad 8 where no solder is attached.

更に、上記実施例においては、制御パッド８を分割するに際して、Ａｌ配線１４上に設けられた金属層１５を、保護膜１６（半田レジスト材料）により分割するように構成したので、半田のリフロー工程時に、半田の小さな粒が飛散して制御パッド８の４個の分割パッド８ａ中の１個または２個の分割パッド８ａ上に付着することがあっても、保護膜１６により、半田は、付着した分割パッド８ａ上で広がるだけとなり、他の分割パッド８ａ上にまで広がることを防止できる。   Further, in the above embodiment, when the control pad 8 is divided, the metal layer 15 provided on the Al wiring 14 is divided by the protective film 16 (solder resist material), so that the solder reflow process is performed. Even if a small particle of solder may scatter and adhere to one or two of the four divided pads 8a of the control pad 8, the solder adheres due to the protective film 16. It spreads only on the divided pad 8a and can be prevented from spreading to other divided pads 8a.

図５は本発明の第２の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第２の実施例では、制御パッド８を分割するに際して、Ａｌ配線１４上に設けられた金属層１５を保護膜１６により分割する代わりに、図５に示すように、金属層１５の上に制御パッド８分割用の保護膜（半田レジスト材料）１７を設けるように構成した。   FIG. 5 shows a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, when the control pad 8 is divided, instead of dividing the metal layer 15 provided on the Al wiring 14 by the protective film 16, as shown in FIG. A protective film (solder resist material) 17 for dividing the control pad 8 is provided.

そして、上述した以外の第２の実施例の構成は、第１の実施例と同じ構成となっている。従って、第２の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。   The configuration of the second embodiment other than that described above is the same as that of the first embodiment. Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained.

図６は本発明の第３の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第３の実施例では、制御パッド８を分割するに際して、Ａｌ配線１４上に設けられた金属層１５を保護膜１６により分割する代わりに、図６に示すように、Ａｌ配線１４及び金属層１５を制御パッド８分割用の保護膜（半田レジスト材料）１６で分割するように構成した。   FIG. 6 shows a third embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. In the third embodiment, when the control pad 8 is divided, instead of dividing the metal layer 15 provided on the Al wiring 14 by the protective film 16, as shown in FIG. 15 is divided by a protective film (solder resist material) 16 for dividing the control pad 8.

そして、上述した以外の第３の実施例の構成は、第１の実施例と同じ構成となっている。従って、第３の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。   The configuration of the third embodiment other than that described above is the same as that of the first embodiment. Accordingly, in the third embodiment, substantially the same operational effects as in the first embodiment can be obtained.

また、上記各実施例においては、制御パッド８を４個の分割パッド８ａに分割するように構成したが、これに限られるものではなく、２個、３個、または５個以上に分割するように構成しても良い。   In each of the above embodiments, the control pad 8 is divided into four divided pads 8a. However, the present invention is not limited to this, and the control pad 8 is divided into two, three, or five or more. You may comprise.

本発明の第１の実施例を示す半導体素子の上面図The top view of the semiconductor element which shows 1st Example of this invention 図１中II−II線に沿う断面図1 is a cross-sectional view taken along line II-II in FIG. 半導体装置の縦断面図Longitudinal section of semiconductor device 第１の電極及び制御パッドの製造工程を説明する図The figure explaining the manufacturing process of a 1st electrode and a control pad 本発明の第２の実施例を示す図２相当図FIG. 2 equivalent view showing a second embodiment of the present invention 本発明の第３の実施例を示す図２相当図FIG. 2 equivalent view showing a third embodiment of the present invention.

符号の説明Explanation of symbols

図面中、１は半導体装置、２は半導体素子、３は下側ヒートシンク（金属体）、４は上側ヒートシンク（金属体）、５はヒートシンクブロック（金属体）、６は半田、７は第１の電極、８は制御パッド、８ａは分割パッド、９はボンディングワイヤ、１０は第２の電極、１１はリードフレーム、１２は半導体基板、１３は金属層、１４はＡｌ配線、１５は金属層、１６は保護膜、１７は保護膜を示す。

In the drawings, 1 is a semiconductor device, 2 is a semiconductor element, 3 is a lower heat sink (metal body), 4 is an upper heat sink (metal body), 5 is a heat sink block (metal body), 6 is solder, 7 is a first Electrode, 8 is a control pad, 8a is a split pad, 9 is a bonding wire, 10 is a second electrode, 11 is a lead frame, 12 is a semiconductor substrate, 13 is a metal layer, 14 is an Al wiring, 15 is a metal layer, 16 Denotes a protective film, and 17 denotes a protective film.

Claims (4)

半導体素子の両面に金属体を半田付けして構成された半導体装置において、
前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、
前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、
前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、
前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、前記金属層の上に半田レジスト材料を設けることにより複数に分割されていることを特徴とする半導体装置。 In a semiconductor device configured by soldering metal bodies on both sides of a semiconductor element,
A first electrode provided on one surface of the semiconductor element for soldering the metal body;
A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires ;
Two or more bonding wires bonded to the control pad,
The control pad is formed by providing a metal layer on an Al wiring, and is divided into a plurality of parts by providing a solder resist material on the metal layer . 半導体素子の両面に金属体を半田付けして構成された半導体装置において、
前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、
前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、
前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、
前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、
前記金属層は、半田レジスト材料により複数に分割されていることを特徴とする半導体装置。 In a semiconductor device configured by soldering metal bodies on both sides of a semiconductor element,
A first electrode provided on one surface of the semiconductor element for soldering the metal body;
A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires;
Two or more bonding wires bonded to the control pad,
The control pad is formed by providing a metal layer on the Al wiring,
The metal layer shall be the characterized in that it is divided into a plurality by a solder resist material semiconductors devices. 半導体素子の両面に金属体を半田付けして構成された半導体装置において、
前記半導体素子の一方の面に設けられ、前記金属体を半田付けするための第１の電極と、
前記半導体素子の一方の面における周辺部に設けられ、ボンディングワイヤを２本以上ボンディングすることが可能な面積を有する制御パッドと、
前記制御パッドにボンディングされる２本以上のボンディングワイヤとを備え、
前記制御パッドは、Ａｌ配線上に金属層を設けて形成されていると共に、
前記金属層及び前記Ａｌ配線は、半田レジスト材料により複数に分割されていることを特徴とする半導体装置。 In a semiconductor device configured by soldering metal bodies on both sides of a semiconductor element,
A first electrode provided on one surface of the semiconductor element for soldering the metal body;
A control pad provided in a peripheral portion on one surface of the semiconductor element and having an area capable of bonding two or more bonding wires;
Two or more bonding wires bonded to the control pad,
The control pad is formed by providing a metal layer on the Al wiring,
The metal layer and the Al wiring you characterized in that it is divided into a plurality by a solder resist material semiconductors devices. 半導体素子の一方の面に設けられ半田付け用の第１の電極と、前記半導体素子の一方の面における周辺部に設けられワイヤボンディング用の制御パッドとを備えた半導体装置の製造方法において、
前記制御パッドを形成するためのＡｌ配線の上に、前記制御パッドを分割するための半田レジスト材料を設ける工程と、
前記Ａｌ配線の上に金属層を設ける工程とを備えたことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device, comprising: a first electrode for soldering provided on one surface of a semiconductor element; and a control pad for wire bonding provided at a peripheral portion on one surface of the semiconductor element;
Providing a solder resist material for dividing the control pad on the Al wiring for forming the control pad;
And a step of providing a metal layer on the Al wiring .
JP2005202967A 2005-07-12 2005-07-12 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4305424B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005202967A JP4305424B2 (en) 2005-07-12 2005-07-12 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005202967A JP4305424B2 (en) 2005-07-12 2005-07-12 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2007027183A JP2007027183A (en) 2007-02-01
JP4305424B2 true JP4305424B2 (en) 2009-07-29

Family

ID=37787612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005202967A Expired - Fee Related JP4305424B2 (en) 2005-07-12 2005-07-12 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4305424B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7979257B2 (en) 2003-02-05 2011-07-12 Moldflow Netherlands Limited Apparatus and methods for performing process simulation using a hybrid model

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111630644B (en) * 2018-03-02 2023-07-14 新电元工业株式会社 Semiconductor device and method for manufacturing the same
CN113130515A (en) * 2019-12-31 2021-07-16 格科微电子（上海）有限公司 Method for manufacturing optical fingerprint device
CN113270430A (en) * 2020-02-17 2021-08-17 格科微电子（上海）有限公司 Method for forming infrared cut-off light filtering film in optical fingerprint device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7979257B2 (en) 2003-02-05 2011-07-12 Moldflow Netherlands Limited Apparatus and methods for performing process simulation using a hybrid model

Also Published As

Publication number Publication date
JP2007027183A (en) 2007-02-01

Similar Documents

Publication Publication Date Title
TWI450373B (en) Dual side cooling integrated power device package and module and methods of manufacture
JP5442368B2 (en) IC chip package with direct lead wire
US20190229042A1 (en) Semiconductor device and method for manufacturing semiconductor device
US6992385B2 (en) Semiconductor device, a method of manufacturing the same and an electronic device
JP5271886B2 (en) Semiconductor device and manufacturing method thereof
TWI485817B (en) Microelectronic packages with enhanced heat dissipation and methods of manufacturing
CN107615464B (en) Method for manufacturing power semiconductor device and power semiconductor device
JP6076675B2 (en) Semiconductor device
JP2010021515A (en) Semiconductor device and its manufacturing method
JP6266168B2 (en) Semiconductor device
JP3390661B2 (en) Power module
WO2016166835A1 (en) Semiconductor device
KR20170086828A (en) Clip -bonded semiconductor chip package using metal bump and the manufacturing method thereof
JP6094413B2 (en) Semiconductor module and manufacturing method thereof
JP2019091922A (en) Semiconductor device
JP4305424B2 (en) Semiconductor device and manufacturing method thereof
JP2002329804A (en) Semiconductor device
JP2022168128A (en) Semiconductor device
US20220310409A1 (en) Method to connect power terminal to substrate within semiconductor package
JP6472568B2 (en) Manufacturing method of semiconductor device
JP7460051B2 (en) Semiconductor Device
JP2022143167A (en) Semiconductor device
JP5119092B2 (en) Manufacturing method of semiconductor device
TWI814424B (en) Thinned semiconductor package and packaging method thereof
US7601560B2 (en) Method for producing an electronic circuit

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070820

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080129

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090106

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090224

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090407

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090420

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120515

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120515

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130515

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140515

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees