JP4301134B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit for level-shifting an input signal and outputting it to a circuit operating under a different power supply system, and more particularly to a level shift circuit suitable for a high-side drive circuit.

  FIG. 4 shows a bridge circuit driving apparatus disclosed in Patent Document 1. In FIG. The high-side drive circuit 3 operates by receiving power supply from a bootstrap capacitor C1 connected between the power supply line 1 and the power supply line 2, and is driven via a level shift circuit 4 at its input terminal. A control signal SH is given. While the low-side transistor QL is on, the capacitor C1 is charged to the power supply voltage Vcc via the diode D1.

The level shift circuit 4 includes an inverter 5 for inverting the drive control signal SH, a resistor R1, a transistor Q1, a constant current circuit 7, and a power supply line 1 and a ground line 6 connected in series between the power supply line 1 and the ground line 6. A resistor R2, a transistor Q2 and a constant current circuit 8 connected in series with each other, a transistor Q3 and Q5 connected in series between a power supply line 1 and a power supply line 2, and a power supply line 1 and a power supply line 2 Between the transistors Q4 and Q6 connected in series. When the drive control signal SH is at the H level, the transistors Q1, Q3, and Q6 are turned on, and the transistors Q2, Q4, and Q5 are turned off. When the drive control signal SH is at the L level, the on / off state is inverted.
JP 2003-179482 A

However, in the level shift circuit, the voltage of the power supply line 1 rises to VDD + Vcc-Vf (D1), and this voltage is directly applied to the drains of the transistors Q1 and Q2. For this reason, the transistors Q1 and Q2 need to have a breakdown voltage higher than the above voltage.
Further, in order to reliably turn on the transistors Q3 and Q4 and to protect the gate and source from an excessive voltage, the resistance values of the resistors R1 and R2 and the current values of the constant current circuits 7 and 8 are set accurately. There is a need. However, it is difficult to set the resistance value with high accuracy in the semiconductor manufacturing process, and in actuality, it is impossible to manufacture with the circuit configuration as it is.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a level shift circuit that can use an element having a lower withstand voltage and is less susceptible to variations in element constants.

  According to the means described in claim 1, a load circuit, a second transistor, a first transistor, a resistor or a constant current circuit is connected in series between the third power supply line and the second power supply line. The selection circuit selects a higher one of the voltage of the fourth power supply line and the predetermined bias voltage and supplies the selected one to the gate of the second transistor. The gate and source of the second transistor are protected by a voltage limiting circuit. The bias voltage is necessary when the voltage of the fourth power supply line drops to a voltage that is insufficient to turn on the second transistor.

  When the first transistor is turned on in response to the input signal, the second transistor is turned on by a voltage output from the selection circuit (hereinafter referred to as a selection voltage), and the second transistor is turned on from the third power supply line through the load circuit. Current flows through the second transistor. As a result, the level shift circuit outputs an L-level signal voltage to a circuit provided between the third power supply line and the fourth power supply line. On the other hand, when the first transistor is turned off in response to the input signal, the second transistor is also turned off and no current flows through the load circuit. As a result, the level shift circuit outputs an H level signal voltage to a circuit provided between the third power supply line and the fourth power supply line.

  In this level shift circuit, the gate potential of the second transistor is fixed by a selection voltage, that is, the voltage of the fourth power supply line or a predetermined bias voltage, and the voltage of the third power supply line is the same as that of the first transistor. Applied to the series circuit with the second transistor. Therefore, the voltage of the third power supply line is shared by these two transistors, and an element having a breakdown voltage lower than the voltage of the third power supply line can be used for each transistor. Further, since the drain potential of the second transistor is determined according to the selection voltage, it is not easily affected by variations in element constants.

  According to the second aspect of the present invention, the fifth transistor, the second transistor, the first transistor, the first resistor, or the first resistor is provided between the third power supply line and the second power supply line. A constant current circuit is connected in series, and a resistor, a fourth transistor, a third transistor, a second resistor, or a second constant current circuit is connected in series. The output of this level shift circuit has a push-pull circuit configuration composed of a fifth transistor and a second transistor. The selection circuit selects a higher one of the voltage of the fourth power supply line and a predetermined bias voltage and supplies the selected one to the gates of the second and fourth transistors. The gate and source of the second and fourth transistors are protected by first and second voltage limiting circuits, respectively.

  When the first transistor is turned on and the third transistor is turned off in accordance with the input signal, the second transistor is turned on, the fourth transistor is turned off, and the resistance connected between the gate and source of the fifth transistor The voltage drop is zero. As a result, the fifth transistor is turned off, and the level shift circuit outputs an L-level signal voltage to a circuit provided between the third power supply line and the fourth power supply line.

  On the other hand, when the first transistor is turned off and the third transistor is turned on in accordance with the input signal, the second transistor is turned off and the fourth transistor is turned on, and is connected between the gate and source of the fifth transistor. A voltage drop occurs in the resistor and the fifth transistor is turned on. As a result, the level shift circuit outputs an H level signal voltage to a circuit provided between the third power supply line and the fourth power supply line.

  In this level shift circuit, the gate potentials of the second and fourth transistors are fixed by a selection voltage, that is, the voltage of the fourth power supply line or a predetermined bias voltage, and the voltage of the third power supply line is the first voltage. It is applied to the series circuit of the transistor and the second transistor and the series circuit of the third transistor and the fourth transistor. Accordingly, the voltage of the third power supply line is shared by the first transistor, the second transistor, and the third transistor and the fourth transistor, respectively, and each transistor has a withstand voltage lower than the voltage of the third power supply line. It is possible to use an element that has the same. Further, since the drain potential of the fourth transistor is determined according to the selection voltage, an excessive voltage is not applied between the gate and the source of the fifth transistor even if the element constant varies.

  According to the means described in claim 3, of the two diodes whose cathodes are connected to each other, only the diode that receives the higher one of the voltage of the fourth power supply line and the bias voltage is turned on. 2. A selection voltage is applied to the gate of the fourth transistor.

  According to the means described in claim 4, the bias voltage is set to a value higher than at least the threshold voltage of the second and fourth transistors plus the forward voltage of the diode. Therefore, when the bias voltage is higher than the voltage of the fourth power supply line, when the first or third transistor is turned on, the second or fourth transistor can be reliably turned on.

  According to the means described in claim 5, the gate-source voltages of the second and fourth transistors are limited to be less than or equal to the Zener voltage of the Zener diode constituting the voltage limiting circuit. Therefore, the second and fourth transistors are protected even when the voltage of the fourth power supply line increases.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 shows a driving device 11 for transistors QH and QL constituting a bridge circuit. Between a terminal 13 to which a main circuit voltage VDD (for example, 28 V) is applied and a terminal 14 having a ground potential, a high-side N-channel MOS transistor QH and a low-side N-channel MOS transistor QL are connected to a terminal 12. Are connected in series with The transistors QH and QL are connected to diodes DH and DL of the polarities shown in the drawing, respectively.

  The drive device 11 includes a drive circuit 15 that drives the transistor QH, a drive circuit 16 that drives the transistor QL, a bootstrap circuit 17 that generates a power supply voltage of the drive circuit 15, and a level shift circuit 18 that converts the level of the drive control signal SH. It is composed of The driving device 11 is configured as a semiconductor integrated circuit (IC) using a BiCMOS manufacturing process.

  The drive circuit 16 on the low side side operates by receiving a power supply voltage Vcc (for example, 5V) from the power supply lines 19 and 20, and outputs a drive voltage corresponding to the drive control signal SL to the gate of the transistor QL. ing. On the other hand, the drive circuit 15 on the high side operates by receiving power supply from the capacitor C11 charged in the bootstrap circuit 17 that receives the power supply voltage Vs (for example, 14V), and performs drive control via the level shift circuit 18. The signal SH is input, and a drive voltage corresponding to the drive control signal SH is output to the gate of the transistor QH.

  The level shift circuit 18 shifts the level of the drive control signal SH generated by a control circuit (not shown) provided between the power supply lines 19 and 20, and connects between both terminals of the capacitor C 11, that is, between the power supply lines 21 and 22. It is a circuit that outputs to the drive circuit 15 connected between them. The power line 22 is connected to the terminal 12 of the bridge circuit. These power supply lines 19, 20, 21, and 22 correspond to the first, second, third, and fourth power supply lines in the present invention, respectively.

  The drive control signal SH is directly applied to the gate of the N-channel MOS transistor Q13 and is also applied to the gate of the N-channel MOS transistor Q11 via the inverter 23. Resistors R11 and R12 (corresponding to first and second resistors) are connected between the sources of the transistors Q11 and Q13 and the power supply line 20, respectively, and the drain sides (nodes Na and Nb) of the transistors Q11 and Q13 are connected. ) Are connected in series with N-channel MOS transistors Q12 and Q14.

  The gates of the transistors Q12 and Q14 are connected to each other. Between the gates and sources of the transistors Q12 and Q14, Zener diodes D11 and D12 (corresponding to first and second voltage limiting circuits), respectively, with the gate side as a cathode. Is connected. A diode D13 having the illustrated polarity is connected between the gates of the transistors Q12 and Q14 and the power supply line 19, and a diode D14 having the illustrated polarity is connected between the gates of the transistors Q12 and Q14 and the power supply line 22. Is connected. These diodes D13 and D14 constitute a selection circuit 24, and the power supply voltage Vcc becomes a bias voltage.

  A resistor R15, a P-channel MOS transistor Q15, and a resistor R13 are connected in series between the power supply line 21 and the drain of the transistor Q12 (node Nc). The power supply line 21 and the drain of the transistor Q14 (node Nd) Between the two resistors R16 and R14 are connected in series. The drain of the transistor Q12 (node Nc) and the drain of the transistor Q15 (node Ne) are output nodes of the level-shifted drive control signal SH.

  The gate of the transistor Q15 is connected to the power supply line 21 via the emitter-collector of the NPN transistor Q16. The base of the transistor Q16 is connected to a common connection point between the resistors R16 and R14, and a diode D15 having the polarity shown is connected between the base and emitter of the transistor Q16. This transistor Q16 is added to shorten the turn-off time of the transistor Q15. The transistors Q11 to Q15 of the level shift circuit 18 described above correspond to the first to fifth transistors in the present invention, respectively.

Next, a specific circuit configuration of the drive circuit 15 will be described.
Transistors Q17 and Q18 constituting a push-pull circuit are connected in series between the power supply lines 21 and 22 of the drive circuit 15, and the common connection node Nf is connected to the gate of the transistor QH of the main circuit. ing.

  Two sets of current mirror circuits 25 and 26 composed of PNP transistors are connected to the power line 21. Of these, the current mirror circuit 25 includes transistors Q19 and Q20, and supplies a current necessary for turning on the transistor Q18. On the other hand, the current mirror circuit 26 includes transistors Q21 and Q22, and supplies a current necessary to turn off the transistor Q18.

  The emitter of the transistor Q19 is connected to the node Nc between the collector and emitter of the transistor Q23, and via the resistor R17 and the diode D16. The transistor Q23 controls the supply of current to the current mirror circuit 25 in accordance with the voltage at the node Nc, and its base is connected to the node Nf. The emitter of the transistor Q20 is connected to the power supply line 22 via the resistor R18, and is further connected to the gates of the transistors Q18 and Q24. Transistor R25 for turning off transistors Q18 and Q24 is connected in parallel to resistor R18, and its gate is connected to node Nc via resistor R19 and diode D17. A resistor R20 is connected between the gate and source of the transistor Q25. The diodes D16 and D17 prevent current from flowing around.

  The transistor Q24 is made to have the same characteristics as the transistor Q18, and functions to lower the gate potential of the transistor Q17 while the transistor Q18 is on. The gate of the transistor Q17 is connected to the node Ne via resistors R22 and R21, and the common connection point of the resistors R22 and R21 is connected to the drain of the transistor Q24 via a diode D18 that prevents current from flowing around. ing.

  The emitter of the transistor Q21 constituting the current mirror circuit 26 is connected to the node Nf via the resistor R23 and the drain and source of the transistor Q26. The gate of the transistor Q26 is connected to the node Ne via the resistor R24, and the transistor Q26 controls the supply of current to the current mirror circuit 26 in accordance with the voltage at the node Ne. The emitter of transistor Q22 is connected to the gate of transistor Q25.

  As is well known, the bootstrap circuit 17 is a circuit that charges the capacitor C11 from the power supply line 27 that supplies the power supply voltage Vs while the low-side transistor QL of the bridge circuit is on. The drive circuit 15 uses the charging voltage of the capacitor C11 as the power supply voltage. Between the power line 27 and the power line 21, a resistor R25 and a diode D19 that form a charging path are connected in series.

Next, the operation of this embodiment will be described with reference to FIG.
The drive control signals SH and SL used in PWM control and the like repeat H level (= Vcc) and L level (= 0 V) at a predetermined switching frequency, and have different levels except for the dead time period. When drive control signals SH and SL are H level and L level, respectively, transistor QH is turned on and transistor QL is turned off. When drive control signals SH and SL are respectively L level and H level, transistor QH is turned off. Transistor QL is turned on.

  FIG. 2 shows respective waveforms of the drive control signal SH based on the potential of the power supply line 20, the voltage VHS of the power supply line 22, the voltage VBS of the power supply line 21, and the voltage V (Nd) of the node Nd. The change waveform of the rise or fall of each voltage at times t1 and t2 is drawn slightly exaggerated. The actual change is very fast and does not always change linearly.

Hereinafter, the operation of the level shift circuit 18 and the drive circuit 15 in each level state of the drive control signals SH and SL will be described in detail.
(1) When drive control signal SH is at H level and drive control signal SL is at L level [Operation of level shift circuit 18]
When the drive control signal (SH, SL) changes from (L level, H level) to (H level, L level) at time t1 shown in FIG. 2, the transistor Q13 is turned on immediately thereafter. At this time, since the voltage VHS of the power supply line 22 has not yet increased, VHS <Vcc, and the diode D13 is turned on in the selection circuit 24. When the transistor Q13 is turned on, Vcc-Vf (D13) (Vf: forward voltage of the pn junction) is applied between the gate and source of the transistor Q14, so that the transistor Q14 is also turned on. As a result, the drain current of (Vcc−Vf (D13)) / R12 flows through the transistors Q13 and Q14.

  When the transistors Q13 and Q14 are turned on, the gate capacitance of the transistor Q15 is transiently charged through the diode D15, and the transistor Q15 is turned on. After the transistor Q15 is turned on, current constantly flows from the power supply line 21 to the transistors Q14 and Q13 via the resistors R16 and R14. Further, when the drive control signal SH becomes H level, the transistor Q11 is immediately turned off, and accordingly, the transistor Q12 is also turned off.

  That is, the output portion of the level shift circuit 18 has a push-pull circuit configuration composed of transistors Q15 and Q12. When the transistor Q15 is turned on, the voltage V (Nc) at the node Nc and the voltage V (Ne) at the node Ne are It approaches the potential of the power line 21. As described above, the level shift circuit 18 shifts the level of the H-level drive control signal SH input from the power supply system including the power supply lines 19 and 20, and drives the drive circuit of different power supply systems including the power supply lines 21 and 22. 15 is output as it is as logic at H level.

[Operation of Drive Circuit 15]
When the potential of the node Ne rises, the gate potential of the transistor Q17 rises and the transistor Q17 is turned on, and the transistor Q18 is turned off as described later. If there is a period in which the transistors Q17 and Q18 are simultaneously turned on in this transient state, a through current flows and the electric charge accumulated in the capacitor C11 is discharged, and a sufficient boosting action by the bootstrap circuit 17 cannot be obtained. Therefore, a transistor Q24 having the same on / off state as the transistor Q18 is provided, and an increase in the gate potential of the transistor Q17 is suppressed while the transistor Q24 is on.

  On the other hand, when the potential of the node Ne rises, the transistors Q23, Q19, and Q20 are turned off, and the current flowing through the resistor R18 is cut off. Further, the transistor Q26 is turned on, and a current flows through the resistor R20 via the current mirror circuit 26. The voltage drop of the resistor R20 turns on the transistor Q25, discharges the gate charges of the transistors Q18 and Q24, and turns off the transistors Q18 and Q24. In the subsequent steady state, the transistors Q17 and Q26 are in the subthreshold state, so that the current flowing through the current mirror circuit 26 is substantially zero. Thereby, the current consumption of the drive circuit 15 can be minimized.

[Examination of device breakdown voltage in level shift circuit 18]
When the transistor QH is turned on, the transistor QL is turned off, and the voltage VHS of the power supply line 22 exceeds the power supply voltage Vcc, the selection circuit 24 turns on the diode D14 instead of the diode D13. When the voltage VHS further rises, the Zener diode D12 turns on. In this case, the drain current of the transistor Q13 is the sum of the current flowing through the resistors R16 and R14 and the transistor Q14 and the current flowing from the power supply line 22 through the diodes D14 and D12.

At this time, the voltage V (Nb) at the node Nb and the voltage V (Nd) at the node Nd are expressed by the following equation (1) if the drain-source voltage of the transistor Q14 is sufficiently small. Here, Vz (D12) is a Zener voltage of the diode D12, which is higher than the threshold voltage Vth of the transistors Q12 and Q14 and lower than the breakdown voltage between the gate and source of the transistors Q12 and Q14 (an example) As 5V).
V (Nc) = V (Nd) = VHS−Vf (D14) −Vz (D12) (1)

In the state where the transistor QH is sufficiently turned on, the voltage VHS is substantially equal to the main circuit voltage VDD, so that the voltages V (Nc) and V (Nd) are expressed by the following equation (2).
V (Nc) = V (Nd) = VDD−Vf (D14) −Vz (D12) (2)

The maximum value V (C11) max of the voltage charged to the capacitor C11 (the voltage across the terminals of the capacitor C11) is expressed by equation (3).
V (C11) max = Vs-Vf (D19) (3)

The voltage VBS of the power supply line 21 with respect to the potential of the power supply line 20 is expressed by the following equation (4).
VBS = VDD + V (C11) max = VDD + Vs-Vf (D19) (4)

When the voltage drop of the resistor R14 is ignored, the gate-source voltage VGS (Q15) of the transistor Q15 is expressed by the following equation (5).
VGS (Q15) = V (C11) max + Vf (D14) + Vz (D12) -Vf (D15)
= Vs + Vz (D12) -Vf (5)

  That is, when the drive control signal SH is at the H level and the drive control signal SL is at the L level, the voltage VBS of the power supply line 21 is the difference between the main circuit voltage VDD and the bootstrap power supply voltage Vs as shown in the equation (4). It rises to near the addition voltage. However, in this embodiment, the voltage V (Nd) of the node Nd when the transistors Q13 and Q14 are turned on is a value based on the main circuit voltage VDD (for example, VDD-6V) as shown in the equation (2). It will only decline. For this reason, the gate-source voltage VGS (Q15) of the transistor Q5 does not exceed a value (for example, Vs + 4 V) based on the power supply voltage Vs as shown in the equation (5), and the gate-source voltage of the transistor Q5 Can be protected from high voltage.

  Further, the drain potential (= voltage V (Nc)) of the transistor Q12 in the off state rises to the voltage VBS shown in the equation (4), but an intermediate voltage VHS−Vf (D14) is applied to the gate of the transistor Q12. Therefore, the voltage VBS is shared by the transistors Q12 and Q11 based on the intermediate voltage. Therefore, the transistors Q11 and Q12 can be protected from a high voltage.

(2) When drive control signal SH is at L level and drive control signal SL is at H level [Operation of level shift circuit 18]
When the drive control signal (SH, SL) changes from (H level, L level) to (L level, H level) at time t2 shown in FIG. 2, the transistor Q11 is immediately turned on. At this time, since the voltage VHS of the power supply line 22 has risen to the vicinity of the main circuit voltage VDD, VHS> Vcc, and the diode D14 is turned on in the selection circuit 24. When the transistor Q11 is turned on, current flows from the power supply line 22 through the diodes D14 and D11 and the transistor Q11, and the Zener voltage Vz of the diode D11 is applied between the gate and source of the transistor Q12, so that the transistor Q12 is also turned on. Transition. At this time, a current of (VHS−Vf (D14) −Vz (D12)) / R11 flows through the transistors Q11 and Q12.

  On the other hand, when the drive control signal SH becomes L level, the transistor Q13 is turned off, and accordingly, the transistor Q14 is also turned off. As a result, the diode D15 is turned off, the transistor Q16 is temporarily turned on, and the gate charge of the transistor Q15 is discharged. As a result, the transistor Q15 is rapidly turned off.

When the transistor Q12 is turned on and the transistor Q15 is turned off, the voltage V (Nc) at the node Nc and the voltage V (Ne) at the node Ne are expressed by the following equation (6) with the potential of the power supply line 20 as a reference.
V (Nc) = V (Ne) = VHS−Vf (D14) −Vz (D11) (6)

  If the Zener voltage Vz (D11) of the diode D11 is 5V, the voltage V (Nc) at the node Nc and the voltage V (Ne) at the node Ne are reduced by about 6V from the voltage VHS of the power supply line 22. Thus, the level shift circuit 18 shifts the level of the L-level drive control signal SH input from the power supply system including the power supply lines 19 and 20, and drives the drive circuits of different power supply systems including the power supply lines 21 and 22. 15 is output as L level logic as it is.

[Operation of Drive Circuit 15]
When the voltages of the nodes Nc and Ne decrease, the gate potential of the transistor Q17 decreases and the transistor Q17 immediately shifts to the off state. At the same time, the diodes D16 and D17 are turned on, the gate potential of the transistor Q25 is lowered, and a current flows through the resistor R18 via the transistor Q23 and the current mirror circuit 25. The transistors Q18 and Q24 are turned on by the voltage drop of the resistor R18. In this case, the transistors Q26, Q21, and Q22 are in an off state.

The transistor Q23 is turned on when the following equation (7) is satisfied.
V (Nf) −V (Nc)> 2 · Vf (7)
When the transistor Q18 is turned on, the voltage V (Nf) at the node Nf becomes substantially equal to the voltage VHS of the power supply line 22. When the decreasing voltage VHS is still about 6V or more, the diodes D14 and D11 are turned on, and the voltage V (Nc) at the node Nc is approximately VHS-6V. In this case, the relationship of V (Nf) −V (Nc) = 6V> 2 · Vf shown in the equation (7) is established, and the transistor Q23 is turned on.

  Thereafter, when the voltage VHS drops below 5V and the diode D13 is turned on instead of the diode D14, the voltage V (Nc) at the node Nc becomes 5V−Vf (D13) −VGS (Q14), which is shown in the equation (7). V (Nf) -V (Nc) is VHS-5V + Vf (D13) + VGS (Q14). Here, when Vf≈1V is approximated, when the voltage VHS falls below 6V−VGS (Q14), the transistor Q23 turns off. Therefore, the transistor Q23 is temporarily turned on when the transistors QH and QL are in the on / off transition state, but is turned off in the steady state where the transistor QH is off and the transistor QL is on. Thereby, the current consumption of the drive circuit 15 can be minimized.

[Examination of device breakdown voltage in level shift circuit 18]
When the transistor QH is turned off, the transistor QL is turned on, and the voltage VHS of the power supply line 22 becomes almost 0 V, the voltage VBS of the power supply line 21 becomes low as shown in the equation (8).
VBS = V (C11) max = Vs−Vf (D19) (8)

  Therefore, any withstand voltage problem does not occur in any of the transistors Q13, Q14, and Q15 in the off state.

  As described above, according to the present embodiment, the transistors Q12 and Q14 that mirror their switching states are connected in series to the transistors Q11 and Q13 that are turned on and off by the drive control signal SH, and the transistors Q12 and Q14 The voltage VHS of the high-side power supply line 22 is applied to the gate via the selection circuit 24. This configuration limits the drop in the drain voltage of the transistor Q14 in the on state while the high-side transistor QH is on, so that the resistance values of the resistors R14 and R16 and the like vary in manufacturing. However, the gate-source of the transistor Q15 can be protected from an excessive voltage. Further, since the transistors Q11 and Q12 in the off state share the voltage VBS of the power supply line 21 during the same period, the level shift circuit 18 is configured using a transistor having a breakdown voltage lower than the voltage VBS (= VDD + Vs−Vf). can do.

Since the output portion of the level shift circuit 18 has a push-pull circuit configuration, the level shift circuit 18 has a sufficient current drive capability for the drive circuit 15.
Since the transistor Q16 for discharging the gate charge of the transistor Q15 is connected between the gate and source of the transistor Q15, the turn-off time of the transistor Q15 can be shortened.

  Since the selection circuit 24 is provided and the voltage VHS of the power supply line 22 or the power supply voltage Vcc, whichever is higher, is applied to the gates of the transistors Q12 and Q14, the voltage VHS is close to 0V as in this embodiment. Even when the voltage drops to the level of Q1, the transistor Q12 or Q14 can be sufficiently turned on. The voltage input to the anode of the diode D13 of the selection circuit 24 is not limited to the power supply voltage Vcc. Based on this input voltage, the minimum value of the drain potential (voltage V (Nd)) of the transistor Q14 during the period when the drive control signal SH is at the H level can be set to an appropriate value.

  In the drive circuit 15, the transistor Q24 having the same on / off state as the transistor Q18 is provided, and the rise of the gate potential of the transistor Q17 is suppressed while the transistor Q24 is on. Therefore, the transistors Q17 and Q18 constituting the push-pull circuit are configured. Are not simultaneously turned on, and a sufficient boosting action can be obtained for the bootstrap circuit 17.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 3 shows a driving device for the transistors QH and QL constituting the bridge circuit. The same components as those in FIG. The drive device 28 includes a level shift circuit 30 that shifts the level of the drive control signal SH and outputs it to the drive circuit 29. The circuit configuration of the drive circuit 29 is not limited as long as it has an ability to drive the transistor QH. For example, the drive circuit 29 may be the drive circuit 15 shown in FIG.

  The level shift circuit 30 has a single output configuration. A resistor R26 (corresponding to a load circuit), a transistor Q12, a transistor Q11, and a resistor R11 are connected in series between the power lines 21 and 20, and a drive control signal SH is connected to the gate of the transistor Q11 via an inverter 23. Is entered. A Zener diode D11 is connected between the gate and source of the transistor Q12, and a bias voltage V1 is applied to the anode of the diode D13 of the selection circuit 24 via a resistor R27. As the bias voltage V1, the power supply voltage Vcc may be used as in the first embodiment.

  In this configuration, when the drive control signal (SH, SL) changes from (L level, H level) to (H level, L level), the transistors Q11 and Q12 are turned off, and the voltage V (Nc) at the node Nc is supplied from the power source. It becomes equal to the voltage VBS of the line 21. The drive circuit 29 turns on the transistor QH according to the drive control signal at the H level output from the level shift circuit 30. The operations of the selection circuit 24 and the diode D11 in this case are as described in the first embodiment.

  The drain potential (= voltage V (Nc)) of the transistor Q12 in the off state rises to the voltage VBS shown in the above equation (4), but the gate of the transistor Q12 has an intermediate value of VHS−Vf (D14). Since a voltage is applied, voltage VBS is shared by transistors Q12 and Q11. Therefore, the transistors Q11 and Q12 can be protected from a high voltage.

On the other hand, when the drive control signal (SH, SL) changes from (H level, L level) to (L level, H level), the transistor Q11 is turned on, and the current is supplied from the power supply line 22 through the diodes D14, D11, and the transistor Q11. Flows. As a result, the Zener voltage Vz of the diode D11 is applied between the gate and source of the transistor Q12, and the transistor Q12 is also turned on. At this time, the voltage V (Nc) of the node Nc is expressed by the above-described equation (6). The drive circuit 29 drives the transistor QH off in accordance with the L level drive control signal output from the level shift circuit 30.
As described above, according to this embodiment, the same operation and effect as those of the first embodiment can be obtained except that the level shift circuit 30 has a single output configuration.

(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
In each of the above-described embodiments, the level shift circuits 18 and 30 are used as signal transmission means to the high-side drive circuits 15 and 29 of the bridge circuit. However, the present invention is not limited to this, and signals are sent to circuits operating under different power supply systems. It is also applicable when transmitting

When the voltage VHS is always a value that can sufficiently turn on the transistor Q12 or Q14, the bias voltage applied to the anode of the diode D13 of the selection circuit 24 can be 0V. In this case, the selection circuit 24 always selects the voltage VHS of the power supply line 22, but the present invention includes such a case.
Instead of the first resistor R11 and the second resistor R12, a first constant current circuit and a second constant current circuit may be used, respectively. The load circuit is not limited to the resistor R26, and may be an active load, for example.

The circuit block diagram of the drive device which shows the 1st Embodiment of this invention The figure which shows each waveform of drive control signal SH, voltage VHS, voltage VBS, and voltage V (Nd) FIG. 1 equivalent diagram showing a second embodiment of the present invention 1 equivalent diagram showing the prior art

Explanation of symbols

18 and 30 are level shift circuits, 19 to 22 are power supply lines (first to fourth power supply lines), 24 is a selection circuit, Q11 to Q15 are MOS transistors (first to fifth transistors), and D11 and D12 are Zener diodes (first and second voltage limiting circuits), R11 and R12 are resistors (first and second resistors), and R26 is a resistor (load circuit).

Claims (5)

An input signal given from a circuit provided between the first power supply line and the second power supply line is level-shifted, and the circuit provided between the third power supply line and the fourth power supply line is changed to a circuit provided between the third power supply line and the fourth power supply line. On the other hand, in the output level shift circuit,
A first transistor that operates using the input signal as a gate signal;
A resistor or a constant current circuit connected between the first transistor and the second power supply line;
A second transistor connected in series to the first transistor;
A load circuit connected between the third power supply line and the second transistor;
A selection circuit that selects a higher one of the voltage of the fourth power supply line and a predetermined bias voltage and applies the selected voltage to the gate of the second transistor;
A voltage limiting circuit connected between the gate and source of the second transistor and limiting the voltage between the gate and source to a predetermined value or less,
A level shift circuit characterized in that an output signal corresponding to the input signal is extracted from the drain of the second transistor. An input signal given from a circuit provided between the first power supply line and the second power supply line is level-shifted, and the circuit provided between the third power supply line and the fourth power supply line is changed to a circuit provided between the third power supply line and the fourth power supply line. On the other hand, in the output level shift circuit,
A first transistor that operates using an inverted signal of the input signal as a gate signal;
A first resistor or a first constant current circuit connected between the first transistor and the second power supply line;
A second transistor connected in series to the first transistor;
A first voltage limiting circuit which is connected between the gate and source of the second transistor and limits the voltage between the gate and source to a predetermined value or less;
A third transistor that operates using a non-inverted signal of the input signal as a gate signal;
A second resistor or a second constant current circuit connected between the third transistor and the second power supply line;
A fourth transistor connected in series to the third transistor;
A second voltage limiting circuit which is connected between the gate and source of the fourth transistor and limits the voltage between the gate and source to a predetermined value or less;
A selection circuit that selects a higher one of the voltage of the fourth power supply line and a predetermined bias voltage and applies the selected one to the gates of the second and fourth transistors;
A fifth transistor connected between the third power supply line and the second transistor;
A resistor connected between the third power supply line and the fourth transistor and between the gate and source of the fifth transistor;
A level shift circuit characterized in that an output signal corresponding to the input signal is extracted from the drain of the second transistor.   The selection circuit is composed of two diodes having cathodes connected to each other. The commonly connected cathode is an output terminal, and the anode of the diode is an input terminal for the voltage of the fourth power supply line. 3. The level shift circuit according to claim 1, wherein the level shift circuit is an input terminal for the bias voltage.   4. The level according to claim 3, wherein the bias voltage is set to a value higher than a voltage value obtained by adding a forward voltage of a diode to a threshold voltage of at least the second and fourth transistors. Shift circuit. 5. The level shift circuit according to claim 1, wherein the voltage limiting circuit is configured by a Zener diode.

Images