JP4296248B2 - Single flux quantum logic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a single flux quantum (SFQ) logic circuit.
[0002]
[Prior art]
Single-flux-quantum (SFQ) logic circuits using superconducting elements can operate with a clock of 100 MHz or higher (IEEE Trans. On Applied Superconductivity. Vol. 3, No. 1, March 1991, pp. 3-28) .
[0003]
The SFQ circuit is configured by using a Josephson junction and an inductance formed by a superconducting wiring. A resistor is not used for the signal transmission path, and the magnetic flux quantum is used as an information carrier. In the SFQ circuit, when a superconducting closed loop including a Josephson junction and an inductance L is formed and the magnetic flux quantum Ф0 can be held in the loop, when the critical current is represented by Ic, L · Ic is 1/0 of Ф0. Design parameters are determined to be about 2 to 1 times.
[0004]
[Problems to be solved by the invention]
In the SFQ circuit, since no resistance is used for the signal transmission path, the bias current supplied to the Josephson junction also flows to and interferes with the circuits before and after the Josephson junction, resulting in unstable operation. . That is, the bias current is not isolated between the logic circuits.
[0005]
Further, although the chip on which the SFQ circuit is formed is magnetically shielded, it is not perfect, and unnecessary magnetic flux may be trapped in the superconducting loop when it is cooled to operate the chip.
[0006]
In view of such problems, the object of the present invention is to provide a single flux quantum logic circuit capable of preventing a bias current supplied to a Josephson junction from flowing to and interfering with a circuit adjacent to the Josephson junction. Is to provide.
[0007]
Another object of the present invention is to provide a single-flux quantum logic circuit that can be automatically reset with a simple configuration and can suppress a reduction in operating margin.
[0008]
[Means for solving the problems and their effects]
The single flux quantum logic circuit of claim 1, wherein the first single flux quantum basic logic gate is connected to the second single flux quantum basic logic gate via a Josephson transfer line.
In the Josephson transfer line, a resistor is connected in series with an inductance.
[0009]
According to this single magnetic flux quantum logic circuit, the direct current bias current flowing through the Josephson junction cannot flow to the basic logic gate on the resistance side due to the presence of the resistance, so that the operation is stabilized. That is, the first basic logic gate and the second basic logic gate can avoid the interference of the DC bias current by the Josephson transfer line.
[0010]
Further, even when an unnecessary magnetic flux is trapped in the closed loop before the start of the operation in which the DC bias current is not supplied when the chip on which the circuit is formed is cooled, the time constant determined by the inductance L and the resistance R By waiting for a time sufficiently longer than L / R, the trapped magnetic flux disappears and the circuit is reset. That is, establishment of unnecessary magnetic flux traps can be reduced.
[0011]
The single-flux quantum logic circuit according to claim 2, wherein the resistance value R of the resistor is equal to the time constant L / R of a series connection circuit of the inductance having the value L and the resistor. It is determined to be larger.
[0012]
The single flux quantum logic circuit according to claim 3, wherein the resistance value R of the resistor satisfies the relational expression R << 2LIcRn / Ф0, where Ic, Rn and Ф0 are the Josephson junctions, respectively. The critical current value, the normal resistance value of the Josephson junction, and the single flux quantum value.
[0013]
The single-flux quantum logic circuit according to claim 4 is the junction resistance according to claim 4, wherein the resistance is a metal or an oxide for preventing passage of a superconducting current between spaced superconductors.
[0014]
The single flux quantum logic circuit according to claim 5, wherein the resistor includes one selected from the group of Mo, Al, Au, Pt, Cu, Pd, Au—Pd, ITO, and RuOx. Made of material.
[0015]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
FIG. 1 shows an SFQ logic circuit according to a first embodiment of the present invention.
[0018]
In this circuit, SFQ Josephson transfer lines (SFQJTL) 13 and 14 are connected between the SFQ basic logic gates 10 and 11 and between the SFQ basic logic gates 11 and 12, respectively. Each of the circuits 10 and 11 is a conventional SFQ basic logic gate composed of a Josephson junction and an inductance, and each of the circuits 13 and 14 is a Josephson junction and an inductance in a conventional SFQ Josephson transfer line. In each closed loop including a resistor, a resistor is inserted so as to avoid a DC bias current path passing through the Josephson junction. The inductance is formed by superconductor wiring.
[0019]
The DC bias current IB is supplied to any of the circuits 10 to 14. The SFQ basic logic gates 10, 11 and 12 are supplied with clocks T1, T2 and T3, respectively, and each basic logic gate outputs a logical operation result when a clock is supplied after an input signal is supplied.
[0020]
In SFQJTL13, a resistor R1 is connected between the inductance L1 and the Josephson junction J1, and a DC bias current IB is supplied to the Josephson junction J1. One end on the input side of the inductance L1 of the SFQJTL 13 forms a closed loop with the output stage of the SFQ basic logic gate 10. SFQJTL14 has the same configuration as SFQJTL13, and inductance L2 is connected between inductance L2 and Josephson junction J2, and DC bias current IB is supplied to Josephson junction J2. One end on the input side of the inductance L2 of the SFQJTL 14 forms a closed loop with the output stage of the SFQ basic logic gate 11.
[0021]
SFQ basic logic gates are: AND gate, OR gate, exclusive OR gate, negation gate, D flip-flop, RS flip-flop, DC / SFQ conversion circuit, SFQ-DC conversion circuit, branch circuit, junction circuit, multiplexer Circuit or demultiplexer circuit.
[0022]
The clocks T2 and T3 are generated by the timing circuit 15 which is an SFQ Josephson transfer line in response to the clock T1. J3 to J8 are Josephson junctions, L4, L5, L7 and L8 are inductances, and R4 and R7 are resistances. Each of J3, J4J6, J6 and J7 is supplied with a DC bias current IB, which corresponds to the DC bias current IB supplied to the circuits 10, 13, 11 and 14, respectively. The DC bias current IB is, for example, 75% of the critical current Ic of the Josephson junction. The resistor R4, the inductance L4, and the Josephson junction J4 of the timing circuit 15 correspond to SFQJTL13, and the resistor R7, the inductance L7, and the Josephson junction J7 of the timing circuit 15 correspond to SFQJTL14. The resistors R4 and R7 of the timing circuit 15 adjust timing in response to an increase in signal propagation delay due to the resistors of the JTLs 13 and 14, and eliminate unnecessary magnetic flux traps to be described later.
[0023]
When an SFQ pulse is supplied to the inductance L1 in response to the clock T1, it flows through the resistor R1 to the Josephson junction J1. When the current flowing through the Josephson junction J1 exceeds the critical current Ic, the Josephson junction J1 enters a voltage state, and the current is switched to the basic logic gate 11 side.
[0024]
Since the resistor R1 is connected to the inductance L1, and the resistor R1 is a closed loop component, the transfer current is reduced. Therefore, in order to stably perform such SFQ pulse transmission operation, it is necessary to prevent the transfer flux to the next stage from being attenuated and the single magnetic flux quantum that is the information carrier to disappear.
[0025]
That is, the value of R must be determined so that the time constant R / L, which is the quotient of the value R of the resistor R1 and the value L of the inductance L1, is larger than the switching time Tsw of the Josephson junction. The switching time Tsw is substantially equal to the signal propagation delay time Tsp of the first stage JTL. Tsp can be expressed by approximately L · Ic / Ic · Rn, where Ic and Rn are the critical current and normal resistance of the Josephson junction, respectively.
[0026]
Here, in order to enable stable transfer of the flux quantum Ф0 to the closed loop of the next stage, L · Ic is designed to have a value of about 1/2 to ¼ of the size 単 一 0 of the single flux quantum.
[0027]
When L · Ic = Ф0 / 2, the signal propagation delay time Tsp is almost Ф0 / 2Ic · Rn. Accordingly, the condition that R should satisfy is Ф0 / 2Ic · Rn << L / R, that is, R << 2L · Ic · Rn / Ф0.
[0028]
For example, when the Josephson junction is made of Nb / AlOx / Nb and the critical current density is 2500 A / cm 2, Ic · Rn is about 0.3 mV, and when Ic = 0.25 mA, the inductance L is about 8 pH. It becomes the following value. At this time, R << 2L · Ic · Rn / Ф0 = 2.3Ω. Therefore, for example, R = 0.2Ω is determined. The DC bias current is isolated by this resistor, eliminating interference between basic logic gates.
[0029]
If the resistor R1 having such a value is inserted into a closed loop including the inductance L1 and the Josephson junction J1, the chip on which the circuit is formed is cooled and the DC bias current is not supplied before starting the operation. Even if the magnetic flux is trapped in the closed loop, the trapped magnetic flux disappears and the circuit is reset by waiting for a time sufficiently longer than the time constant L / R. Establishing can be reduced.
[0030]
The resistance is, for example, a junction resistance in which a metal or an oxide for preventing the passage of a superconducting current is joined between spaced superconductors. The material of the resistance is a material having a small specific resistance value, for example, Mo, Al, Au, Pt, Cu, Pd, Au—Pd, ITO, RuOx, or an alloy thereof.
[0031]
The same applies to other JTLs including resistors.
[0032]
In the SFQ circuit, it is necessary to make the current-voltage characteristics of the Josephson junction have no hysteresis, so a shunt resistor is connected in parallel to the Josephson junction as necessary so that the McCamber parameter is about 1. To do.
[0033]
FIG. 2 shows a case where the SFQ basic logic gate 10 is a 2-input AND gate 10A. In FIG. 2, L21 to L24 and L26 to L28 are inductances, R21 to R24 and R26 to R27 are resistors, and J21 to J28 are Josephson junctions. IN1 and IN2 are inputs, and OUT is an output.
[0034]
The JTL 13 forms a closed loop with the Josephson junction J25 of the output stage of the AND gate 10A. The logical sum of the inputs IN1 and IN2 is supplied to the closed loop as an SFQ pulse or no pulse by the pulse of the clock T.
[0035]
In the normal operation, the DC bias current IB flowing into the Josephson junction J1 does not branch to the AND gate 10A side by the resistor R1, so that the operation is stable.
[0036]
Even in a transient operation such as switching, a loss occurs due to the resistor R1, so that the influence of signal reflection to the AND gate 10A is reduced.
[0037]
Since the AND gate 10A has a more complex circuit than the JTL 13, if a resistor is inserted in each closed loop in the AND gate 10A, the operation margin is lower than that when a resistor is inserted in the JTL due to variations in element characteristics. , The non-stickiness is reduced and the cost is increased. In the present invention, since the resistor is inserted only in the JTL, such a problem is solved.
[0038]
FIG. 3 shows a case where the SFQ basic logic gate 10 is a two-input OR gate 10B. In FIG. 3, L31 to L34 and L36 to L38 are inductances, R31 to R34, R36 and R37 are resistors, and J31 to J38 are Josephson junctions. IN1 and IN2 are inputs, and OUT is an output.
[0039]
The JTL 13 forms a closed loop with the Josephson junction J37 of the output stage of the OR gate 10B, and the same operation as described above is performed in the JTL 13.
[0040]
FIG. 4 shows a case where the SFQ basic logic gate 10 is a two-input exclusive OR gate C. In FIG. 4, L41 to L44 and L47 are inductances, R41 to R44 are resistances, and J41 to J47 are Josephson junctions. IN1 and IN2 are inputs, and OUT is an output.
[0041]
The JTL 13 forms a closed loop with the Josephson junction J46 of the output stage of the exclusive OR gate 10C, and the same operation as described above is performed in the JTL 13.
[0042]
FIG. 5 shows a case where the SFQ basic logic gate 10 is a negative gate D. In FIG. 5, L51, L52 and L55 to L57 are inductances, R51, R52 and R55 to R57 are resistances, and J51 to J54 and J56 are Josephson junctions. IN is an input and OUT is an output.
[0043]
The JTL 13 forms a closed loop with the Josephson junction J54 in the output stage of the negative gate 10D, and the same operation as described above is performed in the JTL 13.
[0044]
The same applies to the SFQ basic logic gates 11 and 12.
[0045]
FIG. 6 shows the SFQ logic circuit of the first embodiment of the present invention.
[0046]
In FIG. 6, JA, J1P, JB, and J2P added to the configuration of FIG. 1 are Josephson junctions, and L1P and L2P are inductances.
[0047]
In this circuit, both JTLs 13A and 14A have two stages, and no resistor is inserted in the first stage. The first stage is a buffer circuit for steepening the blunted pulse waveform, and the purpose can be achieved more than when a resistor is inserted.
[0048]
FIG. 7 shows a case where the SFQ basic logic gate 10 is a 2-input AND gate 10A.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an SFQ logic circuit according to a first embodiment of the present invention.
2 is a diagram illustrating a circuit example in which a 2-input SFQ AND gate and a single-stage SFQJTL are connected as a configuration example of a part of FIG. 1;
3 is a diagram illustrating a circuit in which a 2-input SFQ OR gate and a single-stage SFQJTL are connected as a part of the configuration example of FIG. 1;
4 is a diagram showing, as a partial configuration example of FIG. 1, a circuit in which a 2-input SFQ exclusive OR gate and one stage of SFQJTL are connected.
FIG. 5 is a diagram illustrating a circuit in which an SFQ negation gate and one stage of SFQJTL are connected as a configuration example of a part of FIG. 1;
FIG. 6 is a schematic configuration diagram showing an SFQ logic circuit according to a second embodiment of the present invention.
FIG. 7 is a diagram showing a circuit in which a 2-input SFQ AND gate and two stages of SFQJTL are connected.
[Explanation of symbols]
10-12 SFQ basic logic gate 10A SFQ AND gate 10B SFQ OR gate 10C SFQ exclusive OR gate 10D SFQ negation gate 13, 13A, 14, 14A SFQJTL
L1-L8, L1P, L2P, L11-L14, L21-L28, L31-L38, L41-L47, L51-L57 Inductance R1-R7, R11-R14, R21-R27, R31-R37, R41-R44, R51- R57 Resistor J1-J8, JA, J1P, JB, J2B, J11-J14, J21-J28, J31-J38, J41-J47, J51-J56 Josephson junction IB DC bias current T, T1-T3 clock

Claims (5)

In a single flux quantum logic circuit in which a first single flux quantum basic logic gate is connected to a second single flux quantum basic logic gate via a Josephson transfer line,
The Josephson transfer line includes a series connection circuit of an inductance and a resistor connected between the first single flux quantum basic logic gate and the second single flux quantum basic logic gate, and one end of the Josephson transfer line connected in series A Josephson junction connected to one end of the circuit on the second single flux quantum basic logic gate side;
A bias current is supplied to one end of the Josephson junction, and a single flux quantum signal is transmitted from the first single flux quantum basic logic gate to the second single flux quantum basic logic gate.
A single magnetic flux quantum logic circuit.   The resistance value R of the resistor is determined such that a time constant L / R of a series connection circuit of the inductance having the value L and the resistor is larger than the switching time. 1. A single flux quantum logic circuit according to 1.   The resistance value R of the resistor satisfies the relational expression R << 2LIcRn / Ф0, where Ic, Rn, and Ф0 are the critical current value of the Josephson junction, the normal resistance value of the Josephson junction, and the single magnetic flux, respectively. 3. The single flux quantum logic circuit according to claim 2, wherein the single flux quantum logic circuit is a quantum value.   4. The single flux quantum logic circuit according to claim 3, wherein the resistance is a junction resistance in which a metal or an oxide is joined between spaced superconductors.   The single resistor according to claim 4, wherein the resistor is formed of a material including one selected from the group consisting of Mo, Al, Au, Pt, Cu, Pd, Au-Pd, ITO, and RuOx. One-flux quantum logic circuit.

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