JP4293028B2 - On-chip decoupling capacitor insertion method - Google Patents

Description

  The present invention relates to a method for inserting an on-chip decoupling capacitor cell into an integrated circuit such as an LSI, and an integrated circuit device that can be produced using this method.

  When designing LSIs that operate at high speeds in a fine process, an on-chip decoupling capacitor (capacitor charge / discharge function is used to absorb noise [voltage fluctuation] generated in the wiring [power supply line] connecting the power supply terminals of the LSI. Therefore, a capacitor disposed on the power supply line is required. Specifically, this is realized by arranging a large number of cells in the LSI, in which the gate of the transistor is connected to the VDD terminal and the drain is connected to the GND terminal. These cells (cells having an on-chip decoupling capacitor function and not a logical function) are called on-chip decoupling capacitor cells. The on-chip decoupling capacitor cell is mounted on the LSI by preparing and spreading the on-chip decoupling capacitor cell having a specific wiring pattern in advance before laying out the logic circuit, and by laying out the logic circuit. There is a method in which on-chip decoupling capacitor cells prepared in advance are laid in the empty area of the LSI after this.

In addition, the on-chip decoupling capacitor is obtained by calculating the amount of on-chip decoupling capacitors for each power grid, reducing the arrangement area for the required area, and correcting the placement plan for the result after the logic circuit placement. There is a technique that secures the insertion region (see, for example, Patent Document 1).
JP 2002-288253 A

The conventional method of laying on-chip decoupling capacitor cells before performing the above-described logic circuit layout tends to insert more than necessary in order to lay down the required capacitors to some extent, When the logic circuit is subsequently laid out, there is a problem that the resources (consumed memory, processing speed) of the layout tool may be deteriorated.
In addition, the conventional method of laying on-chip decoupling capacitor cells after performing the above-described logic circuit layout obtains the required capacitor amount using a power supply analysis tool based on the actual logic circuit layout. In the high area, the wiring of the on-chip decoupling capacitor cell and the wiring of the logic integrated circuit interfere with each other, so that it is not possible to place enough capacitors. There has been a problem that the chip size may be increased, for example, such as a backlash or the like, or securing an extra space around the arrangement and wiring area.

Further, in the prior art disclosed in Patent Document 1, when a critical path (path with severe delay time) is configured on a plurality of power grids, a critical path is caused by a long signal wiring extending between the power grids. There is a possibility that the delay time will be deteriorated and the performance required for the integrated circuit may not be satisfied. In this method, since the on-chip decoupling capacitor cell is inserted before the wiring process, it is possible to suppress an increase in delay time by additionally inserting a repeater between the power grids to shorten the signal wiring. is there. However, doing so requires recalculation and reinsertion of the required amount of on-chip decoupling capacitor cells due to the addition of repeaters. As a result, there is a problem that it is difficult to design to satisfy both the required amount of on-chip decoupling capacitor cells and the performance of the integrated circuit.
Therefore, the present invention solves the above problems, prevents interference between the wiring of the on-chip decoupling capacitor cell and the general wiring of the integrated circuit, and ensures a sufficient amount of capacitor while satisfying the performance of the integrated circuit. This is the issue.

According to the on-chip decoupling capacitor insertion method of the present invention, when the first on-chip decoupling capacitor cell is inserted into the integrated circuit, the wiring in the first on-chip decoupling capacitor cell and the general wiring of the integrated circuit DOO detects whether short, has a different wiring patterns from the open and shorted case, the first on-chip decoupling capacitor cell said first on-chip decoupling capacitor cell, wherein When the second on-chip decoupling capacitor cell having the same capacity as the first on-chip decoupling capacitor cell can be replaced, the first on-chip decoupling capacitor cell is replaced with the second on-chip decoupling capacitor cell. and replacing the first on-chip decoupling If the capacitor cell cannot be replaced with the second on-chip decoupling capacitor cell, the third on-chip decapacitor cell has a smaller capacity than the first on-chip decoupling capacitor cell. replaced by the decoupling capacitor cell, if not satisfied capacitor cell volume and is characterized that you insert the fourth on-chip decoupling capacitor cell to another free space.

  According to the present invention, particularly in an area where the placement and wiring density is high, interference between the wiring of the on-chip decoupling capacitor cell and the wiring of the logic integrated circuit is prevented, and a sufficient amount of capacitor is secured while satisfying the performance of the integrated circuit. It becomes possible to do. Therefore, it is possible to obtain an effect of preventing an increase in the chip size, such as a retroactive change such as changing the layout of the logic circuit so as to lower the arrangement and wiring density after the design is completed, and securing an extra space around the arrangement and wiring area. it can.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a flowchart showing a procedure of an on-chip decoupling capacitor cell insertion method according to the present invention. Next, the overall operation in the LSI layout design will be described.
In FIG. 1, first, various libraries and placement and routing information input step 101 inputs information necessary for LSI layout such as placement and routing information of LSI and physical library information. Next, a design rule input step 102 inputs a design rule for calculating the amount of on-chip decoupling capacitor cells required during the LSI layout. Next, the on-chip decoupling capacitor cell amount calculation step 103 refers to the placement and routing information input in step 101 and the design rule input in step 102, and determines the on-chip decoupling capacitor cell amount required for the LSI. calculate. For example, an on-chip decoupling capacitor cell required for each region determined by a power wiring interval (power grid) passing through the LSI vertically and horizontally by using the technique shown in the publicly known example such as Patent Document 1 is used. A quantity is calculated.

  Next, an on-chip decoupling capacitor cell adding step 104 is necessary for the vacant part in the region similarly determined by the step 103 based on the on-chip decoupling capacitor cell amount calculated in the step 103. Add on-chip decoupling capacitor cells until the quantity is met. An on-chip decoupling capacitor cell is configured by connecting a gate and a VDD (power supply) terminal and a drain and a GND (ground) terminal of a transistor arranged in the cell by a metal wiring and a contact. It has a fixed amount of wiring capacity determined by the width and length.

FIG. 2 shows an example of the wiring pattern of the on-chip decoupling capacitor cell 1.
Vertical and horizontal wirings 4 connected to the VDD terminal 2 and the GND terminal 3 in the cell 1 are constituted by a first metal layer formed on the substrate. For simplicity, description of components other than the metal layer is omitted.

  Next, in the on-chip decoupling capacitor cell replacement step 105, is the wiring 4 in the on-chip decoupling capacitor cell 1 added in step 104 short-circuited with the general signal wiring of the LSI input in step 101? If it is short-circuited, it is replaced with another on-chip decoupling capacitor cell.

FIG. 3 shows an example in which the wiring 4 in the on-chip decoupling capacitor cell 1 and the general signal wiring 5 of the LSI are short-circuited. Since the general signal wiring 5 is the same metal first layer as the wiring 4 of the cell 1, a short portion 6 where the two intersect is generated.
As the other on-chip decoupling capacitor cell, a cell having the same wiring capacity as the cell 1 and having a different wiring pattern is used.

FIG. 4 shows an example of another on-chip decoupling capacitor cell 7 having the same capacitance and different wiring patterns.
In FIG. 3, both the vertical and horizontal wirings 4 are formed of the metal first layer, but in another cell 7 shown in FIG. 4, the horizontal wiring 8 is formed of the metal first layer, and the vertical wiring 9 is A metal second layer formed on the metal first layer is formed, and the metal first layer and the metal second layer of the wirings 8 and 9 are connected via a contact 10.
FIG. 5 shows an example in which a short circuit with the general signal wiring 5 can be avoided by using the cell 7 of FIG.
Since the general signal wiring 5 is the same metal first layer as the wiring 8, a short circuit with the metal second layer wiring 9 can be avoided.

If the short circuit cannot be avoided even if the cell 7 is used, the cell 7 is replaced with another on-chip decoupling capacitor cell having a small wiring capacity (small wiring pattern).
FIG. 6 shows an example of another on-chip decoupling capacitor cell 11 having a small wiring pattern. As shown in the figure, the horizontal wiring 12 is composed of a first metal layer, and the vertical wiring 13 is composed of a second metal layer.
FIG. 7 shows an example in which a short circuit with the general signal wiring 5 can be avoided in the cell 11 of FIG. In the figure, two general signal wirings 5 in the first metal layer are connected via a wiring 14 in the second metal layer and a contact 10.

Since the cell 11 has a small wiring pattern and a small amount of capacitor, it can be considered that the required amount of on-chip decoupling capacitor cell cannot be satisfied by replacing the cell 11 with the cell 1. In that case, the process returns to step 104, and this operation is repeated until there is no short circuit while inserting the on-chip decoupling capacitor cell 11 in another empty area.
Next, the placement and routing information output step 106 outputs the placement and routing information of the LSI to which the on-chip capacitor cell is added by the above processing.

  According to the present embodiment, when an on-chip decoupling capacitor cell is inserted into an LSI, it is detected whether the wiring in the on-chip decoupling capacitor cell is short-circuited with the existing LSI wiring. If so, replace it with another on-chip decoupling capacitor cell with a different wiring pattern, and insert the on-chip decoupling capacitor cell obtained based on the actual placement and routing results while suppressing changes in the placement and routing results. Therefore, it is possible to prevent the interference between the wiring of the on-chip decoupling capacitor and the wiring of the logic integrated circuit, and to arrange a sufficient amount of the capacitor while satisfying the performance of the integrated circuit, in an area where the arrangement wiring density is high. Become. Therefore, it is possible to obtain an effect of preventing an increase in the chip size, such as a retroactive change such as changing the layout of the logic circuit so as to lower the arrangement and wiring density after the design is completed, and securing an extra space around the arrangement and wiring area. it can.

4 is a flowchart showing a procedure of an on-chip decoupling capacitor insertion method according to an embodiment of the present invention. It is a block diagram which shows the example of the wiring pattern of an on-chip decoupling capacitor cell. It is a block diagram which shows the example which the wiring of the on-chip decoupling capacitor cell and the general signal wiring short-circuited. It is a block diagram which shows the example of the wiring pattern of another on-chip decoupling capacitor cell. It is a block diagram which shows the example which avoided the short circuit with the wiring of another on-chip decoupling capacitor cell, and a general signal wiring. It is a block diagram which shows the other example of the wiring pattern of another on-chip decoupling capacitor cell. It is a block diagram which shows the other example which avoided the short circuit with the wiring of other on-chip decoupling capacitor cells, and a general signal wiring.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 On-chip decoupling capacitor cell 2 VDD terminal 3 GND terminal 5 General signal wiring 6 Short location 7, 11 Other on-chip decoupling capacitor cell 8, 12 Horizontal wiring 9, 13 Vertical wiring 10 Contact 14 General signal wiring Wiring to connect

Claims (3)

Detecting whether or not the wiring in the first on-chip decoupling capacitor cell and the general wiring of the integrated circuit are short-circuited when the first on-chip decoupling capacitor cell is inserted into the integrated circuit; If you are short-circuited,
The first on-chip decoupling capacitor cell has a wiring pattern different from that of the first on-chip decoupling capacitor cell, and a second on-chip decoupling having the same capacity as the first on-chip decoupling capacitor cell. If replaceable with a ring capacitor cell, replace the first on-chip decoupling capacitor cell with the second on-chip decoupling capacitor cell;
When the first on-chip decoupling capacitor cell cannot be replaced with the second on-chip decoupling capacitor cell, the first on-chip decoupling capacitor cell is replaced with the first on-chip decoupling capacitor cell. Replace with a third on-chip decoupling capacitor cell of smaller capacity,
An on-chip decoupling capacitor insertion method comprising inserting a fourth on-chip decoupling capacitor cell in another empty area when the amount of capacitor cells cannot be satisfied.   The second on-chip decoupling capacitor cell has a wiring pattern in which a metal first layer and a metal second layer thereon are connected via a contact, and the general wiring is composed of the metal first layer. The method of inserting an on-chip decoupling capacitor according to claim 1. In the third on-chip decoupling capacitor cell, the first metal layer and the second metal layer thereon are connected via a contact, and the wiring is smaller than the wiring pattern of the first on-chip decoupling capacitor cell. 2. The on-chip decoupling capacitor insertion method according to claim 1, further comprising a pattern, wherein the general wiring is made of the first metal layer.

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