JP4272547B2 - Field effect transistor and integrated circuit device and switch circuit using the same - Google Patents

Description

  The present invention relates to a field effect transistor, an integrated circuit device using the same, and a switch circuit, and more particularly to a field effect transistor used in a high frequency communication device or a switch circuit.

  In a high-frequency communication device typified by a cellular phone, a modulation doped field effect transistor (MODFET) using an electron supply layer doped with an n-type impurity on an undoped channel layer is widely used. ing.

  Conventionally, indium gallium arsenide (InGaAs) having a high electron mobility is used for the channel layer of the MODFET, and aluminum gallium arsenide (AlGaAs), which is a material having a band gap larger than that of InGaAs, is used for the electron supply layer. ing.

  However, since AlGaAs is a material having a high interface state density, it becomes difficult to increase the current density of the MODFET by trapping electrons in the interface state. Specifically, the interface state formed on the surface of the electron supply layer functions as a trap that captures electrons and holds the electrons on the surface of the electron supply layer, and the negative charges of the electrons captured by the traps are in the channel region. Narrow the depletion layer. As a result of the phenomenon that the depletion layer is constricted, so-called frequency dispersion of the drain current occurs in which the maximum current density when a high-frequency signal is applied to the gate is significantly reduced as compared with the case where a direct current is applied.

  To solve this problem, by using indium gallium phosphide (InGaP) instead of AlGaAs as the material constituting the electron supply layer, traps generated in the electron supply layer are reduced, and the current density of the field effect transistor is reduced. Increase is possible (see, for example, Patent Document 1).

FIG. 7 shows a conventional MODFET cross-sectional configuration using InGaP for the electron supply layer. As shown in FIG. 7, on a compound semiconductor substrate 101 made of GaAs, a buffer layer 102 made of undoped GaAs, a barrier layer 103 made of AlGaAs doped with an n-type impurity, and an undoped In _0.2 Ga _0.8. A channel layer 104 made of As, an electron supply layer 105 made of InGaP doped with an n-type impurity, and a cap layer made of GaAs formed with an opening exposing the electron supply layer 105 and doped with an n-type impurity 107 are sequentially stacked. A gate electrode 108 is formed on the electron supply layer 105 exposed in the opening of the cap layer 107 by a Schottky junction. A source electrode 109 and a drain electrode 110 are formed on the cap layer 107.

  Since InGaP is a material having a lower interface state density than AlGaAs, the interface state of the electron supply layer 105 exposed at the opening of the cap layer 107 can be reduced. The maximum current density can be increased.

  By the way, in a conventional MODFET, when a semiconductor layer (InGaP layer) made of InGaP is crystal-grown by a generally used method for manufacturing a compound semiconductor, Ga atoms and In atoms are alternately arranged in the same plane in the group III atomic layer. A natural superlattice arranged in the order is formed.

In recent years, for example, as described in Patent Document 2, a method of forming an InGaP layer in which the natural superlattice structure is destroyed and the arrangement of Ga atoms and In atoms in the group III atomic layer is disordered is known. In addition, field effect transistors have been developed in which the interface resistance between the InGaP layer and another semiconductor layer is reduced by destroying such a natural superlattice and using InGaP.
Japanese Unexamined Patent Publication No. 63-228763 (FIG. 3) JP-A-11-243058

  However, according to the conventional MODFET, since the gate electrode 108 is formed by a Schottky junction with the electron supply layer 105 made of InGaP, the reverse breakdown voltage of the gate electrode 108 with respect to the drain electrode 110 is increased in the electron supply layer 105. It is experimentally known that it is lower than when AlGaAs is used.

  As described above, when the conventional MODFET uses InGaP to improve the maximum current density at the time of applying a high-frequency signal, the gate breakdown voltage is reduced due to material restrictions of InGaP. There is a problem that it is difficult to achieve both improvement in gate breakdown voltage.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described conventional problems, and to make it possible to achieve both improvement in maximum current density and improvement in gate breakdown voltage in a field effect transistor.

  In order to achieve the above object, the present invention is configured such that an InGaP layer having a natural superlattice destroyed and having a thickness of a predetermined value or less is provided on the Schottky layer.

  Specifically, a field effect transistor according to the present invention is formed on a first compound semiconductor layer (channel layer) in which carriers travel and a first compound semiconductor layer, and carriers are transferred to the first compound semiconductor layer. Formed on the second compound semiconductor layer (carrier supply layer) to be supplied, the third compound semiconductor layer (Schottky layer) formed on the second compound semiconductor layer, and the third compound semiconductor layer The third compound semiconductor layer is provided with a gate electrode that forms a Schottky junction, and the third compound semiconductor layer has a phosphation in which a natural superlattice is destroyed at least on the upper side and the thickness is set to a predetermined value or less. Indium gallium is included.

  According to the field effect transistor of the present invention, since the third compound semiconductor layer includes indium gallium phosphide (InGaP) in which the natural superlattice is broken at least above, the interface state in the third compound semiconductor layer The maximum current density can be improved by reducing the density. In addition, since the thickness of indium gallium phosphide contained in the third compound semiconductor layer is set to a predetermined value or less, the breakdown voltage of the gate electrode is improved. This is because, when indium gallium phosphide whose natural superlattice structure is destroyed is used on the third compound semiconductor layer, indium gallium phosphide whose natural superlattice structure is destroyed is used on the third compound semiconductor layer. Based on the knowledge of the inventors of the present application that the breakdown voltage of the gate electrode first increases rapidly and then gradually decreases as the thickness of indium gallium phosphide is increased from the state that is not included. Therefore, by setting the thickness of the indium gallium phosphide included in the upper portion of the third compound semiconductor layer and having a destroyed natural superlattice structure to a predetermined value or less, the breakdown voltage of the gate electrode is reduced to the third compound semiconductor layer. As compared with the case where indium gallium phosphide whose natural superlattice structure is broken is not formed on the upper portion of the GaN, the breakdown voltage is increased.

  In the field effect transistor of the present invention, the thickness of the indium gallium phosphide contained in the third compound semiconductor layer is preferably 8 nm or less. In this case, the breakdown voltage of the gate electrode is surely increased as compared with the configuration in which the third compound semiconductor layer does not include indium gallium phosphide.

  In the field effect transistor of the present invention, when indium gallium phosphide is included only in the upper part of the third compound semiconductor layer, the lower part of the third compound semiconductor layer is preferably made of aluminum gallium arsenide.

  In the field effect transistor of the present invention, the second compound semiconductor layer is preferably made of aluminum gallium arsenide.

  The field effect transistor of the present invention preferably further includes a protective film made of a low dielectric constant material formed on the third compound semiconductor layer so as to cover the gate electrode. In this way, the third compound semiconductor layer and the gate electrode are covered with the protective film having a low dielectric constant, so that the parasitic capacitance of the gate electrode can be reduced. In addition, since at least the upper part of the third compound semiconductor layer is made of InGaP, which is a material that is difficult to oxidize, reliability is not lowered even when a low dielectric constant material is used.

  In the field effect transistor of the present invention, the low dielectric constant material is preferably benzocyclobutene.

An integrated circuit device according to the present invention is directed to an integrated circuit device in which a field effect transistor and a passive element electrically connected to the field effect transistor are formed on a substrate. On the first compound semiconductor layer, the second compound semiconductor layer formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer, and on the second compound semiconductor layer A third compound semiconductor layer formed on the third compound semiconductor layer and a gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer. At least an upper portion thereof includes indium gallium phosphide in which the natural superlattice is broken and the thickness is set to a predetermined value or less.

  According to the integrated circuit device of the present invention, the field effect transistor according to the present invention is used as the field effect transistor, and the field effect transistor according to the present invention and the passive element are integrated on one substrate. Since the improvement of the maximum current density and the improvement of the breakdown voltage of the gate electrode can be realized simultaneously in the field effect transistor, the circuit characteristics can be drastically improved.

  A first switch circuit according to the present invention includes a field effect transistor having a gate electrode, a drain electrode, and a source electrode, the drain electrode and the source electrode serving as input / output terminals, one end connected to the gate electrode, and the other end A field effect transistor is intended for a switch circuit including a resistance element serving as a control terminal. The field-effect transistor is formed on a first compound semiconductor layer in which carriers travel, and on the first compound semiconductor layer. A second compound semiconductor layer for supplying carriers to the semiconductor layer; a third compound semiconductor layer formed on the second compound semiconductor layer; and a third compound semiconductor layer formed on the third compound semiconductor layer, The third compound semiconductor layer has a compound semiconductor layer and a gate electrode that forms a Schottky junction, and the third compound semiconductor layer has a natural superlattice broken at least on its top and a thickness set to a predetermined value or less. Including the emissions indium gallium.

  Each of the second switch circuits according to the present invention includes a field effect transistor having a gate electrode, a drain electrode, and a source electrode, the drain electrode and the source electrode serving as input / output terminals, Each of the field effect transistors includes a first compound semiconductor layer in which carriers run, a first compound semiconductor layer, and a first compound semiconductor layer that is electrically connected to each other. A second compound semiconductor layer formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer; a third compound semiconductor layer formed on the second compound semiconductor layer; 3 having a gate electrode that forms a Schottky junction with the third compound semiconductor layer, and the third compound semiconductor layer has a natural superlattice at least on the top thereof. Destroyed and thickness comprises indium gallium phosphide which is set to a predetermined value or less.

  According to the first and second switch circuits, since the field effect transistor according to the present invention is used, a failure (burst failure) that cannot be sufficiently switched from the off state to the on state can be prevented. Switch characteristics can be obtained.

  According to the field effect transistor of the present invention, the interface state density of the Schottky layer is reduced to improve the maximum current density when a high frequency signal is applied, and the natural superlattice included above the Schottky layer is destroyed. Since the thickness of indium gallium phosphide is set to a predetermined value or less, the reverse breakdown voltage of the Schottky electrode is improved.

  Furthermore, by applying the field effect transistor according to the present invention to a switch circuit, a burst failure in the switch circuit can be prevented.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a field effect transistor according to a first embodiment of the present invention. As shown in FIG. 1, on a compound semiconductor substrate 11 made of gallium arsenide (GaAs), for example, a buffer layer 12 made of aluminum gallium arsenide (AlGaAs) having a thickness of about 500 nm and a thickness of about 100 nm. A barrier layer 13 made of n-type AlGaAs, a channel layer 14 made of undoped indium gallium arsenide (InGaAs) with a thickness of about 15 nm, a carrier supply layer 15 made of n-type AlGaAs with a thickness of about 20 nm, a thickness The Schottky layer 16 is made of undoped indium gallium phosphide (InGaP) with a thickness of about 5 nm, the natural superlattice in InGaP is broken, and the GaAs is doped with n-type impurities with a thickness of about 100 nm. A cap layer 17 having an opening exposing a part of the layer 16 is sequentially laminated. That.

  Here, InGaP in which the natural superlattice is destroyed means InGaP having a crystal structure in which Ga atoms and In atoms are irregularly arranged in the group III atomic layer.

  In general, when an InGaP layer is formed by crystal growth, a natural superlattice in which Ga layers and In layers are alternately arranged in a group III atomic layer is formed. However, by growing an InGaP layer at a low temperature, the natural superlattice is formed. Can be formed. In the following description, InGaP in which such a natural superlattice is broken is referred to as disordered (Disordered) InGaP.

  On the Schottky layer 16 exposed in the opening of the cap layer 17, a gate electrode 18 that forms a Schottky junction with the Schottky layer 16 is formed by a laminated film (Ti / Al) of titanium and aluminum. On the cap layer 17, a source electrode 19 and a drain electrode 20 made of a gold germanium (AuGe) alloy are formed as ohmic electrodes, respectively.

  The material constituting the gate electrode 18 is not limited to Ti / Al, and any material that forms a Schottky junction with the Schottky layer 16 may be used. For example, a laminated film (Ti / Ti / Ti / Ti) may be used. Pt / Au) or tungsten silicide (WSi) can be used.

  The material constituting the cap layer 17 is not limited to GaAs, and for example, InGaAs may be used. When InGaAs is used as the material constituting the cap layer 17, Ti / Pt / Au can be used as the material constituting the source electrode 19 and the drain electrode 20 in place of the AuGe-based alloy.

As a specific composition of each semiconductor layer in the field effect transistor according to the first embodiment, for example, In _0.2 Ga _0.8 As is used for InGaAs constituting the channel layer 14, and AlGaAs constituting the carrier supply layer 15 is used. Al _0.2 Ga _0.8 As is used, and In _0.5 Ga _0.5 P is used for InGaP constituting the Schottky layer 16. The carrier supply layer 15 is planarly doped with silicon (Si) having a doping concentration of about 4 × 10 ¹² cm ⁻³ .

  In the first embodiment, the entire Schottky layer 16 having a thickness of 5 nm is made of disordered InGaP, but is not limited thereto. For example, when the thickness of disordered InGaP is set to 3 nm, the remaining 2 nm is formed of AlGaAs. In addition, when the thickness of disordered InGaP is set to 7 nm, carrier supply is performed so as not to change the distance between the channel layer 14 and the gate electrode 18, which is a parameter for determining the threshold voltage Vth of the transistor. It is necessary to reduce the thickness of the layer 15 by 2 nm.

  In the field effect transistor according to the first embodiment, since the Schottky layer 16 made of InGaP is provided on the carrier supply layer 15 made of AlGaAs, the interface state density of the Schottky layer 16 is reduced. Therefore, frequency dispersion can be suppressed. As a result, even when a high frequency signal is applied to the gate electrode 18, a high maximum current density can be realized.

  Furthermore, as a feature of the first embodiment, disordered InGaP having a thickness of more than 0 nm and not more than 10 nm, here 5 nm, is formed on the upper part of the Schottky layer 16. An improvement in reverse breakdown voltage is realized. Here, the reverse breakdown voltage of the gate electrode 18 refers to a breakdown voltage against a negative voltage applied to the gate electrode 18 between the gate electrode 18 and the drain electrode 20.

  Hereinafter, the relationship between the thickness of the Schottky layer 16 and the reverse breakdown voltage of the gate electrode 18 will be described with reference to the drawings.

  FIG. 2 shows the relationship between the thickness of InGaP included in the upper part of the Schottky layer 16 and the reverse breakdown voltage of the gate electrode 18 in the field effect transistor according to the first embodiment based on experiments. In FIG. 2, the horizontal axis represents the thickness of InGaP included in the upper part of the Schottky layer 16, and the vertical axis represents the reverse breakdown voltage of the gate electrode 18. Here, for example, when the thickness of InGaP in the Schottky layer 16 is 0 nm, the Schottky layer 16 is made of AlGaAs bulk, and when the thickness of InGaP is 10 nm, the Schottky layer 16 The upper part includes InGaP having a thickness of 10 nm, and the remainder is made of AlGaAs. A solid line indicates the field effect transistor according to the first embodiment in which disordered arrangement InGaP is used for InGaP included in the upper part of the Schottky layer 16, and a broken line is for comparison and included in the upper part of the Schottky layer 16. The case where InGaP having a natural superlattice structure is used for InGaP is shown.

  As shown in FIG. 2, when the thickness of InGaP included in the upper part of the Schottky layer 16 is 0 nm, that is, when the Schottky layer 16 is entirely formed of AlGaAs, the reverse breakdown voltage is about 12V.

  As shown by a solid line in FIG. 2, in the configuration according to the first embodiment in which disordered arrangement of InGaP is included in the upper part of the Schottky layer 16, when the thickness of InGaP in the Schottky layer 16 increases to about 2 nm, As the reverse breakdown voltage suddenly increases and then the InGaP thickness increases, the reverse breakdown voltage gradually decreases. When the thickness of InGaP exceeds about 8 nm, the reverse breakdown voltage becomes less than about 12V. Get smaller.

  On the other hand, when the natural superlattice InGaP is included in the upper part of the Schottky layer 16 as shown by a broken line in FIG. 2, the reverse breakdown voltage sharply increases when the thickness of the natural superlattice InGaP increases to about 2 nm. Thereafter, the reverse breakdown voltage hardly changes even when the thickness of InGaP of the natural superlattice increases.

  As apparent from FIG. 2, in the first embodiment in which disordered arrangement of InGaP is included in the upper part of the Schottky layer 16, the reverse breakdown voltage of the gate electrode 18 is such that the gate electrode 18 is made of AlGaAs. There is a disordered InGaP thickness that increases the reverse breakdown voltage of the gate electrode 18 as compared to the case where the gate electrode 18 is formed on the top. Specifically, when the thickness of the disordered InGaP included in the upper part of the Schottky layer 16 is 10 nm or less, more preferably 8 nm or less, the reverse breakdown voltage of the gate electrode 18 on the Schottky layer 16 made of AlGaAs is increased. It becomes larger than the case where it is formed.

  On the other hand, when InGaP having a natural superlattice structure is included in the upper portion of the Schottky layer 16, the reverse breakdown voltage increases as compared with the case where the gate electrode 18 is formed on the Schottky layer 16 made of AlGaAs. There is nothing.

  As described above, the disordered arrangement of InGaP having a thickness greater than 0 nm and not greater than 8 nm is included in the upper portion of the Schottky layer 16, so that the reverse breakdown voltage is increased so that the gate electrode 18 is placed on the Schottky layer 16 made of AlGaAs. It becomes larger than the case where it forms.

In the first embodiment, Al _0.2 Ga _0.8 As is used for AlGaAs constituting the carrier supply layer 15 and In _0.5 Ga _0.5 P is used for InGaP included in the upper part of the Schottky layer 16. Even when the composition and impurity concentration of each semiconductor layer are changed, the reverse breakdown voltage of the gate electrode 18 is larger than that in the case where the gate electrode 18 is formed on the Schottky layer 16 made of AlGaAs. It is possible to set the thickness of InGaP.

  That is, even when the composition and impurity concentration of each semiconductor layer are changed, the reverse breakdown voltage of the gate electrode 18 first increases sharply as the thickness of InGaP included in the upper part of the Schottky layer 16 is increased. After that, when the thickness of InGaP included in the upper part of the Schottky layer 16 becomes larger than a predetermined value, the reverse breakdown voltage becomes smaller than the reverse breakdown voltage when InGaP is not included. Therefore, the thickness of InGaP included in the upper portion of the Schottky layer 16 is a predetermined value, that is, the thickness when the reverse breakdown voltage is the same as the reverse breakdown voltage when InGaP is not included in the upper portion of the Schottky layer 16. Accordingly, the reverse breakdown voltage of the gate electrode 18 becomes larger than that when the gate electrode 18 is formed on the Schottky layer 16 made of AlGaAs.

  As described above, according to the first embodiment, disordered InGaP in which the natural superlattice is broken is included in at least the upper part of the Schottky layer 16, and the thickness of the InGaP layer is set to a predetermined value or less. As a result, it is possible to improve both the maximum current density and the reverse breakdown voltage.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 shows a cross-sectional configuration of a field effect transistor according to the second embodiment of the present invention. In FIG. 3, the same components as those in FIG.

  As shown in FIG. 3, a buffer layer 12, a barrier layer 13, a channel layer 14, a carrier supply layer 15, a Schottky layer 16, and a cap layer 107 are sequentially stacked on the compound semiconductor substrate 11. A gate electrode 18 as a Schottky electrode is formed on the Schottky layer 16 exposed in the recess opening of the cap layer 17, and an ohmic electrode is formed on the cap layer 17 sandwiched on both sides of the gate electrode 18. A source electrode 19 and a drain electrode 20 are respectively formed.

  A protective film 21 made of benzocyclobutene (BCB) is provided on the cap layer 17 over the entire surface including the gate electrode 18, the source electrode 19, and the drain electrode 20.

  The material constituting the protective film 21 is not limited to BCB. For example, SLK (aromatic hydrocarbon polymer of Dow Chemical Company), FSG (silicon glass to which fluorine is added), porous silicon, organic siloxane or the like SOG ( A low dielectric constant material (so-called low-k material) such as spin on glass can be used.

  In general, silicon nitride (SiN) having excellent moisture resistance is used as a material for the protective film 21 covering the Schottky layer 16. On the other hand, in the second embodiment, since the Schottky layer 16 is made of InGaP, which is a material that is not easily oxidized, it is not necessary to use a material having excellent moisture resistance.

  That is, according to the second embodiment, since the reliability of the field effect transistor does not decrease even if the SiN film is not formed on the Schottky layer 16, a low dielectric constant material having a relative dielectric constant smaller than that of SiN is used. Since the protective film 21 can be formed using this, the parasitic capacitance of the field effect transistor can be reduced.

  Further, in the second embodiment, as in the first embodiment, the Schottky layer 16 is made of disordered InGaP and has a thickness of 10 nm or less. Therefore, the Schottky layer made of AlGaAs is used. A field effect transistor is realized in which the reverse breakdown voltage of the gate electrode 18 is improved as compared with the case where the gate electrode 18 is formed thereon. Thereby, in the field effect transistor using InGaP for the Schottky layer 16, it is possible to achieve both the improvement of the maximum current density and the improvement of the gate breakdown voltage.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a cross-sectional structure of an integrated circuit device according to the third embodiment of the present invention. As shown in FIG. 4, an epitaxial layer 31 made of a compound semiconductor is formed by crystal growth on a compound semiconductor substrate 30 made of, for example, GaAs.

  A field effect transistor having the same configuration as the field effect transistor according to the first embodiment is formed in a region indicated by reference numeral 32 on the substrate 30 and the epitaxial layer 31. On the substrate 30, the resistance element 33 and the capacitive element 34 are integrated to form an MMIC (monolithic microwave integrated circuit).

  The resistance element 33 is made of, for example, polysilicon (PS), tungsten silicide nitride (WSiN), or nickel chrome (NiCr). Here, WSiN or NiCr is particularly preferable. The capacitive element 34 includes, for example, a lower electrode 34a and an upper electrode 34c made of platinum (Pt), and a capacitive insulating film 34b made of, for example, silicon nitride (SiN) sandwiched therebetween.

  As shown in FIG. 4, the drain electrode 20 of the field effect transistor 32 is electrically connected to one terminal of the resistance element 33 by a metal wiring 36 formed on the interlayer insulating film 35. The other terminal of the element 33 is electrically connected to the lower electrode 34 a of the capacitive element 34 by a metal wiring 36.

  As described in the first embodiment, the field effect transistor 32 can realize both the improvement of the maximum current density and the improvement of the gate breakdown voltage, so that the power characteristic determined by the product of the maximum current density and the breakdown voltage can be obtained. It becomes possible to improve.

  Therefore, the MMIC in which the field effect transistor 32, the resistance element 33, and the capacitance element 34 are integrated can realize a switch circuit having excellent electrical characteristics.

  Needless to say, the integrated circuit according to the third embodiment has excellent electrical characteristics even when applied to a power amplifier.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows a configuration of a switch circuit according to the fourth embodiment of the present invention. As shown in FIG. 5, the switch circuit 40 includes a field effect transistor 41 having the same configuration as that of the first embodiment, and a resistance element 42 connected to the gate electrode of the field effect transistor. Yes.

A terminal on the opposite side of the gate electrode in the resistance element 42 is connected to a control terminal 43 to which a DC voltage (DC bias) is applied.

  The source electrode of the field effect transistor 40 is connected to the high-frequency signal input terminal 44, and the drain electrode is connected to the output terminal 45.

  With this configuration, as is well known, when a control voltage higher than the threshold voltage Vth set in the field effect transistor 41 is applied to the control terminal 43, the high-frequency signal input from the input terminal 44 is output to the output terminal. On the contrary, when a control voltage lower than the threshold voltage Vth is applied, the high frequency signal input from the input terminal 44 can be prevented from being output.

  At this time, the field effect transistor 41 according to the fourth embodiment includes a disordered arrangement of InGaP at least above the Schottky layer, so that the maximum current density is improved. Therefore, the frequency dispersion of the drain current is suppressed. Is done. As a result, switching failure (burst failure) that occurs when the switch is switched from the off state to the on state can be suppressed.

  Furthermore, in order to increase the maximum power, which is an important characteristic of the switch circuit, it is important to make the threshold voltage Vth of the field effect transistor 41 shallow (small in absolute value). When the voltage Vth is shallow, there is a problem that a burst failure occurs.

  However, when the switch circuit 40 according to the fourth embodiment is used, the gate breakdown voltage is improved because the thickness of the disordered InGaP included in the upper part of the Schottky layer is set to 8 nm or less. . Therefore, even when the threshold voltage Vth is designed to be shallow, burst failure can be reliably prevented, so that the switch circuit 40 can perform switching of extremely large high-frequency power.

(One Modification of Fourth Embodiment)
Hereinafter, a modification of the fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows a configuration of a switch circuit according to a modification of the fourth embodiment of the present invention. In FIG. 6, the same components as those shown in FIG. As shown in FIG. 5, the switch circuit 50 includes a first switch circuit 40A and a second switch circuit 40B, and the second switch circuit 4 0 B is connected to the output terminal 45 of the first switch circuit 40A. A shunt is connected to the ground 46.

  In the switch circuit 50, a control voltage higher than the threshold voltage Vth of the field effect transistor 42 is applied to the first control terminal 43A of the first switch circuit 40A, and the second switch circuit 40B has a second control voltage. By applying a control voltage lower than the threshold voltage Vth of the field effect transistor 42 to the second control terminal 43B, the high frequency signal input to the input terminal 44 is transmitted to the output terminal 45, and the switch circuit 50 Is turned on.

On the contrary, a control voltage lower than the threshold voltage Vth of the field effect transistor 42 is applied to the first control terminal 43A of the first switch circuit 40A, and the second switch circuit 40B By applying a control voltage higher than the threshold voltage Vth of the field effect transistor 41 to the second control terminal 43B, the high frequency signal input to the input terminal 44 is not transmitted to the output terminal 45, and the switch The circuit 50 is turned off.

Thus, when controlling the ON state and the OFF state of the switch circuit 50 by the control voltage applied to each control terminal 43A, 43B, the field effect having the same configuration as the field effect transistor according to the first embodiment. Since the type transistor 41 is used, a burst failure due to the frequency dispersion of the drain current can be prevented, so that the two sets of the field effect transistors 41 can be reliably switched between the on state and the off state. As a result, extremely good switch characteristics can be realized.

  A so-called SPDT (Single-Pole Double-Throw) with one input and two outputs or a DPDT (Double-Pole with two inputs and two outputs), which can be realized by connecting a plurality of switch circuits 40 described in the fourth embodiment. Needless to say, the present invention can be applied to a wide variety of switching circuits such as Double-Throw.

  The field effect transistor according to the present invention and the integrated circuit device and the switch circuit using the same improve the reverse breakdown voltage of the Schottky electrode, and further apply the field effect transistor according to the present invention to the switch circuit. It has the effect of preventing burst defects in the switch circuit, and is useful in the field of high-frequency communication equipment or switch circuits.

1 is a configuration cross-sectional view illustrating a field effect transistor according to a first embodiment of the present invention. It is a graph which shows the relationship between the thickness of the Schottky layer in a field effect transistor, and gate breakdown voltage. It is a structure sectional view showing a field effect type transistor concerning a 2nd embodiment of the present invention. It is a structure sectional view showing an integrated circuit device concerning a 3rd embodiment of the present invention. It is a circuit diagram which shows the switch circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the switch circuit which concerns on the modification of the 4th Embodiment of this invention. It is a structure sectional view showing a conventional field effect transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Compound semiconductor substrate 12 Buffer layer 13 Barrier layer 14 Channel layer 15 Carrier supply layer 16 Schottky layer 17 Cap layer 18 Gate electrode 19 Source electrode 20 Drain electrode 21 Protective film 30 Compound semiconductor substrate 31 Epitaxial layer 32 Field effect transistor 33 Resistance Element 34 Capacitor 34a Lower electrode 34b Capacitor insulating film 34c Upper electrode 35 Interlayer insulating film 36 Metal wiring 40 Switch circuit 40A First switch circuit 40B Second switch circuit 41 Field effect transistor 42 Resistive element 43 Control terminal 43A First Control terminal 43B second control terminal 44 input terminal 45 output terminal 46 ground 50 switch circuit

Claims (8)

A first compound semiconductor layer in which a carrier travels;
A second compound semiconductor layer made of aluminum gallium arsenide formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer;
A third compound semiconductor layer made of disordered indium gallium phosphide formed on the second compound semiconductor layer;
A gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer;
The third compound semiconductor layer state, and are less thick Saga 5 nm,
The field effect transistor , wherein the third compound semiconductor layer is provided so that a reverse breakdown voltage of the gate electrode is increased as compared with a case where the third compound semiconductor layer is not formed . A first compound semiconductor layer in which a carrier travels;
A second compound semiconductor layer formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer;
A third compound semiconductor layer formed on the second compound semiconductor layer;
A gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer;
The third compound semiconductor layer includes disordered indium gallium phosphide having a thickness of 5 nm or less on at least an upper portion thereof,
When the indium gallium phosphide is contained only in the upper portion of the third compound semiconductor layer, a lower portion of the third compound semiconductor layer is Ri Do from aluminum gallium arsenide,
The indium gallium phosphide, the comparison with the case of not forming the indium gallium phosphide, the reverse breakdown voltage becomes large so provided have to that electric field-effect transistor, wherein Rukoto gate electrode. The field effect transistor according to claim 2 , wherein the second compound semiconductor layer is made of aluminum gallium arsenide.   4. The semiconductor device according to claim 1, further comprising a protective film made of a low dielectric constant material formed on the third compound semiconductor layer so as to cover the gate electrode. The field effect transistor described in 1.   The field effect transistor according to claim 4, wherein the low dielectric constant material is benzocyclobutene. An integrated circuit device in which a field effect transistor and a passive element electrically connected to the field effect transistor are formed on a substrate,
The field effect transistor is:
A first compound semiconductor layer in which a carrier travels;
A second compound semiconductor layer made of aluminum gallium arsenide formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer;
A third compound semiconductor layer made of disordered indium gallium phosphide formed on the second compound semiconductor layer;
A gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer;
The third compound semiconductor layer state, and are less thick Saga 5 nm,
The integrated circuit device , wherein the third compound semiconductor layer is provided so that a reverse breakdown voltage of the gate electrode is increased as compared with a case where the third compound semiconductor layer is not formed . A field effect transistor having a gate electrode, a drain electrode, and a source electrode, wherein the drain electrode and the source electrode serve as input / output terminals; and a resistance element having one end connected to the gate electrode and the other end serving as a control terminal A switch circuit comprising:
The field effect transistor is:
A first compound semiconductor layer in which a carrier travels;
A second compound semiconductor layer made of aluminum gallium arsenide formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer;
A third compound semiconductor layer made of disordered indium gallium phosphide formed on the second compound semiconductor layer;
A gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer;
The third compound semiconductor layer state, and are less thick Saga 5 nm,
The switch circuit , wherein the third compound semiconductor layer is provided so that a reverse breakdown voltage of the gate electrode is increased as compared with a case where the third compound semiconductor layer is not formed . Each has a gate electrode, a drain electrode, and a source electrode, the drain electrode and the source electrode serve as input / output terminals, and a resistor having one end connected to the gate electrode and the other end serving as a control terminal A plurality of switch circuits electrically connected to each other,
Each of the field effect transistors is
A first compound semiconductor layer in which a carrier travels;
A second compound semiconductor layer made of aluminum gallium arsenide formed on the first compound semiconductor layer and supplying carriers to the first compound semiconductor layer;
A third compound semiconductor layer made of disordered indium gallium phosphide formed on the second compound semiconductor layer;
A gate electrode formed on the third compound semiconductor layer and having a Schottky junction with the third compound semiconductor layer;
The third compound semiconductor layer state, and are less thick Saga 5 nm,
The switch circuit , wherein the third compound semiconductor layer is provided so that a reverse breakdown voltage of the gate electrode is increased as compared with a case where the third compound semiconductor layer is not formed .

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