JP4271206B2 - Semiconductor integrated circuit and design / manufacturing method thereof - Google Patents

Description

  The present invention relates to a general-purpose logic module and an ASIC using the same, and more particularly to a technique for configuring an on-chip capacitor while preventing the occurrence of off-leakage current.

  Conventionally, general-purpose logic modules such as a general field programmable gate array (FPGA) and a mask programmable functional block-based gate array are known.

  This general-purpose logic module forms a basic circuit called a general-purpose logic cell in an array by electrically connecting MOS transistors formed on a semiconductor substrate with a wiring layer of m layers (m is an integer of 1 or more). Based on this, the above-mentioned general-purpose logic cell is electrically connected by an n-layer (n is an integer of 1 or more) wiring layer to form an ASIC (Application Specific Integrated Circuit) in which a desired logic circuit is incorporated. This is a semiconductor device that can be made. The basic circuit is generally composed of a logic circuit having a small function such as an inverter circuit, a NAND circuit, a NOR circuit, or a multiplexer.

  By using this general-purpose logic module, the n-layer wiring pattern is designed so as to realize a desired logic circuit, and a lithography mask on which the wiring pattern is baked is used as a base wired up to the m-th layer. A semiconductor chip on which a desired logic circuit is formed is obtained by a semiconductor manufacturing process in which a wiring layer is formed on a semiconductor substrate.

  This general-purpose logic module is used as follows. For example, the semiconductor manufacturer discloses information on the semiconductor substrate formed up to the m-th layer to the user. The user designs a desired logic circuit based on the disclosed information, and requests a semiconductor manufacturer to manufacture a semiconductor chip for realizing the logic circuit. A semiconductor manufacturer automatically designs an n-layer wiring pattern based on a logic circuit received from a user, and manufactures a semiconductor chip as described above.

  In a general gate array, a base on which no wiring layer is formed is prepared, and all the wiring layers are formed according to a user's request. Compared to the gate array having such a configuration, the general-purpose logic module has an advantage that a construction period from the design of the logic circuit by the user to the completion of the semiconductor chip is shortened.

As a general-purpose logic module as described above, for example, Japanese Patent Application Laid-Open No. 7-106949 (US Pat. No. 5,055,718) discloses a “general-purpose combination” composed of a four-input multiplexer (MUX) in which three two-input multiplexers are combined. Logic module "is disclosed. As another general-purpose logic module, US Pat. No. 5,684,412 discloses “CELL FORMING PART OF A CUSTOMIZABLE ARRAY”. Japanese Patent Laid-Open No. 61-61437 discloses a master slice type integrated circuit that uses an unused area not used for a logic function as a decoupling capacitor between VDD and GND. Furthermore, Japanese Patent Laid-Open No. 2-241061 discloses a CMOS gate array provided with a decoupling capacitor for absorbing noise between a power supply potential and an installation potential.
JP 7-106949 A US Pat. No. 5,684,412 JP 61-61437 A Japanese Patent Laid-Open No. 2-241061

  In the conventional general-purpose logic module described above, some MOS transistors included in the general-purpose logic cell are already connected to the power supply (VDD) wiring and the ground (GND) wiring, respectively. In such a MOS transistor, an off-leakage current is generated between the source and the drain. Therefore, even a MOS transistor included in an unconnected general-purpose logic cell that is not used as a logic circuit generates off-leakage current.

  FIG. 3 shows the relationship between the gate length Leff, power supply voltage Vcc, and off-leakage current Ioff of the MOS transistor. As shown in FIG. 3, the off-leakage current increases as the gate length decreases and the power supply voltage decreases. Therefore, with the recent miniaturization of MOS transistors, power consumption due to off-leakage current cannot be ignored.

  When a logic circuit is configured using a general-purpose logic module in which a large number of general-purpose logic cells are integrated, it is said that the proportion of general-purpose logic cells actually used is about 50%. Therefore, in a logic circuit configured using a general-purpose logic module, a large amount of power is consumed by unused general-purpose logic cells, and improvement is desired.

  On the other hand, in recent years, the operating frequency of the ASIC has been significantly improved. As a result, due to the switching operation of the MOS transistor, noise occurs in the power supply line inside the general-purpose logic module, causing a malfunction.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a general-purpose logic module capable of preventing the occurrence of off-leakage current in a general-purpose logic cell not used as a logic circuit, and an ASIC using the same. There is.

  The means for solving the problem will be described below using the numbers and symbols used in the [Embodiments of the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Mode for carrying out the invention]. It should not be used to interpret the technical scope of the described invention.

  According to an object of the present invention, a semiconductor integrated circuit forms a base on which one or a plurality of types of general-purpose logic cells formed by being partially connected by a first wiring layer are arranged in an array, and the base A logic circuit is formed by forming a second wiring layer for connecting the general-purpose logic cell.

  In the semiconductor integrated circuit, the first general-purpose logic cell includes a first inverter (A) whose input is connected to the first terminal (T1) and a second inverter (B) whose input is connected to the second terminal (T4). A third inverter (C) whose input is connected to a third terminal (T7), an input is connected to the output of the first inverter (A), and a first control input is connected to the third terminal (T7). A first transfer gate (E) having a second control input connected to the output of the third inverter (C) and an output connected to a fourth terminal (T10); and the second inverter (B) An input is connected to the output, a first control input is connected to the output of the third inverter (C), a second control input is connected to the third terminal (T7), and an output is supplied to the fourth terminal (T10). And a second transfer gate (D) connected thereto. A wiring connecting the first inverter (A), the second inverter (B), the third inverter (C), the first transfer gate (E), and the second transfer gate (D) is the first wiring. The inverter is formed of a layer, and at least one of the first inverter (A), the second inverter (B), and the third inverter (C) is connected to only one of a power source and a ground. The inverter connected to only one of the power supply and the ground has a connection terminal for connecting the other of the power supply and the ground in the second wiring layer, and the semiconductor integrated circuit has the connection terminal open. At least one general-purpose logic cell is provided as the general-purpose logic cell.

  A semiconductor integrated circuit is formed by the general-purpose logic module in which the logic circuit is formed by forming the second wiring layer for connecting the general-purpose logic cells.

  A decoupling capacitor is formed by connecting the other of the power supply or the ground to an input corresponding to the inverter connected only to one of the power supply or the ground.

  The semiconductor integrated circuit may be an ASIC.

  In another aspect of the present invention, a semiconductor integrated circuit forms a base on which one or a plurality of types of general-purpose logic cells formed by being partially connected in a first wiring layer are arranged in an array, A logic circuit is formed on the base by forming a second wiring layer for connecting the general-purpose logic cell.

In the semiconductor integrated circuit design method, in the first general-purpose logic cell, the input of the first inverter (A) is connected to the first terminal (T1), and the input of the second inverter (B) is connected to the second terminal (T4). Connect the input of the third inverter (C) to the third terminal (T7), connect the input of the first transfer gate (E) to the output of the first inverter (A), and connect the third terminal ( T7) is connected to the first control input of the first transfer gate (E), the output of the third inverter (C) is connected to the second control input of the first transfer gate (E), and the fourth terminal The output of the first transfer gate (E) is connected to (T10), the input of the second transfer gate (D) is connected to the output of the second inverter (B), and the output of the third inverter (C) The second transfer gate D) is connected to the first control input, the second terminal of the second transfer gate (D) is connected to the third terminal (T7), and the second transfer gate (D) is connected to the fourth terminal (T10). ), The first inverter (A), the second inverter (B), the third inverter (C), the first transfer gate (E), and the second transfer gate (D) The first wiring layers are connected.
At least one of the first inverter (A), the second inverter (B), and the third inverter (C) is an inverter connected to only one of a power source and a ground, and is connected only to one of the power source and the ground The inverter has a connection terminal for connecting the other of the power supply and the ground to the second wiring layer. The semiconductor integrated circuit includes at least one of the first general-purpose logic cells whose connection terminals are open as the general-purpose logic cells.

  In another aspect of the present invention, a semiconductor integrated circuit forms a base on which one or a plurality of types of general-purpose logic cells formed by being partially connected in a first wiring layer are arranged in an array, A logic circuit is formed on the base by forming a second wiring layer for connecting the general-purpose logic cell.

In the method of manufacturing a semiconductor integrated circuit, in the first general-purpose logic cell, the input of the first inverter (A) is connected to the first terminal (T1), and the input of the second inverter (B) is connected to the second terminal (T4). The input of the third inverter (C) is connected to the third terminal (T7), the input of the first transfer gate (E) is connected to the output of the first inverter (A), and the third terminal The first control input of the first transfer gate (E) is connected to (T7), the second control input of the first transfer gate (E) is connected to the output of the third inverter (C), and the fourth The output of the first transfer gate (E) is connected to the terminal (T10), the input of the second transfer gate (D) is connected to the output of the second inverter (B), and the output of the third inverter (C) The second transferage at the output The first control input of the second transfer gate (D), the second control input of the second transfer gate (D) to the third terminal (T7), and the second transfer gate to the fourth terminal (T10). The output of (D) is connected to the first inverter (A), the second inverter (B), the third inverter (C), the first transfer gate (E), and the second transfer gate (D). Are connected by the first wiring layer. At least one of the first inverter (A), the second inverter (B), and the third inverter (C) is an inverter connected to only one of a power source and a ground, and is connected only to one of the power source and the ground The inverter has a connection terminal for connecting the other of the power supply and the ground to the second wiring layer.
A semiconductor integrated circuit is manufactured that includes at least one first general-purpose logic cell having the connection terminal open as the general-purpose logic cell.

  As described above in detail, according to the present invention, it is possible to provide a general-purpose logic module that can prevent the occurrence of off-leakage current in a general-purpose logic cell that is not used as a logic circuit, and an ASIC using the same. Further, by using a transistor in a general-purpose logic cell that is not connected and is not logically used as a decoupling capacitor, noise generated in the power supply line inside the chip is suppressed and stable operation is possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In the general-purpose logic module according to the first embodiment of the present invention, a basic circuit called a general-purpose logic cell is arrayed by electrically connecting MOS transistors formed on a semiconductor substrate with a first wiring layer composed of, for example, three layers. The general-purpose logic cells are electrically connected by a second wiring layer made up of two layers, for example, and used as a base to form a desired logic circuit. An IC (integrated circuit) formed using a general-purpose logic module in which such a logic circuit is incorporated is referred to as “ASIC” in this specification. In the first and second embodiments of the present invention, the general-purpose logic cell is composed of an inverting type two-input multiplexer. However, the present invention is not limited to this, and other various logic circuits are used as the general-purpose logic cell. Can do.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a general-purpose logic cell that forms a general-purpose logic module according to Embodiment 1 of the present invention. This general-purpose logic cell includes basic cells A, B, C, D, and E configured by being connected through a first wiring layer.

  Each of the basic cells A, B, and C is configured by connecting a P-channel MOS and an N-channel MOS in series. The P-channel MOS and N-channel MOS included in each of the basic cells A, B, and C correspond to the transistor of the present invention.

  In the basic cell A, the terminal T2 drawn from the source of the P channel MOS to the second wiring layer is not connected (indicated as “NC” in FIG. 1; the same applies hereinafter), and the N channel The terminal T3 drawn from the source of the MOS is grounded by the first wiring layer or the second wiring layer. Further, the terminal T1 drawn from the gates of the P channel MOS and the N channel MOS to the second wiring layer is not connected. The basic cell A functions as an inverter when the terminal T2 is connected to the power supply VDD in the second wiring layer, and inverts and outputs the input signal.

  Similarly, in the basic cell B, the terminal T5 drawn from the source of the P channel MOS to the second wiring layer is not connected, and the terminal T6 drawn from the source of the N channel MOS is connected to the first wiring layer or the second wiring. Grounded at the layer. The terminal T4 drawn from the gates of the P channel MOS and N channel MOS to the second wiring layer is not connected. The basic cell B functions as an inverter when the terminal T5 is connected to the power supply VDD in the second wiring layer, and inverts and outputs the input signal.

  Similarly, in the basic cell C, the terminal T8 drawn from the source of the P channel MOS to the second wiring layer is not connected, and the terminal T9 drawn from the source of the N channel MOS is connected to the first wiring layer or the second wiring. Grounded at the layer. The terminal T7 drawn from the gates of the P-channel MOS and N-channel MOS to the second wiring layer is not connected. The basic cell C functions as an inverter when the terminal T8 is connected to the power source VDD in the second wiring layer, and inverts and outputs the input signal.

  Each of the transfer gates D and E has a structure in which a P channel MOS and an N channel MOS are connected in parallel, that is, a structure in which a source and a drain are connected to each other. Depending on the signal supplied to the gate, the signal supplied to the input terminal is allowed to pass or the signal supplied to the input terminal is prevented from passing. Hereinafter, the gate of the P-channel MOS is referred to as a first control input terminal, and the gate of the N-channel MOS is referred to as a second control input terminal.

  The output of the basic cell A is connected to the input terminal of the basic cell E (transfer gate). The terminal T10 drawn from the output of the basic cell E to the second wiring layer is not connected. The output of the basic cell B is connected to the input terminal of the basic cell D (transfer gate). The output of the basic cell D is connected to the terminal T10.

  The terminal T7 described above is connected to the second control input terminal of the basic cell D and the first control input terminal of the basic cell E. The output of the basic cell C is connected to the first control input terminal of the basic cell D and the second control input terminal of the basic cell E.

  In this general-purpose logic cell, the P-channel MOS and N-channel MOS constituting the basic cells A, B, C, D, and E, and the wiring connecting these basic cells are formed in the first wiring layer to form the base. Yes. The terminals T1, T2, T4, T5, T7, T8, and T10 can be connected by a second wiring layer formed on the base. This general-purpose logic cell is configured to exhibit various functions by connecting or not connecting the terminals T1, T2, T4, T5, T7, T8, and T10 in the second wiring layer.

  For example, by connecting the terminal T2, terminal T5, and terminal T8 of this general-purpose logic cell to the power supply VDD, an inverting output type two-input multiplexer in which the first stage is an inverter and the second stage is a transfer gate Is configured. In this case, the terminals T1 and T4 are input terminals, the terminal T7 is a selection signal input terminal, and the terminal T10 is an output terminal.

  If this multiplexer is used, various logic elements can be configured depending on the connection method of the terminals T1, T4, T7 and T10. Some examples of logic elements composed of general-purpose logic cells are described in Japanese Patent Application No. 2000-319269 filed earlier by the applicant of the present application.

  Further, by leaving the terminals T2, T5, T8, and T10 of this general-purpose logic cell unconnected, and connecting the terminals T1, T4, and T7 to the power supply VDD, the basic cells A, B, and C are connected. Each N-channel MOS and the N-channel MOS of the basic cell D function as a decoupling capacitor disposed between the power supply VDD and the ground GND.

  The general-purpose logic module according to the first embodiment of the present invention is configured by integrating a plurality of general-purpose logic cells configured as described above. If this general-purpose logic module is used, the second wiring for connecting the general-purpose logic cells on the base on which the general-purpose logic cells formed by being partially connected in the first wiring layer are arranged in an array. By forming the layer, an ASIC including a logic circuit having a desired function can be formed. In this case, the source of the P-channel MOS constituting the basic cell of the general-purpose logic cell that is not used for forming the logic circuit is not connected to the power supply VDD. In addition, an on-chip capacitor is formed by connecting the gate of the MOS included in the basic cell of the general-purpose logic cell that is not used for forming the logic circuit to the power supply VDD through the second wiring layer.

When manufacturing an ASIC using this general-purpose logic module, a base on which general-purpose logic cells are arranged in an array is formed by connecting a part of the first wiring layer, and a general-purpose is formed on the formed base. A logic circuit is formed by forming a second wiring layer for connecting the logic cells. When forming the base, the source of the P-channel MOS included in each general-purpose logic cell is not connected to the power supply VDD. When forming the logic circuit, the source of the P channel MOS included in each of the general-purpose logic cells used for forming the logic circuit is connected to the power supply VDD, and the general-purpose logic cell not used for forming the logic circuit. The source of the P-channel MOS included in each of these is left unconnected to the power supply VDD. When a logic circuit is formed, an on-chip capacitor is formed by connecting the gate of the MOS included in each general-purpose logic cell not used for forming the logic circuit to the power supply VDD through the second wiring layer. .

  Further, when designing an ASIC using this general-purpose logic module, a wiring pattern of the second wiring layer is designed so as to realize a desired logic circuit, and a lithography mask on which the wiring pattern is burned is used for 3 A semiconductor chip on which a desired logic circuit is formed is obtained by a semiconductor manufacturing process in which a second wiring layer is formed on a semiconductor substrate as a base layer that is wired up to the layer.

  An ASIC using this general-purpose logic module can be provided to the user by the following method. For example, a semiconductor manufacturer discloses information on a semiconductor substrate formed up to three layers to a user. The user designs a desired logic circuit based on the disclosed information, and requests a semiconductor manufacturer to manufacture a semiconductor chip for realizing the logic circuit. A semiconductor manufacturer automatically designs a two-layer wiring pattern based on a logic circuit received from a user, manufactures a semiconductor chip as described above, and provides it to the user.

  As described above, according to the general-purpose logic module according to the first embodiment of the present invention, since the terminals T2, T5, and T8 of the general-purpose logic cell that are not used for configuring the logic circuit are not connected, the basic cell The off-leakage current between the source and drain of the MOS transistor that constitutes can be made substantially zero. As a result, the power consumption of the ASIC as a whole can be suppressed.

For example, as shown in FIG. 3, when the gate length Leff is 0.13 μm and the power supply voltage Vcc is 1.5 V, the off-leakage current Ioff is 5 nA / μm. Now, in a 10M gate (40M transistor) scale chip, assuming that the gate width is 1.6 μm and 50% of the gates are not used to form a logic circuit, “5 [nA / μm] * per chip Current consumption of 1.6 [μm] * (40 * 10 ⁶ [Tr]) * 0.5 = 160 [mA] ”is saved.

  Further, by connecting the terminals T1, T4, and T7 of the general-purpose logic cell to the power supply VDD, the N-channel MOSs of the basic cells A, B, C, and D of the general-purpose logic cell function as the capacitor CAP. And acts as a decoupling capacitor inserted between the ground GND. Therefore, noise on the power supply line due to the switching operation of the MOS transistor can be suppressed, and a situation in which a malfunction occurs can be avoided.

For example, in a 10M gate (40M transistor) scale chip, the capacity when 50% of the gate is used as an on-chip capacitor is as follows. Since each general-purpose logic cell includes 10 transistors, when the gate capacitance is 2.5 fF, the total on-chip capacitance is “2.5 [fF] * (40 * 10 ⁶ [Tr]) * 0.5. = 50 [nF] ”.

(Embodiment 2)
FIG. 2 is a circuit diagram showing the configuration of a general-purpose logic cell used in the general-purpose logic module according to Embodiment 2 of the present invention. This general-purpose logic cell is composed of basic cells A, B, C, D and E.

  Each of the basic cells A, B, and C is configured by connecting a P-channel MOS and an N-channel MOS in series. The P channel MOS and N channel MOS included in each of the basic cells A, B, and C correspond to elements of the present invention.

  In the basic cell A, the terminal T2 drawn from the source of the P channel MOS is connected to the power supply VDD in the first wiring layer or the second wiring layer. A terminal T3 drawn from the source of the N-channel MOS to the second wiring layer is not connected. Further, the terminal T1 drawn from the gates of the P channel MOS and the N channel MOS to the second wiring layer is not connected. The basic cell A functions as an inverter by connecting the terminal T3 to the ground GND, and inverts and outputs the input signal.

  Similarly, in the basic cell B, the terminal T5 drawn from the source of the P channel MOS is connected to the power supply VDD in the first wiring layer or the second wiring layer. A terminal T6 drawn from the source of the N-channel MOS to the second wiring layer is not connected. The terminal T4 drawn from the gates of the P channel MOS and N channel MOS to the second wiring layer is not connected. The basic cell B functions as an inverter when the terminal T6 is connected to the ground GND, and inverts and outputs the input signal.

  Similarly, in the basic cell C, the terminal T8 drawn from the source of the P channel MOS is connected to the power supply VDD in the first wiring layer or the second wiring layer. A terminal T9 drawn from the source of the N channel MOS to the second wiring layer is not connected. The terminal T7 drawn from the gates of the P-channel MOS and N-channel MOS to the second wiring layer is not connected. The basic cell C functions as an inverter by connecting the terminal T9 to the ground GND, and inverts and outputs the input signal.

  Each of transfer gates D and E is the same as those in the first embodiment. The output of the basic cell A is connected to the input terminal of the basic cell E (transfer gate). The terminal T10 drawn from the output of the basic cell E to the second wiring layer is not connected. The output of the basic cell B is connected to the input terminal of the basic cell D (transfer gate). The output of the basic cell D is connected to the terminal T0.

  The terminal T7 described above is connected to the second control input terminal of the basic cell D and the first control input terminal of the basic cell E. The output of the basic cell C is connected to the first control input terminal of the basic cell D and the second control input terminal of the basic cell E.

  In the general-purpose logic cell, the P-channel MOS and N-channel MOS constituting the basic cells A, B, C, D, and E, and the wiring connecting these basic cells are formed in the first wiring layer to form the base. Yes. Terminals T1, T3, T4, T6, T7, T9, and T10 are provided in the second wiring layer formed on the base. This general-purpose logic cell is configured to exhibit various functions by connecting or not connecting terminals T1, T3, T4, T6, T7, T9, and T10 in the second wiring layer.

  For example, a terminal T3, a terminal T6, and a terminal T9 of this general-purpose logic cell are connected to the ground GND, so that an inverting output type two-input multiplexer in which the first stage is an inverter and the second stage is a transfer gate. Is configured. In this case, the terminals T1 and T2 are input terminals, the terminal T7 is a selection signal input terminal, and the terminal T10 is an output terminal. If this multiplexer is used, various logic elements can be configured depending on the connection method of the terminals T1, T4, T7 and T10.

  Further, by leaving the terminals T3, T6, T9, and T10 of this general-purpose logic cell unconnected, and connecting the terminals T1, T4, and T7 to the ground GND, the basic cells A, B, and C are connected. Each P channel MOS and the P channel MOS of the basic cell E constitute a decoupling capacitor arranged between the power supply VDD and the ground GND.

  The general-purpose logic module of the present invention is configured by integrating a plurality of general-purpose logic cells configured as described above. If this general-purpose logic module is used, a logic circuit having a desired function can be configured by connecting the terminals of the general-purpose logic module with the second wiring layer.

  Manufacture, design, and provision of an ASIC using the general-purpose logic module according to the second embodiment can be realized in the same manner as in the first embodiment.

  As described above, according to the general-purpose logic module according to the second embodiment of the present invention, the terminals T3, T6, and T9 of the general-purpose logic cells that are not used for configuring the logic circuit are not connected. The off-leakage current between the source and drain of the MOS transistor that constitutes can be made substantially zero. As a result, the power consumption of the ASIC as a whole can be suppressed.

  Further, by connecting the terminals T1, T4, and T7 of the general-purpose logic cell to the ground GND, the P-channel MOS of the basic cells A, B, C, and D of the general-purpose logic cell function as a capacitor CAP. And acts as a decoupling capacitor inserted between the ground GND. Therefore, noise on the power supply line due to the switching operation of the MOS transistor can be suppressed, and a situation in which a malfunction occurs can be avoided.

FIG. 1 is a circuit diagram showing a configuration of a general-purpose logic cell according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of a general-purpose logic cell according to Embodiment 2 of the present invention. FIG. 3 is a diagram showing the relationship among the gate length Leff, power supply voltage Vcc, and off-leakage current Ioff of the MOS transistor.

Explanation of symbols

A, B, C, D, E Basic cell CAP capacitor T1-T10 terminal VDD power supply GND Ground

Claims (6)

A base on which one or a plurality of types of general-purpose logic cells formed by being partially connected in the first wiring layer is arranged in an array is formed, and the general-purpose logic cell is connected on the base A semiconductor integrated circuit in which a logic circuit is formed by forming a second wiring layer for:
The first general purpose logic cell is
A first inverter whose input is connected to the first terminal;
A second inverter whose input is connected to the second terminal;
A third inverter whose input is connected to the third terminal;
An input is connected to the output of the first inverter, a first control input is connected to the third terminal, a second control input is connected to the output of the third inverter, and an output is connected to the fourth terminal. 1 transfer gate,
An input connected to the output of the second inverter, a first control input connected to the output of the third inverter, a second control input connected to the third terminal, and an output connected to the fourth terminal 2 transfer gates,
A wiring connecting the first inverter, the second inverter, the third inverter, the first transfer gate, and the second transfer gate is formed by the first wiring layer;
At least one of the first inverter, the second inverter, and the third inverter is an inverter connected to only one of a power supply and a ground,
The inverter connected only to one of the power supply and the ground has a connection terminal for connecting the other of the power supply and the ground in the second wiring layer,
A semiconductor integrated circuit comprising at least one of the first general-purpose logic cells whose connection terminals are open as the general-purpose logic cells.   2. The semiconductor integrated circuit according to claim 1, formed by the general-purpose logic module in which the logic circuit is formed by forming the second wiring layer for connecting the general-purpose logic cells.   3. The semiconductor integrated circuit according to claim 1, wherein a decoupling capacitor is formed by connecting the other of the power supply or the ground to an input corresponding to the inverter connected only to one of the power supply or the ground.   4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an ASIC. A base on which one or a plurality of types of general-purpose logic cells formed by being partially connected in the first wiring layer is arranged in an array is formed, and the general-purpose logic cell is connected on the base A semiconductor integrated circuit in which a logic circuit is formed by forming a second wiring layer for:
In the first general-purpose logic cell, the input of the first inverter is connected to the first terminal, the input of the second inverter is connected to the second terminal, the input of the third inverter is connected to the third terminal, and the first inverter The first transfer gate input is connected to the output of the first transfer gate, the first control input of the first transfer gate is connected to the third terminal, and the second control input of the first transfer gate is connected to the output of the third inverter. And connecting the output of the first transfer gate to the fourth terminal, connecting the input of the second transfer gate to the output of the second inverter, and connecting the first of the second transfer gate to the output of the third inverter. Connecting a control input, connecting the second control input of the second transfer gate to the third terminal, connecting the output of the second transfer gate to a fourth terminal, First inverter, said second inverter, said third inverter, said first transfer gate, and connecting the second transfer gates by the first wiring layer,
At least one of the first inverter, the second inverter, and the third inverter is an inverter connected to only one of a power supply and a ground,
The inverter connected only to one of the power supply and the ground has a connection terminal for connecting the other of the power supply and the ground in the second wiring layer,
A method of designing a semiconductor integrated circuit so as to include at least one of the first general-purpose logic cells whose connection terminals are open as the general-purpose logic cells. A base on which one or a plurality of types of general-purpose logic cells formed by being partially connected in the first wiring layer is arranged in an array is formed, and the general-purpose logic cell is connected on the base A semiconductor integrated circuit in which a logic circuit is formed by forming a second wiring layer for:
In the first general-purpose logic cell, the input of the first inverter is connected to the first terminal, the input of the second inverter is connected to the second terminal, the input of the third inverter is connected to the third terminal, and the first inverter The first transfer gate input is connected to the output of the first transfer gate, the first control input of the first transfer gate is connected to the third terminal, and the second control input of the first transfer gate is connected to the output of the third inverter. And connecting the output of the first transfer gate to the fourth terminal, connecting the input of the second transfer gate to the output of the second inverter, and connecting the first of the second transfer gate to the output of the third inverter. Connecting a control input, connecting the second control input of the second transfer gate to the third terminal, connecting the output of the second transfer gate to a fourth terminal, First inverter, said second inverter, said third inverter, said first transfer gate, and connecting the second transfer gates by the first wiring layer,
At least one of the first inverter, the second inverter, and the third inverter is an inverter connected to only one of a power supply and a ground,
The inverter connected only to one of the power supply and the ground has a connection terminal for connecting the other of the power supply and the ground in the second wiring layer,
A method of manufacturing a semiconductor integrated circuit comprising at least one of the first general-purpose logic cells whose connection terminals are open as the general-purpose logic cells.

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