JP4266250B2 - Interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit interposed between signal lines for transmitting signals, and more specifically, smoothly transfers information between module circuits by an interface circuit provided between buses formed on a semiconductor chip. The present invention relates to a semiconductor device capable of performing
[0002]
[Prior art]
With the rapid development of miniaturization technology for forming semiconductor circuits on a semiconductor substrate at high density, it has become possible to realize highly functional semiconductor integrated circuits on a single semiconductor chip. Each function of the integrated circuit is classified according to its purpose, for example, a central processing circuit, a storage circuit, an input / output circuit, and the like. Each of these functions is further divided into details and realized as a module circuit. The user / manufacturer of the integrated circuit selects a function that achieves the object from the module circuit, and configures a single integrated circuit that realizes the desired function on the semiconductor substrate.
[0003]
These module circuits need to exchange information with each other in order to realize their functions, and are connected to signal lines for transmitting the information to each other, so-called buses. The bus is divided into an address bus, a data bus, a control bus, and the like corresponding to information to be transmitted.
[0004]
The resistance and stray capacitance of the signal line itself delay the signal propagating on the bus. The increase in operating frequency as the density of integrated circuits increases increases the bus wiring distance. Further, due to signal propagation delay and signal waveform deterioration, it becomes difficult to maintain the operation of the entire integrated circuit properly, causing a malfunction. In order to deal with such a problem, an interface circuit for receiving / transmitting signals is provided on the bus, and the above-described problem is avoided by dividing the transmission length of the bus into a short length. For example, Japanese Patent Laid-Open No. 8-123591 (multiplexed bus circuit) attempts to prevent signal waveform deterioration and time margin reduction by installing a circuit unit on the bus and shortening the transmission length of the bus.
[0005]
[Problems to be solved by the invention]
However, the circuit unit employs a configuration in which each information of address, data, and control for transmitting the bus is temporarily stored in the latch circuit and is sent out on the bus after a predetermined clock cycle. In particular, the address information and the data information are latched bidirectionally and sent out on the bus after a predetermined clock cycle. In such a configuration, for example, when data stored in a memory is read, there is at least two delays from when a read command of the central processing unit is transmitted until the desired data is read by the central processing unit. This unnecessarily reduces the processing speed of the entire integrated circuit.
[0006]
[Means for Solving the Problems]
The present invention has been made to solve the above-mentioned problems. For information transmitted from the central processing unit, information that is not given a time delay in the interface circuit and is sent from the expansion side bus to the central processing unit is provided. By providing a predetermined time delay in the interface, an interface is provided which can secure the transmission length of the entire bus and can alleviate the decrease in the processing speed of the entire integrated circuit.
[0007]
【Example】
The configuration and characteristics of the present invention will be understood with reference to the following description and drawings. FIG. 1 is a block diagram for explaining the present invention, and particularly shows an integrated circuit 10 having a bus configuration using an interface module. In the present invention, the bus connected to the central processing unit (CPU) 11 is referred to as a main bus 12, and the bus configured via the interface module 13 is referred to as an expansion bus 14. However, the present invention is particularly limited to these names. The bus connected to a processing module (corresponding to the CPU 11 in FIG. 1) having a high degree of information processing is called a main bus here. In FIG. 1, for simplicity of explanation, a static random access memory (SRAM) 15 is coupled to the main bus 12 in addition to the CPU 11, but other processing modules may be connected. . On the expansion bus 14 side, a dynamic random access memory (DRAM) 16 and an input / output (I / O) port 17 are connected. Other processing modules may be combined, but are omitted for simplicity.
[0008]
The CPU 11 issues instructions to the SRAM 15, DRAM 16, I / O port 17, etc. in order to execute processing according to the program steps, and these instructions are sent via the main bus 12, the interface module 13, and the expansion bus 14. It is transmitted to a predetermined processing module. The interface module 13 passes information such as a command from the CPU 11 to the expansion bus 14 as it is and transmits it to a predetermined processing module. When information stored at a predetermined address of a processing module, for example, the DRAM 16 is sent to the CPU 11, the information is sent from the DRAM 16 to the data bus in the expansion bus 14 and transmitted to the interface module 13. The interface module 13 stores and holds the received data for a predetermined time and then outputs it to the main bus 12. The predetermined time can be easily measured in synchronization with, for example, a clock cycle. The output data is captured by the CPU 11 from the main bus 12, and a series of processing sequence of data capture is completed.
[0009]
FIG. 2 is a detailed block diagram of the interface module 13. The main bus 12 and the expansion bus 14 are respectively connected to the interface module 13 and are composed of a control bus 21, a data bus 22, and an address bus 23 as shown in FIG. Each bus is classified according to signal contents, and is used as a path for transmitting various control signals, data information, and address information. The internal structure of the interface module 13 is roughly divided into a circuit block coupled to a control bus 21, a data bus 22, and an address bus 23. That is, the interface module 13 has a timing control 24 connected to the control bus 21, a latch 25 and data driver 26 connected to the data bus 22, and an address driver 27 connected to the address bus 23. . The timing control 24, the latch 25, the data driver 26, and the address driver 27 have normal input circuit sections and output circuit sections that can be easily configured by those skilled in the art, and are connected to the control, data, and address buses, respectively. Is done. When the predetermined control signal satisfies a certain condition, the timing control 24 sends the control signal to the latch 25 and the data driver 26 via the signal line 28 and the signal line 29, respectively. The latch control signal sent via the signal line 28 gives the timing for storing and storing the data information on the data bus 22 on the expansion bus 14 side in the memory unit in the latch 25. Further, the data control signal supplied from the signal line 29 is a signal for switching the transmission direction of the data information on the data bus 22, and the data information stored in the latch 25 is used as the data bus 22 on the main bus 12 side. The operation of the data driver 26 is stopped for a period of time during which data is transmitted. As a result, the data sent to the data bus 22 on the main bus 12 side is prevented from returning to the data bus 22 on the expansion bus 14 side.
[0010]
Next, the operation of the interface module 13 will be described with reference to the timing charts of FIGS. First, a processing sequence in which the CPU 11 fetches data stored in the DRAM 16 connected to the expansion bus 14 side will be described. FIG. 3 shows a sequence in which the CPU 11 reads data stored in the DRAM 16, and shows signal waveforms on the main bus 12 and the expansion bus 14, respectively. Since the signal waveform on the expansion bus is located away from the CPU 11, a slight transmission delay is observed due to the resistance of the signal line and the stray capacitance. In FIG. 3, the main bus 12 and the expansion bus are easily understood. The signal waveform delay at 14 is highlighted.
[0011]
The CPU 11 proceeds with the processing steps based on a clock (CLK) signal generated inside or outside the CPU 11. When the CPU 11 reads data stored in the DRAM 16, first, an address (ADD-R) signal is sent to the address bus 23, and a TREQ signal, which is a kind of control signal indicating a data transfer request, is asserted at time t1 ( It means making the signal logically "true", where the signal level goes from high to low). Further, a read / write signal (R / (inverted) W signal) indicating whether the CPU 11 is in the read mode or the write mode is asserted while the address signal is being output effectively (the signal level is maintained at a high level). .) The TREQ signal and the read / write signal are transmitted via the timing control 24 to the control bus on the expansion bus 14 side. Similarly, an address signal is also sent to the address bus 23 on the expansion bus 14 side via the address driver 27. Since the main bus 12 and the expansion bus 14 have a slight time delay, for example, the TREQ signal asserted at the time t1 is asserted at the time t2 in the expansion bus.
[0012]
The clock signal and the address signal are also transmitted to the expansion bus side through a similar time delay and are given to the DRAM 16. The DRAM 16 takes in the address signal when the clock signal transitions at time t3, outputs the data (DATA-R) signal stored at the address to the data bus 22, and sends the data signal properly. Is acknowledged at time t4 (the signal level goes low). The timing control 24 receives the acknowledge signal, captures the data signal on the data bus at the timing when the clock signal transitions from low to high at time t5, and stores it in a predetermined storage location. The acknowledge signal is asserted while the data signal is being output. At the time t6, the output of the data signal ends, and at the same time, the acknowledge signal ends. The termination leads to generation of an ABORT signal and serves to prohibit other processing modules from starting operation for a predetermined period until at least the CPU 11 completes the read mode.
[0013]
The timing control 24 sends the stored data signal to the data bus 22 on the main bus 12 side at a predetermined period, for example, at time t7 when one cycle of the clock signal has elapsed. In this embodiment, a configuration is shown in which the data signal is held for one cycle period of the clock signal. However, since a reference signal having a cycle shorter than that of the clock signal is usually created, the clock signal is shorter than one cycle of the clock signal. It is also possible to adopt a configuration that delays by a period. Simultaneously with the transmission of the data signal, the timing control 24 generates an acknowledge signal and outputs it to the main bus 12 side. After confirming that the acknowledge signal is asserted (the signal level is low), the CPU 11 captures the data signal transmitted on the data bus 22 at time t8 when the clock signal transitions from low to high. With this capture, the CPU 11 completes a series of read modes.
[0014]
In the reading mode as described above, the address signal, control signal and the like issued from the CPU 11 are not temporarily stored and stored by the interface module 13 and are immediately transferred to the expansion bus side upon reception. A signal transmitted from the expansion bus side to the main bus side is held for a predetermined time and then output to the main bus side.
[0015]
Next, processing steps in the write mode in which the CPU 11 writes data into the DRAM 16 will be described with reference to FIGS. FIG. 4 is a timing chart showing signal waveforms on the signal lines in the main bus 12 and the expansion bus 14 as in FIG.
[0016]
The CPU 11 outputs an address (ADD-W) signal of data to be written to the address bus 23. This address signal is transmitted to the address bus 23 on the expansion side via the address driver 27 of the interface module 13. The DRAM 16 captures this address signal at time t11 when the clock signal transitions from low to high. The CPU 11 sends a write data (DATA-W) signal to the data bus at time t12, one cycle after time t11. This data signal is transmitted to the data bus on the expansion bus 14 side via the data driver 26. The DRAM 16 inputs the data signal on the data bus at time t13 when the clock signal transitions from low to high, and writes the data to a predetermined address corresponding to the address signal that has already been captured. When the data is stored, the DRAM 16 outputs an acknowledge signal indicating that the data has been properly written to the CPU 11. This acknowledge signal is latched for a predetermined time as described in the read mode and then sent to the main bus 12 side to notify the CPU 11 that data has been correctly written. Further, the interface module 13 generates an abort signal so that other modules do not start operation while the data signal exists on the data bus after the acknowledge signal is output. When the acknowledge signal is received by the CPU 11, the write mode of the CPU 11 is finished.
[0017]
Next, FIG. 5 shows how the present invention is arranged on a semiconductor chip. FIG. 5 is a plan view of the semiconductor chip 30 as viewed from above. Although the main bus and the expansion bus can be configured on the chip in any manner by the processing modules coupled to them, in other words, depending on the function of the integrated circuit, two expansion buses are shown in FIG. A state in which 31 and 32 are coupled to the main bus 35 via the interface modules 33 and 34 is shown. A CPU 36 and a memory 37 are connected to the main bus 35. A memory 38 and an I / O 39 are connected to the expansion bus 31, and a memory 40 is connected to the expansion bus 32. FIG. 5 shows a case where an expansion bus is connected to the main bus, but it is also possible for those skilled in the art to connect the expansion bus to the expansion bus via an interface module and extend the bus. It is.
[0018]
【The invention's effect】
As described above, since the interface circuit is interposed in the signal line, a transmission delay is given only in one direction of the signal, and transmission is performed without giving a time delay in the other direction. This simplifies and can reduce the cost. In addition, since the signal line can be extended using the interface circuit, an electronic device with higher function can be configured. Furthermore, since a circuit having various functions can be connected to the extended signal line regardless of the transmission characteristic of the signal line, the development period of the electronic device can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an overall configuration of the present invention;
FIG. 2 is a detailed block diagram showing an embodiment of an interface module according to the present invention.
FIG. 3 is a timing sequence in which the central processing unit reads data stored in a DRAM.
FIG. 4 is a timing sequence in which the central processing unit writes data to the DRAM.
FIG. 5 is a plan view showing an arrangement of interface modules and processing modules on a semiconductor substrate.
[Explanation of symbols]
10 Integrated Circuit 11 Central Processing Unit (CPU)
12 Main bus 13 Interface module 14 Expansion bus 15 SRAM
16 DRAM
17 I / O port 21 Control bus 22 Data bus 23 Address bus 24 Timing control 25 Latch 26 Driver 27 Driver 28 Signal line 29 Signal line

Claims (15)

An interface circuit coupled to a main bus and an expansion bus formed in an electronic device:
Receiving a first data information transmitted from the central processing unit on the data line in the main bus, a first driver circuit for sending the first data information without delay to the data lines in said expansion bus;
Receiving said first control signal transmitted from the CPU on the control line in the main bus and sends without delay the first control signal to said control lines in said expansion bus, said expansion in response to and the data latch signal; transmitted on said data lines in Choba scan, the control circuit generates the data latch signal for controlling the transmission of the second data information to said central processing unit said second storing data information, the data latch circuit delivering the second data information to the data line in the main-bus after a first predetermined time;
An interface circuit comprising: 2. The interface circuit according to claim 1, wherein the first predetermined time is one cycle of a clock signal in the first control signal. Said data latch circuit, during the presence of the acknowledge signal on the control line in the expansion bus indicating that said second data information is effectively transmitted to the data lines in said main bus, the first 2. The interface circuit according to claim 1, wherein two data information is stored. The acknowledge signal, the interface circuit according to claim 3, wherein the sent from the module circuitry to perform a specific process that is coupled to said expansion bus to said control lines in said expansion bus. 4. The interface circuit according to claim 3, wherein the control circuit delays the acknowledge signal by the first predetermined time and sends it to the control line in the main bus . 5. The control circuit according to claim 4, wherein the module circuit sends an abort signal for prohibiting the start of processing by the module circuit to the control line in the expansion bus for a predetermined period after receiving the acknowledge signal. Interface circuit. It is transmitted to the control line before Symbol in expansion bus, a second control signal to the central processing unit and characterized in that it is delivered to the control line in the main bus after a second predetermined time period after the latch The interface circuit according to claim 1. 8. The interface circuit according to claim 7, wherein the second predetermined time is one cycle of a clock signal in the second control signal. Wherein the control circuit, said the period for transmitting a data signal on said expansion Choba scan to a central processing equipment, which generates a signal for inhibiting the operation of said first driver circuit, providing to said first driver circuit The interface circuit according to claim 1. Receiving said address information on the address lines in the main bus, according to claim 1, wherein further comprising a second driver circuit for sending without delay the address information to the address line in said expansion bus Interface circuit.   The interface circuit according to claim 1, wherein the interface circuit is formed on a single semiconductor substrate. An integrated circuit formed on a semiconductor substrate comprising:
A first plurality of module circuits each including a central processing unit, each performing a specific process;
A first signal line coupled to each of the first plurality of module circuits for transmitting address information, data information, and a control signal;
A second plurality of module circuits each performing a specific process;
A second signal line coupled to each of the second plurality of module circuits for transmitting the address information, the data information, and the control signal; and interposed between the first signal line and the second signal line and, the address information, the data information, and the control signal a interface circuit to pass to each other, receiving the data information and the control signal is transmitted on the first signal Line, said second signal sent without delay to the line, the data information and after storing said control signal, said data information and said control signal is transmitted on the second signal line after the predetermined period of time is transmitted to the second signal line The interface circuit for sending to the first signal line;
An integrated circuit comprising: The interface circuit, the data information of the second signal line of one period only the delayed second signal line of the clock signal of said in control signal after forme Ri capture the data information to the first signal line 13. The integrated circuit according to claim 12, wherein the integrated circuit is sent out. The first signal line, the further coupled to the third signal line via the second interface circuit that have a function of the interface circuit of the same or equalization, whereby the address information, the data information, and the control 13. The integrated circuit according to claim 12, wherein a signal is transmitted between the second signal line and the third signal line.   Each of the first and second plurality of module circuits has a predetermined occupied area on the semiconductor substrate, and the first and second signal lines are between the first and second plurality of module circuits. 13. The integrated circuit according to claim 12, wherein the integrated circuit is provided.

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