CN116092552A - Controller and control method for pseudo-static random access memory - Google Patents

Abstract

The present disclosure provides a controller and a control method for a pseudo static random access memory. The controller includes: the digital controller is used for receiving an operation request and generating PSRAM transmission signals which are adaptive to the types of the eight paths of serial input/output interfaces based on the operation request; the input end of the physical layer interface is connected with the digital controller, and the output end is connected with the PSRAM interface and used for generating a PSRAM interface signal which is adaptive to the type of the PSRAM interface based on the PSRAM transmission signal. According to the controller provided by the embodiment of the disclosure, different PSRAM chips can be supported, and the flexibility of PSRAM chip selection is improved.

Description

Controller and control method for pseudo-static random access memory

technical field

The present disclosure relates to the technical field of integrated circuits, in particular to a controller and a control method for a pseudo-static random access memory.

Background technique

Pseudo Static Random Access Memory (PSRAM for short) is a process and technology that uses Dynamic Random Access Memory (DRAM for short), and realizes a process similar to Static Random Access Memory (Static Random-Access Memory). Memory, referred to as SRAM) the same random access memory (Random Access Memory, referred to as RAM).

The PSRAM interface is a SRAM interface that is compatible with SRAM and similar to SRAM in terms of access timing and other characteristics by modifying the DRAM interface and changing the refresh circuit to a self-refresh circuit at the same time. The PSRAM interface also has the low cost of the DRAM interface. , low power consumption, high memory density and simple SRAM interface.

Contents of the invention

The disclosure provides a PSRAM controller and a control method.

In a first aspect, the present disclosure provides a controller for pseudo-static random access memory, including: a digital controller and a physical layer interface, the input end of the physical layer interface is connected to the digital controller, and the output end is connected to the Described pseudo-static random access memory PSRAM interface connection, wherein:

The digital controller is configured to receive an operation request, and generate a PSRAM transmission signal adapted to the type of the eight-way serial input and output interface based on the operation request;

The physical layer interface is configured to generate a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal.

In a second aspect, the present disclosure provides a control method for a controller of a pseudo-static random access memory based on any one of the present disclosure, including:

Receive operation requests;

generating a PSRAM transmission signal adapted to the type of the eight-way serial input and output interface based on the operation request;

and generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal.

The controller for the pseudo-static random access memory provided by the embodiment of the present disclosure includes a digital controller and a physical layer interface, wherein the digital controller generates an interface adapted to the type of the eight-way serial input and output interface based on the operation request. Pseudo-static random access memory PSRAM transmission signals, so that PSRAM transmission signals are applicable to different PSRAM interfaces; the physical layer interface generates PSRAM interface signals adapted to the type of PSRAM interface based on the PSRAM transmission signals, because the PSRAM interface signals are based on the PSRAM interface Type, so the generated PSRAM interface signal can be compatible with different types of PSRAM interface and transmission protocol, so that the controller can support different PSRAM chips, improving the flexibility of PSRAM chip selection.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the present disclosure, and do not constitute a limitation to the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a schematic structural diagram of a PSRAM controller provided by an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a digital controller provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a sending transmission module provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a state machine in a data shifter provided by an embodiment of the present disclosure;

FIG. 5 is a working flow chart of a state machine when a register module performs a write operation in an embodiment of the present disclosure;

FIG. 6 is a working flowchart of a state machine when a register module performs a read operation in an embodiment of the disclosure;

FIG. 7 is a work flow diagram of a state machine during a storage write operation in an embodiment of the present disclosure;

FIG. 8 is a working flow diagram of a state machine during a storage read operation in an embodiment of the present disclosure;

Fig. 9 is a working flow chart of the state machine during semi-sleep operation in the embodiment of the present disclosure;

Fig. 10 is a working flow chart of the state machine when exiting the semi-sleep in the embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of a physical layer interface provided by an embodiment of the present disclosure;

FIG. 12 is a flowchart of a control method for a pseudo-static random access memory provided by an embodiment of the present disclosure.

Detailed ways

In order for those skilled in the art to better understand the technical solution of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and they should be considered exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In the case of no conflict, various embodiments of the present disclosure and various features in the embodiments can be combined with each other.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "consisting of" are used in this specification, the stated features, integers, steps, operations, elements and/or components are specified to be present but not excluded to be present or Add one or more other features, integers, steps, operations, elements, components and/or groups thereof. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art and the present disclosure, and will not be interpreted as having idealized or excessive formal meanings, Unless expressly so limited herein.

Each manufacturer has its own PSRAM interface specification, such as HyperBus Interface interface specification, APM OPI interface specification and Xccela OPI interface specification. These interface protocols all use OPI (Octal SPI, eight-way data serial input and output) and DDR (Double Data Rate, double data rate), but in terms of the number and function of control signals, read and write transmission protocols, chip internal register module access, and half sleep (Half Sleep)/deep power down (deep power down) mode entry and exit, etc. with large differences. However, the relevant PSRAM interface cannot be flexibly configured according to the PSRAM chip, so that the PSRAM interface can only support a certain type of interface, and cannot meet the actual requirements of being compatible with multiple PSRAM interfaces.

FIG. 1 is a schematic structural diagram of a PSRAM controller provided by an embodiment of the present disclosure. Referring to FIG. 1, the PSRAM controller includes a digital controller 1 and a physical layer interface 2, wherein the digital controller 1 is configured to receive access requests (including but not limited to read and write requests), and perform compatibility and control on different PSRAM chips . The input end of the physical layer interface 2 is connected to the digital controller 1, and the output end is connected to the PSRAM interface, and is used to generate a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal, so as to communicate with the PSRAM interface. Different PSRAM chips exchange information.

It should be noted that, in the embodiment of the present disclosure, the digital controller 1 may have multiple input terminals and multiple output terminals, and the number of input terminals and output terminals may be set as required, which is not limited in the embodiment of the present disclosure. The physical layer interface 2 may have multiple input ports and multiple output ports, and the number of input ports and output ports may be set as required, which is not limited in this embodiment of the present disclosure.

In some embodiments, the digital controller 1 is configured to receive an operation request, and generate a PSRAM transfer signal adapted to the type of the eight-channel serial input and output interface based on the operation request. Wherein, in the embodiment of the present disclosure, the digital controller 1 includes two input terminals, which are respectively connected to the APB bus and the AHB bus. Operation requests can be transmitted to the controller through the APB bus and the AHB bus, and the operation requests include but are not limited to read and write requests and register module access requests. The PSRAM transfer signal is a signal that the PSRAM can recognize. PSRAM transmission signals include read and write commands, entry/exit semi-sleep (hybrid sleep), entry/exit transmission signals corresponding to each transmission state in deep power-off operation.

In some embodiments, the input end of the physical layer interface 2 is connected to the digital controller 1, and the output end is connected to the PSRAM interface, for generating PSRAM interface signals adapted to the type of the PSRAM interface based on the PSRAM transmission signal. Among them, the PSRAM interface includes but is not limited to the interface corresponding to AP 8M "APS6408L-OBMx DDR OPI Xccela PSRAM", the interface corresponding to AP 4M "APS3208K-OTx OPI DDR PSRAM", the interface corresponding to WB 8M "W956D8MBYA" and the interface corresponding to WB 4M "W955D8MBYA" 》Corresponding interfaces (for ease of description, hereinafter referred to as AP 8M interface, AP 4M interface, WB 8M interface and WB 4M interface respectively).

In the embodiment of the present disclosure, the input end of the physical layer interface 2 is connected to the digital controller 1, and the output end is connected to the PSRAM interface, for generating a PSRAM interface adapted to the type of the PSRAM interface based on the PSRAM transmission signal signal, and transmit the timing together with the digital controller 1. In the embodiment of the present disclosure, the physical layer interface 2 can be compatible with various PSRAM interfaces, for example, it can be compatible with AP 8M interface, AP 4M interface, WB 8M interface and WB 4M interface.

In some embodiments, there are two interfaces at the input end (system side) of the digital controller 1, namely an Advanced Peripheral Bus (Advanced Peripheral Bus, APB) interface and an Advanced High Performance Bus (Advanced High Performance Bus, AHB-Lie) interface. The APB interface is used to access the control and status register module (Control and Status Register, CSR) in the digital controller 1. The AHB-Lite interface is used for memory array write/read and mode register block write/read in PSRAM memory devices based on CSR settings. The output end of the digital controller 1 is connected with the input end of the physical layer interface 2 .

In some embodiments, the memory controller clock mem_clk_0 and the phase-shifted memory controller clock mem_clk_90 are input to the digital controller 1 and the physical layer interface 2, the memory controller clock mem_clk_90 has the same frequency as the phase-shifted memory controller clock mem_clk_0, but the phase Lag 90 degrees.

Fig. 2 is a structural block diagram of a digital controller provided by an embodiment of the present disclosure. As shown in Figure 2, digital controller 1 comprises register module 11, AHB slave control module 12, read and write transaction transmission module 13, first synchronizer 14 and second synchronizer 15, wherein, register module 11 and AHB slave The control module 12 is connected to the read-write transaction transmission module 13 by signals, and the AHB slave control module 12 is connected to the register module 11 and the read-write transaction transmission module 13 by signals.

Wherein, the register module 11 serves as a slave of the APB and is connected to the APB interface signal. The register module 11 includes a control and status register module, which receives APB write transactions and outputs control signals and timing parameters to the AHB slave control module 12 and the read-write transaction transmission module 13 . The register module 11 is also used to receive and store status signals.

In some embodiments, the register module 11 is used for generating APB control signals and timing parameters based on the received APB operation request, and receiving and storing the transmission status signal.

Wherein, the APB operation request includes one or more of an APB read request and an APB write request. Transmission status signals include but are not limited to PSRAM access transmission status, such as data strobe clock (Data Strobe clock, DQS) timeout signal, DPD/HALF SLEEP entry and exit, and completion signal of GLOBAL RESET instruction.

The AHB slave control module 12 is used to respond to the received AHB operation request, obtain AHB command information based on the APB control signal and timing parameters; and transmit the received PSRAM transmission status information to the AHB master. Wherein, the AHB operation request includes one or more of an AHB read request and an AHB write request.

Exemplarily, the AHB slave control module 12 parses AHB read and write transactions, and outputs transfer parameters (transfer type, read and write length, transfer size), read and write addresses, and write data. The AHB slave control module 12 includes an asynchronous first-in-first-out (FIFO) module (not shown in the figure), which is used for cross-clock domain synchronization and synchronization of command addresses and data between the AHB slave controller clock ahb_clk and the memory controller clock mem_clk_0 cache. The AHB slave control module 12 is also used for receiving the timeout signal of the data strobe clock, and for feeding back the transmission status to the AHB master.

The read and write transaction transmission module 13 is used to generate a PSRAM transmission signal based on the APB control signal and the AHB instruction information, and receive the PSRAM read data and clock signal from the physical layer interface 2, and sample the operation request based on the clock signal, and Transmitting the sampling result to the AHB slave control module; and receiving a transmission status signal.

Wherein, the AHB instruction information includes but not limited to transmission parameters (transmission type, read and write length, and transmission size), read and write addresses, and read and write data.

The read-write transaction transmission module 13 is used to realize the read-write transaction transmission of the PSRAM storage and the register module. The read-write transaction transmission module 13 receives the control signal from the register module 11 and the command address and the write data of the AHB slave control module 12 to generate PSRAM The signal is transmitted to the physical layer interface 2; and the read data and clock signal from the physical layer interface 2 are received and output to the AHB slave control module 12 after sampling. The read-write transaction transmission module 13 also outputs a plurality of state indication signals, and a plurality of states include the overtime signal and the transmission completion signal of the data strobe clock (DQS), etc., the DQS overtime signal is used to indicate whether the DQS returns overtime, and the transmission completion signal is used for Indicates the completion of each instruction.

In some embodiments, the read and write transaction transmission module 13 includes a command processing (INSTRN_HANDLER) module 131, a sending transmission (TX_PATH) module 132, and a receiving transmission (RX_PATH) module 133, wherein the command processing module 131 is used to process information from the register module 11 Various instructions, such as edge detection for the received APB control signal, and output APB control valid signal and APB transmission signal. In some embodiments, the instructions output by the register module 11 include but are not limited to read and write transmission, semi-sleep entry/exit, deep power-off entry/exit, and PSRAM reset, and output the instruction valid signal to the sending transmission after performing edge detection on the instruction signal. Module 132.

The transmitting and transmitting module 132 is configured to generate PSRAM transmission signals based on various transmission states when transmitting APB control signals and AHB instruction information.

The receiving and transmitting module 133 is used for cross-clock domain transmission based on the data returned by the physical layer interface, and when the preset conditions are met, the data of the physical layer interface is output, and when the timeout of the data strobe signal is determined according to the timing parameters, the timeout indication is output Signal.

In some embodiments, the receiving and transmitting module 133 further includes an asynchronous FIFO module (not shown in the figure), which is used for cross-clock domain transmission of received data from the data strobe clock DQS to the memory controller clock mem_clk_0. Sampling and reading data with both edges of the received data strobe clock DQS is written into the asynchronous FIFO module, and the data is read and output when the asynchronous FIFO module is not empty. The receiving and transmitting module 133 is also configured to detect whether the DQS is timed out according to timing parameters and output an indication signal.

In some embodiments, referring to FIG. 3 , the sending and transmitting module 132 includes a data shifter 321, which is used to access register modules, read and write storage, semi-sleep/deep power-off entry and exit operations according to various commands, addresses, and data. Status generates PSRAM transfer signals. The data shifter 321 designs an independent state machine (FSM) for various serial input and output (OPI) interfaces to support multiple interfaces and transmission protocols.

In some embodiments, the data shifter 321 includes a plurality of state machines, each state machine corresponds to the type of an eight-way serial input and output interface, and each state machine is for the type of the corresponding eight-way serial input and output interface , generating a PSRAM transfer signal based on each transfer state.

Exemplarily, referring to Fig. 4, the data shifter is provided with three state machines (FSM) 41a, 41b, 41c, and each state machine 41a, 41b, 41c is connected with a pseudo-static memory type multiplexer 42, and the pseudo-static memory type The multiplexer 42 receives the PSRAM type (PSRAM_type) transmission signal, and selects the corresponding state machine 41a, 41b, 41c according to the PSRAM type, and the state machine 41a, 41b, 41c generates the PSRAM transmission signal, and transmits the PSRAM transmission signal to the physical layer interface.

The data shifter provided by the embodiment of the present disclosure is provided with multiple state machines, and each state machine can correspond to one or more similar eight-way serial input and output interfaces, which avoids one state machine being compatible with multiple eight-way serial input and output interfaces. The interface is cumbersome. When an eight-channel serial input and output interface fails, the eight-channel serial input and output interface can be quickly located through the state machine. Moreover, when adding other eight-way serial input and output interfaces, it is only necessary to add a state machine correspondingly, without affecting the original state machine.

Referring to FIG. 3 , the transmission transmission module 132 also includes a timing check module 322 and a write boundary check module 323, wherein the timing check module (timing_checker) 322 is used to generate a first indication signal based on a timing parameter, and transmit the first indication signal to the data shifter 321 . Exemplarily, the timing check module 322 counts according to timing parameters (such as cs pull-down time, half-sleep/deep power-off exit time, etc.), and outputs an indication signal to the data shifter 321 when the time is up.

The write boundary checker (wr_pg_bndry_checker) module 323 is configured to output a second indication signal when it is determined based on the parameters of the storage page and the storage address that the boundary of the storage page is reached. Exemplarily, the write boundary checking module 323 judges whether the write address reaches the boundary according to the storage page size parameter and the storage write address, and outputs an indication signal to the data shifter 321 . The data shift register module 321 transmits the APB control signal and the AHB instruction information in response to the first indication signal and the second indication signal.

In some embodiments, referring to FIG. 2 , the digital controller 1 further includes a first synchronizer 14 and a second synchronizer 15 , and both the first synchronizer 14 and the second synchronizer 15 can be two-stage synchronizers.

Wherein, the first synchronizer 14 is used for cross-clock domain transmission of the timeout signal from the clock signal of the digital controller to the clock signal of the AHB; for example, the first synchronizer 14 gates the data output by the read-write transaction transmission module 13 The timeout signal of the clock is transmitted across the clock domain from the memory controller clock mem_clk_0 to the AHB slave controller clock ahb_clk.

The second synchronizer 15 is used for cross-clock domain transmission of the transmission completion signal from the clock signal of the digital controller to the clock signal of the APB. Exemplarily, the second synchronizer 15 transmits the transmission completion signal output by the read/write transaction transmission module 13 across clock domains from the memory controller clock mem_clk_0 to the APB clock apb_clk (APB clock used for CSR).

FIG. 5 is a working flow chart of the state machine when the register module performs a write operation in an embodiment of the present disclosure. Referring to FIG. 5 , take the state machine 41a receiving the PSRAM type transmission signal of the AP 8M interface as an example.

In step S501, the state machine is in an idle state (IDLE).

Step S502, when the register module access request is valid (reg_xfer_valid=1), the state machine jumps from the idle state to the sending command state (SEND_CMD).

Step S503, within one clock cycle (cmd_cycle_cnt=1), the state machine jumps from the sending command state to the sending address state (ADDR).

Step S504, jumping to the transmission delay state (TX_LATENCY) after two clock cycles (wr_rd=1, addr_cycle_cnt=2).

Step S505, jumping to the sending data state (TX_DATA) after the timer satisfies the waiting clock period (wait_expired).

Step S506, the register module data transmission is fixed at one clock cycle, after one clock cycle (wdata_valid=0), the state machine jumps to the waiting transmission completion state (WAIT_TR_EXPIRY), and returns to the idle state after the sending clock cycle is completed (twc_expired=1) .

It should be noted that when the eight-way serial input and output interfaces are WB 8M and WB 4M interfaces, no delay is required, therefore, step S503 can be directly skipped to step S505.

Through the above steps S501 to S506, the write operation of the register module can be realized.

FIG. 6 is a working flow chart of the state machine when the register module performs a read operation in an embodiment of the present disclosure. Referring to FIG. 6, take the state machine 41a receiving the transmission signal of the AP 8M interface as an example.

In step S601, the state machine is in an idle state (IDLE).

Step S602, when the access request of the register module is valid (reg_xfer_valid=1), the state machine jumps from the idle state to the sending command state (SEND_CMD).

Step S603, within one clock cycle (cmd_cycle_cnt=1), the state machine jumps from the sending command state to the sending address state (ADDR).

Step S604, jump to read data state (RD_DATA) after two clock cycles (wr_rd=0, addr_cycle_cnt=2).

Step S605, after reading the required address length (rd_done=1), jump to the FIFO refresh state (FIFO_FLUSH), and refresh the FIFO to avoid affecting the next reading.

Step S606, jump to waiting for transmission completion state (WAIT_TR_EXPIRY) after FIFO flushing is completed (fifo_flush_done=1), and return to idle state after completion of reading clock cycle (trc_expired=1).

Through the above steps S601 to S606, the read operation of the register module can be realized.

FIG. 7 is a working flowchart of a state machine during a storage write operation in an embodiment of the present disclosure. Referring to FIG. 7, take the state machine 41a receiving the transmission signal of the AP 8M interface as an example.

In step S701, the state machine is in an idle state (IDLE).

Step S702, when the storage access request is valid (mem_xfer_valid=1), the state machine jumps from the idle state to the sending command state (SEND_CMD).

Step S703, within one clock cycle (cmd_cycle_cnt=1), the state machine jumps from the sending command state to the sending address state (ADDR).

Step S704, jumping to the transmission delay state (TX_LATENCY) after two clock cycles (wr_rd=1, addr_cycle_cnt=2).

Step S705, jumping to the sending data state (TX_DATA) after the timer satisfies the waiting clock period (wait_expired).

In step S705, if the address reaches the page boundary, then send up to the data at the boundary, otherwise send all the data.

Step S706, after the data transmission is completed, jump to the state of waiting for transmission completion (WAIT_TR_EXPIRY).

Step S707, judge whether the address reaches the boundary (wr_pg_bndy=1), if so, jump to step S702, and start a write operation from the address after the boundary (step S702 to step S706); When the boundary is reached (twc_expired=1), jump to step S701 and return to the idle state.

Through the above steps S701 to S707, the storage write operation can be realized.

Through the above steps S601 to S606, the read operation of the register module can be realized.

FIG. 8 is a working flowchart of a state machine during a storage read operation in an embodiment of the present disclosure. Referring to FIG. 8, take the state machine 41a receiving the transmission signal of the AP 8M interface as an example.

In step S801, the state machine is in an idle state (IDLE).

Step S802, after the storage access request is valid (reg_xfer_valid=1), jump from the idle state to the sending command state (SEND_CMD).

Step S803, within one clock cycle (cmd_cycle_cnt=1), the state machine jumps from the sending command state to the sending address state (ADDR).

Step S804, jump to read data state (RD_DATA) after two clock cycles (wr_rd=1, addr_cycle_cnt=2).

Step S805, judging whether the data strobe clock (DQS_time_out=1) has timed out, if yes, then jump to step S806; if not, then jump to step S808.

In step S806, the state machine jumps to the read error state (RD_ERROR). After waiting for a preset time length, jump to step S809.

Step S807, the state machine jumps to the FIFO refresh state (FIFO_FLUSH) after reading the required address length (rd_done=1), so as to avoid affecting the next reading.

Step S808 , after the FIFO refresh is completed (fifo_flush_done=1), jump to the wait for transmission completion state (WAIT_TR_EXPIRY), and return to the idle state after the read cycle is completed (trc_expired=1).

Through the above steps S801 to S808, the storage read operation can be realized.

FIG. 9 is a working flow chart of the state machine during semi-sleep operation in the embodiment of the present disclosure. Referring to FIG. 9, take the state machine 41a receiving the transmission signal of the AP 8M interface as an example.

In step S901, the state machine is in an idle state (IDLE).

Step S902, when the semi-sleep access request is valid (hs_xfer_valid=1), the state machine jumps from the idle state to the sending command state (SEND_CMD).

Step S903, within one clock cycle (cmd_cycle_cnt=1), the state machine jumps from the sending command state to the sending address state (ADDR).

Step S904, jumping to the transmission delay state (TX_LATENCY) after two clock cycles (wr_rd=1, addr_cycle_cnt=2).

Step S905, jumping to the sending data state (TX_DATA) after the timer satisfies the waiting clock period (wait_expired).

Step S906, the half-sleep data transmission is fixed as one clock cycle, after one clock cycle (wdata_valid=0), the state machine jumps to the waiting transmission completion state (WAIT_TR_EXPIRY), and returns to the idle state after the sending clock cycle is completed (twc_expired=1) .

Through the above steps S901 to S906, the semi-sleep operation can be realized.

Fig. 10 is a working flow chart of the state machine when exiting half-sleep in an embodiment of the present disclosure. Referring to Figure 10, the steps for exiting the semi-sleep state include:

Step S1001, the state machine is in an idle state (IDLE).

Step S1002, when the exit half-sleep command is valid (hs_exit_valid=1), jump from the idle state to the half-sleep exit state (HS EXIT).

In step S1002, exit the half-sleep state by pulling down the chip select (CE) signal, and the time for pulling down the chip select (CE) signal is sufficient and meets the time when PSRAM exits the half-sleep state and can receive the next command (ce_low_expired=1, txhs_expired=1) Then return to idle state.

It should be noted that the entry and exit operations of the deep power-off are similar to the entry and exit operations of the semi-sleep, and the flow of the state machine is similar, and will not be repeated here. It should also be noted that, in the embodiments of the present disclosure, half-sleep and mixed-sleep are only different in expressions, and when performing an entry/exit operation, both commands and state machine workflows are the same.

FIG. 11 is a schematic structural diagram of a physical layer interface provided by an embodiment of the present disclosure. Referring to Figure 11, the physical layer interface is used to generate memory interface signals and is compatible with different PSRAM interfaces, wherein the PSRAM interface includes but is not limited to AP8M/4M interface and WB 8M/4M interface. Among them, the AP 8M interface is a single-ended clock, and the AP 4M interface and WB 8M/4M interface are differential clocks. The DQS_DM of AP 8M has two functions, including the data strobe clock (DQ strobe clock during reads, DQS) function during reading and the data mask during writing (Data mask during writes, DM) function, while AP4M includes both DQS and DM A signal, and the DQS signal is also required for write operations. The read and write data strobe signal (RWDS) of the WB8M/4M interface is similar to the DQS_DM signal of the AP 8M interface. In the command address phase of the serial input and output bus, the WB 8M/4M interface judges whether additional delay is required. The physical layer interface provided by the embodiments of the present disclosure can output various related signals, and then each type of PSRAM can be connected as required.

The clock gating processing (SCLK_GATE_INST) module 21 is used to generate clock signals SCLK and SCLKN for the PSRAM according to the phase shift memory controller clock and clock enable.

Exemplarily, the clock gating processing module 21 generates clock signals SCLK and SCLKN for the PSRAM according to the phase shift memory controller clock mem_clk_90 and the clock enable sclk_en. Among them, SCLKN and SCLK are a set of differential clocks, that is, they are completely complementary, and N represents the opposite of the clock signal SCLK.

The data input and output selection processing (DQ_OUT_MUX_INST) module 22 is used to split the data input and output into two parts of the storage controller clock according to the high and low levels of the storage controller clock, such as the low byte and high byte of the data input and output .

For example, the data input and output selection processing module 22 splits the data input and output dq_out_ip[15:0] into two parts of the data input and output dq_out[7:0] according to the high and low levels of the memory controller clock mem_clk_0.

In some embodiments, after splitting the data input and output dq_out_ip[15:0], the data input and output dq_out[7:0] and the data input and output enable dq_oe_ip are subjected to tri-state processing through a tri-state gate to obtain a high-removal High-impedance state other than low level and low level.

The data mask output selection processing (DM_OUT_MUX_INST) module 23 is used to enable the data mask to be split into two parts of the data mask when the high and low levels of the storage controller clock are output according to the data mask, such as the low word of the data mask section and high byte.

Exemplarily, the data mask output selection processing module 23 is used to enable dm_oe_ip to split the data mask dm_ip[1:0] into data of two clock cycles when the memory controller clock mem_clk_0 is high or low according to the data mask output enable dm_oe_ip Mask DM.

In some embodiments, DQS not only needs to be used as a DQ strobe, but also needs to be kept as 0 in some phases of the OPI bus. Therefore, the design data strobe clock output enable dqs_oe_ip is 2 bits wide.

The data strobe clock output selection processing (DQS_OUT_MUX_INST) module 24 is used to generate data strobe clock output dqs_out compatible with different PSRAM interfaces based on clock signal, data mask, PSRAM type, and data strobe clock output enable.

In some embodiments, the data strobe clock output selection processing module 24 is used to generate a data strobe clock output dqs_out compatible with different PSRAM interfaces based on the clock signal SCLK, the data mask DM, the PSRAM type, and the data strobe clock output enable dqs_oe_ip , wherein the data strobe clock output dqs_out includes the DQS_DM/RWDS signal.

Illustratively, when dqs_oe_ip is 2, the dqs_out that data strobe clock output selection processing module 24 outputs is 0; When dqs_oe_ip is 1 and psram_type is AP 4M, the dqs_out that data strobe clock output selection processing module 24 outputs is SCLK ; When dqs_oe_ip is 1 and psram_type non-AP 4M, the dqs_out that data strobe clock output selects processing module 24 outputs is DM; When dqs_oe_ip is 0, the dqs_out that data strobe clock output selects processing module 24 outputs is high resistance This ensures that the data strobe clock data mask DQS_DM under the AP 4M interface does not have the DM function.

The data strobe clock gating processing (DQS_GATE_INST) module 25 is used to enable dqs_oe_ip[1:0] to gate the input data strobe clock data mask DQS_DM based on the data strobe clock output to obtain the data strobe clock input signal dqs_in. In some embodiments, during the non-data phase, dqs_in remains at 0 to avoid interference with the sampling of read data.

In some embodiments, because the DQS_DM of the WB 8M/4M interface indicates whether additional delay is required at the OPI bus command address stage, the physical layer interface additionally outputs the data strobe clock that has not been processed by the data strobe clock gating processing module 25 Initial value dqs_initial, and output dqs_initial to the digital controller.

The data strobe clock selection operation completion delay (DQS_MUXED_DELAY) module 26 is used to physically delay the data strobe clock input signal (dqs_in), so that the data returned by PSRAM lags behind the data strobe clock to meet the flip-flops required for sampling build time.

In the embodiment of the present disclosure, the data strobe clock selection operation completion delay module 26 physically delays the data strobe clock input signal (dqs_in), so that the data returned by PSRAM lags behind the data strobe clock, so as to meet the trigger required for sampling to ensure successful sampling.

In some embodiments, because the data input and output returned by the PSRAM will lag behind the data strobe clock (for example, a few tenths of a nanosecond behind), considering that at different SCLK frequencies, the time of the data input and output returned by the PSRAM behind the data strobe clock is different. , the data strobe clock selection operation completion delay module 26 adopts a multi-stage delay.

In some embodiments, the data strobe clock selection operation completion delay module 26 includes a physical control register module, which is used to select delay stages, and each delay stage corresponds to a different delay time.

For example, each stage of delay can select the number of delay stages through the physical control register module phy_ctrl_reg0, and each stage of delay uses an input-output buffer (IOBUF). Chip select low effective ce_n_ip can be directly output as CE_N.

The controller for the pseudo-static random access memory provided by the embodiment of the present disclosure includes a digital controller and a physical layer interface, wherein the digital controller generates a pseudo-static random access memory adapted to the type of the eight-way serial input and output interface based on an operation request. The random access memory PSRAM transmits the signal, so that the PSRAM transmission signal is applicable to different PSRAM interfaces; the physical layer interface generates the PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal. Since the PSRAM interface signal is generated according to the type of the PSRAM interface, Therefore, the generated PSRAM interface signals can be compatible with different types of PSRAM interfaces and transmission protocols, so that the controller can support different PSRAM chips and improve the flexibility of PSRAM chip selection.

The embodiment of the present disclosure also provides a control method for a pseudo-static random access memory, which is based on the controller for a pseudo-static random access memory provided by an embodiment of the present disclosure. Provides a controller for pseudo-static random access memory.

FIG. 12 is a flowchart of a control method for a pseudo-static random access memory provided by an embodiment of the present disclosure. Referring to Figure 12, the control methods include:

Step S1201, receiving an operation request.

Wherein, the operation request can be transmitted to the controller through the APB bus and the AHB bus, and the operation request includes but not limited to a storage read and write request and a register module access request. Exemplarily, the operation request may be a read-write request or a read-write request from the APB or AHB.

Step S1202, generating a PSRAM transmission signal adapted to the type of the eight-channel serial input and output interface based on the operation request.

In some embodiments, the PSRAM transmission signals include read and write commands, entering/exiting semi-sleep (hybrid sleep), entering/exiting transmission signals corresponding to each state in the deep power-off operation.

Step S1203, for generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal.

The control method for the pseudo-static random access memory provided by the embodiment of the present disclosure generates a pseudo-static random access memory PSRAM transmission signal adapted to the type of the eight-way serial input and output interface based on the operation request, so that the PSRAM transmission signal is applicable to different PSRAM interface; based on the PSRAM transmission signal, a PSRAM interface signal adapted to the type of the PSRAM interface is generated. Since the PSRAM interface signal is generated according to the type of the PSRAM interface, the generated PSRAM interface signal can be compatible with different types of PSRAM interfaces and transmission protocols. The controller can support different PSRAM chips, and the flexibility of PSRAM chip selection is improved.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a program segment, or a portion of an instruction that contains one or more executable instruction. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

Example embodiments have been disclosed herein, and while specific terms have been employed, they are used and should be construed in a generic descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be described in combination with other embodiments, unless explicitly stated otherwise. Combinations of features and/or elements. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims (11)

1. a kind of controller for pseudo-static random access memory, it is characterized in that, comprise digital controller and physical layer interface, the input end of described physical layer interface is connected with described digital controller, output end is connected with pseudo-static random access memory PSRAM interface connection, where: The digital controller is configured to receive an operation request, and generate a PSRAM transmission signal adapted to the type of the eight-way serial input and output interface based on the operation request; The physical layer interface is configured to generate a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal. 2. The controller according to claim 1, wherein the operation request comprises an Advanced Peripheral Bus APB operation request and a High Performance Bus AHB operation request; The digital controller includes: The register module is used to generate APB control signals and timing parameters based on the received APB operation request, and receive and store the transmission status signal; The AHB slave control module is used to respond to the received AHB operation request, obtain AHB command information based on the APB control signal and timing parameters; and transmit the received transmission status information of the PSRAM to the AHB master; A read-write transaction transmission module, configured to generate the PSRAM transmission signal based on the APB control signal and the AHB instruction information, and receive an operation request and a clock signal from the physical layer interface, and based on the clock signal Sampling the operation request, and transmitting the sampling result to the AHB slave control module. 3. The controller according to claim 2, wherein the read-write transaction transmission module comprises: A command processing module, configured to perform edge detection on the received APB control signal, and output an APB control valid signal and an APB transmission signal; The receiving and transmitting module is configured to perform cross-clock domain transmission based on the data returned by the physical layer interface, and output the data of the physical layer interface when a preset condition is satisfied, and determine when the data strobe signal times out according to the timing parameters , output a timeout indication signal; The sending transmission module is configured to generate the PSRAM transmission signal based on each transmission state when transmitting the APB control signal and the AHB instruction information. 4. The controller according to claim 3, wherein the sending transmission module includes a data shift register module, and the data shift register module includes a plurality of state machines, each of which is connected to one of the state machines Corresponding to the type of the eight-way serial input-output interface, each of the state machines generates the PSRAM transmission signal based on each transmission state for the corresponding type of the eight-way serial input-output interface. 5. The controller according to claim 3, wherein the sending transmission module further comprises: a timing checking module, configured to generate a first indication signal based on the timing parameters; A write boundary check module, configured to output a second indication signal when the boundary of the storage page is determined based on the parameters of the storage page and the storage address; The data shift register module transmits the APB control signal and the AHB instruction information in response to the first indication signal and the second indication signal. 6. The controller according to claim 2, wherein the digital controller further comprises: a first synchronizer for cross-clock domain transmission of a timeout signal from the clock signal of the digital controller to the clock signal of the AHB; The second synchronizer is used to transmit the transmission completion signal across clock domains from the clock signal of the digital controller to the clock signal of the APB. 7. The controller according to claim 1, wherein the APB operation request comprises one or more of an APB read request and an APB write request; The AHB operation request includes one or more of an AHB read request and an AHB write request. 8. The controller according to claim 1, wherein the physical layer interface comprises: A clock gating processing module, configured to generate clock signals SCLK and SCLKN for the PSRAM according to the phase-shift memory controller clock and clock enable; The data input and output selection processing module is used to split the data input and output into two parts of the storage controller clock according to the high and low levels of the storage controller clock; The data mask output selection processing module is used to enable the data mask to be split into two parts of the data mask when the storage controller clock is high or low according to the data mask output; The data strobe clock output selection processing module is used to generate a data strobe clock output compatible with different PSRAM interfaces based on the clock signal, data mask, PSRAM type, and data strobe clock output enable; A data strobe clock gating processing module, configured to gate the input data strobe clock data mask based on the data strobe clock output to obtain a data strobe clock input signal; The data strobe clock selection operation completion delay module is used for physically delaying the input signal of the data strobe clock, so that the data returned by the PSRAM lags behind the data strobe clock. 9. The controller according to claim 8, wherein the data strobe clock selection operation completion delay module includes a physical control register module, and the physical control register module is used to select the number of delay stages, each of the The delay series correspond to different delay times. 10. A control method based on the controller for pseudo-static random access memory described in any one of claims 1-9, characterized in that, comprising: Receive operation requests; generating a PSRAM transmission signal adapted to the type of the eight-way serial input and output interface based on the operation request; and generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal. 11 . The control method according to claim 10 , wherein the PSRAM transmission signals include transmission signals corresponding to transmission states in read and write commands, entering/exiting semi-sleep, and entering/exiting deep power-off operation.

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