CN116092552A - Controller and control method for pseudo-static random access memory - Google Patents

Abstract

The present disclosure provides a controller and a control method for a pseudo static random access memory. The controller includes: the digital controller is used for receiving an operation request and generating PSRAM transmission signals which are adaptive to the types of the eight paths of serial input/output interfaces based on the operation request; the input end of the physical layer interface is connected with the digital controller, and the output end is connected with the PSRAM interface and used for generating a PSRAM interface signal which is adaptive to the type of the PSRAM interface based on the PSRAM transmission signal. According to the controller provided by the embodiment of the disclosure, different PSRAM chips can be supported, and the flexibility of PSRAM chip selection is improved.

Description

Controller and control method for pseudo-static random access memory

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a controller and a control method for a pseudo-static random access memory.

Background

pseudo-Static Random Access Memory (PSRAM) (Pseudo Static Random Access Memory) is a process and technology that uses dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) to implement Random Access Memory (Random Access Memory, RAM) similar to Static Random Access Memory (SRAM).

The PSRAM interface is an SRAM interface which is compatible with the SRAM and similar to the SRAM in terms of access time sequence and other characteristics by modifying the DRAM interface and changing a refresh circuit into a self-refresh (self-refresh) circuit, and has the advantages of low cost, low power consumption, high memory density, simplicity of the SRAM interface and the like.

Disclosure of Invention

The present disclosure provides a PSRAM controller and a control method.

In a first aspect, the present disclosure provides a controller for a pseudo-static random access memory, comprising: the system comprises a digital controller and a physical layer interface, wherein the input end of the physical layer interface is connected with the digital controller, and the output end of the physical layer interface is connected with the pseudo static random access memory PSRAM interface, wherein:

the digital controller is used for receiving an operation request and generating PSRAM transmission signals which are adaptive to the types of eight paths of serial input/output interfaces based on the operation request;

the physical layer interface is configured to generate a PSRAM interface signal adapted to a type of the PSRAM interface based on the PSRAM transmission signal.

In a second aspect, the present disclosure provides a control method for a controller of a pseudo-static random access memory according to any one of the present disclosure, including:

receiving an operation request;

generating a pseudo static random access memory PSRAM transmission signal which is adaptive to the type of the eight paths of serial input/output interfaces based on the operation request;

and generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal.

The controller for the pseudo-static random access memory provided by the embodiment of the disclosure comprises a digital controller and a physical layer interface, wherein the digital controller generates pseudo-static random access memory PSRAM transmission signals which are adaptive to the types of the eight paths of serial input/output interfaces based on operation requests, so that the PSRAM transmission signals are applicable to different PSRAM interfaces; the physical layer interface generates PSRAM interface signals which are adaptive to the type of the PSRAM interface based on the PSRAM transmission signals, and the PSRAM interface signals are generated according to the type of the PSRAM interface, so that the generated PSRAM interface signals can be compatible with PSRAM interfaces and transmission protocols of different types, different PSRAM chips can be supported by a controller, and the flexibility of PSRAM chip selection is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

fig. 1 is a schematic structural diagram of a PSRAM controller according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a digital controller according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a sending transmission module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a state machine in a data shifter according to an embodiment of the present disclosure;

FIG. 5 is a flowchart of the operation of the state machine of the register module when performing a write operation in an embodiment of the present disclosure;

FIG. 6 is a flowchart of the operation of the state machine of the register module when performing a read operation in an embodiment of the present disclosure;

FIG. 7 is a workflow diagram of a state machine at the time of a store write operation in an embodiment of the present disclosure;

FIG. 8 is a workflow diagram of a state machine at the time of a store read operation in an embodiment of the present disclosure;

FIG. 9 is a workflow diagram of a state machine at semi-sleep operation in an embodiment of the present disclosure;

FIG. 10 is a workflow diagram of a state machine upon exiting semi-sleep in an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a physical layer interface according to an embodiment of the disclosure;

fig. 12 is a flowchart of a control method for a pseudo-static random access memory according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Each manufacturer has a respective PSRAM interface specification, such as HyperBus Interface interface specification, APM OPI interface specification and Xccela OPI interface specification, and these several interface protocols all use OPI (Octal SPI, eight-way Data serial input output) and DDR (Double Data Rate), but they are very different in terms of the number and functions of control signals, read-write transmission protocol, access of register modules inside the chip, and entry and exit of half sleep (deep power down) modes. However, the related PSRAM interfaces cannot be flexibly configured according to the PSRAM chip, so that the PSRAM interfaces can only support a certain type of interfaces, and the practical requirements of being compatible with multiple PSRAM interfaces cannot be met.

Fig. 1 is a schematic structural diagram of a PSRAM controller according to an embodiment of the present disclosure. Referring to fig. 1, the PSRAM controller includes a digital controller 1 and a physical layer interface 2, wherein the digital controller 1 is configured to receive access requests (including but not limited to read and write requests) and to be compatible and control different PSRAM chips. The input end of the physical layer interface 2 is connected with the digital controller 1, and the output end is connected with the PSRAM interface and used for generating PSRAM interface signals which are adaptive to the type of the PSRAM interface based on the PSRAM transmission signals so as to exchange information with different PSRAM chips.

It should be noted that, in the embodiment of the present disclosure, the digital controller 1 may have a plurality of input terminals and a plurality of output terminals, and the number of the input terminals and the number of the output terminals may be set according to needs, which is not limited in the embodiment of the present disclosure. The physical layer interface 2 may have a plurality of input terminals and a plurality of output terminals, and the number of the input terminals and the output terminals may be set as required, which is not limited by the embodiment of the present disclosure.

In some embodiments, the digital controller 1 is configured to receive the operation request, and generate a pseudo static random access memory PSRAM transmission signal adapted to the type of the eight-way serial input output interface based on the operation request. In the embodiment of the disclosure, the digital controller 1 includes two input terminals respectively connected to the APB bus and the AHB bus. The operation request may be transmitted to the controller via the APB bus and the AHB bus, and the operation request includes, but is not limited to, a read-write request and a register module access request. The PSRAM transmission signal is a signal that the PSRAM can recognize. The PSRAM transmission signals comprise a read-write command, a half sleep entering/exiting (mixed sleep) and transmission signals corresponding to each transmission state in a deep power-off entering/exiting operation.

In some embodiments, the physical layer interface 2 has an input connected to the digital controller 1 and an output connected to the PSRAM interface for generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transfer signal. The PSRAM interfaces include, but are not limited to, an interface corresponding to AP 8M APs6408L-OBMx DDR OPI Xccela PSRAM, an interface corresponding to AP 4M APs3208K-OTx OPI DDR PSRAM, an interface corresponding to WB8M W956D8MBYA, and an interface corresponding to WB 4M W955D8MBYA (hereinafter, simply referred to as AP 8M interface, AP 4M interface, WB8M interface, and WB 4M interface, respectively, for convenience of description).

In the embodiment of the disclosure, an input end of the physical layer interface 2 is connected with the digital controller 1, and an output end of the physical layer interface 2 is connected with the PSRAM interface, and is used for generating a PSRAM interface signal adapted to a type of the PSRAM interface based on the PSRAM transmission signal, and transmitting a timing sequence together with the digital controller 1. The physical layer interface 2 in the embodiment of the disclosure may be compatible with various PSRAM interfaces, such as an AP 8M interface, an AP 4M interface, a WB8M interface, and a WB 4M interface.

In some embodiments, there are two interfaces at the input (system side) of the digital controller 1, namely an advanced peripheral bus (Advanced Peripheral Bus, APB) interface and an advanced high-performance bus (Advanced High Performance Bus, AHB-Lie) interface. The APB interface is used to access control and status register modules (Control and Status Register, CSR) within the digital controller 1. The AHB-Lite interface is used for memory array write/read and mode register module write/read in PSRAM memory devices based on CSR settings. The output end of the digital controller 1 is connected with the input end of the physical layer interface 2.

In some embodiments, the memory controller clock mem_clk_0 and the phase-shifted memory controller clock mem_clk_90 are input to the digital controller 1 and the physical layer interface 2, and the memory controller clock mem_clk_90 is the same frequency as the phase-shifted memory controller clock mem_clk_0, but is phase-delayed by 90 degrees.

Fig. 2 is a block diagram of a digital controller according to an embodiment of the present disclosure. As shown in fig. 2, the digital controller 1 includes a register module 11, an AHB slave control module 12, a read-write transaction transmission module 13, a first synchronizer 14 and a second synchronizer 15, where the register module 11 is in signal connection with the AHB slave control module 12 and the read-write transaction transmission module 13, and the AHB slave control module 12 is in signal connection with the register module 11 and the read-write transaction transmission module 13.

The register module 11 is connected with an APB interface signal as a slave of the APB. The register module 11 includes a control and status register module that receives APB write transactions and outputs control signals and timing parameters to the AHB slave control module 12 and the read-write transaction transfer module 13. The register module 11 is also used for receiving and storing status signals.

In some embodiments, the register module 11 is configured to generate APB control signals and timing parameters based on a received APB operation request, and to receive and store transmission status signals.

Wherein the APB operation request includes one or more of an APB read request, an APB write request. The transfer state signals include, but are not limited to, PSRAM access transfer state, data strobe clock (Data Strobe clock, DQS) timeout signal, DPD/HALF SLEEP entry exit, completion signal of GLOBAL RESET instruction.

The AHB slave control module 12 is configured to obtain AHB instruction information based on the APB control signal and the timing parameter in response to the received AHB operation request; and transmitting the received transmission state information of the PSRAM to the AHB host. Wherein the AHB operation request includes one or more of an AHB read request and an AHB write request.

Illustratively, the AHB slave control module 12 parses the AHB read-write transaction and outputs the transfer parameters (transfer type, read-write length, transfer size), read-write address, and write data. The AHB slave control module 12 includes an asynchronous first-in first-out (FIFO) module (not shown) for clock domain-crossing synchronization and buffering of command addresses and data between the AHB slave controller clock AHB _clk and the memory controller clock mem_clk_0. The AHB slave control module 12 is further configured to receive a timeout signal of the data strobe clock, and to feed back a transmission status to the AHB master.

The read-write transaction transmission module 13 is configured to generate a PSRAM transmission signal based on the APB control signal and the AHB instruction information, receive PSRAM read data and a clock signal from the physical layer interface 2, sample an operation request based on the clock signal, and transmit a sampling result to the AHB slave control module; and receiving the transmission status signal.

The AHB instruction information includes, but is not limited to, a transmission parameter (transmission type, read-write length, transmission size), a read-write address, and read-write data.

The read-write transaction transmission module 13 is used for realizing PSRAM storage and read-write transaction transmission of the register module, and the read-write transaction transmission module 13 receives a control signal from the register module 11 and command address and write data of the AHB slave control module 12 to generate a PSRAM transmission signal to the physical layer interface 2; and receives the read data and the clock signal from the physical layer interface 2, samples the read data and the clock signal, and outputs the sampled read data and clock signal to the AHB slave control module 12. The read-write transaction transmission module 13 also outputs a plurality of status indication signals including a timeout signal of a data strobe clock (DQS) for indicating whether DQS returns to timeout, a transmission completion signal for indicating the completion of each instruction, and the like.

In some embodiments, the read/write transaction transmission module 13 includes a command processing (instrn_handover) module 131, a transmit transmission (tx_path) module 132, and a receive transmission (rx_path) module 133, wherein the command processing module 131 is configured to process various instructions from the register module 11, such as edge detection for received APB control signals, and output APB control valid signals and APB transmission signals. In some embodiments, the instructions output by the register module 11 include, but are not limited to, read/write transfer, semi-sleep entry/exit, deep power down entry/exit, and PSRAM reset, and the edge detection of the instruction signal outputs an instruction valid signal to the send transfer module 132.

The transmission module 132 is configured to generate a PSRAM transmission signal based on each transmission state when transmitting the APB control signal and the AHB instruction information.

The receiving and transmitting module 133 is configured to perform cross-clock domain transmission based on data returned by the physical layer interface, output the data of the physical layer interface when a preset condition is satisfied, and output a timeout indication signal when determining that the data strobe signal is timeout according to the timing parameter.

In some embodiments, the receive transfer module 133 further includes an asynchronous FIFO module (not shown) for receiving cross-clock domain transfers of data from the data strobe clock DQS to the memory controller clock mem_clk_0. And the received data strobe clock DQS is used for double-edge sampling and reading data, then the data is written into the asynchronous FIFO module, and the data is read out and output when the asynchronous FIFO module is not empty. The receiving and transmitting module 133 is further configured to detect whether the DQS is overtime and output an indication signal according to the timing parameter.

In some embodiments, referring to FIG. 3, the transmit transfer module 132 includes a data shifter 321 for generating PSRAM transfer signals in accordance with various commands, addresses and data in various states of access register module, read-write memory, semi-sleep/deep power down access operations. The data shifter 321 designs a separate state machine (FSM) for various types of serial input Output (OPI) interfaces to support a variety of interfaces and transport protocols.

In some embodiments, the data shifter 321 includes a plurality of state machines, each state machine corresponding to a type of eight serial input output interface, each state machine generating a PSRAM transmit signal based on a respective transmit state for the type of eight serial input output interface corresponding thereto.

For example, referring to fig. 4, the data shifter sets three state machines (FSMs) 41a, 41b, 41c, each state machine 41a, 41b, 41c is connected to a pseudo static memory type multiplexer 42, the pseudo static memory type multiplexer 42 receives a PSRAM type (psram_type) transmission signal and selects the corresponding state machine 41a, 41b, 41c according to the PSRAM type, and the state machine 41a, 41b, 41c generates the PSRAM transmission signal and transmits the PSRAM transmission signal to the physical layer interface.

According to the data shifter provided by the embodiment of the disclosure, the plurality of state machines are arranged, each state machine can correspond to one or more similar eight-way serial input/output interfaces, the trouble caused by the fact that one state machine is compatible with the plurality of eight-way serial input/output interfaces is avoided, and when a certain eight-way serial input/output interface fails, the eight-way serial input/output interfaces can be positioned quickly through the state machines. When other eight paths of serial input/output interfaces are added, the state machines are correspondingly added, and the original state machines are not affected.

Referring to fig. 3, the sending transmission module 132 further includes a timing checking module 322 and a write boundary checking module 323, wherein the timing checking module (timing_tracker) 322 is configured to generate a first indication signal based on the timing parameter, and transmit the first indication signal to the data shifter 321. Illustratively, the timing check module 322 clocks according to timing parameters (e.g., cs pull-down time, exit time of half sleep/deep power down, etc.), and outputs an indication signal to the data shifter 321 after the time arrives.

The write boundary check (wr_pg_bs_tracker) module 323 is configured to output a second indication signal when determining that a boundary of a memory page is reached based on a parameter of the memory page and a memory address. Illustratively, the write boundary check module 323 determines whether the write address reaches a boundary based on the memory page size parameter and the memory write address and outputs an indication signal to the data shifter 321. The data shift register module 321 transmits APB control signals and AHB instruction information in response to the first and second instruction signals.

In some embodiments, referring to fig. 2, the digital controller 1 further includes a first synchronizer 14 and a second synchronizer 15, and both the first synchronizer 14 and the second synchronizer 15 may employ two stages of synchronizers.

Wherein the first synchronizer 14 is configured to transmit a timeout signal from a clock signal of the digital controller to a clock signal of the AHB across clock domains; illustratively, the first synchronizer 14 transmits the timeout signal of the data strobe clock output by the read-write transaction transmission module 13 from the memory controller clock mem_clk_0 to the AHB slave controller clock AHB _clk across clock domains.

The second synchronizer 15 is used for cross-clock domain transmission of the transmission completion signal from the clock signal of the digital controller to the clock signal of the APB. Illustratively, the second synchronizer 15 transfers the transfer completion signal output by the read-write transaction transfer module 13 from the memory controller clock mem_clk_0 to the APB clock apb_clk (APB clock for CSR) across clock domains.

FIG. 5 is a flowchart of the operation of the state machine of the register module when performing a write operation in an embodiment of the present disclosure. Referring to fig. 5, a state machine 41a receives PSRAM type transmission signals of the AP 8M interface as an example.

In step S501, the state machine is in an IDLE state (IDLE).

In step S502, after the register module access request is valid (reg_xfer_valid=1), the state machine jumps from the idle state to the SEND command state (send_cmd).

In step S503, the state machine jumps from the send command state to the send address state (ADDR) within one clock cycle (cmd_cycle_cnt=1).

In step S504, after two clock cycles (wr_rd=1, addr_cycle_cnt=2), the transmission delay state (tx_latency) is skipped.

In step S505, the process jumps to the transmit DATA state (tx_data) after the timer satisfies the wait clock period (wait_expire).

In step S506, the register module data transmission is fixed to one clock cycle, and after one clock cycle (wdata_avalid=0), the state machine jumps to the WAIT for transmission completion state (wait_tr_expry), and returns to the idle state after the transmission clock cycle is completed (twc _expied=1).

Note that, when the eight-way serial input/output interface is WB8M and WB 4M, no delay is required, and therefore, the process may jump from step S503 to step S505 directly.

Through the above steps S501 to S506, a register module write operation can be realized.

FIG. 6 is a flowchart of the operation of the state machine of the register module when performing a read operation in an embodiment of the present disclosure. Referring to fig. 6, the state machine 41a receives a transmission signal of the AP 8M interface as an example.

In step S601, the state machine is in an IDLE state (IDLE).

In step S602, when the access request of the register module is valid (reg_xfer_valid=1), the state machine jumps from the idle state to the SEND command state (send_cmd).

In step S603, the state machine jumps from the send command state to the send address state (ADDR) within one clock cycle (cmd_cycle_cnt=1).

In step S604, after two clock cycles (wrrd=0, addr_cycle_cnt=2), the read DATA state (rd_data) is skipped.

In step S605, after reading the required address length (rd_done=1), the process jumps to the FIFO refresh state (fifo_flush) and the FIFO is refreshed to avoid affecting the next reading.

In step S606, after FIFO refresh is completed (fifo_flush_done=1), the process jumps to a WAIT for transmission completion state (wait_tr_expry), and after completion of the read clock period (trc_expied=1), the process returns to an idle state.

Through the above steps S601 to S606, a read operation of the register module can be realized.

FIG. 7 is a workflow diagram of a state machine at the time of a store write operation in an embodiment of the present disclosure. Referring to fig. 7, the state machine 41a receives a transmission signal of the AP 8M interface as an example.

In step S701, the state machine is in an IDLE state (IDLE).

In step S702, when the memory access request is valid (mem_xfer_valid=1), the state machine jumps from the idle state to the SEND command state (send_cmd).

In step S703, the state machine jumps from the send command state to the send address state (ADDR) within one clock cycle (cmd_cycle_cnt=1).

In step S704, after two clock cycles (wr_rd=1, addr_cycle_cnt=2), the transmission delay state (tx_latency) is skipped.

Step S705, jump to the transmit DATA state (tx_data) after the timer has satisfied the wait clock period (wait_expire).

In step S705, if the address reaches the page boundary, it is sent to the data at the boundary, otherwise, all the data is sent.

Step S706, after the completion of data transmission, jumps to a WAIT for transmission completion state (wait_tr_expry).

Step S707, determining whether the address reaches the boundary (wr_pg_bypass=1), if so, jumping to step S702, and starting a write operation from the address after the boundary (steps S702 to S706); if not, it indicates that the address does not reach the boundary (twc _expired=1) after the completion of the transfer, and the process goes to step S701 to return to the idle state.

Through the above steps S701 to S707, a memory write operation can be realized.

Through the above steps S601 to S606, a read operation of the register module can be realized.

FIG. 8 is a workflow diagram of a state machine at the time of a store read operation in an embodiment of the present disclosure. Referring to fig. 8, a state machine 41a receives a transmission signal of the AP 8M interface is taken as an example.

In step S801, the state machine is in an IDLE state (IDLE).

Step S802, after the storage access request is valid (reg_xfer_valid=1), jumps from the idle state to the SEND command state (send_cmd).

In step S803, the state machine jumps from the send command state to the send address state (ADDR) within one clock cycle (cmd_cycle_cnt=1).

In step S804, after two clock cycles (wr_rd=1, addr_cycle_cnt=2), the read DATA state (rd_data) is skipped.

Step S805, determining whether the data strobe clock (dqs_time_out=1) is overtime, if yes, jumping to step S806; if not, go to step S808.

In step S806, the state machine jumps to the read ERROR state (RD_ERROR). After waiting for the preset time length, the process goes to step S809.

In step S807, the state machine jumps to the FIFO refresh state (fifo_flush) after reading the required address length (rd_done=1) to avoid affecting the next reading.

In step S808, the FIFO refresh is completed (fifo_flush_done=1), and then the transmission WAIT state (wait_tr_expry) is skipped, and the idle state is returned after the read cycle is completed (trc_expied=1).

Through the above steps S801 to S808, a memory read operation can be realized.

Fig. 9 is a workflow diagram of a state machine at half sleep operation in an embodiment of the present disclosure. Referring to fig. 9, the state machine 41a receives a transmission signal of the AP 8M interface as an example.

In step S901, the state machine is in an IDLE state (IDLE).

In step S902, after the semi-sleep access request is valid (hs_xfer_valid=1), the state machine jumps from the idle state to the SEND command state (send_cmd).

In step S903, the state machine jumps from the send command state to the send address state (ADDR) within one clock cycle (cmd_cycle_cnt=1).

In step S904, the transmission delay state (tx_latency) is skipped after two clock cycles (wr_rd=1 and addr_cycle_cnt=2) are continued.

In step S905, the process jumps to the transmit DATA state (tx_data) after the timer satisfies the wait clock period (wait_expire).

In step S906, the semi-sleep data transmission is fixed to one clock cycle, and after one clock cycle (wdata_avalid=0), the state machine jumps to the WAIT for transmission completion state (wait_tr_expry), and returns to the idle state after the transmission clock cycle is completed (twc _expied=1).

Through the above steps S901 to S906, the semi-sleep operation can be achieved.

FIG. 10 is a flowchart of the operation of the state machine when exiting semi-sleep in an embodiment of the present disclosure. Referring to fig. 10, the step of exiting the semi-sleep state includes:

in step S1001, the state machine is in an IDLE state (IDLE).

In step S1002, when the EXIT half sleep command is valid (hs_exit_valid=1), the process jumps from the idle state to the half sleep EXIT state (HS EXIT).

In step S1002, the semi-sleep state is exited by pulling down a chip select (CE) signal, and the idle state is returned after the pull down time is sufficient and the PSRAM is satisfied to exit the semi-sleep state until the time (ce_low_acknowledge=1, txhs_acknowledge=1) at which the next command can be received.

It should be noted that, the deep power down entry and exit operation is similar to the semi-sleep entry and exit operation, and the flow of the state machine is not described here again. It should be further noted that, in the embodiment of the present disclosure, the half sleep and the mixed sleep are merely different expressions, and the command and the workflow of the state machine are the same when the entering/exiting operation is performed.

Fig. 11 is a schematic structural diagram of a physical layer interface according to an embodiment of the present disclosure. Referring to fig. 11, the physical layer interface is used to generate memory interface signals while being compatible with different PSRAM interfaces including, but not limited to, an AP 8M/4M interface and a WB8M/4M interface. The AP 8M interface is a single-ended clock, and the AP 4M interface and the WB8M/4M interface are differential clocks. DQS_DM of AP 8M has two functions, including a data strobe clock (DQ strobe clock during reads, DQS) function during read and a data mask (Data mask during writes, DM) function during write, while AP 4M includes both DQS and DM signals and the DQS signal is also required for write operations. The read-write data strobe signal (RWDS) of the WB8M/4M interface is similar to the DQS_DM signal of the AP 8M interface, and the WB8M/4M interface judges whether additional delay is required in the command address stage of the serial input/output bus. The physical layer interface provided by the embodiment of the disclosure can output various related signals, and then can be connected with each PSRAM as required.

The clock gating process (sclk_gate_inst) module 21 is used to generate clock signals SCLK and SCLKN for PSRAM from the phase-shifted memory controller clock and clock enable.

Illustratively, the clock gating processing module 21 generates the clock signals SCLK and SCLK for PSRAM from the phase-shifted memory controller clock mem_clk_90 and the clock enable sclk_en. Wherein SCLK and SCLK are a set of differential clocks, i.e., are fully complementary, and N is the inverse of clock signal SCLK.

The data input/output selection process (dq_out_mux_inst) block 22 is configured to split the data input/output into two parts of the memory controller clock, i.e., a low byte and a high byte of the data input/output, according to the high and low levels of the memory controller clock.

Illustratively, the data input/output selection processing module 22 splits the data input/output dq_out_ip [15:0] into two portions of data input/output dq_out [7:0] according to the high and low levels of the memory controller clock mem_clk_0.

In some embodiments, after splitting the data input/output dq_out_ip [15:0], the data input/output dq_out [7:0] and the data input/output enable dq_oe_ip are tri-stated through a tri-state gate to obtain a high impedance state except a high level and a low level.

The data mask output selection process (dm_out_mux_inst) block 23 is for splitting the data mask into two parts of data mask, i.e., low and high bytes of the data mask, according to the data mask output enable at the high and low levels of the memory controller clock.

Illustratively, the data mask output selection processing module 23 is configured to split the data mask dm_ip [1:0] into two clock cycles of the data mask DM according to the data mask output enable dm_oe_ip when the memory controller clock mem_clk_0 is at a high-low level.

In some embodiments, DQS is required to remain at 0 not only as DQ strobe, but also at some stage of the OPI bus, thus designing the data strobe clock output enable dqs_oe_ip to be 2bit wide.

The data strobe clock output selection process (dqs_out_mux_inst) block 24 is operable to generate a data strobe clock output dqs_out compatible with different PSRAM interfaces based on the clock signal, the data mask, the type of PSRAM, and the data strobe clock output enable.

In some embodiments, the data strobe clock output selection processing module 24 is configured to generate a data strobe clock output dqs_out compatible with different PSRAM interfaces based on the clock signal SCLK, the data mask DM, the PSRAM type, the data strobe clock output enable dqs_oe_ip, wherein the data strobe clock output dqs_out comprises dqs_dm/RWDS signals.

Illustratively, when dqs_oe_ip is 2, the dqs_out output by the data strobe clock output selection processing module 24 is 0; when dqs_oe_ip is 1 and psram_type is AP 4M, dqs_out output by the data strobe clock output selection processing module 24 is SCLK; when dqs_oe_ip is 1 and the psram_type is not AP 4M, the dqs_out output by the data strobe clock output selection processing module 24 is DM; when dqs_oe_ip is 0, dqs_out output by the data strobe clock output selection processing module 24 is high-impedance, thus ensuring that the data strobe clock data mask dqs_dm under the AP 4M interface has no DM function.

The data strobe clock gating process (dqs_gate_inst) module 25 is configured to GATE the input data strobe clock data mask dqs_dm based on the data strobe clock output enable dqs_oe_ip [1:0], to obtain the data strobe clock input signal dqs_in. In some embodiments, dqs_in remains at 0 during the non-data phase, avoiding interference with the sampling of read data.

In some embodiments, because DQS_DM of the WB8M/4M interface indicates whether additional delay is required in the OPI bus command address phase, the physical layer interface additionally outputs a data strobe clock initial value dqs_initial that is not processed by the data strobe clock gating processing module 25 and outputs dqs_initial to the digital controller.

The data strobe clock select operation completion DELAY (dqs_muxed_delay) module 26 is used to physically DELAY the data strobe clock input signal (dqs_in) so that the data returned by the PSRAM lags the data strobe clock to meet the trigger setup time required for sampling.

In the disclosed embodiment, the data strobe clock selection operation completion delay module 26 physically delays the data strobe clock input signal (dqs_in) such that the data returned by the PSRAM lags the data strobe clock to meet the trigger setup time required for sampling, thereby ensuring successful sampling.

In some embodiments, the data strobe clock selection completion delay module 26 employs a multi-stage delay in view of the time difference of the data input and output returned by the PSRAM to the data strobe clock at different SCLK frequencies, as the data input and output returned by the PSRAM may lag the data strobe clock (e.g., lag by a fraction of a nanosecond).

In some embodiments, the data strobe clock selection operation completion delay module 26 includes a physical control register module for selecting a number of delay stages, each corresponding to a different delay time.

For example, each level of delay may select a delay progression through a physical control register module phy_ctrl_reg0, with each level of delay employing an input-output buffer (IOBUF). The chip select low active ce_n_ip can be directly output as ce_n.

The controller for the pseudo-static random access memory provided by the embodiment of the disclosure comprises a digital controller and a physical layer interface, wherein the digital controller generates pseudo-static random access memory PSRAM transmission signals which are adaptive to the types of eight paths of serial input/output interfaces based on operation requests, so that the PSRAM transmission signals are applicable to different PSRAM interfaces; the physical layer interface generates PSRAM interface signals which are adaptive to the type of the PSRAM interface based on the PSRAM transmission signals, and the PSRAM interface signals are generated according to the type of the PSRAM interface, so that the generated PSRAM interface signals can be compatible with PSRAM interfaces and transmission protocols of different types, different PSRAM chips can be supported by the controller, and the flexibility of PSRAM chip selection is improved.

The embodiments of the present disclosure also provide a control method for a pseudo-static random access memory, which is based on the controller for a pseudo-static random access memory provided by the embodiments of the present disclosure, and for saving the space, the controller for a pseudo-static random access memory provided by the embodiments of the present disclosure is incorporated herein by reference.

Fig. 12 is a flowchart of a control method for a pseudo-static random access memory according to an embodiment of the present disclosure. Referring to fig. 12, the control method includes:

step S1201, an operation request is received.

Wherein the operation request may be transmitted to the controller via the APB bus and the AHB bus, the operation request including, but not limited to, a memory read-write request and a register module access request. The operation request may be, for example, a read-write request or a read-write request from an APB or an AHB.

Step S1202 generates a pseudo static random access memory PSRAM transmission signal adapted to the type of the eight-way serial input output interface based on the operation request.

In some embodiments, the PSRAM transfer signals include read and write commands, enter/exit half sleep (mixed sleep), enter/exit deep power down operation, and transfer signals corresponding to the states.

Step S1203 is to generate a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transfer signal.

According to the control method for the pseudo-static random access memory, provided by the embodiment of the disclosure, based on an operation request, pseudo-static random access memory PSRAM transmission signals adaptive to the types of eight paths of serial input/output interfaces are generated, so that the PSRAM transmission signals are applicable to different PSRAM interfaces; and generating PSRAM interface signals which are adaptive to the type of the PSRAM interface based on the PSRAM transmission signals, wherein the PSRAM interface signals are generated according to the type of the PSRAM interface, so that the generated PSRAM interface signals can be compatible with PSRAM interfaces and transmission protocols of different types, different PSRAM chips can be supported by a controller, and the flexibility of PSRAM chip selection is improved.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (11)

1. The utility model provides a controller for pseudo-static random access memory, its characterized in that includes digital controller and physical layer interface, the input of physical layer interface is connected with digital controller, the output is connected with pseudo-static random access memory PSRAM interface, wherein:

the digital controller is used for receiving an operation request and generating PSRAM transmission signals which are adaptive to the types of eight paths of serial input/output interfaces based on the operation request;

the physical layer interface is configured to generate a PSRAM interface signal adapted to a type of the PSRAM interface based on the PSRAM transmission signal.

2. The controller of claim 1, wherein the operation request comprises an advanced peripheral bus APB operation request and a high performance bus AHB operation request;

the digital controller includes:

the register module is used for generating an APB control signal and a time sequence parameter based on the received APB operation request, receiving a transmission state signal and storing the transmission state signal;

the AHB slave control module is used for responding to the received AHB operation request and obtaining AHB instruction information based on the APB control signal and the time sequence parameter; transmitting the received transmission state information of the PSRAM to an AHB host;

and the read-write transaction transmission module is used for generating the PSRAM transmission signal based on the APB control signal and the AHB instruction information, receiving an operation request and a clock signal from the physical layer interface, sampling the operation request based on the clock signal and transmitting a sampling result to the AHB slave control module.

3. The controller of claim 2, wherein the read-write transaction transmission module comprises:

the command processing module is used for carrying out edge detection on the received APB control signal and outputting an APB control effective signal and an APB transmission signal;

the receiving and transmitting module is used for carrying out cross-clock domain transmission based on the data returned by the physical layer interface, outputting the data of the physical layer interface when the preset condition is met, and outputting a timeout indication signal when the data strobe signal is determined to be timeout according to the time sequence parameter;

and the sending and transmitting module is used for generating the PSRAM transmission signal based on each transmission state when the APB control signal and the AHB instruction information are transmitted.

4. A controller according to claim 3, wherein the send transmission module comprises a data shift register module comprising a plurality of state machines, each corresponding to a type of the eight serial input output interface, each of which generates the PSRAM transmission signal based on a respective transmission state for the type of the eight serial input output interface corresponding thereto.

5. A controller according to claim 3, wherein the send transmission module further comprises:

a timing sequence checking module for generating a first indication signal based on the timing sequence parameter;

the write boundary checking module is used for outputting a second indication signal when determining that the boundary of the memory page is reached based on the parameters and the memory address of the memory page;

the data shift register module transmits the APB control signal and the AHB instruction information in response to the first and second instruction signals.

6. The controller of claim 2, wherein the digital controller further comprises:

a first synchronizer for cross-clock domain transmission of a timeout signal from a clock signal of the digital controller to a clock signal of the AHB;

a second synchronizer for transmitting a transmission completion signal from the clock signal of the digital controller to the clock signal of the APB across clock domains.

7. The controller of claim 1, wherein the APB operation request comprises one or more of an APB read request, an APB write request;

the AHB operation request comprises one or more of an AHB read request and an AHB write request.

8. The controller of claim 1, wherein the physical layer interface comprises:

the clock gating processing module is used for generating clock signals SCLK and SCLK for the PSRAM according to the clock of the phase shift memory controller and clock enabling;

the data input/output selection processing module is used for splitting the data input/output into two parts of memory controller clocks according to the high level and the low level of the memory controller clocks;

a data mask output selection processing module for splitting the data mask into two parts according to the data mask output enable when the high level and the low level of the clock of the memory controller are outputted;

a data strobe clock output selection processing module for generating data strobe clock outputs compatible with different PSRAM interfaces based on clock signals, data masks, PSRAM types, data strobe clock output enabling;

the data gating clock gating processing module is used for gating the input data mask of the data gating clock based on the output enable of the data gating clock to obtain a data gating clock input signal;

and the data strobe clock selection operation completion delay module is used for physically delaying the data strobe clock input signal so that the data returned by the PSRAM lags behind the data strobe clock.

9. The controller of claim 8, wherein the data strobe clock selection operation completion delay module comprises a physical control register module for selecting a number of delay stages, each of the number of delay stages corresponding to a different delay time.

10. A control method based on the controller for pseudo-static random access memory according to any one of claims 1 to 9, characterized by comprising:

receiving an operation request;

generating a pseudo static random access memory PSRAM transmission signal which is adaptive to the type of the eight paths of serial input/output interfaces based on the operation request;

and generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal.

11. The control method according to claim 10, wherein the PSRAM transfer signals include a read/write command, a enter/exit half sleep, and a enter/exit transfer signal corresponding to each transfer state in a deep power-down operation.

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