JP4255628B2 - Infrared two-dimensional sensor array system - Google Patents

Description

ここで、ｎは３２、ｆは１ｋＨｚ、ｊは虚数単位である。
【０１４８】
上式からフーリエ係数Ｃａは複素平面上のベクトルとなり、上述のとおり、実軸側の係数をＸ、虚軸側の係数をＹと置く。
【０１４９】
１ｋＨｚの正弦波の振幅は、このベクトルの大きさ、サンプリングのタイミングに対する位相差はベクトルのＸ軸からの回転角で表わされる。複数の周期にわたって上式を計算した場合は、ベクトルの大きさが周期数に比例するが、位相角は変化しない。サンプリングにノイズが含まれる場合は、周期数の平方根に比例してＳ／Ｎが向上する。
【０１５０】
上式を実行するための回路をＦＰＧＡ１１０に実装する場合、サンプリングのタイミングは決まっているので、サンプリングデータに乗ずるサインやコサインの関数は３２種類の決まった数値になる。実際にはこれらの関数はπ／２周期で左右や上下に反転した形なので、８個の数値を用いるだけでよく、この８個の係数値をＦＰＧＡ１１０のフーリエ係数記憶部２１１６中のＲＯＭ（Read Only Memory）テーブルに記録させる。
【０１５１】
サンプリングデータは、たとえば、１２ビット（１ビットが約１．２２ｍＶ）であるが、最下位ビットはノイズが大きく意味を持たないので、この場合、上位１１ビットのみを計算に使用すればよい。また、オフセット調整後の信号の振幅は増幅後であっても１Ｖ以下であるので、サンプリングデータが１２ビットの場合は、フーリエ係数の計算に有効なビット数は１０ビット以下である。
【０１５２】
そこで、この８個の係数値は、サンプリングデータを１２ビットとするシステムでは、１０ビットデータとすればよい。したがって、掛算は２１ビット幅が必要である。２１ビットの掛算回路は非常に大きな回路となり、また遅延も大きい。したがって、回路規模の抑制のためには、シフトレジスタと足算回路を用いて１０クロックで動作する掛算回路を構成することが可能である。この掛算結果の数値を、さらにＦＰＧＡ１１０のフーリエ係数記憶部２１１６中のＲＡＭ（Random Access Memory）に加算することにより、フーリエ係数を求める。
【０１５３】
本システムでは、一例として、２１ビット整数を１周期に３２（２の５乗）回加算し、最大２５６（２の８乗）周期まで加算することにしたので、最大３４ビットになる可能性がある。しかしながら、実際の最大振幅は１Ｖ以下と考えられるので、この足算は３１ビット幅で行なうこととすることができる。
【０１５４】
また、このような構成の場合は、３１ビット中下位ビットは、計算後は、ノイズのため意味をなさないので、本システムでは、パーソナルコンピュータ１００に送信するデータは下位１５ビットを無視して上位１６ビットのみとしてもよい。
【０１５５】
振幅（ピークツーピーク）が１Ｖの１ｋＨｚ正弦波に対して、１周期分の上記の計算を行ない、下位１５ビットを無視すると、フーリエ係数（ベクトル）の大きさ（ベクトルの長さ）は約１０２となる。
【０１５６】
これから、計算を行なった周期をＮ、計算されたフーリエ係数の大きさをＦとすれば、実際の信号強度Ｖは次式で与えられる
Ｖ＝Ｆ／Ｎ／１０２
歪成分の高調波が重畳した実際の信号波形（１６０倍の増幅後）において、オシロスコープ付属のＦＦＴ機能により求めた１ｋＨｚの振幅が１２．６ｍＶのとき、１２５周期のフーリエ係数計算により上式から求められる振幅値は１２．９ｍＶとなり非常によく一致していることが確認された。
【０１５７】
［アナログ信号処理部およびＡ／Ｄコンバータ］
図３に示した赤外線２次元センサアレイ１０では、赤外線検出センサからの信号は数ｍＶ以下であるので増幅が必要である。また、デジタル回路部から発生する高周波ノイズや、誘電体膜および処理回路の歪みによると考えられる高周波成分をできるだけ少なくするとともに、６０Ｈｚ成分や直流成分もカットする必要がある。そのためにバンドパスフィルタ１４０．０〜１４０．１５を使用する。
【０１５８】
しかしながら、フィルタの遮断特性を急峻にすると過渡特性が長くなり、１画素当りの駆動時間も長くする必要が生じる。したがって、フィルタの遮断特性にも最適な次数が要求される。これらを考慮して設計されたアナログ回路部であるバンドパスフィルタ１４０．０〜１４０．１５について、さらに説明しておく。
【０１５９】
たとえば、駆動正弦波の周波数を１ｋＨｚとすると、出力信号には、それに対する高調波の歪が現れる。
【０１６０】
そこで、６０Ｈｚ成分や直流成分と、この歪成分をカットすることを考慮して、バンドパスフィルタ１４０．０〜１４０．１５を、たとえば、中心周波数１ｋＨｚ、利得４５ｄＢ（１８０倍）の特性を有するように設計する。
【０１６１】
図１０は、このようなバンドパスフィルタ１４０．０の構成を示す概略ブロック図である。他のバンドパスフィルタ１４０．１〜１４０．１５の構成も同様である。
【０１６２】
入力側は、赤外線検出センサからの出力をＪ−ＦＥＴのソースフォロアによって受けている。この回路は５Ｖ単電源で駆動する。フィルタへの２．５Ｖ入力は、５Ｖ電源からツェナダイオードにより２．５Ｖに低電圧化し、フィルタに安定に供給するためのバッファを使用して生成したものである。
【０１６３】
（１） 利得周波数特性
図１１は、図１０に示した回路の利得周波数特性を示す図である。
【０１６４】
図１１（ａ）はシミュレーション結果であり、図１１（ｂ）は実測値である。シミュレーション、実測値ともに中心周波数１ｋＨｚ成分は約４５ｄＢの利得がある。また、１ｋＨｚ成分に対して２ｋＨｚ成分は約２５ｄＢの減衰がある。
【０１６５】
（２） 時間応答特性
赤外線センサの１画素当りに必要な駆動時間は、画素切換時のノイズやフィルタの時間応答特性を考慮して決める必要がある。フィルタの帯域幅を狭くすればするほど、ノイズ除去能力は高くなるが、信号が急変したときのフィルタ出力が定常状態に達するまでの時間は長くなる。この時間応答特性のために、波形処理は要求されている精度に落ち着くまでの時間を待ってから行なわないと誤った結果となってしまう。
【０１６６】
したがって、１６×１６あるいはそれ以上の２次元アレイにおいては、定常状態に達するまでの時間をなるべく短くする必要がある。
【０１６７】
図１２は、図１０に示したバンドパスフィルタの時間応答特性を示す図である。ここで、図１２は、バンドパスフィルタに正弦波１ｋＨｚの信号を１０波形バースト信号として入力したときの出力応答波形である。
【０１６８】
図１２（ａ）はシミュレーション結果であり、図中の５ｍｓから１５ｍｓまではバースト信号を入力したときの出力応答波形である。図１２（ｂ）は実測値であり、図中に示したようなタイミングで信号入力の開始終了を行なったときの出力信号波形である。
【０１６９】
シミュレーションおよび実測値ともに、立上がり、立下がりの３ｍｓの間は信号が安定しない。よって、逆にいえば、以上説明したような測定のパラメータの条件下では、バンドパスフィルタ１４０．０〜１４０．１５からの出力信号の振幅をＦＰＧＡ１１０により、１ｋＨｚのフーリエ係数計算する場合に、画素の切換から３ｍｓ以降の信号を取込めば、十分な精度のデータを得ることができることがわかる。
【０１７０】
したがって、以上説明したような構成により、高感度であって、かつチョッパレス、しかも比較的簡易な構造等の特徴を有する容量変化検出型赤外線センサを用いて、センサアレイを実動作させることが可能となる。
【０１７１】
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
【０１７２】
【発明の効果】
以上説明したとおり、本発明の容量変化検出型赤外センサを２次元に配列した赤外線２次元イメージセンサに対する駆動回路および赤外線２次元イメージセンサシステムにより、室温で高感度かつ簡易な構成の赤外線検出回路を実現することができ、高感度かつ高密度画素の室温動作赤外線２次元イメージセンサを実現することが可能となる。
【図面の簡単な説明】
【図１】 本発明に係る２次元センサアレイ中の、１つのセンサおよびそれを駆動する回路を等価的に示す図である。
【図２】 信号源ＶＧ１およびＶＧ２により、赤外線センサＩＲＳに与えられる信号波形を示す図である。
【図３】 素子駆動正弦波パルスにより補正を行なうことが可能な赤外線２次元センサアレイおよびその駆動回路の構成を説明する概略ブロック図である。
【図４】 ２次元赤外線センサアレイ１０およびＦＰＧＡ１１０の構成を説明するための概略ブロック図である。
【図５】 ＦＰＧＡ１１０の構成をより詳しく説明するためのブロック図である。
【図６】 パーソナルコンピュータ１００の構成の一部を抜き出して示す概略ブロック図である。
【図７】 フーリエ係数を係数Ｘと係数Ｙの２次元ベクトルで表現した場合において、赤外線非照射時と赤外線照射時のベクトルを表す概念図である。
【図８】 送受信のフローを示すフローチャートである。
【図９】 Ｄ／Ａコンバータ１２０．０〜１２０．１６により出力する正弦波の波形を模式的に示す図である。
【図１０】 バンドパスフィルタ１４０．０の構成を示す概略ブロック図である。
【図１１】 図１０に示した回路の利得周波数特性を示す図である。
【図１２】 図１０に示したバンドパスフィルタの時間応答特性を示す図である。
【符号の説明】
１０ 赤外線センサアレイ、１００ パーソナルコンピュータ、１１０ ＦＰＧＡ、１２０．０〜１２０．１６ Ｄ／Ａコンバータ、Ｃｒｅｆ 参照キャパシタ、１３０．０〜１３０．１５ アンプ、１４０．０〜１４０．１５ バンドパスフィルタ、１５０．０〜１５０．１５ Ａ／Ｄコンバータ、１１０２ インターフェース部、１１０４ 駆動波形計算部、１１０６ Ｄ／Ａ制御部、１１０８スイッチング制御部、１１１０ Ａ／Ｄ制御部、１１１２ フーリエ係数計算部、２１０２ データ・コマンドインターフェース部、２１０４ 基準タイミング生成部、２１０６ 振幅・位相データ記憶部、２１０８．０〜２１０８．１６駆動波形計算回路、２１１０．０〜２１１０．１６ Ｄ／Ａ制御回路、２１１２．０〜２１１２．１５ Ａ／Ｄ制御回路、２１１４ フーリエ係数計算回路、２１１６ フーリエ係数記憶部、２１１８ スイッチングパルス生成部、３０００ キーボード、３００２ マンマシンインターフェイス部、３００４ 画像表示用パラメータ設定部、３００６ 画素駆動パラメータ記憶部、３００８ 画像データ計算部、３０１０ 画像表示部、３０１２ 素子駆動パラメータ計算部、３０１４ Ｉ／Ｏカード部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a configuration of an infrared two-dimensional sensor array system for driving an infrared two-dimensional image sensor capable of measuring a two-dimensional distribution of infrared intensity emitted from a target object.
[0002]
[Prior art]
Infrared rays (heat rays) having a wavelength of about 10 μm are radiated from an object or human body at room temperature, and by measuring this, information on their presence and temperature can be obtained in a non-contact manner. By utilizing this, various applications such as automatic doors, intrusion warning devices, cooking monitors for microwave ovens, and chemical measurement have been made.
[0003]
In such measurement, the most important key device is an infrared sensor, which can be roughly divided into two types: a quantum infrared sensor and a thermal infrared sensor.
[0004]
The quantum infrared sensor has high sensitivity and excellent detection ability, but has a problem in practicality in that the apparatus is large because cooling is necessary. On the other hand, the thermal infrared sensor has a merit that it can be operated at room temperature, although its sensitivity is slightly inferior to that of the quantum infrared sensor, and is highly practical.
[0005]
For this reason, many thermal infrared sensors have been proposed, such as those using the pyroelectric effect, resistance bolometers, dielectric bolometers, thermopiles, and Golay cells.
[0006]
Above all, the dielectric bolometer that detects the temperature change of the dielectric constant by applying an electric field has excellent characteristics such as higher sensitivity than other sensors and the need for a chopper, and is expected from practical knowledge. Yes.
[0007]
Furthermore, as a more advanced infrared sensing, it is expected to be applied to an infrared image sensor (thermography) that can obtain the temperature distribution of an object or landscape without contact.
[0008]
Japanese Patent Application Laid-Open No. 11-271141 (Japanese Patent Application No. 10-72571) discloses a configuration in which a reference capacitor and an infrared detection capacitor are provided in an infrared sensor corresponding to each pixel in a capacitance change detection type infrared two-dimensional sensor array. Has been. This infrared detection capacitor has a high dielectric material whose dielectric constant changes depending on temperature, for example, ferroelectric BST [(Ba _1-x Sr _x ) TiO _Three ] (Composition ratio x = 0.33 vicinity) is sandwiched between electrodes. In this infrared sensor, when the infrared rays are not irradiated, the capacitances of the infrared detection capacitor and the reference capacitor are the same, and the output of the infrared detection capacitor varies due to the temperature rise caused by the infrared absorption during the irradiation.
[0009]
[Problems to be solved by the invention]
However, when an infrared sensor as described above is actually created, the characteristics of the infrared detection capacitor and the reference capacitor vary within a pixel and between pixels, and there is a difference in the capacitances.
[0010]
Due to the difference in capacitance, an output offset exists in the infrared sensor corresponding to each pixel even when infrared irradiation is not performed.
[0011]
Since the output after receiving infrared rays from the heat source to be the target of the infrared sensor is, for example, about several mV or less, the output offset needs to be further reduced by one or two digits from several mV. In the case of a single infrared detection sensor element, the capacitance deviation can be corrected by adding an external capacitor (variable capacitor, etc.). However, in the case of a multi-pixel sensor (sensor array), such an external element is added especially when the number of pixels is large. Correction by is impossible in reality.
[0012]
Further, when capturing a two-dimensional image, the correction that stably reduces the output offset to several mV or less at each frame time needs to be performed within a sufficiently short time for each frame. In terms of the correction speed, adjustment by an external element is impossible.
[0013]
However, in this case, it is difficult to actually operate the sensor array by using a capacitance change detection type infrared sensor having high sensitivity, chopperless, and relatively simple structure.
[0014]
The present invention has been made in order to solve the above-described problems. The object of the present invention is to eliminate the need for using a chopper or performing correction with an external element, and is easy to integrate and detect. It is an object to provide an infrared two-dimensional sensor array system having a configuration capable of achieving both improvement in sensitivity and high resolution.
[0015]
[Means for Solving the Problems]
In order to solve such problems, the infrared two-dimensional sensor array system according to the present invention corrects an offset output generated due to variations in capacitance values, dielectric losses, parasitic resistance values, and the like between the infrared detection capacitor and the reference capacitor. A drive signal is applied as described above.
[0016]
That is, the infrared two-dimensional sensor array system according to claim 1 includes an infrared two-dimensional sensor array in which a plurality of infrared detection sensors are arranged in a matrix, and each infrared detection sensor is in series with a reference capacitor and a reference capacitor. Switch means for selectively reading out a signal level from a connection node between an infrared detection capacitor connected and having a capacitance value changed according to incident infrared rays, and one end of a reference capacitor and one end of the infrared detection capacitor A first signal source for applying a reference signal to the other end of the reference capacitor, and a second signal source for applying a drive signal to the other end of the infrared detection capacitor, The signal source changes the amplitude and phase of the drive signal to predetermined values according to the infrared detection sensor from which the signal level is to be read. That.
[0017]
In the infrared two-dimensional sensor array system according to claim 2, in addition to the configuration of the infrared two-dimensional sensor array system according to claim 1, the first signal source is provided in common to the plurality of infrared detection sensors, and the second The signal source includes a plurality of signal output means provided for each column of the infrared two-dimensional sensor array, and selects a row of the infrared two-dimensional sensor array so that the switch means belonging to the selected row is turned on. And a plurality of signal reading means provided for each column of the infrared two-dimensional sensor array for reading the signal level via the switch means.
[0018]
In addition to the configuration of the infrared two-dimensional sensor array system according to claim 2, the infrared two-dimensional sensor array system according to claim 3 is a signal for extracting a signal having a desired frequency component from outputs of a plurality of signal reading means. And a frequency component calculation for calculating a first real component and a first imaginary component of a Fourier coefficient corresponding to a desired frequency for each of the outputs of the plurality of signal reading units. Means, a first vector composed of a first real component and a first imaginary component, and a desired value for each of the outputs of the plurality of signal read-out means when the infrared two-dimensional sensor array is not irradiated with infrared light An infrared detection level is derived based on a difference vector between the second vector composed of the second real component and the second imaginary component when the Fourier coefficient corresponding to the frequency is calculated. And a external level calculation means.
[0019]
In addition to the configuration of the infrared two-dimensional sensor array system according to claim 2, the infrared two-dimensional sensor array system according to claim 4 outputs a reference signal output from the first signal source and a second signal source. Both drive signals are sinusoidal waves, and further include drive signal parameter storage means for storing the phase and amplitude of a signal to be applied as a drive signal for each infrared detection sensor.
[0020]
5. The infrared two-dimensional sensor array system according to claim 5, in addition to the configuration of the infrared two-dimensional sensor array system according to claim 3, the desired frequency is the frequency of the drive signal. Sensor array system.
[0021]
In addition to the configuration of the infrared two-dimensional sensor array system according to claim 3, the infrared two-dimensional sensor array system according to claim 6 updates the second real number component and the second imaginary number component according to a user request. Update means for doing so.
[0022]
In addition to the configuration of the infrared two-dimensional sensor array system according to claim 3, the infrared two-dimensional sensor array system according to claim 7 is an infrared ray by the infrared level calculation means for the row selected at the first timing by the row selection means. At least a part of the detection level derivation process and the calculation process of the frequency component calculation unit for the row selected by the row selection unit at the second timing after the first timing are performed in parallel.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
[Configuration of infrared sensor and its driving method]
FIG. 1 is a diagram equivalently showing one sensor and a circuit for driving the sensor in a two-dimensional sensor array according to the present invention.
[0024]
As shown in FIG. 1, in each capacitance change detection type infrared sensor IRS constituting the sensor array, the light receiving unit capacitor Cd etches the substrate from the back surface in order to suppress the heat conduction and improve the thermal response characteristic. Thus, it is formed in a region where the thickness of the silicon substrate is reduced, or a region where the silicon substrate is removed by etching the substrate from the back surface or the front surface. On the other hand, the reference capacitor portion Cref is formed on the silicon bulk.
[0025]
Here, the reference capacitor portion Cref is expressed as a parallel connection of a capacitor C1 and a resistor R1 as an equivalent circuit in consideration of the presence of the leakage current. On the other hand, the light receiving unit capacitor Cd is also expressed as a parallel connection of a capacitor C2 and a resistor R2 as an equivalent circuit.
[0026]
One end of the light-receiving unit capacitor Cd and one end of the reference capacitor unit Cref are coupled at a node nc. An AC signal is supplied from the signal source VG1 to the other end of the reference capacitor unit Cref, and an AC signal is supplied from the signal source VG2 to the other end of the light receiving unit capacitor Cd. The potential of the node nc is output as an output signal from the infrared sensor IRS via the transistor Ta. The transistor Ta is selectively turned on or off by the switching signal Ssw.
[0027]
FIG. 2 is a diagram showing signal waveforms given to the infrared sensor IRS by the signal sources VG1 and VG2.
[0028]
Basically, when each of the reference capacitor Cref and the light-receiving unit capacitor Cd is driven by a pair of sine waves having the same amplitude from the signal sources VG1 and VG2 and having their phases inverted, the difference in thermal response to infrared rays An output voltage is generated at the common electrode node nc. At this time, the capacitances of the two capacitors should ideally be the same.
[0029]
However, as described above, actually, there is a difference of several percent between the capacitances of the two capacitors Cd and Cref due to variations in film thickness and film quality during film formation, variations in capacitor area during lithography, and leakage resistance components. Exists.
[0030]
On the other hand, the amount of change in capacitance due to infrared rays is typically 0.1% or less of the original capacitance, although depending on the amount of infrared rays. If the element is driven with an amplitude of V, the infrared signal will be several mV or less, but for example, in order to capture it as digital data using an 8- to 12-bit AD converter, Considering the resolution, the signal level is too small.
[0031]
Therefore, although amplification of about 100 times is necessary, a signal (offset) due to variation in capacitance is also amplified 100 times at the same time, so that the amplification system is saturated. Alternatively, it is difficult to obtain an infrared response signal component behind a large offset. Therefore, it is necessary to correct the difference between the capacitance values of the light receiving unit capacitor Cd and the reference capacitor Cref.
[0032]
In order to correct such a difference in capacitance value, it is possible to adjust the offset value by changing the amplitude and phase of the element driving sine wave pulse for each element.
[0033]
In FIG. 2, as an example, a state in which the signal output from the signal source VG2 is shifted by the phase difference δθ from the inverted signal of the signal output from the signal source VG1 is shown. Further, the amplitude of the output signal from the signal source VG2 is changed as necessary.
[0034]
In this way, the electrical correction by adjusting the phase and amplitude of the drive pulse, for example, is output from a signal source outside the sensor array, compared to the case where correction is performed by externally attaching a capacitor or the like outside the element. Since it is only necessary to adjust the phase / amplitude of the output signal, it is possible to easily correct the output drift due to the temperature change.
[0035]
In FIG. 2, the reference signal Cref and the light receiving unit capacitor Cd are driven based on a state in which each of the reference capacitors Cref and the light receiving unit capacitor Cd is driven by a pair of sine waves having the same amplitude from the signal sources VG1 and VG2 and having the phases inverted. However, the present invention is not limited to such a case, and the signals from the signal sources VG1 and VG2 are a pair of signals whose phases are inverted with respect to each other. As long as the signal is used as a reference, the signal is not limited to a sine wave.
[0036]
[Configuration and drive system of two-dimensional infrared sensor array system]
FIG. 3 is a schematic block diagram for explaining the configuration of an infrared two-dimensional sensor array that can be corrected by the element driving sine wave pulse as described above and a driving circuit thereof.
[0037]
Referring to FIG. 3, infrared sensor array 10 includes capacitance change type infrared detection sensors arranged in an array of m (columns) × n (rows) (m, n: natural numbers). Each infrared detection element corresponds to a pixel. Further, the m × n sensors have an equivalent configuration in which m line sensors composed of 1 × n sensors are repeated. From the m line sensors, m number of sensors are arranged in parallel. Data is read out.
[0038]
In the following, for the sake of simplicity of explanation, the infrared sensor array 10 includes, for example, 16 × 16 infrared detection sensors arranged in a matrix, and each 16 × 16 array is an independent 1 × 16 line sensor. It is assumed to be configured as a repeating array of
[0039]
The reason why the 1 × 16 line sensor is repeatedly arranged is that pixel output data is obtained simultaneously in parallel from each column, and data reading per frame is performed compared to the case where two-dimensional all pixel data is output in series and time series. This is because the speed can be increased. Further, there is an advantage that the influence between lines when a defective pixel is generated is reduced in the array.
[0040]
A 16 × 16 sensor array is selected by correcting and applying a driving sine wave for each column by a field programmable gate array (FPGA) 110 controlled by the personal computer 100. The infrared detection sensors belonging to the row are driven.
[0041]
Here, the corrected sine wave value calculated by the FPGA 110 is given to the infrared detection sensors in the corresponding line sensors by the D / A converters 120.0 to 120.15 provided for the respective line sensors. It is done. Furthermore, the D / A converter 120.16 is controlled by the FPGA 110, and the reference capacitor Cref is driven for all the pixels by the output.
[0042]
On the other hand, the FPGA 110 outputs signals Ssw0 to Ssw15 for driving the transistors Ta of the infrared detection sensor IRS in order to select a row in the infrared sensor array 10. That is, the FPGA 110 sequentially selects the switching transistors of the infrared sensor belonging to the selected row in each line sensor in order to scan the infrared frame image obtained from the 16 × 16 two-dimensional array.
[0043]
The data read from the 16 × 16 infrared sensor array is amplified by amplifiers 130.0 to 130.15 provided for each line sensor, and then includes a desired frequency by bandpass filters 140.0 to 140.15. After extracting only the components in the narrowest possible frequency region, they are converted into digital signals by the A / D converters 150.0 to 150.15 and given to the FPGA 110.
[0044]
As described above, since the signal from the element is several mV or less, it is necessary to perform amplification. In addition, it is necessary to reduce the high frequency noise generated from the digital circuit part and the high frequency component considered to be caused by the distortion of the dielectric film and the processing circuit as much as possible, and cut the 60 Hz component and DC component of the power supply. Therefore, bandpass filters 140.0 to 140.15 are provided in the configuration shown in FIG.
[0045]
The FPGA 110 extracts only the signal component due to the incident infrared rays by calculating the Fourier coefficient of the digital signal from each line sensor obtained in this way as will be described later.
[0046]
The data for which the Fourier coefficient is calculated in the FPGA 110 in this manner is sent back to the personal computer 100, where an infrared two-dimensional image is finally formed in the personal computer 100 and output on a display (not shown). The
[0047]
FIG. 4 is a schematic block diagram for explaining the configuration of the two-dimensional infrared sensor array 10 and the FPGA 110 described in FIG. In FIG. 4, for the sake of simplicity of explanation, only two rows and two columns are extracted from the configuration of the sensor array 10 of FIG.
[0048]
Hereinafter, the configuration and the flow of processing will be described in more detail with reference to FIG.
[0049]
The driving sine wave to be applied to the infrared sensor corresponding to each pixel obtains an integrated value after giving at least a plurality of times, for example, about 8 pulses to one pixel in consideration of noise at the time of switching and a transient response of the filter. There is a need. On the other hand, the frequency of the driving sine wave is suitably about 1 kHz, for example, due to the frequency characteristics of the dielectric constant of the ferroelectric film used in the infrared detection sensor.
[0050]
Therefore, driving of one pixel requires at least 8 mS in the above example. That is, when driving a 16 × 16 two-dimensional array, if there is only one pair of driving sine wave sources, the time required to drive all the pixels and make a round (frame time) is 2048 mS at minimum. This corresponds to obtaining an image of one frame in 2 seconds. However, in order to obtain an infrared image in almost real time, it is desirable to read out image data at a rate of 5 frames or more per second (frame time: 200 ms or less).
[0051]
Therefore, 16 pairs of driving sine waves for driving the two-dimensional infrared sensor array 10 shown in FIGS. 3 and 4 are generated simultaneously by the D / A converters 120.0 to 120.15. The 16 pixels corresponding to each column are driven simultaneously and independently to shorten the frame time. On the other hand, the sine wave for driving the reference capacitor Cref may be common to all pixels, and is generated by the D / A converter 120.16. Therefore, 17 drive sine waves (16 for the light receiving unit capacitor and 1 for the reference capacitor) are generated at the same time.
[0052]
For this reason, the FPGA 110 simultaneously calculates 17 sine wave data having different amplitudes and phases in the drive waveform calculation unit 1104 in accordance with control from the personal computer 100. Further, the FPGA 110 controls the D / A converters 120.0 to 120.16 by the D / A control unit 1106 according to the calculation result of the drive waveform calculation unit 1104, and outputs from the buffers 121.0 to 121.16. The waveform is applied to each infrared detection sensor in the sensor array 10.
[0053]
Here, when the infrared detection sensors are arranged in a two-dimensional array, the number of pixels is increased as compared with the line sensor, and further, the number of pixels needs to be increased in order to increase the resolution. Therefore, if the optimum amplitude and phase of each individual infrared detection sensor are stored in the memory on the FPGA 110, it is necessary that a large-scale memory is mounted on the FPGA 110.
[0054]
Rather, in the system shown in FIG. 4, the data corresponding to the amplitude and phase correction values for each pixel is stored in the memory in the personal computer 100, and the data for up to 16 pixels is stored in the personal computer before switching the driving pixel. The computer 100 is configured to transmit to the FPGA 110. This eliminates the need to mount a large capacity memory on the FPGA 110.
[0055]
As described above, the FPGA 110 sets the optimum amplitude and phase for the infrared detection sensor corresponding to the row to be read out of the infrared detection sensors belonging to each column of the sensor array 10 based on a preset compensation value. The D / A converters 120.0 to 120.15 output the drive signals to the corresponding columns.
[0056]
Further, the switching control unit 1108 in the FPGA 110 sequentially selects the rows of the sensor array 10 based on the switching timing data given from the personal computer 100 and the accurate clock signal given from the crystal oscillator (not shown). The switching signal is generated.
[0057]
On the other hand, in order for the personal computer 100 to simultaneously receive signals from the 16 A / D converters 150.0 to 150.15, the personal computer 100 needs to have an input / output interface corresponding thereto. Furthermore, it is not realistic that the Fourier coefficient calculation is simultaneously performed on the personal computer 100 due to restrictions on the data transfer speed and the calculation speed for the personal computer 100.
[0058]
Therefore, in the configuration shown in FIG. 4, the A / D control unit 1101 in the FPGA 110 controls the 16 A / D converters 150.0 to 150.15, and the Fourier coefficient calculation unit 1112 on the FPGA 110 The Fourier coefficient calculation for 16 pixels is performed, and the result is transmitted to the personal computer 100 via the interface unit 1102.
[0059]
Of course, when the number of pixels becomes larger, the function realized by the FPGA 110 in FIG. 4 and the function realized on the personal computer 100 are integrated and a dedicated LSI is provided to drive the pixels. It is also possible.
[0060]
On the other hand, the personal computer 100 controls the entire imaging and displays an image. At this time, as shown in FIG. 4, if the control is performed from the personal computer 100 in adjusting the optimum amplitude and phase for each pixel, the software can be mounted relatively easily. In addition, it is possible to perform optimum offset adjustment by feedback from the measurement image data.
[0061]
[Configuration of FPGA 110]
FIG. 5 is a block diagram for explaining the configuration of the FPGA 110 shown in FIG. 4 in more detail.
[0062]
Referring to FIG. 5, the data / command interface unit 2102 in the interface unit 1102 with the personal computer 100 receives data from the personal computer in accordance with the control code from the personal computer 100, and transmits the data to each unit in the FPGA 110. Send data. Further, the data / command interface unit 2102 transmits data received from each unit of the FPGA 110 to the personal computer 100 in accordance with the control code.
[0063]
On the other hand, the reference timing generation unit 2104, not shown in FIG. 4, captures the timing of driving waveform calculation and the data acquisition of the A / D converter based on the data supplied from the personal computer 100 and the clock signal from the crystal oscillator. Timing, Fourier coefficient calculation timing, data storage, data transmission timing to the interface with the personal computer 100, and switching timing for scanning of the infrared detection sensor are generated.
[0064]
Here, the received data from the personal computer 100 includes, for example, the horizontal address (column address) and vertical address (row address) of the element, and the amplitude of the driving sine wave corresponding to each infrared detection sensor. There is phase data. The data transmitted to the personal computer 100 includes, for example, the Fourier coefficient from each infrared detection sensor and the elapsed time after switching to the selected infrared detection sensor.
[0065]
The amplitude / phase data storage unit 2106 in the drive waveform calculation unit 1104 receives the amplitude and phase data of the drive waveform sent from the personal computer 100 via the interface unit 1102 for each infrared detection sensor in the sensor array 10. Remember. The amplitude / phase data storage unit 2106 sends data to the drive waveform calculation circuits 2108.0 to 2108.16 for generating waveforms for driving each element at an appropriate timing. Note that with respect to the drive waveform calculation circuit 2108.16, since the waveform of the reference wave is calculated, the data for generating the waveform without sending the data from the amplitude / phase data storage unit 2106 may be a fixed value.
[0066]
Based on the data sent from the amplitude / phase data storage unit 2106 and the reference timing of the calculation sent from the reference timing generation unit 2104, the drive waveform calculation circuits 2108.0 to 2108.16 are D / A converters at each moment. Data of 120.0 to 120.16 is calculated, and the data is sent to the D / A control circuits 2110.0 to 2110.16. The drive waveform calculation circuit 2108.16 and the D / A control circuit 2110.16 are for driving the reference electrode capacitor Cref. Seventeen drive waveform calculation circuits 2108.0 to 2108.16 are provided in parallel, including for driving the reference capacitor.
[0067]
D / A control circuits 2110.0 to 2110.16 in the D / A control unit 1106 control the D / A converters 120.0 to 120.16 and send them from the drive waveform calculation circuits 2108.0 to 2108.16. The transmitted data is sent to the D / A converters 120.0 to 120.16. Seventeen D / A control circuits 2110.0 to 2110.16 are also provided in parallel.
[0068]
The A / D control circuits 2112.0 to 2112.15 in the A / D control unit 1110 control the A / D converters 150.0 to 150.15 according to the timing sent from the reference timing generation unit 2104, and A Data is taken in from / D converters 150.0 to 150.15. Sixteen A / D control circuits 2112.0 to 2112.15 are provided in parallel.
[0069]
The Fourier coefficient calculation unit 1112 includes a Fourier coefficient calculation circuit 2114 and a Fourier coefficient storage unit 2116. The Fourier coefficient calculation circuit 2114 uses the data sent from the A / D control circuits 2112.0 to 2112.15 in accordance with the timing sent from the reference timing generation unit 2104 and uses 16 Fourier coefficients for each column of the sensor array 10. Perform the calculation. Further, the calculation result is sent to the Fourier coefficient storage unit 2116.
[0070]
The Fourier coefficient storage unit 2116 stores the Fourier coefficient sent from the Fourier coefficient calculation circuit 2114 for each element, and sends the Fourier coefficient to the personal computer 100 via the interface unit 1102 in accordance with the timing sent from the reference timing generation unit 2104. To do.
[0071]
The switching pulse generator 2118 in the switching controller 1108 generates a pulse for turning on and off the switching transistor Ta in each infrared detection sensor at an appropriate timing according to the timing from the reference timing generator.
[0072]
[Configuration of Control Personal Computer 100]
FIG. 6 is a schematic block diagram showing a part of the configuration of the personal computer 100.
[0073]
Referring to FIG. 6, man-machine interface unit 3002 sends each parameter input from keyboard 3000 by the user to image display parameter setting unit 3004 and pixel drive parameter storage unit 3006.
[0074]
The image display parameter setting unit 3004 sets and stores parameters used at the time of image display, for example, “zero vector” and “sensitivity coefficient” of each pixel according to key input. The image data calculation unit 3008 calculates the “zero vector” of the pixel based on the output of the sensor array 10, and the image display parameter setting unit 3004 receives the calculated value. As will be described later, the “zero vector” of each pixel means a vector of complex Fourier coefficients of the output of each infrared detection sensor in the sensor array 10 when infrared rays are not irradiated.
[0075]
For example, the image data calculation unit 3008 receives a signal (Fourier coefficient) for each pixel from the I / O card unit 3014 that transmits and receives data to and from the FPGA 110 with a data width of 24 bits, and transmits the signal from the image display parameter setting unit 3004. Display data is calculated using the zero vector and sensitivity coefficient of each pixel. Based on the calculation result of the image data calculation unit 3008, the image display unit 3010 displays a pseudo color image reflecting the temperature distribution of the measurement target on the screen of the personal computer 100.
[0076]
The pixel drive parameter storage unit 3006 stores optimum phase and amplitude data for each pixel drive according to a procedure described later. Phase and amplitude data are received from the man-machine interface unit 3002 during manual calibration and from the image data calculation unit 3008 during automatic calibration.
[0077]
The element drive parameter calculation unit 3012 receives the phase and amplitude data of each pixel from the pixel drive parameter storage unit 3006, calculates the pixel address, and sends the data to the I / O card unit 3014 at an appropriate timing.
[0078]
The I / O card unit 3014 performs communication and control with the FPGA 110, receives the Fourier coefficient of each pixel and the elapsed time after switching the row of the selected infrared detection sensor from the FPGA 110, and sends the address of each pixel to the FPGA 110. And transmit amplitude and phase data.
[0079]
In the above description, the external interface of the personal computer 100 is the I / O card unit 3014. Of course, as long as data can be exchanged with a predetermined bit width and a desired speed, Other interfaces may be used.
[0080]
[Operation of infrared two-dimensional sensor array system]
In the following, in the personal computer 100, the procedure for setting various parameters by the man-machine interface and the operation of each unit will be described in more detail.
[0081]
Referring to FIGS. 3 and 4 again, control personal computer 100 performs various parameter settings, image display, communication and control with FPGA 110, and data holding and offset adjustment processing of the optimum amplitude and phase of each pixel. .
[0082]
Therefore, the control personal computer 100 performs the following operations and controls in order to perform functions such as control of the FPGA 110, image display, and calibration (offset adjustment).
[0083]
i) Normal scan
Signals from the pixels are taken into the personal computer 100 through the FPGA 110, processed to be pseudo-colored, and displayed as a two-dimensional image. At this time, “zero vector value” to be described later is updated in accordance with an instruction from the user.
[0084]
ii) Manual calibration
Calibration (offset adjustment) is performed with the pixels fixed.
[0085]
Since the real axis coefficient and the imaginary axis coefficient of the Fourier coefficient are displayed in real time on the screen of the personal computer 100, the amplitude and phase of the drive sine wave applied to the pixel are changed by an instruction from the user while viewing the screen display. .
[0086]
Even during manual calibration, the zero vector value of a pixel fixed by an instruction from the user can be updated.
[0087]
iii) Automatic calibration
Calibration is automatically performed during normal scan. Since the calibration for the number of horizontal pixels (maximum 16 pixels) can be performed at the same time, the calibration is completed at high speed.
[0088]
iv) Measuring changes over time
In response to an instruction from the user at the time of manual calibration, data for the number of horizontal pixels is stored up to a maximum of 20,000 points, and automatically stored in a file at the end of calibration.
[0089]
v) Saving calibration data
Phase, amplitude, and sensitivity data for each pixel when calibration is performed are automatically saved. Even if the measurement software is terminated once, this parameter is automatically read when the measurement software is started next time, so that it is not necessary to reset the parameter unless the element is changed.
[0090]
(Various parameter setting functions)
In order to drive the infrared sensor and perform signal processing and image display, it is necessary to set various parameters and perform control and calculation of the FPGA 110.
[0091]
Such parameters are set by a man-machine interface using the personal computer 100. Hereinafter, the parameters set in this way will be described in more detail.
[0092]
i) Number of pixels
The number of pixels in the two-dimensional array is represented by the number of vertical pixels × the number of horizontal pixels. Note that 1 × 16 and 16 × 1 have different meanings. In 1 × 16, all 16 processes such as a D / A converter and an A / D converter are performed simultaneously (in parallel), and switching is not performed. On the other hand, in 16 × 1, processing is performed pixel by pixel, and 16 pixels are scanned. Therefore, even if the number of pixels is the same, 1 × 16 can capture data of all pixels 16 times faster.
[0093]
ii) Display settings
As will be described later in detail in the operation of the FPGA 110, when performing the Fourier coefficient calculation of the data of each pixel, the phase of the signal output due to the drive sine wave is π / 2. The shifted component is calculated.
[0094]
For convenience, the in-phase component is referred to as “real axis coefficient X”, and the component shifted by π / 2 is referred to as “imaginary axis coefficient Y”.
[0095]
FIG. 7 is a conceptual diagram showing vectors when infrared light is not irradiated and when infrared light is irradiated, when a Fourier coefficient is expressed by a two-dimensional vector of a coefficient X and a coefficient Y.
[0096]
Here, when no infrared irradiation is performed, for example, in an infrared camera equipped with an infrared two-dimensional sensor array, the shutter is closed in order to block incident infrared rays to the infrared two-dimensional sensor array.
[0097]
Originally, the vector at the time of non-irradiation with infrared rays should have a magnitude of 0 by adjusting the offset, but in practice it is difficult to make it completely zero. In addition, since there is a drift in the output of the infrared detection sensor, this vector has a finite value even when infrared rays are not irradiated.
[0098]
Therefore, the vector (“zero vector”) of each pixel at the time of non-infrared irradiation is stored, and the infrared of each pixel is displayed based on the magnitude of the difference vector between the zero vector and the vector at the time of infrared irradiation at the time of image display. Derives and displays levels. For example, the absolute value of the difference vector may be used as the infrared detection level.
[0099]
iii) Zero vector import
The above-described zero vector drifts with time and ambient temperature, so it needs to be updated from time to time. Accordingly, when the personal computer 100 instructs to take in the X / Y values of the zero vector, the value of the zero vector stored at the time of normal scanning and calibration (offset adjustment) is updated.
[0100]
iv) Drive time
The time for driving one pixel is input in units of milliseconds (mS), for example. The time obtained by multiplying this time by the number of vertical pixels is one frame time. Data acquisition starts 3 mS after pixel switching in order to avoid noise and transients during pixel switching. Therefore, the data acquisition time is the time obtained by subtracting 3 mS from the drive time.
[0101]
v) Automatic calibration setting
Even if calibration (offset adjustment) is performed, the zero vector is not completely zero. When it is performed manually, a human can determine the minimum value, but when it is performed automatically, a convergence condition is required. Therefore, the convergence condition of the X and Y coefficients of the zero vector is determined by “calibration change” and “positive side / negative side”.
[0102]
For example, if the deviation of the coefficient of X is 5 and negative, it is determined that convergence has occurred when 0>X> −5 for X of the zero vector.
[0103]
vi) Setting each pixel
Since the sensitivity and drift direction of each pixel are different, it is necessary to set display and calibration parameters for each pixel. By specifying the pixel to be set on the screen on the personal computer 100 and then inputting the sensitivity coefficient, it is possible to perform correction in consideration of the difference in sensitivity for each pixel.
[0104]
vii) Time-lapse measurement settings
It is also possible to set a time interval or the like when measuring a change with time. When the data acquisition timing is designated, the time interval is calculated from the measurement time and the measurement point interval and displayed.
[0105]
[Function and operation of I / O card unit 3014]
The function and operation of the I / O card unit 3014 that is an interface for communicating with and controlling the FPGA 110 will be further described below.
[0106]
i) Contents of communication data
As data transmitted from the personal computer 100, at least the following data is required.
[0107]
That is, 11-bit amplitude and phase 9-bit data of a sine wave for driving each pixel, 4-bit data of an address for designating which element data is transmitted / received, and start / stop of element drive This is the main control code to perform.
[0108]
Also, the received data from the FPGA 110 is as follows.
The real axis and imaginary axis coefficients of each pixel are 16-bit data and 8-bit elapsed time data after switching. Here, the reason why the elapsed time data from the FPGA 110 is used is that the personal computer 100 cannot perform accurate time measurement in units of 1 mS due to the interruption of the OS.
[0109]
In order to transmit and receive all of them simultaneously, a total of 66 bits of output 26 bits and input 40 bits are required. However, there is no I / O port or card having such a bit width in a general-purpose personal computer. Also, there is no room for allocating these I / O pins for communication on the FPGA 110 side.
[0110]
Therefore, 4 bits of data control code for controlling the contents of input / output are added, and instead the simultaneous transmission / reception of data is not performed, and the bit width is reduced by dividing each data into 8 bits or less. It is configured.
[0111]
Since the actual I / O card is 24 bits wide (8 bits × 3 ports), the following bit allocation is performed.
[0112]
1) A port: Output
0 to 5 bits: amplitude and phase data
6 and 7 bits: Main control code
2) B port: Input
0 to 7 bits: Fourier coefficients X and Y and elapsed time after element switching
3) C port: Output
0 to 3 bits: Data control code
4-7 bits: Element address
ii) Communication data rate and communication flow
When the FPGA 110 drives the element (infrared detection sensor) to calculate the Fourier coefficient, the A / D converter is in a transient state for a predetermined time, for example, 3 mS after switching the pixels as described above. Data is not taken in 150.0 to 150.15 and Fourier coefficients are not calculated.
[0113]
That is, during this transient state, the memory on the FPGA 110 holds the data of the Fourier coefficients of the pixels that have been driven previously.
[0114]
Therefore, when the personal computer 100 communicates with the FPGA 110, it is necessary to receive one row of Fourier coefficients from the FPGA 110, for example, a maximum of 16 pixels in this embodiment during this transient state.
[0115]
That is, since 32 bits (4 bytes) of data is received per pixel, a maximum of 64 bytes must be received within 3 mS. However, in actuality, which data of which pixel is received is notified to the FPGA 110 by using 1 byte of the data control code (4 bits) and the transmission address (4 bits). Therefore, the communication time per byte must be within about 23 μS.
[0116]
While the FPGA 110 is driving a certain pixel (up to 16 pixels at the same time), the personal computer 100 uses a total of 20 bits of amplitude and phase data for driving the next pixel (in fact, the transmission data bit width is 6 bits). It is necessary to transmit data corresponding to 4 bytes of data) to the FPGA 110 by the number of pixels (maximum of 64 bytes).
[0117]
The time for the FPGA 110 to take in the data of the A / D converters 150.0 to 150.15 and calculate the Fourier coefficient is, for example, a minimum of 5 mS (when combined with the transient time, the drive time of one pixel is a minimum of 8 mS). It is necessary to send and receive 128 bytes together with the control code sent from the personal computer 100 to the FPGA 110 within the time. In addition, it is necessary to display an image using the Fourier coefficient received earlier.
[0118]
FIG. 8 is a flowchart showing the flow of such transmission / reception.
Referring to FIG. 8, the I / O card unit 3014 of the personal computer 100 calculates Fourier coefficients for one row (16 pixels) for which calculation has been completed in the FPGA 110 based on data that has already been driven and read. Receive (step S100).
[0119]
Further, the I / O card unit 3014 receives an elapsed time from the switching of the selected row of the sensor array 10 from the FPGA 110 (step S102), and the personal computer 100 performs a predetermined transient response from the switching. A loop process for determining whether or not 3 mS has elapsed, for example, is performed (steps S102 and S104).
[0120]
If it is determined that 3 mS has elapsed (step S104), a command to start Fourier coefficient calculation is transmitted from the personal computer 100 to the FPGA 110 (step S106). In response to this, the FPGA 110 reads data from the A / D converters 150.0 to 150.15, the Fourier calculation circuit 2114 sequentially calculates the Fourier coefficients, and the calculation result is the Fourier coefficient storage unit 2116. Stored in As described above, if it takes 5 mS to calculate the Fourier coefficient for one row, for example, in the FPGA 110, 3 mS of the transient response period elapses from the switching of elements, and further after 5 mS elapses from the transmission of the Fourier coefficient calculation start command, That is, after 8 mS [= 3 (mS) +5 (mS)] has elapsed since the switching of the elements, the storage of the newly calculated Fourier coefficient in the Fourier coefficient storage unit 2116 ends.
[0121]
On the other hand, after the transmission of the Fourier coefficient calculation start command, the personal computer 100 subsequently transmits the amplitude and phase of the drive waveform to the FPGA 110 for the infrared detection sensor belonging to the next selected row (step S108).
[0122]
Data for image display is calculated based on the data received in step S100, and image display is performed (step S110).
[0123]
After the processing for displaying an image is completed, the personal computer 100 subsequently determines a loop for determining whether 8 mS has elapsed under the above conditions, for example, when the calculation of the Fourier coefficient is expected to be completed after switching the elements. Processing is performed (step S112, step S114).
[0124]
If it is determined that 8 mS has elapsed (step S114), an instruction to switch elements, that is, a selected row of the sensor array 10, is transmitted from the personal computer 100 to the FPGA 110 (step S116).
[0125]
Thereafter, the process returns to step S100 and repeats the same process.
[Details of operation of FPGA 110]
As described above, the FPGA 110 performs overall control of the imaging system, such as digital data calculation for element driving sine wave, control of the D / A converter and A / D converter, Fourier coefficient calculation, communication with the personal computer 100, and the like. Data output is performed. Hereinafter, the operation will be described in more detail.
[0126]
a) Calculation of sine wave for device drive
A D / A converter 120 is used to drive the device. For example, the D / A converter 120 has a 12-bit resolution (maximum output 4095 mV, resolution 1 mV) with a single 5 volt power supply.
[0127]
Since the output from the element by infrared irradiation is considered to be several mV or less, it is necessary to suppress the output (offset) due to the variation of the element to about 1 mV or less.
[0128]
When the amplitude of the element driving sine wave is changed by 1 mV by the equivalent circuit shown in FIG. 1, the output amplitude changes by 0.5 mV.
[0129]
That is, if the amplitude of the sine wave is changed in units of 1 mV, the offset can be reduced to a maximum of 0.25 mV. Further, the faster the clock frequency applied to the FPGA 110, the faster the FPGA 110 operates. However, if the clock frequency is too high, the operations of the D / A converters 120.0 to 120.16 cannot be caught up. In addition, noise due to unnecessary radiation accompanying high-speed operation also increases.
[0130]
Therefore, the clock frequency is not particularly limited, but is, for example, 16 MHz. When the output timing of a 1 kHz sine wave is controlled at this frequency, the phase resolution is 0.0225 degrees when 360 degrees is divided by 16000. As a result of simulation, it was found that when the phase was changed by 0.0225 degrees when the amplitude was 3.5 V, the output changed by about 0.6 mV. If the phase is adjusted in units of 0.0225 degrees, the maximum offset is about 0.3 mV.
[0131]
From the above, it can be said that if the D / A converters 120.0 to 120.16 having a resolution of 1 mV and a clock of 16 MHz are used for offset adjustment, the offset adjustment capability is sufficient.
[0132]
FIG. 9 is a diagram schematically showing the waveform of a sine wave output by the D / A converters 120.0 to 120.16.
[0133]
When a sine wave is output by the D / A converter 120, as shown in FIG. 9A, a method of making a sine wave by changing the amount of change in amplitude with a constant data output timing; As shown in (b), a method of changing the data output timing while keeping the amount of change in amplitude constant is conceivable.
[0134]
In both cases, a staircase waveform is obtained, but the maximum value of the amplitude change amount in the former case is π / 2 times (about 1.6 times) that in the case of the constant amplitude change amount in the latter case. In a system that measures the difference between two sine waves, if the drive waveform is a smooth sine wave, there is no staircase waveform in the signal, but in the case of a staircase waveform, it is superimposed on the step change as noise in the signal. To do. Therefore, since it is considered that the amount of change is as small as possible, the latter method (FIG. 9B) is adopted in this system.
[0135]
The total of the data reception time and the conversion time of the D / A converters 120.0 to 120.16 used is, for example, approximately 2 μS. In this case, the data output interval needs to be 2 μS or more.
[0136]
In the latter method shown in FIG. 9B, when 1 kHz is divided into 256 (2 to the 8th power), the minimum data output interval is about 2.3 μS. Therefore, under the above conditions, the system may be operated by dividing one cycle into 256 divisions.
[0137]
Since the sine wave is a waveform that is inverted left and right or up and down in a π / 2 period, for example, in order to express this sine wave, one period is divided into four parts, which are divided into 64 points (0th to 63rd) ). In this case, the sine wave is expressed by a 63-stage waveform.
[0138]
Now, the voltage value V (n) at the n-th point can be expressed by the following equation where the one-side amplitude value given from the personal computer 100 is Vpc.
[0139]
V (n) = Vpc × n ÷ 63 + DC offset
However, since the circuit divided by 63 has a large circuit scale, it may be configured to simply ignore the lower 6 bits and use a value equivalently divided by 64. Therefore, in this case, 63/64 of Vpc is the actual one-side amplitude value.
[0140]
Further, if the multiplication part of the above equation is left as it is, it becomes a large multiplication circuit of 11 bits × 6 bits and 17 bits, and it is difficult to mount a maximum of 17 pieces in the FPGA. Therefore, it is possible to configure a multiplier by an adder and a shift register and to make a circuit that operates at 6 clocks (for example, about 0.4 μS).
[0141]
In order to shift the phase, a reference pulse (pulse every 8000 clocks) is generated every half period, and the number of shifts (0.0225 degrees) given by the personal computer 100 is the number of clocks counted from this reference pulse. A reference delay pulse may be generated at the time when the signal becomes equal to (unit), and the output of the sine wave may be started.
[0142]
b) Fourier coefficient calculation
In addition to noise, a distortion component is superimposed on the output signal from the infrared detection sensor of the sensor array 10. For example, when the output is observed with an oscilloscope, the desired signal has a low level. , Hidden by this distortion component.
[0143]
However, by performing fast Fourier transform (hereinafter referred to as FFT), it is possible to take out a change in a signal component of a desired signal having the same frequency as that of the drive signal of the infrared detection sensor, for example, 1 kHz.
[0144]
The FFT algorithm is complicated, and since it is necessary to calculate up to 16 channels simultaneously, it is difficult to implement the circuit in an FPGA. By the way, the FFT calculates all frequencies up to the Nyquist frequency. However, in the present invention, as described above, for example, it is only necessary to extract the frequency component of 1 kHz.
[0145]
In consideration of the distortion signal superimposed on the signal waveform, there is no particular limitation, but the sampling frequency needs to be 4 kHz or more. In general, the sampling frequency is about 10 times as large as the required frequency. Therefore, in the system shown in FIG. 3, for example, sampling may be performed at 32 kHz (2K times 1KHz).
[0146]
At this time, if the i-th data sampled at 32 kHz is Zi, the Fourier coefficient Ca (complex number) for one period can be expressed by the following equation.
[0147]
[Expression 1]

Here, n is 32, f is 1 kHz, and j is an imaginary unit.
[0148]
From the above equation, the Fourier coefficient Ca is a vector on the complex plane, and the coefficient on the real axis side is X and the coefficient on the imaginary axis side is Y as described above.
[0149]
The amplitude of the 1 kHz sine wave is represented by the magnitude of this vector, and the phase difference with respect to the sampling timing is represented by the rotation angle of the vector from the X axis. When the above equation is calculated over a plurality of periods, the magnitude of the vector is proportional to the number of periods, but the phase angle does not change. When the sampling includes noise, the S / N is improved in proportion to the square root of the number of periods.
[0150]
When the circuit for executing the above equation is mounted on the FPGA 110, the sampling timing is determined, and therefore, the sine and cosine functions to be multiplied by the sampling data are 32 kinds of fixed numerical values. Actually, these functions are reversed left and right and up and down in a cycle of π / 2, so it is only necessary to use eight numerical values. These eight coefficient values are stored in ROM (Read in the Fourier coefficient storage unit 2116 of the FPGA 110. Only Memory) table.
[0151]
The sampling data is, for example, 12 bits (1 bit is about 1.22 mV), but the least significant bit has a large noise and has no meaning. In this case, only the upper 11 bits need be used for the calculation. Further, since the amplitude of the signal after the offset adjustment is 1 V or less even after amplification, when the sampling data is 12 bits, the number of bits effective for the calculation of the Fourier coefficient is 10 bits or less.
[0152]
Therefore, these eight coefficient values may be 10-bit data in a system in which sampling data is 12 bits. Therefore, multiplication requires 21 bits. The 21-bit multiplication circuit is a very large circuit and has a large delay. Therefore, in order to suppress the circuit scale, it is possible to configure a multiplication circuit that operates at 10 clocks using a shift register and an addition circuit. The numerical value of the multiplication result is further added to a RAM (Random Access Memory) in the Fourier coefficient storage unit 2116 of the FPGA 110 to obtain a Fourier coefficient.
[0153]
In this system, as an example, since a 21-bit integer is added 32 (2 to the 5th power) times in one cycle and added up to a maximum of 256 (2 to the 8th power) cycle, there is a possibility that the maximum is 34 bits. is there. However, since the actual maximum amplitude is considered to be 1 V or less, this addition can be performed with a 31-bit width.
[0154]
In such a configuration, the lower 31 bits of the 31 bits are meaningless because of noise after the calculation, so in this system, the data transmitted to the personal computer 100 is ignored by ignoring the lower 15 bits. Only 16 bits may be used.
[0155]
When the above calculation for one period is performed on a 1 kHz sine wave having an amplitude (peak-to-peak) of 1 V and the lower 15 bits are ignored, the magnitude (vector length) of the Fourier coefficient (vector) is about 102. It becomes.
[0156]
Assuming that the calculation cycle is N and the magnitude of the calculated Fourier coefficient is F, the actual signal strength V is given by the following equation.
V = F / N / 102
When the amplitude of 1 kHz obtained by the FFT function attached to the oscilloscope is 12.6 mV in the actual signal waveform with the distortion component harmonics superimposed (after amplification by 160 times), it is obtained from the above equation by calculating the Fourier coefficient of 125 periods. The obtained amplitude value was 12.9 mV, which was confirmed to be in good agreement.
[0157]
[Analog signal processor and A / D converter]
In the infrared two-dimensional sensor array 10 shown in FIG. 3, since the signal from the infrared detection sensor is several mV or less, amplification is necessary. In addition, it is necessary to reduce the high frequency noise generated from the digital circuit section and the high frequency components considered to be due to the distortion of the dielectric film and the processing circuit as much as possible, and to cut the 60 Hz component and the direct current component. For this purpose, bandpass filters 140.0 to 140.15 are used.
[0158]
However, when the cutoff characteristic of the filter is steep, the transient characteristic becomes longer, and it is necessary to increase the driving time per pixel. Therefore, an optimum order is also required for the cutoff characteristics of the filter. The bandpass filters 140.0 to 140.15 that are analog circuit portions designed in consideration of these will be further described.
[0159]
For example, if the frequency of the drive sine wave is 1 kHz, harmonic distortion with respect to the output signal appears.
[0160]
Therefore, in consideration of cutting the 60 Hz component and the DC component and the distortion component, the bandpass filters 140.0 to 140.15 have characteristics such as a center frequency of 1 kHz and a gain of 45 dB (180 times), for example. To design.
[0161]
FIG. 10 is a schematic block diagram showing the configuration of such a bandpass filter 140.0. The configurations of the other bandpass filters 140.1 to 140.15 are the same.
[0162]
On the input side, the output from the infrared detection sensor is received by the source follower of the J-FET. This circuit is driven by a single 5V power supply. The 2.5V input to the filter is generated by using a buffer for reducing the voltage to 2.5V from a 5V power source by a Zener diode and supplying the filter stably.
[0163]
(1) Gain frequency characteristics
FIG. 11 is a diagram showing gain frequency characteristics of the circuit shown in FIG.
[0164]
FIG. 11A shows simulation results, and FIG. 11B shows actual measurement values. The center frequency 1 kHz component in both simulation and actual measurement has a gain of about 45 dB. Further, the 2 kHz component has an attenuation of about 25 dB with respect to the 1 kHz component.
[0165]
(2) Time response characteristics
The drive time required for each pixel of the infrared sensor needs to be determined in consideration of noise at the time of pixel switching and the time response characteristics of the filter. The narrower the filter bandwidth, the higher the noise removal capability, but the longer it takes for the filter output to reach a steady state when the signal suddenly changes. Because of this time response characteristic, the waveform processing will give an incorrect result if it is not performed after waiting for the time required to settle to the required accuracy.
[0166]
Therefore, in a 16 × 16 or larger two-dimensional array, it is necessary to shorten the time required to reach a steady state as much as possible.
[0167]
FIG. 12 is a diagram showing time response characteristics of the bandpass filter shown in FIG. Here, FIG. 12 shows an output response waveform when a sine wave 1 kHz signal is input to the bandpass filter as a 10-waveform burst signal.
[0168]
FIG. 12A shows the simulation result, and the output response waveform when a burst signal is input from 5 ms to 15 ms in the figure. FIG. 12B shows measured values, which are output signal waveforms when signal input starts and ends at the timing shown in the figure.
[0169]
In both simulation and actual measurement values, the signal is not stable for 3 ms of rising and falling. Therefore, conversely, under the conditions of the measurement parameters as described above, when the amplitude of the output signal from the bandpass filters 140.0 to 140.15 is calculated by the FPGA 110 as a Fourier coefficient of 1 kHz, It can be seen that sufficiently accurate data can be obtained if a signal of 3 ms or more is taken in after switching.
[0170]
Therefore, with the configuration as described above, it is possible to actually operate the sensor array using a capacitance change detection type infrared sensor having high sensitivity, chopperless, and relatively simple structure. It becomes.
[0171]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0172]
【The invention's effect】
As described above, the infrared detection circuit having a high sensitivity and a simple configuration at room temperature by the driving circuit for the infrared two-dimensional image sensor in which the capacitance change detection type infrared sensor of the present invention is two-dimensionally arranged and the infrared two-dimensional image sensor system. Therefore, it is possible to realize a room temperature operation infrared two-dimensional image sensor having high sensitivity and high density pixels.
[Brief description of the drawings]
FIG. 1 is a diagram equivalently showing one sensor and a circuit for driving the sensor in a two-dimensional sensor array according to the present invention.
FIG. 2 is a diagram showing signal waveforms given to an infrared sensor IRS by signal sources VG1 and VG2.
FIG. 3 is a schematic block diagram illustrating the configuration of an infrared two-dimensional sensor array that can be corrected by an element driving sine wave pulse and a driving circuit thereof.
4 is a schematic block diagram for explaining the configuration of a two-dimensional infrared sensor array 10 and an FPGA 110. FIG.
FIG. 5 is a block diagram for explaining the configuration of the FPGA 110 in more detail.
6 is a schematic block diagram showing a part of the configuration of the personal computer 100. FIG.
FIG. 7 is a conceptual diagram showing vectors when infrared rays are not irradiated and when infrared rays are irradiated, when a Fourier coefficient is expressed by a two-dimensional vector of a coefficient X and a coefficient Y.
FIG. 8 is a flowchart showing a flow of transmission / reception.
FIG. 9 is a diagram schematically showing a waveform of a sine wave output by D / A converters 120.0 to 120.16.
FIG. 10 is a schematic block diagram showing a configuration of a bandpass filter 140.0.
11 is a diagram showing gain frequency characteristics of the circuit shown in FIG.
12 is a diagram showing time response characteristics of the bandpass filter shown in FIG.
[Explanation of symbols]
10. Infrared sensor array, 100 personal computer, 110 FPGA, 120.0 to 120.16 D / A converter, Cref reference capacitor, 130.0 to 130.15 amplifier, 140.0 to 140.15 bandpass filter, 150. 0 to 150.15 A / D converter, 1102 interface unit, 1104 drive waveform calculation unit, 1106 D / A control unit, 1108 switching control unit, 1110 A / D control unit, 1112 Fourier coefficient calculation unit, 2102 data command interface Unit, 2104 reference timing generation unit, 2106 amplitude / phase data storage unit, 2108.0 to 2108.16 drive waveform calculation circuit, 2110.0 to 2110.16 D / A control circuit, 2112.0 to 2121.15 A / D control circuit, 2114 Fourier coefficient calculation circuit, 2116 Fourier coefficient storage unit, 2118 switching pulse generation unit, 3000 keyboard, 3002 man-machine interface unit, 3004 image display parameter setting unit, 3006 pixel drive parameter storage unit, 3008 image data calculation unit, 3010 image display Part, 3012 element drive parameter calculation part, 3014 I / O card part.

Claims (7)

An infrared two-dimensional sensor array in which a plurality of infrared detection sensors are arranged in a matrix;
Each of the infrared detection sensors
A reference capacitor;
An infrared detection capacitor connected in series with the reference capacitor and having a capacitance value that changes in response to incident infrared rays;
Switch means for selectively reading a signal level from a connection node between one end of the reference capacitor and one end of the infrared detection capacitor;
A first signal source for applying an AC reference signal to the other end of the reference capacitor;
A second signal source for applying an alternating drive signal to the other end of the infrared detection capacitor;
The drive signal is based on a signal having the same amplitude as the reference signal and an inverted phase,
The second signal source is in response to said infrared detection sensor, the amplitude and phase of the drive signal is changed by a predetermined value from the value of the reference, the infrared two-dimensional sensor to be read of the signal level Array system. The first signal source is provided in common to the plurality of infrared detection sensors,
The second signal source includes a plurality of signal output means provided for each column of the infrared two-dimensional sensor array,
A row selection means for selecting a row of the infrared two-dimensional sensor array and bringing the switch means belonging to the selected row into a conductive state;
2. The infrared two-dimensional sensor array system according to claim 1, further comprising a plurality of signal reading means provided for each column of the infrared two-dimensional sensor array, for reading the signal level via the switch means. Signal extraction means for extracting a signal of a desired frequency component from the outputs of the plurality of signal reading means;
The signal extraction means includes
Frequency component calculating means for calculating a first real component and a first imaginary component of a Fourier coefficient corresponding to the desired frequency for each of the outputs of the plurality of signal reading means;
The first vector composed of the first real component and the first imaginary component, and the desired output for each of the outputs of the plurality of signal reading means when the infrared two-dimensional sensor array is not irradiated with infrared light. Infrared level calculation means for deriving an infrared detection level based on a difference vector between a second vector composed of a second real number component and a second imaginary number component when calculating a Fourier coefficient corresponding to the frequency of The infrared two-dimensional sensor array system according to claim 2, comprising: The reference signal output from the first signal source and the drive signal output from the second signal source are both sine waves,
The infrared two-dimensional sensor array system according to claim 2, further comprising drive signal parameter storage means for storing a phase and amplitude of a signal to be applied as the drive signal for each infrared detection sensor.   The infrared two-dimensional sensor array system according to claim 3, wherein the desired frequency is a frequency of the drive signal.   The infrared two-dimensional sensor array system according to claim 3, further comprising updating means for updating the second real number component and the second imaginary number component according to a user request.   At least a part of the derivation process of the infrared detection level by the infrared level calculation unit for the row selected at the first timing by the row selection unit and the row selection unit at a second timing after the first timing. The infrared two-dimensional sensor array system according to claim 3, wherein the calculation processing of the frequency component calculation means for the selected row is performed in parallel.

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