JP4254216B2 - Solder paste and method for assembling semiconductor device using the same - Google Patents

Solder paste and method for assembling semiconductor device using the same Download PDF

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JP4254216B2
JP4254216B2 JP2002345116A JP2002345116A JP4254216B2 JP 4254216 B2 JP4254216 B2 JP 4254216B2 JP 2002345116 A JP2002345116 A JP 2002345116A JP 2002345116 A JP2002345116 A JP 2002345116A JP 4254216 B2 JP4254216 B2 JP 4254216B2
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solder
agent
semiconductor element
epoxy resin
solder paste
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JP2004174574A (en
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有史 坂本
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Sumitomo Bakelite Co Ltd
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Sumitomo Bakelite Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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Description

【０００１】
【発明の属する技術分野】
本発明は、半田ペースト及びそれを用いた半導体装置の組立方法に関するものである。
【０００２】
【従来の技術】
半導体素子の高集積化、高密度化と半導体装置の小型化という要求からフリップチップ実装方式が登場した。このフリップチップ実装方式は、従来のワイヤーボンディングによる接続とは異なり、半導体素子と半導体素子搭載用基板とを半田電極を介して電気的接合をすることにより小型、薄型化を可能としたものである。しかし、半導体素子、半導体素子搭載用基板、半田電極に関し、それぞれの熱膨張係数が異なるために冷熱衝撃試験時に熱ストレスが発生する。特に半導体素子中央から遠いコーナー近辺の半田電極には局所的に熱ストレスが集中するため接合部位にクラックが生じ、回路の作動信頼性が大きく低下する等のおそれがあった。
【０００３】
そこで、熱ストレスを緩和する目的から液状注入封止アンダーフィル材による封止が行なわれ工業的に普及している。この液状注入封止アンダーフィル材を用いる一連の製造工程の一例を示す。先ず半導体素子に半田電極を形成する。その形成方法は、半導体素子にフラックス機能を有する活性ロジン等（以下、フラックスという）のカルボン酸化合物を含む半田ペーストを塗布し、加熱して半田粉を一体化させ半田電極を形成する方法と予め作製された所定の大きさの半田ボールにフラックスを塗布して電極形成部位に載置し加熱後、接合させて半田電極を形成する方法が一般的に行われている。この際、フラックスは一部揮散するが一部は変性し半田電極の周りに残る。この残渣はイオン性の不純物を含むことが多く、高温高湿下での半田電極間のリーク電流の原因ともなり好ましくないため、残渣を液体洗浄剤で除去する。更に半導体素子搭載用基板に半田電極を同様のフラックスを介して加熱接合させる。その際も洗浄工程が必要な場合もある。最後に液状注入封止アンダーフィル材を注入硬化させ半導体装置が製造される。このように製造工程は長く、又洗浄工程があるため環境に対する負荷の問題もある。
【０００４】
これらの問題を解決するためにノンフローアンダーフィル材を用いる方法が提案されている。これは半導体素子搭載用基板又は半田電極付半導体素子の電極形成部位に熱硬化性樹脂、硬化剤及びフラックス機能を有する化合物を含む材料を塗布し半導体素子と半導体搭載用基板を重ね、封止と接合を同時に行う技術である（例えば、特許文献１参照。）。ところが、活性ロジンの様な有機系フラックスやハロゲン化合物の様な無機系のフラックス機能を有する化合物等は、硬化後に硬化物中にフリーで残存し、先に述べた半田電極間のリーク問題が発生するおそれがあり、更には急激な高温加熱により工程中に発生するボイドを皆無にすることが困難である。
【０００５】
又半田電極を形成する際に用いられるフラックスを熱硬化性樹脂系とすることにより、半田電極形成と共に半田電極の周りに熱硬化性フラックスが接合し半田補強を行う技術が提案されている（例えば、特許文献２参照。）。この場合の補強は、一度に一つの電極形成部位に施される。即ち、半田ボールないし対応する半導体素子搭載用基板に熱硬化性フラックスを塗布、半田ボールを載置し加熱後、半田電極を形成すると共に半田電極の周りを補強することができる。この方法によると半田電極の補強は一回の工程において、半田電極の片側の補強（半導体素子/半田電極又は半導体搭載用基板/半田電極）を行うことができる。しかし、補強をより強化するためには、全ての半田電極接合の際に用いれば両側の半田電極形成部位の補強を行うことができ、より信頼性向上が期待できる。しかし、上記の方法によると工程が二度になるため工程が長くなる問題は引き続き残っており、半田電極を一括補強できる半導体装置の組立方法が求められている。そこで半田ペーストを半導体素子搭載用基板もしくはウエハー又は個片化した半導体素子に塗布し、加熱処理によりＢ−ステージ化することが可能であれば、その剛性のため半導体素子を半導体素子搭載用基板に接合する際の位置決めが可能であり、更に加熱することにより溶融し、その際フラックス活性が発現するため前記基板と半田電極とを接合させることができ、半田ペーストに含まれる熱硬化性成分が、形成された半田電極の周囲を保護することができる。又Ｂ−ステージ状態で保管すれば半導体装置の生産計画性を向上させることができ、先に述べた半導体装置の組立工程を大幅に短縮することもできる。しかし、このような要求を満たす半田ペーストはなかった。
【０００６】
【特許文献１】
米国特許第５,１２８,７４６号明細書（全頁）
【特許文献２】
国際公開第０１／４７６６０号パンフレット（全頁）
【０００７】
【発明が解決しようとする課題】
本発明は、半田ペーストがＢステージ性を有しており、Ｂ−ステージ状態にすることにより、半導体素子を半導体素子搭載用基板に載置したとき位置ずれ、潰れがなく、半田電極形成を一括に行うことができ、同時に半田電極の全面を硬化した熱硬化性成分で補強でき、従来の液状注入アンダーフィル材で充填する半導体装置の組立方法に比べ製造工程を大幅に短縮化できる半導体装置の組立方法を提供するものである。
【０００８】
【課題を解決するための手段】
本発明は、
［１］ （Ａ）エポキシ樹脂と、常温で結晶の１分子当たり少なくとも２個以上のフェノール性水酸基と１分子当たり少なくとも１個以上の芳香族カルボン酸を有するフラックス機能を有する硬化剤を含む熱硬化性成分、（Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、水酸基を有さない溶剤及び（Ｃ）半田粉を必須成分として配合し、必要により硬化促進剤、着色剤、レベリング剤、カップリング剤、チクソ剤、消泡剤を配合し且つＢ−ステージ性を有する半田ペーストを半導体素子搭載用基板もしくはウエハー又は個片化した半導体素子に塗布し、加熱処理により半田ペーストをＢ−ステージ化後、接合する部位を有する部材に載置し、全体加熱法又は部分加熱法を用いて半田粉の融点以上に加熱し、半田電極形成及び半導体素子／半導体搭載用基板間の電気的接合を行い、且つ熱硬化性成分が前記半田電極の周囲を補強することを特徴とする半導体装置の組立方法、
［２］ （Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、且つ水酸基を有さない溶剤が、ブチルセロソルブアセテートである第［１］項記載の半導体装置の組立方法、
［３］ 第［１］又は［２］項記載の半導体装置の組立方法に用いられる半田ペーストであって、（Ａ）エポキシ樹脂と、常温で結晶の１分子当たり少なくとも２個以上のフェノール性水酸基と１分子当たり少なくとも１個以上の芳香族カルボン酸を有するフラックス機能を有する硬化剤を含む熱硬化性成分、（Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、且つ水酸基を有さない溶剤及び（Ｃ）半田粉を必須成分として配合し、必要により硬化促進剤、着色剤、レベリング剤、カップリング剤、チクソ剤、消泡剤を配合し且つＢ−ステージ性を有することを特徴とする半田ペースト、
である。
【０００９】
【発明の実施の形態】
以下、本発明について詳細に説明する。
本発明に用いられる半田ペーストは、エポキシ樹脂と、常温で結晶の１分子当たり少なくとも２個以上のフェノール性水酸基と１分子当たり少なくとも１個以上の芳香族カルボン酸を有するフラックス機能を有する硬化剤（以下、硬化剤という）を含む熱硬化性成分、前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、水酸基を有さない溶剤及び半田粉を必須成分とし、加熱処理後にＢ−ステージ性を有するものである。尚、本発明での常温とは、２３℃±３℃のことを指す。
本発明に用いられるエポキシ樹脂は、特に限定しないが、例えばビスフェノールＡジグリシジルエーテル型エポキシ樹脂及びそれらの水添物、ビスフェノールＦジグリシジルエーテル型エポキシ樹脂及びその水添物、ビスフェノールＳジグリシジルエーテル型エポキシ樹脂、３，３’，５，５’−テトラメチル−４，４’−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ樹脂、４，４’−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ樹脂、１，６−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、臭素型クレゾールノボラック型エポキシ樹脂、ビスフェノールＡＤジグリシジルエーテル型エポキシ樹脂、１，６−ナフタレンジオールのグリシジルエーテル、アミノフェノール類のトリグリシジルエーテル等ビスフェノール型エポキシ樹脂、ナフタレンジオールのグリシジルエーテル、又直鎖脂肪族グリシジルエーテル類、脂環式エポキシ樹脂類等が挙げられる。
【００１０】
本発明に用いられる常温で結晶の硬化剤としては、例えば２，３−ジヒドロキシ安息香酸、２，４−ヒドロキシ安息香酸、２，５−ヒドロキシ安息香酸、２，６−ヒドロキシ安息香酸、３，４−ジヒドロキシ安息香酸、没食子酸、１，４−ジヒドロキシ−２−ナフトエ酸、３，５−ジヒドロキシ−２−ナフトエ酸、フェノールフタリン、ジフェノール酸等が挙げられるがこの限りではない。これらを硬化剤とした場合、フラックス機能が発現した後エポキシ樹脂と反応し硬化マトリックスの一部になるため、前記したような電気的不良を起こすおそれが極めて低くなる。
【００１１】
本発明に用いられる溶剤は、エポキシ樹脂を溶解させ、硬化剤は溶解しないことが必要である。本発明での溶解しないということは、常温で通常の溶解法（攪拌、振動等）により溶解性が５％以下のことを指し、好ましくは１％以下である。溶剤に対する硬化剤の溶解性が向上するに従い、エポキシ樹脂との反応が常温でも加速され、Ｂ−ステージ性が発現できなくなる。溶剤の具体例としては、モノグリシジルエーテルのような反応性希釈剤、エステル、ケトン、芳香族炭化水素、脂肪族炭化水素等が挙げられる。水酸基を有さない溶剤は、前記硬化剤に対する溶解性が高くＢ−ステージ性を発現させるのは困難であるため使用不可能である。溶解性は、硬化剤の種類により変わるため、予め溶解試験を行い選択使用することが好ましい。このような溶剤を用いることにより、Ｂ−ステージ状態でも硬化剤の結晶が残り、Ｂ−ステージ性が向上する。
【００１２】
本発明に用いられる半田粉は、錫、銀、銅、鉛、亜鉛、ビスマス、アンチモン、インジウム等の金属を組み合わせた、既存の合金半田である。半田粉の粒子径は、少なくとも得られる半田電極の径に比べて小さいことが必要である。作業性等を考慮すると、粒径としては４０μｍ以下が好ましい。半田粉の含有量としては、７５〜９５重量％が好ましく、より好ましくは８０〜９５重量％である。上限値を越えると半田ペーストの粘度が高くなり過ぎ作業性に支障をきたし、下限値未満だと熱硬化性成分が多くなりすぎ半田電極が正確に形成されなくなるおそれがある。又半田ペーストには、必要によって硬化促進剤、着色剤、レベリング剤、カップリング剤、チクソ剤、消泡剤等の各種添加剤を配合することができる。半田ペーストの作製方法は、例えばライカイ機、ロール、遠心混練機等の方法を用いて作製すればよい。
【００１３】
本発明に用いられる半田ペーストが、Ｂ−ステージ性を有するということは、半田ペーストを半導体素子搭載用基板もしくはウエハー又は個片化した半導体素子に塗布し、加熱乾燥した後常温に１ヶ月以上保存しても固形又はタックのある固形状態を維持し、且つ接合時に乾燥した半田ペーストが流動しフラックス作用や半田補強等の機能が発現できることを指す。
【００１４】
本発明の半田ペーストが、Ｂ−ステージ性を発現させるための方法としては、エポキシ樹脂に硬化剤を固体のまま分散させればよいが、半田粉を配合することにより、粘度が高くなりペースト性状が得られにくい場合、溶剤の量を調整すればよい。Ｂ−ステージ性を発現させるためには、加熱処理中に用いた硬化剤が溶解せす゛、且つ所定硬化条件より加熱温度を低く設定することが重要である。
【００１５】
次に、本発明の半田ペーストを用いた半導体装置の組立方法の例について図面を用いて説明するが、これらに限定されるものではない。図１は、回路形成されたウエハー２の電極形成部位５に、熱硬化性成分３と半田粉４を含む半田ペースト１を塗布した状態を示す概念図である。塗布する方法は印刷、ディスペンス等の既存の方法を用いればよい。塗布後、Ｂ−ステージ化するために硬化剤が溶解しない程度に、且つ所定硬化条件より低い温度条件で加熱処理をする。予め加熱処理しＢ−ステージ化することにより半田ペーストは、常温で固体状態なので、半導体素子搭載用基板であるプリント配線板等と接合する際の位置決め時に変形等の問題がない。液状状態の半田ペーストではこのような工程は極めて困難である。図２は、ウエハーを各半導体素子６にダイシングした状態を示す図である。又位置決めを容易にするためにステージを加温させることにより、Ｂ−ステージ化した半田ペーストにタック性を発現させることもできる。この場合、再固化することにより位置がずれ危険性を回避できる。
【００１６】
図３は、Ｂ−ステージ化された半田ペーストを有する半導体素子をプリント配線基板７にフリップチップボンダーにより位置決めし、対応するプリント配線基板の電極形成部位（金属表面パッド）８に載置した状態を示す概念図である。位置決めの際は、Ｂ−ステージ化された部材をボンダー上で加温してタックを持たせるようにして載置すると取り扱いが容易になる。この状態にてフリップチップボンダー上で部分加熱法（パルスヒート法等）により加熱溶融させるか、リフロー炉（全体加熱法）に載置したものを通す。いずれの加熱方法でも半田粉の融点を越える温度に加熱する。昇温中にＢ−ステージ化した半田ペーストが再溶融し半田の融点付近でフラックス作用を発現し、図４に示すように半田の溶融と共に半田粉が一体化し半田電極９を形成し、更にプリント配線基板の電極形成部位８周辺と半導体素子の電極形成部位５の周辺を濡らし、半導体素子側とプリント配線基板側に同時に接合する。並行して溶融したＢ−ステージ化された熱硬化性成分は半田電極の周り、半導体素子、プリント配線基板に浸出し硬化した後は半田電極の全体を補強する。図４は、半導体素子とプリント配線基板が半田電極を介して接合され、半田電極の周り、半導体素子の電極形成部位とプリント配線基板の電極形成部位の周りが硬化した熱硬化性成分１０で補強された状態を示す。予めＢ−ステージ状態にすることにより、半導体素子をプリント配線基板に載置したとき位置ずれ、潰れがなく、半田電極形成、接合を一括で行うことができる。
【００１７】
半田接合条件で硬化が不十分の場合は、ポストベークをすることも可能である。又本発明では予め半導体素子側と基板側の各々に半田ペーストを塗布し、Ｂ−ステージ化後、加熱することにより半田電極形成、接合、硬化した熱硬化性成分での補強を行なうこともできる。
本発明では、ウエハーに塗布し加熱処理により半田ペーストをＢ−ステージ化したものは、個片化して接合する。更にＢ−ステージ化された半田ペーストを有する半導体素子搭載用基板については、必要により個片化して接合する。本発明に用いる半導体素子搭載用基板とは、プラスチックやセラミック等の各種絶縁基板のことをいう。
【００１８】
実施例１
ビスフェノールＡ型エポキシ樹脂（エポキシ当量２００）７０重量部をブチルセロソルブアセテート（ブチルセロソルブアセテートに対する、下記硬化剤の溶解度は１％以下）３０重量部に溶解させたワニス１００重量部、フラックス作用を有する硬化剤として２，５−ジヒドロキシ安息香酸１８重量部、硬化促進剤として２−フェニル−４−エチルイミダゾール０．２重量部、半田粉として融点１８３℃の錫／鉛共晶の半田粉（平均粒径３０μｍ）９０重量部を秤量し３本ロールにて混練・分散後、真空脱泡処理を行い半田ペーストを作製した。作製した半田ペーストを、メタルマスクを用いて印刷法により、厚み３５０μｍのウエハー（個片化した後それぞれの半導体素子で電気的接続性が調べられるようなデイジーチェーンの回路が形成してあるもの、接続金属パッド数：４００、パッド配列：フルアレイ、パッド開口１００μｍ）上に樹脂塗布した。その後８０℃、９０分でＢ−ステージ化を行い、最終厚みが１００μｍ、ウエハーに接する部分の直径が約１２０μｍの突起物を全ての電極形成部位（パッド）上に形成させた。次にダイシングソーを用いてウエハーを半導体素子毎に個片化した（半導体素子サイズ６×６ｍｍ）。更にフリップチップボンダーを用いて１０ｍｍ角のガラス−エポキシ基板（対応部位に金メッキされた開口径１００μｍのパッドが形成してあるもの）に半導体素子を載置し、最高温度２２０℃、最低温度１８３℃で６０秒（昇温を含めた通過時間１８０秒）のＩＲリフロー炉に通した。半田ペースト中の半田粉は一体化し半導体素子及びガラス−エポキシ基板の各接合パッドに接合した。更に半田周辺（半導体素子、ガラス−エポキシ基板部分含む）が熱硬化性成分で覆われていることが確認できた。更に１５０℃で１時間のポストベークを行い硬化させた。又Ｂ−ステージ化した後１ヶ月、２ヶ月それぞれ常温にて保存したものを同様に接合を行い、初期と同様に半田接合がなされていることを確認できた。接続はデイジーチェーンにより調査した。得られたパッケージの信頼性として熱衝撃試験を行い、全てのバンプの接続信頼性を調べた。試験条件は−４０℃⇔１２５℃であり、測定は１００サイクル毎に行い、試験数はＮ＝１０、不良が起こり始めるサイクル数をカウントした（以下、Ｔ／Ｃ信頼性という）。
【００１９】
実施例２
ビスフェノールＡ型エポキシ樹脂（エポキシ当量２００）７０重量部をブチルセロソルブアセテート（ブチルセロソルブアセテートに対する、下記硬化剤の溶解度は１％以下）３０重量部に溶解させたワニス１００重量部、フラックス作用を示す硬化剤としてフェノールフタリン２０重量部、硬化促進剤として２−フェニル−４−エチルイミダゾール０．５重量部、融点２２０℃の錫／銀／銅の半田粉（平均粒径２０μｍ）８０重量部を秤量し３本ロールにて混練・分散後、真空脱泡処理を行い半田ペーストを作製し、リフローの条件を最高温度２５０℃、最低温度２２０℃で６０秒（昇温含めた通過時間１８０秒）とした以外は、実施例１と同様にパッケージを組立、評価を行った。
【００２０】
比較例１
ビスフェノールＡ型エポキシ樹脂（エポキシ当量２００）７０重量部をブチルセロソルブアセテート１０重量部に溶解させたワニス８０重量部、フラックス作用を有する硬化剤として２，５−ジヒドロキシ安息香酸１８重量部、硬化促進剤として２−フェニル−４−エチルイミダゾール０．２重量部を用いて、実施例１と同様の操作でペーストを作製した。次に実施例１の仕様のウエハーに、実施例１と同一の組成の共晶半田粉、活性ロジンを含む半田ペーストを用いて、直径１００μｍの半田電極を形成した後、フラックス洗浄（以下、フラックス洗浄１という）をした後、ダイシングして個片化した半導体素子（個片化後：６×６ｍｍ）の半田電極に、作製したペーストを塗布しフリップチップボンダーを用いて対応する実施例１と同一のガラス−エポキシ基板に載置し、実施例１と同一のリフローを用いて接合した。図５に示すように硬化した熱硬化性成分１０が、半田電極のガラス−エポキシ基板の近い側、即ち基板の電極形成部位の周りを覆っていることが確認された。以後の評価は実施例１と同様に行った。
【００２１】
比較例２
実施例１の仕様のウエハーに、実施例１と同一の組成で、予め作製した直径１００μｍの共晶半田ボールに、比較例１で作製したペーストを塗布しボールマウンターを用いて載置し、実施例１のリフロー条件により半田ボールを溶融させ半田電極を形成させた後、ダイシングして個片化した半導体素子（個片化後：６×６ｍｍ）を得た。半田電極を有する半導体素子の半田電極に活性ロジンを含むペーストを塗布し、実施例１と同一のガラス−エポキシ基板に載置し、実施例１と同一のリフローを用いて接合した。その後フラックス洗浄を行った（以下、フラックス洗浄２という）。図６に示すように硬化した熱硬化性成分１０が、半田電極の半導体素子に近い側、半導体素子の電極形成部位の周りを覆っていることが確認された。以後の評価は実施例１と同様に行った。
【００２２】
比較例３
実施例１の仕様のウエハーに、実施例１と同一の組成で、予め作製した直径１００μｍの共晶半田ボールに、比較例１で作製したペーストを塗布しボールマウンターを用いて載置し、実施例１のリフロー条件により半田ボールを溶融させ半田電極を形成させた後、ダイシングして個片化した半導体素子（個片化後：６×６ｍｍ）を得た。半田電極を有する半導体素子の半田電極に、比較例１で作製したペーストを塗布し、実施例１と同一のガラス−エポキシ基板に載置し、実施例１と同一のリフローを用いて接合した。接合状態、半田電極と半導体素子の電極形成部位、ガラス−エポキシ基板の電極形成部位の周りは良好な被覆状態であることが確認された。
【００２３】
比較例４
実施例１の仕様のウエハーに、実施例１と同一の組成の共晶半田粉、活性ロジンを含む半田ペーストを用いて、直径１００μｍの半田電極を形成した後、（このあたりの条件は）フラックス洗浄（以下、フラックス洗浄１という）をした後、ダイシングして個片化した半導体素子（個片化後：６×６ｍｍ）の半田電極に、上記と同一の半田ペーストを塗布しフリップチップボンダーを用いて対応する実施例１と同一のガラス−エポキシ基板に載置し、実施例１と同一のリフローを用いて接合した。この後に、フラックス洗浄（以下、フラックス洗浄２という）を行った。次に液状注入封止アンダーフィル剤［（ＣＲＰ−４１５２（住友ベークライト（株）・製））を充填させ、１５０℃、１２０分で硬化させた。図７に示すように、硬化したアンダーフィル材１１が充填され、半田電極が補強されている。実施例１と同様の信頼性試験を行った。
【００２４】
【表１】

Figure 0004254216
【００２５】
実施例１、実施例２は、一括接合ができ、半田電極周辺が完全に補強されているため、Ｔ／Ｃ信頼性に優れている。比較例１、比較例２では半田電極が部分的にしか補強されていないので、Ｔ／Ｃ信頼性に劣る。比較例３、比較例４は、Ｔ／Ｃ信頼性には優れている。いずれにしても比較例１〜比較例４は一括接合ができないので、生産性の相対工数の比較では、本発明に較べて劣る。
【００２６】
【発明の効果】
本発明の組立方法に従うと、用いる半田ペーストがＢステージ性を有しており、Ｂ−ステージ状態にすることにより、半導体素子を半導体搭載用基板に載置したとき位置ずれ、潰れがなく、半田電極形成を一括に行うことができ、同時に半田電極の周り、半導体素子の電極形成部位と半導体搭載用基板の電極形成部位の周りを硬化した熱硬化性成分で補強でき、従来の液状注入封止アンダーフィル材で充填する組立方法に比べ、製造工程を大幅に短縮化することができる。Ｂ−ステージ性を有するため、Ｂ−ステージ状態での在庫が可能となり計画的生産を行うことができる。
【図面の簡単な説明】
【図１】 回路形成されたウエハーの電極形成部位に、半田ペーストを塗布した状態を示す断面の概念図である。
【図２】 ウエハーを各半導体素子にダイシングした状態を示す断面の図である。
【図３】 Ｂ−ステージ化された半田ペーストを有する半導体素子をプリント配線基板の電極形成部位に載置した状態を示す断面の概念図である。
【図４】 半導体素子とプリント配線基板が半田電極を介して接合され、半田電極の周り、半導体素子の電極形成部位とプリント配線基板の電極形成部位の周りを硬化した熱硬化性成分で補強された状態を示す断面図である。
【図５】 比較例１における、硬化した熱硬化性成分が、半田電極のガラス−エポキシ基板の近い側、基板の電極形成部位の周りを覆っている状態を示す断面図である。
【図６】 比較例２における、硬化した熱硬化性成分が、半田電極の半導体素子の近い側、半導体素子の電極形成部位の周りを覆っている状態を示す断面図である。
【図７】 比較例４における、硬化したアンダーフィル材が充填され、半田電極が補強されていることを示す断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solder paste and a method for assembling a semiconductor device using the solder paste.
[0002]
[Prior art]
Flip chip mounting methods have emerged due to demands for higher integration and higher density of semiconductor elements and miniaturization of semiconductor devices. Unlike the conventional wire bonding connection, this flip-chip mounting method allows a semiconductor element and a semiconductor element mounting substrate to be electrically bonded via a solder electrode, thereby enabling a reduction in size and thickness. . However, regarding the semiconductor element, the semiconductor element mounting substrate, and the solder electrode, thermal stress is generated during the thermal shock test because the respective thermal expansion coefficients are different. In particular, the thermal stress is concentrated locally on the solder electrode near the corner far from the center of the semiconductor element, so that there is a risk that the operation reliability of the circuit will be greatly reduced due to cracks at the joint portion.
[0003]
Therefore, for the purpose of alleviating thermal stress, sealing with a liquid injection sealing underfill material is performed and is widely used industrially. An example of a series of manufacturing steps using this liquid injection sealing underfill material is shown. First, a solder electrode is formed on a semiconductor element. The formation method includes applying a solder paste containing a carboxylic acid compound such as active rosin having a flux function (hereinafter referred to as flux) to a semiconductor element and heating to integrate the solder powder to form a solder electrode in advance. A method is generally employed in which flux is applied to a solder ball having a predetermined size, placed on an electrode forming portion, heated, and then bonded to form a solder electrode. At this time, the flux is partially volatilized, but part of it is denatured and remains around the solder electrode. Since this residue often contains ionic impurities and causes a leakage current between the solder electrodes under high temperature and high humidity, it is not preferable. Therefore, the residue is removed with a liquid cleaning agent. Further, the solder electrode is heated and bonded to the semiconductor element mounting substrate through the same flux. In this case, a cleaning process may be necessary. Finally, the liquid injection sealing underfill material is injected and cured to manufacture a semiconductor device. As described above, the manufacturing process is long and there is a problem of burden on the environment due to the cleaning process.
[0004]
In order to solve these problems, a method using a non-flow underfill material has been proposed. This is done by applying a material containing a thermosetting resin, a curing agent and a compound having a flux function to the electrode forming portion of the semiconductor element mounting substrate or the semiconductor element with solder electrodes, and stacking the semiconductor element and the semiconductor mounting substrate, sealing This is a technique for performing bonding simultaneously (see, for example, Patent Document 1). However, organic fluxes such as active rosin and inorganic fluxes such as halogen compounds remain free in the cured product after curing, causing the aforementioned leakage problem between solder electrodes. In addition, it is difficult to eliminate voids generated during the process due to rapid high-temperature heating.
[0005]
In addition, a technique has been proposed in which the flux used when forming the solder electrode is a thermosetting resin system, and solder reinforcement is performed by joining the thermosetting flux around the solder electrode together with the solder electrode formation (for example, , See Patent Document 2). In this case, reinforcement is applied to one electrode forming portion at a time. That is, a thermosetting flux can be applied to a solder ball or a corresponding semiconductor element mounting substrate, the solder ball can be placed and heated, and then a solder electrode can be formed and the periphery of the solder electrode can be reinforced. According to this method, the solder electrode can be reinforced on one side of the solder electrode (semiconductor element / solder electrode or semiconductor mounting substrate / solder electrode) in one step. However, in order to further strengthen the reinforcement, if it is used at the time of joining all the solder electrodes, it is possible to reinforce the solder electrode forming portions on both sides, and it can be expected to improve reliability. However, according to the above-described method, the problem that the process becomes long because the process becomes twice remains, and a method for assembling a semiconductor device that can reinforce the solder electrodes collectively is required. Therefore, if it is possible to apply the solder paste to a semiconductor element mounting substrate or wafer or a separated semiconductor element and to make a B-stage by heat treatment, the semiconductor element is applied to the semiconductor element mounting substrate because of its rigidity. Positioning at the time of bonding is possible, further melting by heating, and flux activity is expressed at that time, so the substrate and the solder electrode can be bonded, and the thermosetting component contained in the solder paste is The periphery of the formed solder electrode can be protected. Further, if stored in the B-stage state, the production planability of the semiconductor device can be improved, and the assembly process of the semiconductor device described above can be greatly shortened. However, there has been no solder paste that satisfies these requirements.
[0006]
[Patent Document 1]
US Pat. No. 5,128,746 (all pages)
[Patent Document 2]
WO 01/47660 pamphlet (all pages)
[0007]
[Problems to be solved by the invention]
According to the present invention, the solder paste has a B-stage property, and when the semiconductor element is placed on the substrate for mounting the semiconductor element, the solder electrode is formed without forming a position shift or crushing. A semiconductor device that can be reinforced at the same time with a hardened thermosetting component on the entire surface of the solder electrode, and the manufacturing process can be greatly reduced compared to the conventional method of assembling a semiconductor device filled with a liquid injection underfill material. An assembly method is provided.
[0008]
[Means for Solving the Problems]
The present invention
[1] Thermosetting comprising (A) an epoxy resin and a curing agent having a flux function having at least two phenolic hydroxyl groups per molecule of crystals and at least one aromatic carboxylic acid per molecule at room temperature (B) Solvent that dissolves the epoxy resin, does not dissolve the curing agent, and contains a solvent having no hydroxyl group and (C) solder powder as essential components, and if necessary, a curing accelerator, a colorant, and a leveling agent , A soldering paste containing a coupling agent, a thixotropic agent and an antifoaming agent and having a B-stage property is applied to a semiconductor element mounting substrate or wafer or a semiconductor element separated into individual pieces, and the solder paste is B- After being staged, it is placed on a member having a part to be joined, and heated to the melting point or higher of the solder powder using the whole heating method or the partial heating method, and the solder electrode formation and the semiconductor element are performed. A method of assembling a semiconductor device, wherein electrical connection between the child / semiconductor mounting substrate is performed, and a thermosetting component reinforces the periphery of the solder electrode;
[2] (B) The method of assembling the semiconductor device according to item [1], wherein the solvent that does not dissolve the epoxy resin and does not dissolve the curing agent and does not have a hydroxyl group is butyl cellosolve acetate.
[3] A solder paste used in the method for assembling a semiconductor device according to [1] or [2] , wherein (A) an epoxy resin and at least two phenolic hydroxyl groups per molecule of crystal at room temperature And a thermosetting component containing a curing agent having a flux function having at least one aromatic carboxylic acid per molecule, (B) dissolving the epoxy resin, not dissolving the curing agent, and having a hydroxyl group A non-solvent and (C) solder powder as essential components, and if necessary, a curing accelerator, a colorant, a leveling agent, a coupling agent, a thixotropic agent, an antifoaming agent, and a B-stage property Solder paste,
It is.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail.
The solder paste used in the present invention comprises an epoxy resin, a curing agent having a flux function having at least two phenolic hydroxyl groups per molecule of crystals and at least one aromatic carboxylic acid per molecule at room temperature ( Hereinafter referred to as a curing agent), the epoxy resin is dissolved, the curing agent is not dissolved, a solvent having no hydroxyl group and solder powder are essential components, and B-stage properties are obtained after heat treatment. Is. In addition, the normal temperature in this invention refers to 23 degreeC +/- 3 degreeC.
The epoxy resin used in the present invention is not particularly limited. For example, bisphenol A diglycidyl ether type epoxy resins and hydrogenated products thereof, bisphenol F diglycidyl ether type epoxy resins and hydrogenated products thereof, bisphenol S diglycidyl ether type Epoxy resin, 3,3 ′, 5,5′-tetramethyl-4,4′-dihydroxybiphenyl diglycidyl ether type epoxy resin, 4,4′-dihydroxybiphenyl diglycidyl ether type epoxy resin, 1,6-dihydroxybiphenyl Diglycidyl ether type epoxy resin, phenol novolac type epoxy resin, bromine type cresol novolac type epoxy resin, bisphenol AD diglycidyl ether type epoxy resin, 1,6-naphthalenediol glycidyl ether, aminophenol Examples thereof include bisphenol-type epoxy resins such as triglycidyl ethers of diols, glycidyl ethers of naphthalene diol, linear aliphatic glycidyl ethers, and alicyclic epoxy resins.
[0010]
Examples of the curing agent for crystals used at normal temperature in the present invention include 2,3-dihydroxybenzoic acid, 2,4-hydroxybenzoic acid, 2,5-hydroxybenzoic acid, 2,6-hydroxybenzoic acid, and 3,4. -Dihydroxybenzoic acid, gallic acid, 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy-2-naphthoic acid, phenolphthaline, diphenolic acid and the like are not limited thereto. When these are used as curing agents, the flux function is exhibited and then reacts with the epoxy resin to become a part of the curing matrix, so that the possibility of causing electrical failures as described above becomes extremely low.
[0011]
The solvent used in the present invention needs to dissolve the epoxy resin and not the curing agent. The fact that it does not dissolve in the present invention means that the solubility is 5% or less, preferably 1% or less, at ordinary temperature by a usual dissolution method (stirring, vibration, etc.). As the solubility of the curing agent in the solvent improves, the reaction with the epoxy resin is accelerated even at room temperature, and the B-stage property cannot be expressed. Specific examples of the solvent include reactive diluents such as monoglycidyl ether, esters, ketones, aromatic hydrocarbons and aliphatic hydrocarbons. A solvent having no hydroxyl group cannot be used because it has high solubility in the curing agent and it is difficult to develop B-stage properties. Since solubility changes with kinds of hardening | curing agent, it is preferable to perform a dissolution test beforehand and to use it selectively. By using such a solvent, crystals of the curing agent remain even in the B-stage state, and the B-stage property is improved.
[0012]
The solder powder used in the present invention is an existing alloy solder in which metals such as tin, silver, copper, lead, zinc, bismuth, antimony, and indium are combined. It is necessary that the particle diameter of the solder powder be at least smaller than the diameter of the obtained solder electrode. Considering workability and the like, the particle size is preferably 40 μm or less. As content of solder powder, 75 to 95 weight% is preferable, More preferably, it is 80 to 95 weight%. If the upper limit is exceeded, the viscosity of the solder paste will be too high and workability will be hindered, and if it is less than the lower limit, the thermosetting component will increase so much that the solder electrode may not be formed accurately. The solder paste may contain various additives such as a curing accelerator, a colorant, a leveling agent, a coupling agent, a thixotropic agent, and an antifoaming agent, if necessary. What is necessary is just to produce the production methods of a solder paste, for example using methods, such as a reika machine, a roll, and a centrifugal kneader.
[0013]
The solder paste used in the present invention has a B-stage property, which means that the solder paste is applied to a semiconductor element mounting substrate, a wafer, or an individual semiconductor element, heat-dried, and stored at room temperature for one month or longer. Even so, it means that the solid state with a solid or tack is maintained, and the solder paste dried at the time of joining flows to exhibit functions such as flux action and solder reinforcement.
[0014]
The solder paste of the present invention can be used as a method for expressing the B-stage property. The curing agent may be dispersed as a solid in the epoxy resin, but by adding the solder powder, the viscosity increases and the paste properties If it is difficult to obtain, the amount of solvent may be adjusted. In order to develop B-stage properties, it is important that the curing agent used during the heat treatment dissolves and that the heating temperature is set lower than the predetermined curing conditions.
[0015]
Next, an example of a method for assembling a semiconductor device using the solder paste of the present invention will be described with reference to the drawings, but is not limited thereto. FIG. 1 is a conceptual diagram showing a state in which a solder paste 1 containing a thermosetting component 3 and solder powder 4 is applied to an electrode forming portion 5 of a wafer 2 on which a circuit is formed. An existing method such as printing or dispensing may be used as the coating method. After the application, heat treatment is performed under a temperature condition lower than a predetermined curing condition so that the curing agent does not dissolve in order to make a B-stage. Since the solder paste is in a solid state at room temperature by performing heat treatment in advance and forming a B-stage, there is no problem of deformation or the like when positioning with a printed wiring board or the like which is a semiconductor element mounting substrate. Such a process is extremely difficult with a solder paste in a liquid state. FIG. 2 is a view showing a state where the wafer is diced into the respective semiconductor elements 6. Further, by heating the stage to facilitate positioning, tackiness can be expressed in the B-staged solder paste. In this case, the risk of misalignment can be avoided by resolidification.
[0016]
FIG. 3 shows a state in which a semiconductor element having a B-staged solder paste is positioned on a printed wiring board 7 by a flip chip bonder and placed on an electrode formation site (metal surface pad) 8 of the corresponding printed wiring board. FIG. At the time of positioning, the B-staged member is heated on the bonder and placed so as to have a tack to facilitate handling. In this state, it is heated and melted by a partial heating method (pulse heat method or the like) on a flip chip bonder or passed through a reflow furnace (overall heating method). In any heating method, heating is performed to a temperature exceeding the melting point of the solder powder. During the temperature rise, the B-staged solder paste is re-melted to develop a flux action in the vicinity of the melting point of the solder, and as shown in FIG. The periphery of the electrode forming portion 8 of the wiring board and the periphery of the electrode forming portion 5 of the semiconductor element are wetted and bonded simultaneously to the semiconductor element side and the printed wiring board side. The B-staged thermosetting component melted in parallel reinforces the entire solder electrode after immersing and curing around the solder electrode, the semiconductor element, and the printed wiring board. In FIG. 4, the semiconductor element and the printed wiring board are joined via the solder electrode, and the thermosetting component 10 is reinforced around the solder electrode and around the electrode forming part of the semiconductor element and the electrode forming part of the printed wiring board. Indicates the state that has been performed. By making the B-stage state in advance, there is no displacement or crushing when the semiconductor element is placed on the printed wiring board, and solder electrodes can be formed and bonded together.
[0017]
If the curing is insufficient under the soldering conditions, post-baking can be performed. Further, in the present invention, a solder paste is applied to each of the semiconductor element side and the substrate side in advance, and after making a B-stage, the solder electrode can be formed, bonded, and reinforced with a cured thermosetting component. .
In the present invention, the solder paste applied to the wafer and B-staged by heat treatment is separated into pieces and joined. Further, the semiconductor element mounting substrate having the B-staged solder paste is separated into pieces as necessary and bonded. The semiconductor element mounting substrate used in the present invention refers to various insulating substrates such as plastic and ceramic.
[0018]
Example 1
As a curing agent having 100 parts by weight of a varnish obtained by dissolving 70 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent 200) in 30 parts by weight of butyl cellosolve acetate (the solubility of the following curing agent in butyl cellosolve acetate is 1% or less). 18 parts by weight of 2,5-dihydroxybenzoic acid, 0.2 parts by weight of 2-phenyl-4-ethylimidazole as a curing accelerator, and a tin / lead eutectic solder powder having a melting point of 183 ° C. (average particle size 30 μm) as a solder powder 90 parts by weight was weighed and kneaded and dispersed with three rolls, followed by vacuum defoaming to prepare a solder paste. The produced solder paste is printed using a metal mask by a printing method to form a 350 μm-thick wafer (with a daisy chain circuit in which the electrical connectivity of each semiconductor element can be examined after being separated into individual pieces, The number of connecting metal pads was 400, the pad array was a full array, and the pad opening was 100 μm. Thereafter, B-staging was performed at 80 ° C. for 90 minutes, and protrusions having a final thickness of 100 μm and a diameter of a portion in contact with the wafer of about 120 μm were formed on all electrode formation sites (pads). Next, the wafer was separated into individual semiconductor elements using a dicing saw (semiconductor element size 6 × 6 mm). Further, using a flip chip bonder, a semiconductor element is placed on a 10 mm square glass-epoxy substrate (a gold-plated pad with an opening diameter of 100 μm is formed on the corresponding part), and the maximum temperature is 220 ° C. and the minimum temperature is 183 ° C. And passed through an IR reflow furnace for 60 seconds (passing time including temperature rise: 180 seconds). The solder powder in the solder paste was integrated and bonded to each bonding pad of the semiconductor element and the glass-epoxy substrate. Furthermore, it was confirmed that the periphery of the solder (including the semiconductor element and the glass-epoxy substrate) was covered with a thermosetting component. Furthermore, it was cured by post-baking at 150 ° C. for 1 hour. In addition, after being B-staged, the samples stored at room temperature for 1 month and 2 months were bonded in the same manner, and it was confirmed that solder bonding was performed as in the initial stage. Connection was investigated by daisy chain. A thermal shock test was performed as the reliability of the obtained package, and the connection reliability of all the bumps was examined. The test conditions were −40 ° C. to 125 ° C., the measurement was performed every 100 cycles, the number of tests was N = 10, and the number of cycles where defects started to occur (hereinafter referred to as T / C reliability) was counted.
[0019]
Example 2
Curing illustrated bisphenol A type epoxy resin (epoxy equivalent 200) 70 parts by weight of butyl Le cellosolve acetate (for butyl cellosolve acetate, solubility is less than 1% below the curing agent) 100 parts by weight of varnish dissolved in 30 parts by weight, the fluxing action 20 parts by weight of phenolphthalin as an agent, 0.5 parts by weight of 2-phenyl-4-ethylimidazole as a curing accelerator, and 80 parts by weight of tin / silver / copper solder powder (average particle size 20 μm) having a melting point of 220 ° C. Then, after kneading and dispersing with three rolls, vacuum defoaming treatment is performed to produce a solder paste, and the reflow conditions are a maximum temperature of 250 ° C. and a minimum temperature of 220 ° C. for 60 seconds (passing time including temperature increase of 180 seconds). A package was assembled and evaluated in the same manner as in Example 1 except that.
[0020]
Comparative Example 1
80 parts by weight of varnish obtained by dissolving 70 parts by weight of a bisphenol A type epoxy resin (epoxy equivalent 200) in 10 parts by weight of butyl cellosolve acetate, 18 parts by weight of 2,5-dihydroxybenzoic acid as a curing agent having a flux action, and as a curing accelerator A paste was prepared in the same manner as in Example 1 using 0.2 parts by weight of 2-phenyl-4-ethylimidazole. Next, a solder electrode having a diameter of 100 μm is formed on a wafer having the same specifications as in Example 1 using a solder paste containing eutectic solder powder and active rosin having the same composition as in Example 1, and then flux cleaning (hereinafter referred to as flux). After washing 1), the prepared paste is applied to a solder electrode of a semiconductor element (after singulation: 6 × 6 mm) that is diced into individual pieces, and using a flip chip bonder, It mounted on the same glass-epoxy board | substrate, and it joined using the same reflow as Example 1. FIG. As shown in FIG. 5, it was confirmed that the cured thermosetting component 10 covered the solder electrode near the glass-epoxy substrate, that is, around the electrode forming portion of the substrate. Subsequent evaluation was performed in the same manner as in Example 1.
[0021]
Comparative Example 2
The paste prepared in Comparative Example 1 was applied to a eutectic solder ball having the same composition as in Example 1 and a diameter of 100 μm previously prepared on a wafer having the specifications of Example 1, and placed using a ball mounter. The solder balls were melted under the reflow conditions of Example 1 to form solder electrodes, and then diced to obtain individual semiconductor elements (after separation: 6 × 6 mm). A paste containing active rosin was applied to the solder electrode of the semiconductor element having the solder electrode, placed on the same glass-epoxy substrate as in Example 1, and bonded using the same reflow as in Example 1. Thereafter, flux cleaning was performed (hereinafter referred to as flux cleaning 2). As shown in FIG. 6, it was confirmed that the cured thermosetting component 10 covers the side near the semiconductor element of the solder electrode and the periphery of the electrode forming portion of the semiconductor element. Subsequent evaluation was performed in the same manner as in Example 1.
[0022]
Comparative Example 3
The paste prepared in Comparative Example 1 was applied to a eutectic solder ball having the same composition as in Example 1 and a diameter of 100 μm previously prepared on a wafer having the specifications of Example 1, and placed using a ball mounter. The solder balls were melted under the reflow conditions of Example 1 to form solder electrodes, and then diced to obtain individual semiconductor elements (after separation: 6 × 6 mm). The paste prepared in Comparative Example 1 was applied to the solder electrode of a semiconductor element having a solder electrode, placed on the same glass-epoxy substrate as in Example 1, and joined using the same reflow as in Example 1. It was confirmed that the bonding state, the solder electrode and the electrode forming portion of the semiconductor element, and the electrode forming portion of the glass-epoxy substrate were in a good covering state.
[0023]
Comparative Example 4
Using a solder paste containing eutectic solder powder and active rosin having the same composition as in Example 1 on a wafer having the same specifications as in Example 1, a solder electrode having a diameter of 100 μm was formed, and the conditions here were fluxes. After cleaning (hereinafter referred to as flux cleaning 1), the same solder paste as above is applied to the solder electrode of a semiconductor element (after separation: 6 × 6 mm) that has been diced into individual pieces, and a flip chip bonder is used. It was mounted on the same glass-epoxy substrate as in Example 1 and used in the same reflow as in Example 1. This was followed by flux cleaning (hereinafter referred to as flux cleaning 2). Next, liquid injection sealing underfill agent [(CRP-4152 (manufactured by Sumitomo Bakelite Co., Ltd.))) was filled and cured at 150 ° C. for 120 minutes. As shown in FIG. 7, the cured underfill material 11 is filled and the solder electrodes are reinforced. The same reliability test as in Example 1 was performed.
[0024]
[Table 1]
Figure 0004254216
[0025]
Examples 1 and 2 are excellent in T / C reliability because they can be joined together and the periphery of the solder electrode is completely reinforced. In Comparative Example 1 and Comparative Example 2, since the solder electrode is only partially reinforced, the T / C reliability is poor. Comparative Example 3 and Comparative Example 4 are excellent in T / C reliability. In any case, Comparative Example 1 to Comparative Example 4 cannot be collectively joined, so that the relative man-hours of productivity are inferior to those of the present invention.
[0026]
【The invention's effect】
According to the assembling method of the present invention, the solder paste to be used has a B-stage property, so that when the semiconductor element is placed on the semiconductor mounting substrate, the solder paste is not misaligned and crushed. Electrode formation can be performed at the same time, and at the same time, around the solder electrode, the electrode formation part of the semiconductor element and the electrode formation part of the semiconductor mounting substrate can be reinforced with a cured thermosetting component, and the conventional liquid injection sealing Compared to the assembly method of filling with an underfill material, the manufacturing process can be greatly shortened. Since it has B-stage characteristics, inventory in the B-stage state is possible and planned production can be performed.
[Brief description of the drawings]
FIG. 1 is a conceptual cross-sectional view showing a state in which a solder paste is applied to an electrode forming portion of a wafer on which a circuit is formed.
FIG. 2 is a cross-sectional view showing a state where a wafer is diced into semiconductor elements.
FIG. 3 is a conceptual cross-sectional view showing a state in which a semiconductor element having a B-staged solder paste is placed on an electrode formation portion of a printed wiring board.
FIG. 4 shows a semiconductor element and a printed wiring board joined together via a solder electrode and reinforced with a thermosetting component around the solder electrode and around the electrode forming part of the semiconductor element and the electrode forming part of the printed wiring board. It is sectional drawing which shows the state.
FIG. 5 is a cross-sectional view showing a state in which a cured thermosetting component covers the vicinity of the glass-epoxy substrate side of the solder electrode and the periphery of the electrode forming portion of the substrate in Comparative Example 1;
FIG. 6 is a cross-sectional view showing a state in which a cured thermosetting component covers the side near the semiconductor element of the solder electrode and the periphery of the electrode forming portion of the semiconductor element in Comparative Example 2;
7 is a cross-sectional view showing that a hardened underfill material is filled and solder electrodes are reinforced in Comparative Example 4. FIG.

Claims (3)

（Ａ）エポキシ樹脂と、常温で結晶の１分子当たり少なくとも２個以上のフェノール性水酸基と１分子当たり少なくとも１個以上の芳香族カルボン酸を有するフラックス機能を有する硬化剤を含む熱硬化性成分、（Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、且つ水酸基を有さない溶剤及び（Ｃ）半田粉を必須成分として配合し、必要により硬化促進剤、着色剤、レベリング剤、カップリング剤、チクソ剤、消泡剤を配合し且つＢ−ステージ性を有する半田ペーストを半導体素子搭載用基板もしくはウエハー又は個片化した半導体素子に塗布し、加熱処理により半田ペーストをＢ−ステージ化後、接合する部位を有する部材に載置し、全体加熱法又は部分加熱法を用いて半田粉の融点以上に加熱し、半田電極形成及び半導体素子／半導体搭載用基板間の電気的接合を行い、且つ熱硬化性成分が前記半田電極の周囲を補強することを特徴とする半導体装置の組立方法。  (A) a thermosetting component comprising an epoxy resin and a curing agent having a flux function having at least two phenolic hydroxyl groups per molecule of crystals and at least one aromatic carboxylic acid per molecule at room temperature; (B) The epoxy resin is dissolved, the curing agent is not dissolved, and a solvent having no hydroxyl group and (C) solder powder are blended as essential components, and if necessary, a curing accelerator, a colorant, a leveling agent, a cup A solder paste containing a ring agent, a thixotropic agent, and an antifoaming agent and having a B-stage property is applied to a semiconductor element mounting substrate, a wafer, or an individual semiconductor element, and the solder paste is made into a B-stage by heat treatment. After that, it is placed on a member having a part to be joined, and heated to a temperature higher than the melting point of the solder powder by using a whole heating method or a partial heating method to form a solder electrode and a semiconductor element. An electrically bonding between the semiconductor mounting substrate, and method of assembling a semiconductor device, characterized in that the thermosetting component to reinforce the periphery of the solder electrodes. （Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、且つ水酸基を有さない溶剤が、ブチルセロソルブアセテートである請求項１記載の半導体装置の組立方法。(B) The method of assembling a semiconductor device according to claim 1, wherein the solvent that does not dissolve the epoxy resin and does not dissolve the curing agent and does not have a hydroxyl group is butyl cellosolve acetate. 請求項１又は２記載の半導体装置の組立方法に用いられる半田ペーストであって、（Ａ）エポキシ樹脂と、常温で結晶の１分子当たり少なくとも２個以上のフェノール性水酸基と１分子当たり少なくとも１個以上の芳香族カルボン酸を有するフラックス機能を有する硬化剤を含む熱硬化性成分、（Ｂ）前記エポキシ樹脂を溶解させ前記硬化剤を溶解せず、且つ水酸基を有さない溶剤及び（Ｃ）半田粉を必須成分として配合し、必要により硬化促進剤、着色剤、レベリング剤、カップリング剤、チクソ剤、消泡剤を配合し且つＢ−ステージ性を有することを特徴とする半田ペースト。3. A solder paste used in the method for assembling a semiconductor device according to claim 1 , wherein (A) an epoxy resin, at least two phenolic hydroxyl groups per molecule of crystal at room temperature and at least one molecule per molecule. A thermosetting component containing a curing agent having the above-mentioned aromatic carboxylic acid and having a flux function, (B) a solvent which dissolves the epoxy resin and does not dissolve the curing agent and does not have a hydroxyl group, and (C) a solder A solder paste comprising a powder as an essential component, a curing accelerator, a colorant, a leveling agent, a coupling agent, a thixotropic agent and an antifoaming agent as necessary, and having a B-stage property .
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