JP4253860B2 - Exposure method and exposure apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an exposure method and an exposure apparatus, and more particularly to an exposure method and an exposure apparatus used in a photolithography process. The present invention can be used as an exposure technique in the case of using various photolithography processes, typically in the case of manufacturing semiconductor devices.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a photolithography process has been employed for various pattern processing and the like including a semiconductor device manufacturing process. Hereinafter, the prior art will be described by taking a case of manufacturing a semiconductor element as an example.
[0003]
In order to improve the performance of semiconductor elements and increase their manufacturing yield, it is important to keep the pattern dimensions when forming patterns on exposed materials such as semiconductor substrates or glass substrates within the allowable range in the device manufacturing process. It is. At the same time, it is also necessary to reduce defects that occur during pattern formation on an exposed material such as a semiconductor substrate or a glass substrate during the manufacturing process of the semiconductor element.
[0004]
In a photolithography process for processing or manufacturing a semiconductor element, a photoresist is generally used. The photoresist used in such a photolithography process has a pattern formation accuracy (for example, a pattern processing dimension) at the stage of selection. Exposure, focus dependence, resolution, post-exposure bake (post-exposure baking temperature dependence, post-exposure standing time dependence), etc., and thoroughly examine and evaluate the exposure of semiconductor substrates, glass substrates, etc. It is usual to select an optimum photoresist material for semiconductor manufacture by evaluating the photoresist coatability on the film to be processed on the material and evaluating the number of defects after exposure and development.
[0005]
In an actual semiconductor mass production process, in order to determine whether a semiconductor wafer, a glass substrate, or the like is processed under appropriate conditions using the photoresist material selected as described above, a wafer for condition determination is used in advance. As shown in FIG. 3, the exposure amount and focus of the exposure apparatus are adjusted as shown in FIG. 3 using a glass substrate or the like, and the exposure amount / focus conditions within which the pattern size to be managed falls within the standard are determined. In FIG. 3, reference numeral 1 denotes a silicon wafer used for determining the conditions, and 2 denotes one chip pattern to be exposed. In the drawing, with respect to the exposure amount and focus given to each chip in the chip array, the exposure amount is shaken at a pitch of ² mJ / cm ² with reference to 40 mJ / cm ^{2 in} the horizontal direction of the figure, and the focus is set in the vertical direction of the figure. Waves are given with a pitch of 0.2 μm with respect to 0 μm. For the exposure amount and focus determined here, a condition that can take a value as close to the design value as possible within the line width tolerance standard is selected and used as a production condition.
[0006]
However, in spite of setting the exposure amount and focus so as to optimally finish the line width in this way, the wafer or glass substrate for actual manufacturing processing can give the line width optimally, but exposure In some cases, defects occur on the developed pattern, and the wafers and glass substrates manufactured and processed are at an unacceptable level in terms of the number of defects generated. For example, in a 0.25 μm device manufacturing process, in one lithography process (typically, resist coating, baking, pattern exposure, post-exposure baking, development, post-baking, one process), 0.25 μm plus or minus 0.25 μm Despite the fact that a good processing line width of 0.2503 μm was obtained with respect to the processing line width standard, the entire area of the 8-inch wafer on which the pattern was formed was inspected for defects. 8380 shape defects or residue defects were generated on an 8-inch silicon wafer.
[0007]
This has significantly reduced the manufacturing yield and has been found to be unacceptable in the device mass production process. As a result of investigating the cause of this defect, the surface condition (hydrophobic and hydrophilic polarity) of the base film before applying the photoresist on the substrate wafer was compared with that when the exposure amount and focus were optimized. Even though the line width is within the allowable range and is very close to the design value, the exposure is increased (overexposure condition) and the focus is set to the plus side. It was found that defects would occur if the line width was not finished fine.
[0008]
[Problems to be solved by the invention]
As described above, the method of selecting a condition where the line width standard is within the allowable range and is as close to the design value as possible, which has been adopted as the conventional method for setting the optimum exposure dose and focus, on the other hand, causes pattern defects. It had the risk of bringing about. The present invention solves this problem of the prior art, and provides an exposure method and an exposure apparatus capable of setting an exposure amount and a focus so that the line width standard is within an allowable range and the number of defects can be reduced. The issue is to provide.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention sets the optimum exposure amount and focus in consideration of the defect generation yield as well as the exposure amount and focus dependency of the transfer line width in photolithography and process. Is.
[0010]
According to the present invention, as the exposure amount and focus setting method, the optimum exposure and the optimum focus are set in consideration of the exposure amount dependency, the focus dependency, and the defect generation yield. In addition to being within, the number of defects is reduced and a high yield can be realized.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in more detail, and specific examples of preferred embodiments of the present invention will be described with reference to the drawings. However, as a matter of course, the present invention is not limited to the illustrated embodiment.
[0012]
The present invention can take the following aspects. In the case of semiconductor manufacturing, using the resist material that you want to use in the semiconductor mass production process, whether the film to be processed on the exposed material (wafer, glass substrate, etc.) used in actual mass production can be processed under appropriate conditions. In order to judge, using the exposure target material (wafer, glass substrate, etc.) prepared in advance under the same conditions as those for mass production, the above resist is appropriately applied thereon, baked, and the exposure amount of the exposure apparatus The exposure is performed under the above conditions and the focus conditions, and then development is performed. Thereafter, the dimension of the pattern to be managed is measured by, for example, a length measuring SEM, and the exposure amount and the focus condition range falling within the allowable standard are obtained. Although the order is not limited, for example, following this, the exposed material (wafer, glass substrate, etc.) is subjected to pattern defect inspection, for example, the exposure amount in which the total number of pattern defects and residual defects falls within the allowable number, And the focus condition range is obtained. Here, with respect to the line width and the defect, the exposure amount to be applied at the time of exposure of a mass production wafer or the like and the focus condition are set within the exposure range and the focus range both within the allowable range.
[0013]
Embodiment 1
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In this embodiment, when setting the optimal exposure and the optimal focus, the defect generated in the exposed material created by the photolithography process is inspected by changing the exposure amount and the focus condition, and the number of generated defects is allowed. An example in which the exposure and focus condition ranges below the level are found, and the optimum condition is determined from the event product of the range and the exposure and focus condition ranges where the measured line width standard falls within the allowable range It is. In particular, an array A in which an exposure amount and a focus condition are set and an array B in which an exposure amount and a focus condition are not set are arranged on one object to be exposed (here, a semiconductor wafer). Pattern defect inspection is performed, and optimal exposure and optimal focus are set. Please refer to FIG. 1 and FIG.
[0014]
An 8-inch silicon wafer is prepared as a material to be exposed, and a Si ₃ N ₄ film is deposited on the wafer by a CVD method to a thickness of 200 nm, followed by pure water jet cleaning and spin drying, and further HMDS (hexamethyldisilazane). It is exposed to steam for 40 seconds, immediately followed by dehydration baking at 180 ° C. for 30 seconds, and a chemically amplified resist (trade name KRF-K2G) manufactured by Nippon Synthetic Rubber Co., Ltd. is added here to a thickness of 0.765 μm. Then, a surface antireflection film (trade name: TSP5A, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied at a thickness of 43 nm, and prebaked at 100 ° C. for 90 seconds. This is the exposure target material 1 for determining the conditions.
[0015]
An exposure arrangement file was created for the purpose of arranging and exposing a 10 mm square chip (one chip is denoted by reference numeral 2) on the entire surface of one sample. Here, the array group A is exposed at an exposure amount of 40 mJ / cm ² with a central condition of plus or minus ² mJ / cm ² pitch, and the focus condition of 0 μm with a center condition of plus or minus 0.2 μm pitch. An exposure file was created by alternately arranging array B with the exposure amount and focus fixed at 40 mJ / cm ² and 0 μm, respectively, for each column. This arrangement is shown in FIG.
[0016]
In FIG. 1, reference numeral 1 denotes a silicon wafer, which is an exposure material for determining the conditions in this example, and 2 denotes a chip pattern to be exposed. The target chip group in array A is indicated by reference numeral 3, and the target chip group in array B is indicated by reference numeral 4. In accordance with this, a mask pattern of a LOCOS layer in which 16 million 0.25 μm rule DRAM (Dynamic Random Access Memory) elements are arranged using an excimer stepper (Nikon Corporation, NSR-2205 EX10B11, KrF excimer laser light). Then, the wafer was exposed.
[0017]
Immediately after exposure, the wafer was post-exposure baked at 110 ° C. and 90 ° C., and then subjected to paddle development for 60 seconds with a TMAH (tetramethylammonium anhydride) 2.38% developer, followed by rinsing with pure water. Then, spin-drying was performed.
[0018]
With respect to the pattern of the array A on the wafer, using a length measuring SEM (manufactured by Hitachi, Ltd .; S8840), the design value of the DRAM LOCOS pattern 0.26 μm is measured for the remaining size of the laser, and the exposure amount / focus setting value is measured. Then, the finished line width was obtained. Based on this, an exposure amount / focus condition group ED (A) that falls within the variation tolerance standard ± 0.025 μm of the 0.25 μm design value was found.
[0019]
Subsequent to the above, in order to obtain the number of pattern defects and the number of resist residue defects at each exposure amount / focus setting value of the array A by comparison inspection with the exposure chip of the array B, the wafer is obtained as a defect inspection machine KAL2132 manufactured by KAL. In random mode (0.62 μm pixel, threshold 50). The defect inspection machine KAL2132 manufactured by KAL is a pattern defect inspection apparatus based on a so-called reflected light type die-to-die comparison.
[0020]
In the comparative inspection, the array group A with the exposure amount / focusing was inspected in comparison with the array group B on both sides thereof, and a case where there was a difference was defined as a defect. The number of occurrences of defects was examined for each exposure amount / focus setting value, and an exposure amount / focus condition range in which the defect level was below an allowable value level was found.
[0021]
In this embodiment, the allowable number of defects on the LOCOS pattern per chip is set to 30 from the viewpoint of yield, and an exposure amount / focus setting condition group ED (B) that satisfies this is found. .
[0022]
FIG. 2 shows ranges ED (A) and ED (B) that satisfy the allowable specifications from the line width measurement result and the number of defects. From FIG. 2, the best exposure amount and the best focus obtained from only the line width standard are 40 mJ / cm ² and 0 μm, respectively, but the number of defects in this case is 58 and does not satisfy the defect number standard. I understand that. It can be seen that the conditions for viewing the line width condition and satisfying the standard for the number of defects are in the vicinity of an exposure amount of 44 mJ / cm ² and +0.4 μm focus.
[0023]
As a result of exposing a mass-produced main body wafer at an exposure amount of 44 mJ / cm ² and a focus of +0.4 μm obtained as described above, 25 mm 10 mm square 16MDRAM patterns were exposed to 25 8-inch wafers, resulting in non-standard line width. In addition, there were none of the 7000 chips out of the defect number standard (280 chips in one wafer, 7000 chips in 25 wafers).
[0024]
On the other hand, when the exposure is 40 mJ / cm ² , which is the optimum condition obtained by the conventional method, and 25 pieces of 8-inch wafers are similarly exposed at a focus of 0 μm, all the line width standards are satisfied in 7000 chips. However, only 537 chips met the defect number standard (30 or less). From this, it is clear that in the conventional setting method, the manufacturing yield of the semiconductor device is remarkably reduced.
[0025]
As described above, according to the present embodiment, it is optimal from the exposure product / focus condition range where the measured line width standard falls within the allowable range, and the event product within the range where the number of inspected defects falls within the allowable range. By applying the method of the present invention that makes it possible to determine the conditions, the line width on the wafer to be manufactured is kept within an allowable range, and defects such as development residual defects at the time of development after exposure are reduced, It has become possible to perform exposure with high yield.
[0026]
In this embodiment, an example is shown in which conditions are determined using a single wafer for condition determination. However, a method for dividing the wafer for condition determination into a plurality of wafers or assigning conditions for each wafer is described. Thus, it is of course possible to obtain the range in which the line width and the number of defects fall within the standard, and to set the optimum condition with the event product, and such an aspect is also included in the present invention.
[0027]
【The invention's effect】
As described above, according to the exposure method and the exposure apparatus of the present invention, the exposure amount and focus can be set so that the line width standard falls within the allowable range and the number of defects can be reduced. The product can be obtained at a high yield.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a first embodiment of the present invention and shows details of condition setting;
FIG. 3 is a diagram showing a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Material to be exposed (conditional wafer), 2 ... Chip (1 piece), 3 ... Target chip group in array A, 4 ... Target chip group in array B, ED (A)・ ・ A range that satisfies the allowable specification of the line width, ED (B)... A range that satisfies the allowable specification of the number of defects.

Claims (4)

Oite to the exposure method in the photolithography process,
A step of forming an exposure file by arranging an array A in which exposure conditions and focus conditions are set on one exposure material and an array B in which exposure conditions and focus conditions are not set, and performing exposure development.
Measuring the line width of the array A, performing a line width measurement inspection,
Comparing the chips of the array A with the chips of the array B, and determining the number of defects generated in the chips of the array A, thereby performing a pattern defect inspection;
Of the conditions of the chips of the array A, the step of setting the optimum exposure amount found from the line width measurement inspection and the pattern defect inspection, and the optimum focus condition,
An exposure method comprising: The arrangement of the array A and the array B is alternated, and the pattern defect inspection is performed by comparing the chip of the array A with the chip of the array B on both sides of the chip of the array A.
The exposure method according to claim 1. The exposure amount and focus of the array B are the best exposure amount and the best focus obtained from only the line width standard.
The exposure method according to claim 1. An exposure apparatus used in a photolithography process,
Optimum exposure and optimum focus setting means considering the exposure amount dependency, focus dependency, and defect generation yield of the transfer line width,
In the optimum exposure and optimum focus setting means, an array A in which an exposure amount and a focus condition are set and an array B in which an exposure amount and a focus condition are not set are arranged on one exposure material, The line width measurement inspection for measuring the line width of the array A, the chip of the array A, and the chip of the array B on both sides of the chip of the array A are compared, and the defect in the chip of the array A An exposure apparatus characterized in that a pattern defect inspection for determining the number of occurrences is performed, and the optimum exposure and the optimum focus are obtained from the line width measurement inspection and the pattern defect inspection .

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