JP4246544B2 - Disk device and disk device logging method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used, for example, in a magnetic disk device (or hard disk device) or other disk device, and in particular, logging data when a failure occurs during operation is independent of the operation of the CPU. The present invention relates to a disk device that can be taken out arbitrarily along a path and a logging method for the disk device.
[0002]
[Prior art]
A conventional example will be described below.
[0003]
(1): Description of Conventional Example 1
FIG. 4 is an explanatory diagram of the first conventional example. Hereinafter, Conventional Example 1 will be described with reference to FIG. As shown in FIG. 4, the magnetic disk device includes a hard disk control LSI (LSI: large-scale integrated circuit) in the control system of the magnetic disk device (hereinafter referred to as “hard disk device”) (hereinafter, referred to as “hard disk device”). The hard disk control LSI is referred to as “HDC LSI”).
[0004]
The HDC LSI 1 includes a CPU 2 that is a CPU for performing various hard disk controls, a hard disk controller (hereinafter referred to as “HDC”) 3 that controls a hard disk device based on the control of the CPU 2, and an RS232C cable. An RS232C interface (hereinafter referred to as “UART”) 4 for connection and a read channel interface (hereinafter referred to as “RDC / IF”) 5 for connecting a read channel are provided.
[0005]
In order to extract logging data when a failure occurs in the hard disk device, the connector 8 is attached to the HDC LSI 1 and the ICE 16 is connected, the connector 7 is attached and the logic analyzer 13 is connected, the personal computer interface 9 To connect a terminal (for example, a personal computer).
[0006]
Further, a terminal (for example, a personal computer) 14 is connected to the UART 4, a read channel (hereinafter referred to as “RDC”) 11 is connected to the RDC / IF 5, and a servo controller (hereinafter “ SVC) 12).
[0007]
In FIG. 4, conventionally, when CPU 2 hangs up or runs away, in order to analyze the data of CPU 2, data analysis at the time of failure is performed by connecting ICE 16 and logic analyzer 13. However, the HDC 3 is made into one channel in the CPU 2, and the state of the internal bus cannot be directly confirmed by the logic analyzer 13. The debug tool has been developed as a solution when a failure occurs by executing a program on the CPU 2. However, if the CPU 2 runs out of control, it cannot be a data analysis unit.
[0008]
(2): Description of Conventional Example 2 (see Patent Document 1)
Hereinafter, Patent Document 1 will be described as Conventional Example 2.
[0009]
Conventional Example 2 relates to a control device and an optical disc player, and is intended to enable easy and quick investigation of the cause of an abnormal operation when an abnormal operation of a product occurs.
[0010]
Then, in the control device that controls the functional means for performing various processes based on the required program, the operation history based on the program up to the operation error in the process based on the program is written in the nonvolatile storage means .
[0011]
However, Conventional Example 2 cannot be realized unless the CPU can operate normally. Therefore, when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data when a failure occurs cannot be extracted.
[0012]
(3): Description of Conventional Example 3 (see Patent Document 2)
Hereinafter, Patent Document 2 will be described as Conventional Example 3.
[0013]
Conventional Example 3 relates to an error data holding method of a magnetic disk device, and is provided with error data holding means for holding in detail the error content detected by the error detection means, and when an error occurs in the magnetic disk device, The error content is directly written in the error data holding means as it is, and the error occurrence location is detected by reading the error content written in the error data holding means later.
[0014]
Further, it is described that the latch means and the display means are provided, and the output of the error detection means is held in the latch means so that the display means is controlled based on the latch means. 1 and 2 are diagrams showing the contents of the invention. In this case, as shown in the figure, there is an error data holding circuit separately from the CPU.
[0015]
However, Conventional Example 3 cannot be realized unless the CPU can operate normally. Therefore, when the CPU 2 is in the hang-up state or the program is in a runaway state, the logging data when the failure occurs cannot be taken out.
[0016]
(4): Description of Conventional Example 4 (see Patent Document 3)
Hereinafter, Patent Document 3 will be described as Conventional Example 4.
[0017]
Conventional Example 4 relates to a VTR with an abnormality display function. It is necessary to identify the abnormal part for repairing the VTR, but it is necessary to identify the history of abnormality, whether the abnormality occurred was a transient state of the VTR state change, and whether the tape running mechanism was a transient state. Because it was unknown, it was difficult to identify the repair location.
[0018]
In order to solve this problem, when an abnormality occurs in the VTR, a plurality of abnormality contents are stored and displayed in time series, and when the abnormality occurs at the transient state of VTR operation mode switching, the fact is stored. It has a means to display.
[0019]
However, Conventional Example 4 cannot be realized unless the CPU operates normally. Therefore, when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data cannot be extracted when a failure occurs.
[0020]
[Patent Document 1]
JP-A-8-297510
[Patent Document 2]
Japanese Patent Laid-Open No. 58-1258
[Patent Document 3]
JP 2000-36142 A
[0021]
[Problems to be solved by the invention]
The conventional apparatus as described above has the following problems.
[0022]
(1): In the conventional example 1, when the CPU 2 hangs up or the program runs away, the logic analyzer 13 or the ICE 16 is connected each time, and the failure analysis is performed again by logging the data before the failure occurs. For this reason, logging data cannot be extracted unless the CPU 2 is operating normally.
[0023]
(2): In the conventional example 1, when the CPU 2 hangs up, the ICE power supply must be turned on / off. Therefore, the state of the CPU 2 at the time of failure is erased.
[0024]
(3): In the above conventional example 1, a debugging tool or the like has been developed, but it is created on the assumption that the CPU 2 operates normally. When a problem occurs, the CPU 2 is already in a hang-up state or the program is It was in a runaway state, leading to the result that the suspected part could not be identified. Therefore, logging data at the time of failure could not be retrieved.
[0025]
(4): Conventional example 2 (see Patent Document 1) includes a control device that controls functional means for performing various processes based on a required program, until an operation error occurs in the process based on the program. It is described that an operation history based on the program is written in a nonvolatile storage means. However, Conventional Example 2 cannot be realized unless the CPU operates normally. Therefore, when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data cannot be extracted when a failure occurs.
[0026]
(5): Conventional Example 3 (see Patent Document 2) relates to an error data holding method of a magnetic disk device, and includes error data holding means for holding the details of errors detected by the error detecting means as they are. When an error occurs in the magnetic disk device, the error content is written in detail in the error data holding means, and the error occurrence location is detected by reading the error content written in the error data holding means later. It is described that it is characterized by that.
[0027]
However, Conventional Example 3 cannot be realized unless the CPU can operate normally. Therefore, when the CPU 2 is in the hang-up state or the program is in a runaway state, the logging data when the failure occurs cannot be taken out.
[0028]
(6): Conventional Example 4 (see Patent Document 3) stores and displays a plurality of abnormality contents in time series when an abnormality occurs in the VTR. However, in Conventional Example 4, a CPU is interposed as shown in FIG. For this reason, Conventional Example 4 cannot be realized unless the CPU operates normally. Therefore, when the CPU 2 is in a hang-up state or the program is in a runaway state, logging data cannot be extracted when a failure occurs.
[0029]
The present invention solves such a conventional problem, and without using an ICE or a logic analyzer used in the conventional example, it is possible to arbitrarily fail without using the CPU and regardless of the state of the CPU. The purpose is to be able to retrieve logging data at the time of occurrence.
[0030]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0031]
(1): In a disk device including a disk control integrated circuit device having a CPU that performs various controls when data is written / read to / from the disk, the disk control integrated circuit device is connected to the CPU. Of the logging data at the time of failure occurrence, only the logging data that matches the preset condition is acquired, and the acquired logging data is independent of the CPU without using the CPU and regardless of the execution of the program by the CPU. A logging circuit having a hardware configuration having a function of outputting to the outside through the route, the logging circuit performing a logging control for acquiring only logging data that matches a preset condition; and A buffer for temporarily storing the logging data of the CPU acquired by the control of the logging control circuit is provided, and a function of outputting the logging data stored in the buffer to the outside is provided. Internal to set various logging conditions including conditions and other conditions And a trigger detection circuit that detects only logging data that matches the locking condition with reference to the logging condition set in the internal control register among the logging data at the time of failure of the CPU, A buffer control circuit that controls when logging data detected by the trigger detection circuit is stored in the buffer according to an instruction from the trigger detection circuit, and a serial control circuit that controls output of the logging data It is characterized by having.
[0032]
(2): In the disk device of (1), the logging circuit includes: Connected to the CPU by an interrupt signal line, and through the interrupt signal line A function for detecting that the CPU is in a hang-up state by determining the content of the interrupt signal acquired from the CPU, and a system bus as information when the CPU hangs up Obtained through It has a feature that enables logging data to be output.
[0033]
(3): Disk device of (1) above Logging method In In a logging method for a disk device including a disk control integrated circuit device having a CPU for performing various controls when writing / reading data to / from the disk, the disk control integrated circuit device performs logging when a failure occurs in the CPU. Of the data, only the logging data that matches a preset condition is acquired, and the acquired logging data is not transmitted to the outside through the CPU and through an independent path regardless of the execution of the program by the CPU. A logging circuit having a hardware configuration having an output function, wherein the logging circuit performs a logging control for acquiring only logging data that matches a preset condition, and controls the logging control circuit CPU logging data temporarily acquired by And a function to output the logging data stored in the buffer to the outside. Various logging conditions including interrupt conditions, address conditions, and other conditions are set in the internal control register in the logging control circuit. The trigger detection circuit in the logging control circuit detects only the logging data that matches the logging condition by referring to the logging condition set in the internal control register among the logging data when the CPU fails In the buffer control circuit in the logging control circuit, in response to an instruction from the trigger detection circuit, control is performed when storing the logging data detected by the trigger detection circuit in the buffer, and the serial number in the logging control circuit In the control circuit, the output control of the logging data is performed. And Features .
[0036]
(Function)
The operation of the present invention based on the above configuration will be described with reference to FIG.
[0037]
(a) :disk In the control integrated circuit device, the logging circuit 20 captures and outputs the internal information and state of the CPU 2 through the independent path regardless of the execution of the program by the CPU 2 without going through the CPU 2. In this case, the logging circuit 20 acquires only the logging data that meets a preset condition from among the logging data when the failure of the CPU 2 occurs, and outputs it to the outside.
[0038]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU 2 without using the ICE or logic analyzer used in the conventional example.
[0039]
(b) : Logging The circuit 20 determines the content of the interrupt signal acquired from the CPU 2 to detect that the CPU 2 is in a hang-up state, or as information when the CPU 2 hangs up as a register in the system bus 24 or the CPU 2. Output logging data including information.
[0040]
In this way, logging data at the time of occurrence of a failure can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or logic analyzer used in the conventional example.
[0041]
(c) : Logging The circuit 20 performs logging control so that the logging control circuit 21 acquires only logging data that matches a preset condition. The buffer 22 temporarily stores the logging data of the CPU 2 acquired by the control of the logging control circuit 21 and outputs the logging data stored in the buffer 22 to the outside.
[0042]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU 2 without using the ICE or logic analyzer used in the conventional example.
[0043]
(d) : Logging Various logging conditions including an interrupt condition, an address condition, and other conditions are set in an internal control register provided in the control circuit 21. In addition, the trigger detection circuit provided in the logging control circuit 21 refers to the logging condition set in the internal control register among the logging data when the failure of the CPU 2 occurs, and only logs the logging data that matches the locking condition. To detect.
[0044]
The buffer control circuit provided in the logging control circuit 21 performs control when storing the logging data detected by the trigger detection circuit in the buffer 22 in accordance with an instruction from the trigger detection circuit. A serial control circuit provided in the logging control circuit 21 performs serial control of the logging data.
[0045]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU 2 without using the ICE or logic analyzer used in the conventional example.
[0046]
(e) :disk When a failure occurs in the CPU 2 by the logging control dedicated circuit (logging circuit 20) provided in the control integrated circuit device, the CPU 2 does not go through the CPU 2 and has an independent path regardless of the execution of the program by the CPU 2. Logging data including internal information and status of the CPU is acquired and output.
[0047]
In this way, logging data at the time of occurrence of a failure can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or logic analyzer used in the conventional example.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following example is an example in which the present invention is applied to a magnetic disk device (hereinafter referred to as “hard disk device”).
[0049]
§1: Description of LSI for HDC
(1): Explanation of the configuration of the LSI for HDC
FIG. 2 is an explanatory diagram of an HDC LSI. As shown in FIG. 2, the hard disk device (magnetic disk device) includes an HDC LSI (hard disk control LSI) 1 in the control system of the hard disk device.
[0050]
The HDC LSI 1 includes a CPU 2 for performing various hard disk controls (control for writing / reading data to / from the disk, etc.) and a logging circuit 20 for acquiring logging data of the CPU 2 (dedicated to logging control). Circuit) and a hard disk control circuit 3 for controlling the hard disk device (servo control system control) based on the control of the CPU 2 and a read channel (control for writing / reading data to / from the disk, etc.) RDC (read channel control circuit) 11 and the like.
[0051]
Further, the logging circuit 20 is provided with a logging control circuit 21 for performing control when acquiring logging data, a buffer 22 for storing logging data, and the like, and a UART (RS232C interface) 23. Reference numeral 24 denotes a system bus which is a path for data and addresses. The interrupt signal output from the CPU 2 when a failure occurs is taken into the logging control circuit 21.
[0052]
The HDC LSI 1 includes a terminal (personal computer) 28 connected to the UART 23, an external circuit (servo controller: SVC) 26 connected to the hard disk control circuit 3, and an external circuit (connected to the hard disk) connected to the RDC 11. Write / read circuit) 27 and the like.
[0053]
Note that the logging circuit 20 is configured by a hardware circuit, and does not pass through the CPU 2 (processor) and is independent of the execution of the program by the CPU 2 and has an internal path and state of the CPU 2. Is a circuit (a dedicated circuit for logging control) having a hardware configuration capable of outputting a signal.
[0054]
(2): Explanation of operation of LSI for HDC
The operation of the logging circuit 20 is as follows. As an operation when the terminal 28 (for example, a personal computer) is used, first, a start / stop request is made from the terminal 28 to the logging circuit 20 by an operation of a keyboard or a mouse of the terminal 28.
[0055]
In addition, logging conditions and the like are set in the logging circuit 20 from the terminal 28. Even when the logging conditions are changed, the logging operation is performed by performing the same operation as described above. Further, when necessary logging conditions are set in the logging circuit 20 in advance, the logging operation can be performed only by making a start / stop request from the terminal 28 to the logging circuit 20 by operating the terminal 28. Do.
[0056]
The logging circuit 20 outputs an interrupt signal from the CPU 2 when a failure occurs in the CPU 2. The logging circuit 20 captures the interrupt signal output from the CPU 2 and compares the content with the set logging condition. If they match, interrupt detection, address detection, and the like are performed, and the data is stored as logging data in a storage medium such as an internal buffer. Thereafter, the stored logging data is output to the terminal 28 or the like, whereby the logging data can be detected.
[0057]
§2: Detailed description of logging control circuit
(1): Explanation of configuration of logging control circuit
FIG. 3 is a detailed configuration diagram of the logging control circuit. The detailed configuration of the logging control circuit 21 is as shown in FIG. As illustrated, the logging control circuit 21 includes a trigger detection circuit 31, an internal control register 32, a buffer control circuit 33, and a serial control circuit 34. The trigger detection circuit 31 is connected to the CPU 2 and takes in an interrupt signal from the CPU 2 and an instruction / data.
[0058]
Further, the buffer control circuit 33 is connected to the trigger detection circuit 31 and controls the buffer 22 based on an instruction from the trigger detection circuit 31. The internal control register 32 is connected to the trigger detection circuit 31, the serial control circuit 34, and the CPU 2. The serial control circuit 34 is connected to the trigger detection circuit 31, the buffer control circuit 33, the internal control register 32, and the UART 23, and is configured to refer to data in the internal control register 32 and to control the UART 23.
[0059]
In the internal control register 32, interrupt conditions, address conditions, and other conditions can be set as logging conditions. In this case, the internal control register 32 is connected to the terminal 28 (see FIG. 2) via the UART 23, and the logging condition can be set or changed from the terminal 28.
[0060]
(2): Explanation of operation of logging control circuit
The operation of the logging control circuit is as follows. The internal control register 32 stores in advance an interrupt condition (interrupt condition when a failure occurs in the CPU 2), an address condition, and other conditions. In the trigger detection circuit 31, interrupt detection, address detection, and other conditions are set as logging conditions.
[0061]
In this way, the CPU 2 starts operating with the information set in the trigger detection circuit 31 and the internal control register 32. Then, it is assumed that a failure occurs during the operation of the CPU 2 and the CPU 2 issues an interruption signal indicating the occurrence of the failure. This interrupt signal is taken into the trigger detection circuit 31, and it is determined whether or not the logging condition set inside is satisfied.
[0062]
In this case, the trigger detection circuit 31 refers to the condition set in the internal control register 32 to determine whether or not the corresponding interrupt signal is satisfied. If it does not match, the trigger detection circuit 31 keeps it as it is, and if it matches, detects the interrupt signal. . Subsequently, the trigger detection circuit 31 detects the corresponding address and other conditions via the system bus 24 and issues an instruction to the buffer control circuit 33.
[0063]
Upon receiving the instruction, the buffer control circuit 33 fetches the address before hang-up output from the CPU 2 via the system bus 24 and stores it in the buffer 22. By such an operation, logging data from the CPU 2 is accumulated in the buffer 22. Thereafter, the serial control circuit 34 controls the UART 23 to take out the data in the buffer 22 and send (output) it to the terminal 28.
[0064]
(Other explanation)
{Circle over (1)} The above description is an example of a hard disk device (magnetic disk device), but the present invention is not limited to such an example, and other similar disk devices (for example, a magneto-optical disk device) are also used. Applicable.
[0065]
{Circle around (2)} The internal control register 32 can also set logging conditions inside in advance. In this case, the present invention can be implemented even if the logging condition cannot be changed from the terminal 28, and either can be implemented even if the logging condition can be changed from the terminal 28.
[0066]
【The invention's effect】
As described above, the present invention has the following effects.
[0067]
(1) :disk In the control integrated circuit device, the logging circuit captures and outputs the internal information and state of the CPU through an independent path without going through the CPU and irrespective of the execution of the program by the CPU. In this case, the logging circuit acquires only the logging data that satisfies a preset condition from among the logging data when the failure of the CPU occurs, and outputs it to the outside.
[0068]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU without using the ICE or logic analyzer used in the conventional example.
[0069]
(2) : Logging The circuit determines the content of the interrupt signal acquired from the CPU to detect that the CPU is in a hang-up state, or uses the system bus or register information in the CPU as information when the CPU hangs up. Output logging data including.
[0070]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU without using the ICE or logic analyzer used in the conventional example.
[0071]
(3) : Logging The circuit performs logging control so that the logging control circuit acquires only logging data that matches a preset condition. The buffer temporarily stores the logging data of the CPU acquired by the control of the logging control circuit, and outputs the logging data stored in the buffer to the outside.
[0072]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU without using the ICE or logic analyzer used in the conventional example.
[0073]
(Four) : Logging Various logging conditions including interrupt conditions, address conditions, and other conditions are set in an internal control register provided in the control circuit. The trigger detection circuit provided in the logging control circuit detects only the logging data that matches the locking condition by referring to the logging condition set in the internal control register among the logging data when the CPU failure occurs. To do.
[0074]
Further, a buffer control circuit provided in the logging control circuit performs control when storing logging data detected by the trigger detection circuit in the buffer according to an instruction from the trigger detection circuit. A serial control circuit provided in the logging control circuit performs serial control of the logging data.
[0075]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU without using the ICE or logic analyzer used in the conventional example.
[0076]
(Five) :disk When a failure occurs in the CPU by the logging control dedicated circuit (logging circuit) provided in the control integrated circuit device, the CPU does not go through the CPU, and the route is independent regardless of the execution of the program by the CPU. Logging data including internal information and status of the CPU is acquired and output.
[0077]
In this way, logging data at the time of failure can be arbitrarily taken out regardless of the state of the CPU without using the ICE or logic analyzer used in the conventional example.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is an explanatory diagram of an HDC LSI in an embodiment of the present invention.
FIG. 3 is a detailed configuration diagram of a logging control circuit according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram of a first conventional example.
[Explanation of symbols]
1 HDC LSI
2 CPU
3 HDC
4 UART
5 RDC / IF
7, 8 connectors
9 PC I / F
11 RDC (read channel)
12 SVC (servo control circuit)
13 Logic analyzer
14, 15 Terminal (PC
16 ICE
20 Logging circuit
21 Logging control circuit
22 buffers
23 UART (RS232C interface)
24 System bus
26, 27 External circuit
28 terminals
31 Trigger detection circuit
32 Internal control register
33 Buffer control circuit
34 Serial control circuit

Claims (3)

In a disk device including an integrated circuit device for disk control having a CPU for performing various controls when writing / reading data to / from the disk,
The integrated circuit device for disk control acquires only the logging data that matches a preset condition among the logging data at the time of the failure of the CPU , and without acquiring the acquired logging data via the CPU. In addition, a logging circuit having a hardware configuration having a function of outputting to the outside through an independent path regardless of the execution of the program by the CPU,
The logging circuit
A logging control circuit that performs logging control to obtain only logging data that matches a preset condition;
A buffer for temporarily storing the logging data of the CPU acquired by the control of the logging control circuit; and a function of outputting the logging data stored in the buffer to the outside,
The logging control circuit includes:
An internal control register that sets various logging conditions including interrupt conditions, address conditions, and other conditions;
A trigger detection circuit that detects only logging data that matches the locking condition with reference to the logging condition set in the internal control register among the logging data at the time of failure of the CPU;
A buffer control circuit for controlling when logging data detected by the trigger detection circuit is stored in the buffer according to an instruction from the trigger detection circuit;
A disk device comprising a serial control circuit for controlling the output of the logging data . The logging circuit is connected to the CPU by an interrupt signal line;
A function of detecting that the CPU is in a hang-up state by determining the content of the interrupt signal acquired from the CPU via the interrupt signal line ;
2. The disk device according to claim 1, further comprising a function of enabling output of logging data obtained via a system bus as information when the CPU is hung up. In a logging method for a disk device comprising a disk control integrated circuit device having a CPU for performing various controls when writing / reading data to / from the disk
The integrated circuit device for disk control acquires only the logging data that matches a preset condition among the logging data at the time of the failure of the CPU, and without acquiring the acquired logging data via the CPU. In addition, a logging circuit having a hardware configuration having a function of outputting to the outside through an independent path regardless of the execution of the program by the CPU,
The logging circuit
A logging control circuit that performs logging control to obtain only logging data that matches a preset condition;
A buffer for temporarily storing the logging data of the CPU acquired by the control of the logging control circuit; and a function of outputting the logging data stored in the buffer to the outside.
Various logging conditions including interrupt conditions, address conditions, and other conditions are set in the internal control register in the logging control circuit.
The trigger detection circuit in the logging control circuit detects only logging data that matches the logging condition by referring to the logging condition set in the internal control register among the logging data at the time of the failure of the CPU. ,
Control for storing logging data detected by the trigger detection circuit in the buffer in response to an instruction from the trigger detection circuit in the buffer control circuit in the logging control circuit And
A logging method for a disk device, wherein output control of the logging data is performed in a serial control circuit in the logging control circuit.

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