JP2004348306A - Disk unit and logging method for disk unit - Google Patents

Disk unit and logging method for disk unit Download PDF

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Publication number
JP2004348306A
JP2004348306A JP2003142827A JP2003142827A JP2004348306A JP 2004348306 A JP2004348306 A JP 2004348306A JP 2003142827 A JP2003142827 A JP 2003142827A JP 2003142827 A JP2003142827 A JP 2003142827A JP 2004348306 A JP2004348306 A JP 2004348306A
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Japan
Prior art keywords
logging
cpu
circuit
disk
control
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JP2003142827A
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Japanese (ja)
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JP4246544B2 (en
Inventor
Fumio Komuro
文男 小室
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Fujitsu Ltd
富士通株式会社
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Publication of JP2004348306A publication Critical patent/JP2004348306A/en
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Abstract

The present invention relates to a disk device and a logging method for the disk device, and arbitrarily retrieves logging data at the time of occurrence of a failure without the intervention of a CPU and regardless of the state of the CPU.
In a disk device including a disk control integrated circuit device having a CPU for performing various controls on a disk, the disk control integrated circuit device executes a program by the CPU without passing through the CPU. A logging circuit 20 having a hardware configuration capable of outputting the internal information and state of the CPU 2 through an independent path regardless of the condition of the CPU 2. It has a function to acquire only logging data that matches with and output it to the outside.
[Selection diagram] Fig. 1

Description

[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for, for example, a magnetic disk device (or a hard disk device) and other disk devices. In particular, logging data in the event of a failure during operation is transmitted to a CPU. The present invention relates to a disk device that can be arbitrarily taken out via an independent path irrespective of an operation, and a logging method for the disk device.
[0002]
2. Description of the Related Art A conventional example will be described below.
[0003]
(1): Description of Conventional Example 1 FIG. 4 is an explanatory diagram of Conventional Example 1. Hereinafter, Conventional Example 1 will be described with reference to FIG. As shown in FIG. 4, the magnetic disk device includes a hard disk control LSI (LSI: large-scale integrated circuit) in a control system of the magnetic disk device (hereinafter, referred to as “hard disk device”). This hard disk control LSI is referred to as “HDC LSI”).
[0004]
The HDC LSI 1 includes a CPU 2 for controlling various hard disks, a hard disk controller (hereinafter referred to as “HDC”) 3 for controlling a hard disk device based on the control of the CPU 2, and an RS232C cable. An RS232C interface (hereinafter referred to as “UART”) 4 for connection, a read channel interface (hereinafter referred to as “RDC / IF”) 5 for connecting a read channel, and the like are provided.
[0005]
In order to retrieve logging data when a failure occurs in the hard disk device, a connector 8 is attached to the HDC LSI 1 to connect the ICE 16, a connector 7 is attached to the logic analyzer 13, and a personal computer interface 9 is connected. To connect a terminal (for example, a personal computer).
[0006]
Further, a terminal (for example, a personal computer) 14 is connected to the UART 4, a read channel (hereinafter, referred to as “RDC”) 11 is connected to the RDC / IF 5, and a servo controller (hereinafter, “RDC”) is connected to the HDC 3. SVC ”) 12).
[0007]
In FIG. 4, conventionally, when a hang-up or a runaway of the CPU 2 occurs, in order to analyze data of the CPU 2, data analysis at the time of occurrence of a failure is performed by connecting the ICE 16 or the logic analyzer 13. However, the HDC 3 is provided as one channel in the CPU 2, and the state of the internal bus cannot be directly confirmed by the logic analyzer 13. The debug tool has been developed as a solution in the event of a failure by executing a program on the CPU 2. However, if the CPU 2 runs away, it cannot be used as a data analyzer.
[0008]
(2): Description of Conventional Example 2 (see Patent Document 1)
Hereinafter, Patent Document 1 will be described as Conventional Example 2.
[0009]
The second conventional example relates to a control device and an optical disc player, and aims to easily and quickly determine the cause of the abnormal operation when the abnormal operation of the product occurs.
[0010]
Then, in a control device for controlling a function means for performing various processes based on a required program, an operation history based on the program up to an operation error in a process of processing based on the program is written in a nonvolatile storage means. .
[0011]
However, the related art 2 cannot be realized unless the CPU can operate normally. Therefore, when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data at the time of occurrence of a failure cannot be extracted.
[0012]
(3): Description of Conventional Example 3 (see Patent Document 2)
Hereinafter, Patent Document 2 will be described as Conventional Example 3.
[0013]
Conventional example 3 relates to an error data holding method of a magnetic disk device. An error data holding device for holding the details of an error detected by an error detecting device in detail is provided when an error occurs in a magnetic disk device. The error content is written in detail in the error data holding means as it is, and the error content written in the error data holding means is read out later to detect an error occurrence portion.
[0014]
It is further described that latch means and display means are provided, the output of the error detection means is held in the latch means, and the display means is controlled based on the output. FIGS. 1 and 2 show diagrams showing the contents of the invention. In this case, as shown in the figure, an error data holding circuit is provided separately from the CPU.
[0015]
However, the related art 3 cannot be realized unless the CPU can operate normally. Therefore, if the CPU 2 is in a hang-up state or a program runs out of control, logging data at the time of occurrence of a failure cannot be extracted.
[0016]
(4): Description of Conventional Example 4 (see Patent Document 3)
Hereinafter, Patent Document 3 will be described as Conventional Example 4.
[0017]
Conventional example 4 relates to a VTR with an abnormal display function. It is necessary to specify an abnormal part for repairing the VTR, but the history of the abnormality, whether or not the situation in which the abnormality occurred is a transient state of the VTR state change, and whether or not the tape running mechanism is in a transient state Because it was unknown, it was difficult to identify the repair location.
[0018]
In order to solve this problem, when an abnormality occurs in a VTR, a plurality of abnormal contents are stored and displayed in a time series, and even when the abnormality occurrence is in a transition state of VTR operation mode switching, the fact is also stored. Added a means to display.
[0019]
However, the related art 4 cannot be realized unless the CPU can operate normally, so that when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data at the time of occurrence of a failure cannot be extracted.
[0020]
[Patent Document 1]
JP-A-8-297510 [Patent Document 2]
JP-A-58-1258 [Patent Document 3]
Japanese Patent Application Laid-Open No. 2000-36142
The above-mentioned prior art has the following problems.
[0022]
(1): In the conventional example 1, when the CPU 2 hangs up or the program runs away, the logic analyzer 13 or the ICE 16 is connected each time the CPU 2 hangs up and the failure analysis is performed again by logging the data before the failure. Therefore, the logging data cannot be extracted unless the CPU 2 is operating normally.
[0023]
(2): In the conventional example 1, if the CPU 2 hangs up, the ICE power supply must be turned on / off. Therefore, the state of the CPU 2 at the time of the failure is erased.
[0024]
(3): In the conventional example 1, a debugging tool or the like is developed, but it is created on the assumption that the CPU 2 operates normally. When a problem occurs, the CPU 2 is already in a hang-up state or the program is He was in a runaway condition, and the result was that the suspected part could not be identified. Therefore, logging data at the time of failure occurrence could not be taken out.
[0025]
(4): In Conventional Example 2 (see Patent Document 1), in a control device that controls functional means for performing various processes based on a required program, a control device that performs an operation error in a process of processing based on the program is described. It describes that an operation history based on the program is written in a nonvolatile storage unit. However, the related art 2 cannot be realized unless the CPU can operate normally, so that when the CPU 2 is in a hang-up state or a program is in a runaway state, logging data at the time of occurrence of a failure cannot be extracted.
[0026]
(5): Conventional example 3 (refer to Patent Document 2) relates to an error data holding method of a magnetic disk device, in which an error data holding means for holding in detail the details of an error detected by an error detecting means is provided. When an error occurs in the magnetic disk device, the error content is written in detail in the error data holding means as it is, and the error content written in the error data holding means is later read out to detect the error occurrence location. Is described.
[0027]
However, the related art 3 cannot be realized unless the CPU can operate normally. Therefore, if the CPU 2 is in a hang-up state or a program runs out of control, logging data at the time of occurrence of a failure cannot be extracted.
[0028]
(6): In Conventional Example 4 (see Patent Document 3), when an abnormality occurs in a VTR, a plurality of abnormal contents are stored and displayed in chronological order. However, in Conventional Example 4, as shown in FIG. 1, a CPU is interposed. Therefore, the conventional example 4 cannot be realized unless the CPU can operate normally, so that when the CPU 2 is in the hang-up state or the program runs out of control, logging data at the time of occurrence of a failure cannot be taken out.
[0029]
The present invention solves such a conventional problem and arbitrarily causes a failure without using a CPU and regardless of the state of the CPU without using an ICE or a logic analyzer used in the conventional example. It is intended to be able to retrieve logging data at the time of occurrence.
[0030]
The present invention has the following configuration to achieve the above object.
[0031]
(1): In a disk device including a disk control integrated circuit device having a CPU for performing various controls at the time of writing / reading data to / from a disk, the disk control integrated circuit device does not pass through the CPU. And a hardware-configured logging circuit capable of outputting internal information and status of the CPU through an independent path regardless of execution of a program by the CPU, wherein the logging circuit stores logging data when a failure occurs in the CPU. Among them, a function of acquiring only logging data meeting a preset condition and outputting the acquired data to the outside is provided.
[0032]
(2): In the disk device of (1), the logging circuit determines the content of the interrupt signal acquired from the CPU to detect that the CPU is in a hang-up state; Has a function of enabling output of logging data including register information in the system bus or the CPU as information when hangs up.
[0033]
(3) In the disk device according to (1), the logging circuit includes a logging control circuit that performs logging control for acquiring only logging data that satisfies a preset condition, and a control by the logging control circuit. A buffer for temporarily storing the acquired logging data of the CPU is provided, and a function of outputting the logging data stored in the buffer to the outside is provided.
[0034]
(4) In the disk device according to (3), the logging control circuit includes an internal control register for setting various logging conditions including an interrupt condition, an address condition, and other conditions, and logging data when a failure occurs in the CPU. Among them, a trigger detection circuit that refers to a logging condition set in the internal control register and detects only logging data that matches the locking condition, and an instruction from the trigger detection circuit causes the trigger detection circuit to A buffer control circuit for controlling the storage of the detected logging data in the buffer, and a serial control circuit for performing serial control of the logging data are provided.
[0035]
(5): In a logging method for a disk device provided with a disk control integrated circuit device having a CPU for performing various controls on the disk, the disk control integrated circuit device is provided with a logging control dedicated circuit, and the logging control dedicated circuit is used. When a failure occurs in the CPU, logging data including the internal information and status of the CPU is acquired and output without using the CPU and by an independent path regardless of the execution of a program by the CPU. It is characterized by the following.
[0036]
(Action)
The operation of the present invention based on the above configuration will be described with reference to FIG.
[0037]
(A): In the above (1), in the disk control integrated circuit device, the logging circuit 20 uses the internal information of the CPU 2 via an independent path without the intervention of the CPU 2 and independently of execution of a program by the CPU 2. And state and output. In this case, the logging circuit 20 acquires only logging data that meets a preset condition from the logging data at the time of occurrence of a failure in the CPU 2 and outputs the logging data to the outside.
[0038]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or the logic analyzer used in the conventional example.
[0039]
(B): In the above (2), the logging circuit 20 detects that the CPU 2 is in a hang-up state by determining the content of the interrupt signal acquired from the CPU 2 or detects a state in which the CPU 2 hangs up. As information, logging data including register information inside the system bus 24 or the CPU 2 is output.
[0040]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or the logic analyzer used in the conventional example.
[0041]
(C): In the above (3), the logging circuit 20 performs the logging control so that the logging control circuit 21 acquires only the logging data meeting the preset condition. Then, the buffer 22 temporarily stores the logging data of the CPU 2 obtained under the control of the logging control circuit 21 and outputs the logging data stored in the buffer 22 to the outside.
[0042]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or the logic analyzer used in the conventional example.
[0043]
(D): In the above (4), various logging conditions including an interrupt condition, an address condition, and other conditions are set in the internal control register provided in the logging control circuit 21. Further, the trigger detection circuit provided in the logging control circuit 21 refers to the logging condition set in the internal control register among the logging data at the time of occurrence of the failure of the CPU 2 and only the logging data matching the rocking condition. To detect.
[0044]
In addition, a buffer control circuit provided in the logging control circuit 21 controls the storage of the logging data detected by the trigger detection circuit in the buffer 22 according to an instruction from the trigger detection circuit. Further, a serial control circuit provided in the logging control circuit 21 performs serial control of the logging data.
[0045]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or the logic analyzer used in the conventional example.
[0046]
(E): In the above (5), when a failure occurs in the CPU 2 by the logging control dedicated circuit (logging circuit 20) provided in the disk control integrated circuit device, the CPU 2 does not pass through the CPU 2 and the CPU 2 performs the processing. The logging data including the internal information and status of the CPU is acquired and output through an independent route regardless of the execution of the program.
[0047]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU 2 without using the ICE or the logic analyzer used in the conventional example.
[0048]
Embodiments of the present invention will be described below in detail with reference to the drawings. The following example is an example in which the present invention is applied to a magnetic disk device (hereinafter, referred to as “hard disk device”).
[0049]
§1: Description of LSI for HDC (1): Description of configuration of LSI for HDC FIG. 2 is an explanatory diagram of the LSI for HDC. As shown in FIG. 2, the hard disk device (magnetic disk device) includes an HDC LSI (hard disk control LSI) 1 in a control system of the hard disk device.
[0050]
The HDC LSI 1 includes a CPU 2 for performing various hard disk controls (such as control for writing / reading data to / from a disk), and a logging circuit 20 (a dedicated logging control) for acquiring logging data of the CPU 2. Circuit), a hard disk control circuit 3 for controlling a hard disk drive (control of a servo control system) based on the control of the CPU 2, and a read channel connected (for example, control for writing / reading data to / from a disk is performed). (Read channel control circuit) 11 and the like.
[0051]
Further, the logging circuit 20 includes a logging control circuit 21 for controlling logging data acquisition, a buffer 22 for storing logging data and the like, and a UART (RS232C interface) 23. Reference numeral 24 denotes a system bus which is a path for data and addresses. Further, an interrupt signal at the time of occurrence of a failure output from the CPU 2 is taken into the logging control circuit 21.
[0052]
The HDC LSI 1 includes a terminal (personal computer) 28 connected to the UART 23, an external circuit (servo controller: SVC) 26 connected to the hard disk control circuit 3, and an external circuit (a hard disk drive) connected to the RDC 11. Write / read circuit) 27 and the like.
[0053]
The logging circuit 20 is configured by a circuit having a hardware configuration. The logging circuit 20 does not pass through the CPU 2 (processor) and has an independent path irrespective of the execution of a program by the CPU 2. This is a circuit having a hardware configuration capable of outputting (logging control dedicated circuit).
[0054]
(2): Description of the operation of the HDC LSI The operation of the logging circuit 20 is as follows. As an operation when the terminal 28 (for example, a personal computer) is used, first, a start / stop request is issued from the terminal 28 to the logging circuit 20 by operating a keyboard, a mouse, or the like of the terminal 28.
[0055]
The terminal 28 sets logging conditions and the like in the logging circuit 20. When changing the logging conditions and the like, the logging operation is performed by performing the same operation as described above. When the necessary logging conditions are set in the logging circuit 20 in advance, the logging operation is performed only by performing a start / stop request from the terminal 28 to the logging circuit 20 by operating the terminal 28. Do.
[0056]
When a failure occurs in the CPU 2, the logging circuit 20 outputs an interrupt signal from the CPU 2. The logging circuit 20 captures the interrupt signal output from the CPU 2 and compares the content with the set logging condition. If they match, interrupt detection, address detection, and the like are performed, and the data is stored as logging data in a storage medium such as an internal buffer. Thereafter, the saved logging data is output to the terminal 28 or the like, so that the logging data can be detected.
[0057]
§2: Detailed description of logging control circuit (1): Description of configuration of logging control circuit FIG. 3 is a detailed configuration diagram of the logging control circuit. The detailed configuration of the logging control circuit 21 is as shown in FIG. As shown, the logging control circuit 21 includes a trigger detection circuit 31, an internal control register 32, a buffer control circuit 33, and a serial control circuit 34. The trigger detection circuit 31 is connected to the CPU 2 and takes in an interrupt signal and an instruction / data from the CPU 2.
[0058]
The buffer control circuit 33 is connected to the trigger detection circuit 31, and controls the buffer 22 based on an instruction from the trigger detection circuit 31. The internal control register 32 is connected to the trigger detection circuit 31, the serial control circuit 34, and the CPU 2. The serial control circuit 34 is connected to the trigger detection circuit 31, the buffer control circuit 33, the internal control register 32, and the UART 23, and is configured to refer to data in the internal control register 32 and control the UART 23.
[0059]
Further, in the internal control register 32, an interrupt condition, an address condition, and other conditions can be set as logging conditions. In this case, the internal control register 32 is connected to the terminal 28 (see FIG. 2) via the UART 23, so that the logging condition can be set or changed from the terminal 28.
[0060]
(2): Description of operation of logging control circuit The operation of the logging control circuit is as follows. The internal control register 32 stores in advance interrupt conditions (interrupt conditions when a failure occurs in the CPU 2), address conditions, and other conditions. In the trigger detection circuit 31, interrupt detection, address detection, other conditions, and the like are set as logging conditions.
[0061]
In this way, the CPU 2 starts operating with the above information set in the trigger detection circuit 31 and the internal control register 32. Then, it is assumed that a failure has occurred during the operation of the CPU 2 and the CPU 2 has issued a failure occurrence interrupt signal. This interrupt signal is taken into the trigger detection circuit 31, and it is determined whether or not the logging condition set therein is satisfied.
[0062]
In this case, the trigger detection circuit 31 refers to the condition set in the internal control register 32 and determines whether or not the interrupt signal is applicable. . Subsequently, the trigger detection circuit 31 detects the corresponding address and other conditions via the system bus 24, and issues an instruction to the buffer control circuit 33.
[0063]
The buffer control circuit 33 receiving the instruction takes in the address and the like before the hang-up output from the CPU 2 via the system bus 24 and stores it in the buffer 22. By such an operation, the logging data from the CPU 2 is accumulated in the buffer 22. Thereafter, the serial control circuit 34 controls the UART 23 to take out the data in the buffer 22 and send (output) it to the terminal 28.
[0064]
(Other explanations)
{Circle around (1)} The above description is an example of a hard disk device (magnetic disk device). However, the present invention is not limited to such an example, but may be applied to other similar disk devices (for example, magneto-optical disk devices). Applicable.
[0065]
{Circle around (2)} The internal control register 32 can also set a logging condition internally in advance. In this case, the present invention can be carried out even if the logging condition cannot be changed from the terminal 28, and can be carried out even if the logging condition can be changed from the terminal 28.
[0066]
As described above, according to the present invention, the following effects can be obtained.
[0067]
(1) According to claim 1, in the disk control integrated circuit device, the logging circuit is configured such that the internal information and status of the CPU are not routed through the CPU and independent of the execution of the program by the CPU. Capture and output. In this case, the logging circuit acquires only logging data that meets a preset condition from among the logging data at the time of occurrence of a failure in the CPU, and outputs it to the outside.
[0068]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU without using the ICE or the logic analyzer used in the conventional example.
[0069]
(2) In the second aspect, the logging circuit determines that the CPU is in a hang-up state by determining the content of the interrupt signal acquired from the CPU, or as information when the CPU hangs up. And outputs logging data including register information inside the system bus or CPU.
[0070]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU without using the ICE or the logic analyzer used in the conventional example.
[0071]
(3): In the third aspect, the logging circuit performs the logging control so that the logging control circuit acquires only the logging data that satisfies a preset condition. The buffer temporarily stores the CPU logging data obtained under the control of the logging control circuit, and outputs the logging data stored in the buffer to the outside.
[0072]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU without using the ICE or the logic analyzer used in the conventional example.
[0073]
(4): In claim 4, various logging conditions including an interrupt condition, an address condition, and other conditions are set in the internal control register provided in the logging control circuit. Also, the trigger detection circuit provided in the logging control circuit refers to the logging condition set in the internal control register and detects only the logging data that matches the locking condition from among the logging data at the time of the occurrence of the CPU failure. I do.
[0074]
Further, a buffer control circuit provided in the logging control circuit controls the storage of the logging data detected by the trigger detection circuit in the buffer in accordance with an instruction from the trigger detection circuit. Further, a serial control circuit provided in the logging control circuit performs serial control of the logging data.
[0075]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU without using the ICE or the logic analyzer used in the conventional example.
[0076]
(5) According to the fifth aspect, when a failure occurs in the CPU, the logging control dedicated circuit (logging circuit) provided in the disk control integrated circuit device can execute the program by the CPU without passing through the CPU. The logging data including the internal information and status of the CPU is acquired and output through an independent path regardless of the execution.
[0077]
In this way, logging data at the time of failure occurrence can be arbitrarily extracted regardless of the state of the CPU without using the ICE or the logic analyzer used in the conventional example.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is an explanatory diagram of an HDC LSI according to an embodiment of the present invention.
FIG. 3 is a detailed configuration diagram of a logging control circuit according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram of Conventional Example 1.
[Explanation of symbols]
1 LSI for HDC
2 CPU
3 HDC
4 UART
5 RDC / IF
7, 8 connector 9 PC I / F
11 RDC (read channel)
12 SVC (servo control circuit)
13 Logic analyzer 14, 15 Terminal (PC 16 ICE)
Reference Signs List 20 logging circuit 21 logging control circuit 22 buffer 23 UART (RS232C interface)
24 System bus 26, 27 External circuit 28 Terminal 31 Trigger detection circuit 32 Internal control register 33 Buffer control circuit 34 Serial control circuit

Claims (5)

  1. In a disk device provided with a disk control integrated circuit device having a CPU for performing various controls when writing / reading data to / from a disk, the disk control integrated circuit device is connected to the CPU without the CPU. A hardware independent logging circuit capable of outputting internal information and status of the CPU on an independent path regardless of the execution of the program by
    The disk device according to claim 1, wherein the logging circuit has a function of acquiring only logging data that satisfies a preset condition from among logging data at the time of occurrence of a failure in the CPU and outputting the logging data to the outside.
  2. The logging circuit,
    A function of detecting that the CPU is in a hang-up state by determining the content of the interrupt signal obtained from the CPU;
    2. The disk device according to claim 1, further comprising a function of enabling output of logging data including a system bus or register information inside the CPU as information when the CPU hangs up.
  3. The logging circuit,
    A logging control circuit that performs logging control to acquire only logging data that matches a preset condition,
    A buffer for temporarily storing CPU logging data obtained under the control of the logging control circuit,
    2. The disk device according to claim 1, further comprising a function of outputting the logging data stored in the buffer to the outside.
  4. The logging control circuit,
    An internal control register for setting various logging conditions including interrupt conditions, address conditions, and other conditions;
    A trigger detection circuit that detects only logging data that matches the locking condition by referring to a logging condition set in the internal control register among the logging data at the time of occurrence of a failure in the CPU;
    A buffer control circuit that performs control when storing the logging data detected by the trigger detection circuit in the buffer according to an instruction from the trigger detection circuit,
    4. The disk device according to claim 3, further comprising a serial control circuit that performs serial control of the logging data.
  5. In a logging method for a disk device including a disk control integrated circuit device having a CPU for performing various controls on a disk,
    A dedicated logging control circuit is provided in the disk control integrated circuit device,
    When a failure occurs in the CPU, the logging data including internal information and status of the CPU is provided by the logging control dedicated circuit without using the CPU and independent of the execution of a program by the CPU. And outputting the obtained data.
JP2003142827A 2003-05-21 2003-05-21 Disk device and disk device logging method Expired - Fee Related JP4246544B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9092453B2 (en) 2012-07-30 2015-07-28 Fujitsu Limited Monitoring device, information processing apparatus, and monitoring method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9092453B2 (en) 2012-07-30 2015-07-28 Fujitsu Limited Monitoring device, information processing apparatus, and monitoring method

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