JP4246122B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an insulated gate field effect transistor (hereinafter simply referred to as a transistor) and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device having a P-channel transistor and an N-channel transistor over the same substrate and a manufacturing method thereof. In particular, the present invention relates to simplification of the manufacturing process.

  There are many semiconductor devices such as ICs that have complementary transistors consisting of P-channel transistors and N-channel transistors on the same substrate. In recent years, a liquid crystal display device and a circuit for driving the liquid crystal display device are formed on an insulating substrate. The circuit for driving the liquid crystal display device has a complementary transistor. is doing.

  When forming a P-channel transistor and an N-channel transistor on the same substrate, impurities to be doped in the semiconductor layer must be divided between the P-channel transistor and the N-channel transistor.

At this time, for example, first, a mask is formed on a semiconductor layer to be a P-channel transistor, and phosphorus is implanted into the semiconductor layer to be an N-channel transistor. Thereafter, the mask is removed, this time, the semiconductor layer to be an N-channel transistor is masked, and boron is implanted into the semiconductor layer to be a P-channel transistor.
As described above, at least two masks are necessary to separate impurities.

On the other hand, a process has been proposed in which the number of doping masks is reduced to one and the process for manufacturing a complementary transistor is simplified. The outline of this process is shown below.
In FIG. 3, after forming a base film 302 on an insulating substrate 301, semiconductor island regions 303 and 304 are formed. Thereafter, a gate insulating film 305 is formed. Then, gate electrodes 306 and 307 are formed on the gate insulating film 305. In this way, the state of FIG.

  Next, phosphorus (P) is implanted into all the semiconductor island regions 303 and 304 using the gate electrodes 306 and 307 as a mask. N-type impurity regions 308 to 311 are thus formed. (Fig. 3 (B))

  Thereafter, a mask 312 is formed over the semiconductor island region 303 to be an N-channel transistor. The mask 312 is formed by a lithography technique using a resist. Then, boron (B) is implanted into the semiconductor island region 304 to be a P-channel transistor. At this time, the dose amount of boron is made larger than the dose amount of phosphorus (P) in FIG. As a result, the impurity regions 310 and 311 are inverted to the p-type. (Figure 3 (C))

  Then, the mask 312 (made of a resist or the like) is removed, and an interlayer insulating film 313 is formed. Next, contact holes are formed in the interlayer insulating film 313 and the gate insulating film 305, and source / drain electrodes 314 to 316 are formed. Thus, an N-channel transistor and a P-channel transistor are obtained on the same substrate. (Fig. 4 (D))

  Thus, a resist is generally used as a doping mask. Lithography technology using a resist is very useful for fine processing in the manufacture of semiconductor devices such as LSI.

  However, since the resist is made of an organic material, there is a very high probability that residual organic contamination will occur after the resist is removed. In the resist removing process, there is also contamination by heavy metal from the etching apparatus. Furthermore, since the substrate is heated to a high temperature in the doping process, the resist is cured by the heat, and it becomes difficult to remove the resist in the subsequent resist removal process, resulting in a problem that productivity is lowered. Further, since ashing is performed with oxygen or the like for a long time, the plasma is damaged.

  Therefore, there is a demand for a process that does not use a resist in the doping process. An object of the present invention is to eliminate a doping mask from a manufacturing process without complicating the manufacturing process.

  The gist of the invention disclosed in this specification is that an interlayer insulating film is used as a doping mask in a method for manufacturing a semiconductor device having a P-channel transistor and an N-channel transistor over the same substrate.

The first of the present invention is a step of forming a top gate type thin film transistor on an insulating substrate. That is,
Forming at least two semiconductor island regions on an insulating substrate;
Forming a gate insulating film on the semiconductor island region;
Forming a gate electrode on the gate insulating film;
Implanting a first impurity into the semiconductor island region using the gate electrode as a mask;
Forming an interlayer insulating film so as to cover the gate insulating film and the gate electrode; patterning the interlayer insulating film; exposing at least one of the gate electrodes;
And a step of injecting a second impurity into the semiconductor island region under the exposed gate electrode, using the gate electrode and the interlayer insulating film as a mask.

A second aspect of the present invention is a step of forming a transistor on a semiconductor substrate. That is,
Forming a gate insulating film on the semiconductor substrate;
Forming at least two gate electrodes on the gate insulating film;
Implanting a first impurity into the semiconductor using the gate electrode as a mask;
Forming an interlayer insulating film so as to cover the gate insulating film and the gate electrode; patterning the interlayer insulating film; exposing at least one of the gate electrodes;
And a step of injecting a second impurity into the semiconductor using the gate electrode and the interlayer insulating film as a mask.

A third aspect of the present invention is a step of forming a bottom gate type transistor. That is,
Forming at least two gate electrodes on an insulating substrate;
Forming a gate insulating film on the gate electrode;
Forming at least two semiconductor layers on the gate insulating film;
Forming an interlayer insulating film on the semiconductor layer;
Patterning the interlayer insulating film, exposing a part of at least one of the semiconductor layers; and
Injecting a first impurity into the exposed semiconductor layer using the interlayer insulating film as a mask, patterning the interlayer insulating film, and exposing the exposed semiconductor layer to a part of another semiconductor layer And a process of
And a step of injecting a second impurity into the semiconductor layer using the interlayer insulating film as a mask.

The semiconductor device manufactured by the process of the present invention has the following characteristics. That is,
In a semiconductor device having at least one P-channel transistor and at least one N-channel transistor,
The P-channel transistor and the N-channel transistor each have a channel formation region, a source region, and a drain region,
A gate electrode formed through a gate insulating film in the vicinity of the channel formation region;
A source wiring electrically connected to the source region;
Drain wiring electrically connected to the drain region;
An interlayer insulating film formed under the source wiring and the drain wiring;
The interlayer insulating film is characterized in that the same impurity as that added to the source region and the drain region of the P-channel transistor or the N-channel transistor is added.

Furthermore, in the above configuration,
The concentration of the impurity added to the interlayer insulating film has a distribution having a gradient in the film thickness direction of the interlayer insulating film.
The interlayer insulating film has a thickness of 0.3 μm or more. Further, the interlayer insulating film is made of an inorganic material.

In addition, there are cases where the interlayer insulating film has two layers. That is,
In a semiconductor device having at least one P-channel transistor and at least one N-channel transistor,
The P-channel transistor and the N-channel transistor each have a channel formation region, a source region, and a drain region,
A gate electrode formed through a gate insulating film in the vicinity of the channel formation region;
A gate wiring electrically connected to the gate electrode;
A source wiring electrically connected to the source region;
Drain wiring electrically connected to the drain region;
A first interlayer insulating film formed on the gate wiring;
A second interlayer insulating film formed between the source wiring or the drain wiring and the first interlayer insulating film;
The first interlayer insulating film is doped with the same impurity as the impurity added to the source region and the drain region of the P-channel transistor or the N-channel transistor.

Further, in the above structure, the concentration of the impurity added to the first interlayer insulating film has a distribution having a gradient in the film thickness direction of the interlayer insulating film.
The first interlayer insulating film has a thickness of 0.3 μm or more. Further, the interlayer insulating film is made of an inorganic material.

As another feature,
In a semiconductor device having at least one P-channel transistor and at least one N-channel transistor,
The P-channel transistor and the N-channel transistor each have a channel formation region, a source region, and a drain region,
A gate electrode formed through a gate insulating film in the vicinity of the channel formation region;
A source wiring connected to the source electrode, a source wiring connected to the source electrode;
A drain electrode connected to the drain region;
A drain wiring connected to the drain electrode and an interlayer insulating film formed under the source wiring or the drain wiring;
The gate insulating film is characterized in that there is a step near the interlayer insulating film and the source electrode or drain electrode.

In addition, as another feature,
At least one P-channel transistor;
At least one N-channel transistor;
A gate wiring electrically connected to a gate electrode of the P-channel transistor or the N-channel transistor;
A source wiring electrically connected to a source region of the P-channel transistor or the N-channel transistor;
A drain wiring electrically connected to a drain region of the P-channel transistor or the N-channel transistor;
An interlayer insulating film provided between the gate wiring and the source wiring or the drain wiring;
The interlayer insulating film is opened on the P-channel transistor and the N-channel transistor.

Further, in the above two structures, the interlayer insulating film is doped with the same impurity as that added to a source region and a drain region of the P-channel transistor or the N-channel transistor. To do.
Furthermore, the concentration of the impurity added to the interlayer insulating film has a distribution having a gradient in the film thickness direction of the interlayer insulating film.
The interlayer insulating film has a thickness of 0.3 μm or more. Further, the interlayer insulating film is made of an inorganic material.

Furthermore, as another invention, the interlayer insulating film can be used not only as a doping mask but also as a spacer for forming an LDD (Lightly Doped Drain) region. That is, as a method for manufacturing a thin film transistor,
Forming a semiconductor island region on an insulating substrate;
Forming a gate insulating film on the semiconductor island region;
Forming a gate electrode on the gate insulating film;
Using the gate electrode as a mask, implanting low-concentration impurities into the semiconductor island region;
Forming an interlayer insulating film covering the gate insulating film and the gate electrode; etching the interlayer insulating film; forming a spacer on a side surface of the gate electrode;
And a step of injecting a high concentration impurity into the semiconductor island region using the gate electrode and the spacer as a mask.

In addition, a transistor formed over a semiconductor substrate can be manufactured similarly. That is,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Implanting low-concentration impurities into the semiconductor using the gate electrode as a mask;
Forming an interlayer insulating film covering the gate insulating film and the gate electrode; etching the interlayer insulating film; forming a spacer on a side surface of the gate electrode;
And a step of injecting a high concentration impurity into the semiconductor using the gate electrode and the spacer as a mask.

  By using the interlayer insulating film as a mask in the doping step, the resist mask for doping can be eliminated. Thereby, organic matter contamination of the semiconductor device can be reduced. In addition, the manufacturing process can be simplified.

  Further, when the interlayer insulating film is used as an LDD spacer, an LDD region can be formed by a simplified process.

  In the processes disclosed in the first and second aspects of the present invention, the interlayer insulating film is used as a mask when doping the second impurity. Further, in the process disclosed in the third aspect of the present invention, it is used as a mask in doping with the first and second impurities.

Since the thickness of the interlayer insulating film is usually 0.3 μm or more, the interlayer insulating film can sufficiently function as a shielding mask at the time of impurity doping. In addition, the most important function inherent in the interlayer insulating film as the crossing spacer of the upper and lower wirings is not impaired by the present invention. Furthermore, when another interlayer insulating film is formed on the interlayer insulating film, the insulation between the upper and lower wirings is improved.
Thus, according to the present invention, the doping mask can be eliminated from the manufacturing process without complicating the manufacturing process.

  Furthermore, the manufacturing process of the present invention can be simplified because etching for forming contact holes in the source region and the drain region is simultaneously performed in the etching step for doping.

  The interlayer insulating film can also be used as an LDD spacer on the side surface of the gate electrode. When this step is used, it is not necessary to form a film for the spacer, and furthermore, a contact hole can be formed simultaneously with the formation of the spacer, so that the process can be simplified.

[Example 1]
In this embodiment, a top gate complementary thin film transistor is manufactured. A manufacturing process diagram of this example is shown in FIGS. 1 and 2, an N-channel transistor is formed on the left side and a P-channel transistor is formed on the right side.

  First, a silicon oxide film 102 is formed as a base film on the insulating substrate 101 to a thickness of 1000 to 3000 mm, preferably 1500 to 2500 mm. As the insulating substrate, a glass substrate or a quartz substrate is used. The silicon oxide film is formed by a plasma CVD method using TEOS.

Next, an amorphous silicon film (not shown) is formed to a thickness of 200 to 800 mm, preferably 500 to 600 mm by plasma CVD. Then, the amorphous silicon film is crystallized by laser or heat. Thereafter, the crystallized silicon film is patterned to form semiconductor island regions 103 and 104. At this time, boron (B) may be added to the amorphous silicon film at a concentration of 1 × 10 ¹⁹ atoms / cm ³ . Since this is done to adjust the threshold value (V _th ) of the transistor, the concentration is appropriately adjusted within the above range. In particular, it is preferable to add it to a silicon film to be an N-channel transistor.

Then, a silicon oxide film is formed as the gate insulating film 105 to a thickness of 800 to 2000 mm, preferably 1000 to 1500 mm. This silicon oxide film is formed by a plasma CVD method using a mixed gas of silane and nitric oxide. Further, as the gate insulating film, silicon nitride or a stacked body of silicon oxide and silicon nitride may be used.
In this way, the state of FIG.

  Next, an aluminum film (not shown) is formed on the gate insulating film 105 by sputtering. A small amount of scandium, titanium, silicon or the like is preferably added to the aluminum film in order to prevent hillocks and whiskers from being generated in the aluminum in the subsequent heating step. Further, tantalum may be used instead of aluminum.

  Thereafter, the surface of the aluminum film is anodized using tartaric acid to form an extremely thin dense anodic oxide film having a thickness of 100 mm. This anodic oxide film has the effect of improving the adhesion of the mask. Then, a resist mask (not shown) is placed on the dense anodic oxide film, and the aluminum film and the dense anodic oxide film are patterned to form gate electrodes 106 and 107.

Next, the side surfaces of the gate electrodes 106 and 107 are anodized using oxalic acid to form porous anodic oxide films 108 and 109. Then, the resist mask is removed, and the gate electrode is anodized again using tartaric acid, and dense anodic oxide films 110 and 111 are formed surrounding the gate electrode.
In this way, the state of FIG.

After obtaining the state of FIG. 1B, phosphorus (P) is ion-implanted into the semiconductor island regions 103 and 104 using the gate electrodes 106 and 107 and the anodic oxide films 108 to 111 as a mask. The dose at this time is 1 × 10 ^{14 to} 9 × 10 ¹⁴ atoms / cm ² , preferably 2 × 10 ^{14 to} 7 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage is 80 kV. This process is called heavy dope with respect to the process of FIG. Thus, n ⁺ -type impurity regions 112 to 115 are formed. (Figure 1 (C))

Thereafter, the porous anodic oxide films 108 and 109 are removed, and an interlayer insulating film 116 is formed to a thickness of 0.3 μm or more, preferably 0.5 μm or more. As the interlayer insulating film, a silicon nitride film, a silicon oxide film, a stack of a silicon nitride film and a silicon oxide film, an organic resin film, a stack of a silicon nitride film and an organic resin film, a stack of a silicon oxide film and an organic resin film, etc. Can be used. If a laminate of a silicon nitride film and an organic resin film is used, organic contamination can be reduced by using a laminate of the silicon nitride film and the organic resin film on top. The same applies to the lamination of the silicon oxide film and the organic resin film. Furthermore, in order to minimize organic contamination, it is preferable to use an inorganic material such as a silicon nitride film, a silicon oxide film, or a stack of a silicon nitride film and a silicon oxide film.
In this way, the state of FIG.

Next, the interlayer insulating film is patterned to form an opening on the semiconductor island region 104 to be a P-channel transistor. At this time, if a material having a high etching rate with respect to the gate insulating film 105 is used for the interlayer insulating film 116, the gate insulating film serves as an etching stopper. For example, a silicon oxide film may be used as the gate insulating film, a silicon nitride film, an organic resin film, or a stacked layer of a silicon nitride film and an organic resin film may be used as the interlayer insulating film. In consideration of organic contamination as described above, it is preferable to use a silicon oxide film as the gate insulating film and a silicon nitride film as the interlayer insulating film.
Further, the gate insulating film may also be etched to stop the etching at the semiconductor layer.

Then, boron (B) is ion-implanted using the interlayer insulating film as a mask. Since the interlayer insulating film has a thickness of 0.3 μm or more, it functions sufficiently as a mask.
In addition, the dose amount at this time is set larger than the dose amount in which phosphorus is implanted in the step of FIG. In this embodiment, the dose is 1 × 10 ^{15 to} 5 × 10 ¹⁵ atoms / cm ² and the acceleration voltage is 65 kV. As described above, since the boron dose is larger than the phosphorus dose, the conductivity types of the impurity regions 114 and 115 are inverted to become p-type impurity regions (source / drain regions) 117 and 118. Reference numeral 119 is a channel formation region of a P-channel transistor.
In this way, the state of FIG.

Then, this time, an opening is formed on the semiconductor island region 105 that will be an N-channel transistor, and phosphorus (P) is implanted again. The phosphorus dose at this time is set to be smaller than the first phosphorus dose. In this embodiment, the dose is 1 × 10 ^{13 to} 5 × 10 ¹³ atoms / cm ² and the acceleration voltage is 80 kV. This process is called light dope with respect to the process of FIG.

By this step, phosphorus is implanted at a concentration lower than that of the n ⁺ -type impurity regions 112 and 113 into the regions 120 and 121 where phosphorus was not implanted at the time of the first phosphorus implantation. These n ⁻ -type impurity regions 120 and 121 are called LDD regions, and have the effect of relaxing the electric field concentration between the gate electrode and the impurity regions and reducing the leakage current. Reference numeral 122 denotes a channel formation region of an N-channel transistor.

Since the dose amount of the second phosphorus implantation is smaller than the dose amount of boron implantation, the conductivity types of the p-type impurity regions 117 and 118 are not reversed.
In this way, the state of FIG.

  Thereafter, a contact hole is formed in the gate insulating film 105, and a metal film (not shown) is formed to cover the gate electrode and the interlayer insulating film. As the metal film, an aluminum film or a laminated film of aluminum and titanium can be used. Then, the metal film is patterned to form source / drain electrodes / wirings 123 to 125. Thereafter, a passivation film 126 is formed.

Thus, a complementary thin film transistor can be formed. Note that in FIG. 2F, n ⁻ -type impurity regions 120 and 121 are formed in FIG. 2F, and these n ⁻ -type impurity regions 120 and 121 are formed in the step of FIG. It may be formed after removing the porous anodic oxide films 108 and 109.

  A semiconductor device having a complementary thin film transistor formed as described above may be characteristic of a transistor manufactured by a conventional method. This will be described with reference to FIG.

First, since the interlayer insulating film functions as a mask at the time of impurity implantation, the interlayer insulating film contains the impurities (phosphorus and boron). Each concentration is 1 × 10 ¹⁷ atoms / cm ³ or more. In addition to being included, as shown on the right side of FIG. 5A, the distribution has a gradient in concentration along the film thickness direction. This indicates that impurities are ion-implanted into the interlayer insulating film. The impurity concentration value (1 × 10 ¹⁷ atoms / cm ³ or more) indicates the maximum value of the gradient.

  In addition, the impurity concentration distribution has a peak, and the position of the peak varies depending on phosphorus and boron. This is because the doping conditions are different in each. Further, it varies depending on light dope and heavy dope.

  Second, the interlayer insulating film forms an opening on the transistor. That is, in FIG. 5A, the interlayer insulating film 116 exists between the gate wiring 501 and the source (drain) electrode / wiring 125. However, there is no interlayer insulating film on the transistor. This is because the interlayer insulating film on the semiconductor island region is removed in order to dope the semiconductor island regions 103 and 104 with impurities.

Third, the gate insulating film has a step near the interlayer insulating film and the source or drain electrode.
FIG. 5B is an enlarged view of a portion surrounded by 502 in FIG. In this figure, a step 503 is formed in the gate insulating film 105 in the vicinity where the interlayer insulating film 116 and the source (drain) electrode 125 are in contact with each other. This is over-etched when the interlayer insulating film is patterned. Of course, overetching may not be performed depending on conditions such as etching time.

  Finally, when a resist is used as a doping mask, a thin resist layer may remain on the gate insulating film. However, the resist layer is not formed on the gate insulating film of the semiconductor device formed according to the present invention.

  Note that although an example in which a thin film transistor is formed over an insulating substrate is described in this embodiment, the transistor can be similarly formed when a transistor is formed over a semiconductor substrate. Further, the structural features of the manufactured semiconductor device are also as described above (FIG. 11). In FIG. 11, reference numeral 1101 denotes a semiconductor substrate, 1102 denotes a field oxide, and other portions are the same as those of the thin film transistor of this embodiment.

[Example 2]
This embodiment is a method for manufacturing a bottom gate type complementary thin film transistor. Manufacturing process diagrams of this example are shown in FIGS. 6 and 7, an N-channel transistor is formed on the left side and a P-channel transistor is formed on the right side. The production conditions not specifically described are the same as those in the first embodiment.

First, a base film 602 is formed over the insulating substrate 601. Next, an aluminum film (not shown) is formed and then patterned to obtain gate electrodes 603 and 604. Then, a gate insulating film 605 is formed so as to cover the gate electrodes 603 and 604. Thereafter, a semiconductor layer (not shown) is formed and patterned to obtain semiconductor island regions 606 and 607. After obtaining the semiconductor island regions 606 and 607, an interlayer insulating film 608 is formed.
In this way, FIG. 6A is obtained.

Next, the interlayer insulating film is patterned to expose portions 609 and 610 of the semiconductor layer to be a P-channel transistor. Then, using the interlayer insulating film as a mask, boron (B) ions are implanted into the exposed semiconductor layers 609 and 610 at a dose of 1 × 10 ^{15 to} 5 × 10 ¹⁵ atoms / cm ² to form p-type impurity regions (source / source). Drain regions) 609 and 610 and a channel formation region 611 are formed. (Fig. 6 (B))

Then, the interlayer insulating film is patterned again to expose portions 612 and 613 of the semiconductor layer to be an N-channel transistor. Thereafter, using the interlayer insulating film as a mask, phosphorus (P) ions are implanted into the exposed semiconductor layers 612 and 613 at a dose of 1 × 10 ^{14 to} 9 × 10 ¹⁴ atoms / cm ² to form n-type impurity regions 612 and 613. (Source / drain regions) 609 and 610 and a channel formation region 614 are formed.

At this time, phosphorus is also implanted into the p-type impurity regions 609 and 610. However, since the dose amount of phosphorus is smaller than the dose amount of boron, the conductivity types of the impurity regions 609 and 610 are not inverted.
In this way, the state of FIG.

  Thereafter, a metal film (not shown) is formed and then patterned to form source wirings and drain wirings 615 to 617. Then, a passivation film 618 is formed to obtain a bottom gate type complementary thin film transistor. (Fig. 7 (D))

  Note that, as described in Embodiment 1, the interlayer insulating film of the semiconductor device manufactured in this embodiment contains impurities (phosphorus and boron), and the concentration thereof is along the film thickness direction. The distribution has a gradient.

Example 3
In Example 1, an LDD region is formed using an anodic oxide film. In this embodiment, a method for forming an LDD region using LDD spacers formed on both sides of a gate electrode using an interlayer insulating film will be described.
Note that manufacturing steps and manufacturing conditions not particularly described are the same as those in the first embodiment.

  First, semiconductor island regions 803 and 804 are formed on a base film 802 formed on an insulating substrate 801. Thereafter, a gate insulating film 805 is formed, and gate electrodes 806 and 807 are formed. (Fig. 8 (A))

Next, phosphorous (P) light doping is performed using the gate electrodes 806 and 807 as a mask. The conditions are the same as those of the light dope of Example 1. Thus, n ⁻ -type impurity regions 808 to 811 are formed. (Fig. 8 (B))

  After that, after forming the interlayer insulating film 812 (FIG. 8C), the interlayer insulating film 812 is patterned to form a hole in the semiconductor island region 804 to be a P-channel transistor. In this embodiment, the gate insulating film is also etched. Of course, the etching may be stopped by a gate insulating film. Then, boron (B) is ion-implanted using the interlayer insulating film as a mask. This doping condition is the same as in Example 1. At this time, the impurity regions 810 and 811 are inverted in conductivity type and become p-type. In addition, a channel formation region 813 is formed. (Figure 9 (D))

  Next, an opening is formed over the semiconductor island region 803 to be an N-channel transistor. At this time, spacers 814 are formed on both sides of the gate electrode 806. Further, phosphorus (P) is implanted again using the interlayer insulating film and the spacer as a mask. The conditions at this time are the same as those of Example 1 for heavy dope.

By this step, the impurity regions 815 and 816 become regions having a higher impurity concentration than the n ⁻ -type impurity regions 817 and 818 (n ⁺ -type impurity regions). Therefore, the impurity regions 817 and 818 become LDD regions. Reference numeral 819 denotes a channel formation region. (Fig. 9 (E))

  Thereafter, in the same manner as in Example 1, source / drain wirings 820 to 822 and a passivation film 823 are formed, and a complementary transistor is formed.

Note that although an example in which a thin film transistor is formed over an insulating substrate is described in this embodiment, the transistor can be similarly formed when a transistor is formed over a semiconductor substrate.
The structural characteristics of the manufactured semiconductor device are also as described in the first embodiment. Further, the spacer contains impurities of phosphorus and boron as in the interlayer insulating film.

  As described above, it is not necessary to bother to form a film for the LDD spacer, and a contact hole is formed when the LDD spacer is formed, so that the process can be simplified. Further, a resist mask for doping is not used.

Example 4
In FIG. 5, there may be a case where sufficient insulation is not obtained only by the interlayer insulating film 116 between the source (drain) wiring 125 and the gate wiring 501. In this case, a second interlayer insulating film 1001 is formed on the interlayer insulating film 116 as shown in FIG. The present embodiment can be applied not only to the first embodiment but also to the second and third embodiments.

  As the second interlayer insulating film, a silicon oxide film, a silicon nitride film, an organic resin film, or a stacked layer thereof can be used. Further, the second interlayer insulating film does not contain impurities (phosphorus or boron) unlike the interlayer insulating film 116.

Example 5
In this embodiment, an application product using a semiconductor device using the present invention will be described. Semiconductor devices using the present invention include semiconductor integrated circuits (logic circuits such as CMOS circuits, DRAM circuits, and SRAM circuits) and peripheral circuits for driving active matrix electro-optical devices. The application products will be described below with examples.

  FIG. 12A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to a peripheral circuit of the display device 2004 and an integrated circuit incorporated in the device.

  FIG. 12B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to a peripheral circuit of the display device 2102 and an integrated circuit incorporated in the device.

  FIG. 12C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to a peripheral circuit of the display device 2205 and an integrated circuit incorporated in the device.

  FIG. 12D illustrates a head mountain display, which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to a peripheral circuit of the display device 2302 and an integrated circuit incorporated in the device.

  FIG. 12E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to a peripheral circuit of the display device 2403 and an integrated circuit incorporated in the device.

  FIG. 12F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to a peripheral circuit of the display device 2503 and an integrated circuit incorporated in the device.

  In addition to the above, the semiconductor device using the present invention can also be used for application products such as personal computers and portable information terminal devices. Thus, a semiconductor device using the present invention can be used over a wide range.

4A and 4B illustrate a manufacturing process of a complementary transistor of the present invention. 4A and 4B illustrate a manufacturing process of a complementary transistor of the present invention. 10A and 10B show a manufacturing process of a conventional complementary transistor. 10A and 10B illustrate a manufacturing process of a conventional complementary transistor. 6A and 6B illustrate a semiconductor device manufactured according to the present invention. 10A and 10B illustrate a manufacturing process of a bottom gate transistor of the present invention. 10A and 10B illustrate a manufacturing process of a bottom gate transistor of the present invention. 10A and 10B illustrate a manufacturing process of a complementary transistor using the spacer of the present invention. 10A and 10B illustrate a manufacturing process of a complementary transistor using the spacer of the present invention. The figure which shows the complementary transistor of this invention. FIG. 3 is a diagram showing a complementary transistor formed over a semiconductor substrate of the present invention. The figure which shows the application product using this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 Base film 103, 104 Semiconductor island region 105 Gate insulating film 106, 107 Gate electrode 108, 109 Porous anodic oxide film 110, 111 Dense anodic oxide film 112-115 n ⁺ impurity region 116 Interlayer insulating film 117 , 118 p impurity regions 119 and 122 the channel forming region 120, 121 n ^- impurity regions 123 to 125 the source / drain electrode and wiring 126 a passivation film

Claims (11)

  A method for manufacturing a semiconductor integrated circuit having a P-channel transistor and an N-channel transistor over an insulating substrate,
  Forming a first semiconductor island region and a second semiconductor island region on the insulating substrate;
  Forming a gate insulating film on the first semiconductor island region and the second semiconductor island region;
  Forming a first gate electrode on the first semiconductor island region and a second gate electrode on the second semiconductor island region via the gate insulating film;
  Using the first gate electrode and the second gate electrode as a mask, a first impurity having a first concentration is implanted into the first semiconductor island region and the second semiconductor island region,
  Forming an interlayer insulating film covering the gate insulating film, the first gate electrode, and the second gate electrode;
  Forming an opening such that the first gate electrode is exposed in the interlayer insulating film, removing a part of the gate insulating film to expose a part of the first semiconductor island region;
  Using the first gate electrode and the interlayer insulating film as a mask, a second impurity is implanted into a part of the first semiconductor island region,
  An opening is formed in the interlayer insulating film so that a part of the second gate electrode is exposed, a spacer is formed on a side surface of the second gate electrode, and another part of the gate insulating film To expose a portion of the second semiconductor island region,
  Using the first gate electrode, the second gate electrode, the interlayer insulating film, and the spacer as a mask, a part of the first semiconductor island region and one of the second semiconductor island regions Implanting a first impurity having a second concentration higher than the first concentration into the portion;
  Covering the interlayer insulating film, forming a metal film electrically connected to a part of the first semiconductor island region and a part of the second semiconductor island region,
  A method for manufacturing a semiconductor integrated circuit, comprising patterning the metal film to form a source wiring and a drain wiring.   A method for manufacturing a semiconductor integrated circuit having a P-channel transistor and an N-channel transistor on a semiconductor substrate,
  Forming a gate insulating film on the semiconductor substrate;
  Forming a first gate electrode and a second gate electrode on the gate insulating film;
  Using the first gate electrode and the second gate electrode as a mask, a first impurity having a first concentration is implanted into the semiconductor substrate;
  Forming an interlayer insulating film covering the gate insulating film, the first gate electrode, and the second gate electrode;
  An opening is formed in the interlayer insulating film to expose the first gate electrode, and a part of the gate insulating film is removed to implant the first impurity in the first semiconductor substrate. Exposing the area,
  Using the first gate electrode and the interlayer insulating film as a mask, a second impurity is implanted into the first region of the semiconductor substrate,
  An opening is formed in the interlayer insulating film so that a part of the second gate electrode is exposed, a spacer is formed on a side surface of the second gate electrode, and another part of the gate insulating film To expose the second region of the semiconductor substrate implanted with the first impurity,
  Using the first gate electrode, the second gate electrode, the interlayer insulating film, and the spacer as a mask, the first region of the semiconductor substrate and the second region of the semiconductor substrate are formed in the first region. Implanting a first impurity having a second concentration greater than the concentration of 1;
  Covering the interlayer insulating film, forming a metal film electrically connected to the first region of the semiconductor substrate and the second region of the semiconductor substrate;
  A method for manufacturing a semiconductor integrated circuit, comprising patterning the metal film to form a source wiring and a drain wiring.   In claim 1 or claim 2,
  A method for manufacturing a semiconductor integrated circuit, wherein the interlayer insulating film is formed to have a thickness of 0.3 μm or more.   In any one of Claims 1 thru | or 3,
  The interlayer insulating film is a silicon nitride film, a silicon oxide film, a laminate of a silicon nitride film and a silicon oxide film, an organic resin film, a laminate of a silicon nitride film and an organic resin film, or a laminate of a silicon oxide film and an organic resin film. A method for manufacturing a semiconductor integrated circuit, which is formed by any of the methods.   A method for manufacturing a semiconductor integrated circuit having a P-channel transistor and an N-channel transistor over an insulating substrate,
  Forming a first semiconductor island region and a second semiconductor island region on the insulating substrate;
  Forming a gate insulating film on the first semiconductor island region and the second semiconductor island region;
  Forming a first gate electrode on the first semiconductor island region and a second gate electrode on the second semiconductor island region via the gate insulating film;
  Using the first gate electrode and the second gate electrode as a mask, a first impurity having a first concentration is implanted into the first semiconductor island region and the second semiconductor island region,
  Forming a first interlayer insulating film covering the gate insulating film, the first gate electrode, and the second gate electrode;
  An opening is formed in the first interlayer insulating film to expose the first gate electrode, and a part of the gate insulating film is removed to expose a part of the first semiconductor island region. ,
  Using the first gate electrode and the first interlayer insulating film as a mask, a second impurity is implanted into a part of the first semiconductor island region,
  An opening is formed in the first interlayer insulating film so that a part of the second gate electrode is exposed, a spacer is formed on a side surface of the second gate electrode, and the gate insulating film And removing a part of the second semiconductor island region to expose a part thereof,
  Using the first gate electrode, the second gate electrode, the first interlayer insulating film, and the spacer as a mask, a part of the first semiconductor island region and the second semiconductor island Injecting a first impurity having a second concentration higher than the first concentration into a part of the region;
  Forming a second interlayer insulating film covering the first gate electrode, the second gate electrode, the first interlayer insulating film, and the spacer;
  Forming a contact hole in the second interlayer insulating film such that a part of the first semiconductor island region and a part of the second semiconductor island region are exposed;
  Covering the second interlayer insulating film, forming a metal film electrically connected to a part of the first semiconductor island region and a part of the second semiconductor island region through the contact hole;
  A method for manufacturing a semiconductor integrated circuit, comprising patterning the metal film to form a source wiring and a drain wiring.   A method for manufacturing a semiconductor integrated circuit having a P-channel transistor and an N-channel transistor on a semiconductor substrate,
  Forming a gate insulating film on the semiconductor substrate;
  Forming a first gate electrode and a second gate electrode on the gate insulating film;
  Using the first gate electrode and the second gate electrode as a mask, a first impurity having a first concentration is implanted into the semiconductor substrate;
  Forming a first interlayer insulating film covering the gate insulating film, the first gate electrode, and the second gate electrode;
  An opening is formed in the first interlayer insulating film to expose the first gate electrode, and a part of the gate insulating film is removed to implant the first impurity in the semiconductor substrate. Exposing the first region;
  Using the first gate electrode and the first interlayer insulating film as a mask, a second impurity is implanted into the first region of the semiconductor substrate,
  An opening is formed in the first interlayer insulating film so that a part of the second gate electrode is exposed, a spacer is formed on a side surface of the second gate electrode, and the gate insulating film A second region of the semiconductor substrate into which the first impurity is implanted is removed by removing a part of the first impurity,
  Using the first gate electrode, the second gate electrode, the first interlayer insulating film, and the spacer as a mask, the first region of the semiconductor substrate and the second region of the semiconductor substrate And implanting a first impurity having a second concentration higher than the first concentration,
  Forming a second interlayer insulating film covering the gate insulating film, the first gate electrode, the second gate electrode, the first interlayer insulating film, and the spacer;
  Forming a contact hole in the second interlayer insulating film so as to expose the first region of the semiconductor substrate and the second region of the semiconductor substrate;
  Covering the second interlayer insulating film, forming a metal film electrically connected to the first region of the semiconductor substrate and the second region of the semiconductor substrate through the contact hole;
  A method for manufacturing a semiconductor integrated circuit, comprising patterning the metal film to form a source wiring and a drain wiring.   In claim 5 or claim 6,
  A method of manufacturing a semiconductor integrated circuit, wherein the first interlayer insulating film is formed to have a thickness of 0.3 μm or more.   In any one of Claim 5 thru | or Claim 7,
  The first interlayer insulating film is a silicon nitride film, a silicon oxide film, a stack of a silicon nitride film and a silicon oxide film, an organic resin film, a stack of a silicon nitride film and an organic resin film, or a silicon oxide film and an organic resin film. A method for manufacturing a semiconductor integrated circuit, comprising:   In any one of Claim 5 thru | or Claim 8,
  A method for manufacturing a semiconductor integrated circuit, wherein the second interlayer insulating film is formed of any one of a silicon oxide film, a silicon nitride film, an organic resin film, or a laminate thereof.   In any one of Claims 1 thru | or 9,
  The method for manufacturing a semiconductor integrated circuit, wherein the first impurity is phosphorus.   In any one of Claims 1 to 10,
  The method for manufacturing a semiconductor integrated circuit, wherein the second impurity is boron.

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