JP4245761B2 - Pulse superposition type high voltage generator for electrostatic application equipment and electrostatic application equipment - Google Patents

Pulse superposition type high voltage generator for electrostatic application equipment and electrostatic application equipment Download PDF

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Publication number
JP4245761B2
JP4245761B2 JP35714199A JP35714199A JP4245761B2 JP 4245761 B2 JP4245761 B2 JP 4245761B2 JP 35714199 A JP35714199 A JP 35714199A JP 35714199 A JP35714199 A JP 35714199A JP 4245761 B2 JP4245761 B2 JP 4245761B2
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high voltage
voltage
pulse
electrostatic application
switch circuit
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JP35714199A
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JP2001170522A (en
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清美 渡辺
修 武田
高稔 奥田
健 桑原
亮太 酒徳
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Trinity Industrial Corp
Origin Electric Co Ltd
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Trinity Industrial Corp
Origin Electric Co Ltd
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Description

【0001】
【産業上の利用分野】
この発明は、静電塗装機、空気清浄器、静電分級装置のような電流の小さな静電応用機器の荷電電極に通常の直流電圧に高電圧パルスを重畳したパルス重畳型高電圧を供給する高電圧発生装置に関する。
【0002】
【従来の技術】
静電塗装は静電気力で塗料をワークに吸着させて塗装するものであり、塗着効率が比較的高いという利点を有しているが、近年では、環境保護などの観点から従来にも増して電力エネルギー量、塗料などの使用量の低減、未着塗料の処理費用の削減などを達成することが求められてきており、さらなる塗着効率のアップが緊急課題となっている。
【0003】
この方策として、本件出願人の一方は特願平11−279141号の特許出願において、通常のほぼ一定レベルの直流高電圧(ここではベース電圧と言う)に高電圧パルスを重畳したパルス重畳型高電圧を静電塗装装置の荷電電極に荷電する方法を提案している。かかるパルス重畳型高電圧の場合には、パルス電圧ピーク値を従来のほぼ一定レベルの荷電電圧よりも高くすることができるので帯電効率を向上させることができ、しかもパルス電圧の幅を200マイクロ秒以下に制限すればスパークに移行しない利点がある。なお、特に静電塗装でスパークが発生すると塗装作業が中断し、また塗料への引火の危険性があるので、スパークを起こしてはならないとされている。
【0004】
【発明が解決しようとする課題】
したがって、本発明は塗装又は捕集効率のアップを可能にし、かつスパークの発生を抑制できる急峻な立ち上がりと立ち下がりをもつパルス重畳型高電圧の発生を、低価格かつシンプルの回路構成で実現できるパルス重畳型高電圧発生装置を提供することを課題とする。
【0005】
【課題を解決するための手段】
【0006】
この発明の請求項1は前記課題を解決するため、複数のコンデンサと複数のダイオードとを縦属接続してなる多段縦属型倍電圧整流回路の最終段と中間段との間に第1と第2の高電圧スイッチ回路を直列に接続すると共に、それらの接続点を抵抗を介して静電応用機器の荷電電極に接続される高電圧出力端子に接続し、前記第1と第2の高電圧スイッチ回路を交互に動作させることにより、中間段に接続された第2の高電圧スイッチ回路がオンのとき中間段の電圧に相当するベース電圧を前記高電圧出力端子から出力し、最終段に接続された前記第1の高電圧スイッチ回路がオンのとき前記最終段と中間段の電圧の差に相当するパルス電圧を前記ベース電圧に重畳したパルス重畳型高電圧を前記高電圧出力端子に出力する静電応用機器用パルス重畳型高電圧発生装置において、前記高電圧スイッチ回路は複数のFET又はIGBTを直列接続した回路であり、これら高電圧スイッチの制御電圧は縦続接続された複数の絶縁トランスを通して供給され、かつこれら複数の絶縁トランスの電位の各々を前記多段縦属型倍電圧整流回路の中間段電位に段階的に固定する静電応用機器用パルス重畳型高電圧発生装置を提供する。
【0007】
この発明の請求項2は前記課題を解決するため、請求項において、前記第1の高電圧スイッチ回路のオン期間は前記第2の高電圧スイッチ回路のオン期間よりも短くなるように設定されている静電応用機器用パルス重畳型高電圧発生装置を提案するものである。
【0008】
この発明の請求項3は前記課題を解決するため、請求項1又は請求項2において、パルス信号発生器を高電圧側に配置し、このパルス信号発生器を前記縦続接続された前記複数の絶縁トランスを通して供給される前記制御電圧で動作させる静電応用機器用パルス重畳型高電圧発生装置を提案するものである。
【0009】
この発明の請求項4は前記課題を解決するため、請求項1ないし請求項3のいずれかの静電応用機器用パルス重畳型高電圧発生装置の前記高電圧出力端子に接続された荷電電極を有することを特徴とする静電応用機器を提案するものである。
【0012】
【発明の実施の形態及び実施例】
この発明の基本的考え方は、交互に高速でスイッチング動作を行う一対の高電圧スイッチ回路を多段縦続型倍電圧整流回路の最終段と中間段に接続し、その最終段に接続した高電圧スイッチ回路のオンで高電圧パルスを発生させ、次に前記中間段に接続した高電圧スイッチ回路をオンさせることにより、静電応用機器と接地された物体との間に形成される浮遊キャパシタンスの充電電荷を放電させて、前記高電圧パルスに相当する電圧から通常の荷電電圧に対応するほぼ一定レベルの直流高電圧(ここではベース電圧と言う)まで急激に低下させ、次のサイクルまではそのベース電圧を保持することにより、急峻な立ち上がりと立ち下がりをもつパルス幅の狭い高電圧パルスを周期的に重畳したパルス重畳型高電圧を静電応用機器の荷電電極に供給することができるので、静電塗装機などの静電応用機器の荷電電極と接地されたワークとの間でスパークを発生させることなく、粒子の帯電率を高め、塗着又は捕集効率を向上させるものである。
【0013】
図1は本発明の一実施例を示す。1はコンデンサとダイオードとからなる回路を複数縦続接続してなる負極性出力のコッククロフト・ウオルトン(以下、CWという)回路又はシュンケル回路のような通常の多段縦続型倍電圧整流回路である。2は多段縦続型倍電圧整流回路1を駆動する高周波高圧トランスであり、その2次高電圧巻線3は巻終わりが多段縦続型倍電圧整流回路1の入力に接続され、巻始めが接地される。その1次巻線4は高周波インバータ5の出力に接続される。多段縦続型倍電圧整流回路1の最終段7の第1出力点X、中間段6の内の第2出力点Yと共通出力点Zとの間に第1と第2の高電圧スイッチ回路8、9が直列接続される。
【0014】
後で詳述するが、第1の高電圧スイッチ回路8の場合にはそのカソードKが第1出力点Xに接続され、そのアノードAは共通出力点Zに接続されるが、第2の高電圧スイッチ回路9の場合にはそのアノードAが第2出力点Yに接続され、そのカソードKは共通出力点Zに接続される。高電圧スイッチ回路8、9は共通出力点Z、放電防止抵抗10を通して静電塗装機の荷電電極11に接続される。荷電電極11に対する他方の電極として作用する被塗装物体であるワーク11’は接地される。光パルス発生回路12は光ファイバー13、14を通して高電圧スイッチ回路8、9をオン、オフ駆動する光駆動信号A、Bを送信する。光駆動信号A、Bは高電圧スイッチ回路8、9を所定のパルス幅、周波数で交互にオンさせ、同時にはオンさせない。
【0015】
次に動作説明に入る前に、数マイクロ秒以下の短時間で立ち上がり、立ち下がる高速スイッチング動作可能な高電圧スイッチ回路8、9の具体的な構成の一例について図2により説明する。この例では高電圧スイッチ回路8、9はほぼ同一構成であり、FETスイッチを高電圧に耐え得る必要個数だけ直列接続すると共に、制御電源を使用しないでFETを駆動できる従属点弧回路構成になっている。この回路によれば、高速動作はもちろんのこと高電圧側にあるFETスイッチの制御が低コストで実現できる。
【0016】
N個のFET21A〜21NがアノードAとカソードK間に直列接続される。各FETのゲート・ソース極間には保護用ゼナーダイオード22A−22Nがそれぞれ接続される。FET21A〜21Nの内の隣り合うゲート間は電圧バランス抵抗23A−23Mにより互いに接続され、また最もアノードA側に位置する最終段のFET21Nのゲート・ドレイン間に電圧バランス抵抗23Nが接続される。さらに、最もカソードK側に位置する初段のFET21Aのゲート・ソース極間にはホトトランジスタ24のコレクタ・ エミッタ極が接続される。なお、各FET21A〜21Nは鎖線で示す極性のボデイダイオードをそれぞれ有することは知られている。
【0017】
これら高電圧スイッチ回路8、9は一般的に知られている従属点弧回路であるのであまり詳細に説明しないが、光ファイバ13又は14を通して光駆動信号A又はBを受けると、ホトトランジスタ24がオンし、FET21Aのゲート・ソース極間を短絡するので、FET21Aはオフし、追随して他のFET21B−21Nもオフする。次に光駆動信号A又はBが消失すると、ホトトランジスタ24はオフし、各FET21A〜21Nのアノード・ カソード間には電圧が印加されているので、FET21Aのゲート極は抵抗23A〜23Nを通してアノード電圧で順バイアスされ、高速でオンする。他のFET21B−21Nも追随して高速でオンする。
【0018】
再び、図1に戻って動作を説明する。図3はこの実施例における光駆動信号a,bの波形と共通出力点Zの出力電圧の波形Qを示す。多段縦続型倍電圧整流回路1の中間段6の第2出力点Yは、例えばベース電圧−90kVを発生する。最終段7の第1出力点Xは重畳するパルス電圧に必要な電圧、例えばベース電圧に−30kVを加えた−120kVを発生する。光駆動信号Aが低レベル、光駆動信号Bが高レベルのとき、第1の高電圧スイッチ回路8が高速でオン、第2の高電圧スイッチ回路9がオフである。これに伴い、静電塗装機の荷電電極11には第1の高電圧スイッチ回路8、共通出力点Z、抵抗10を通してベース電圧である−90kVに−30kVを加えた−120kVにほぼ等しい直流高電圧が加えられる。
【0019】
次にほぼ100マイクロ秒後に光駆動信号A,Bが反転し、光駆動信号Aが高レベル、光駆動信号Bが低レベルになると、第1の高電圧スイッチ回路8が高速でオフ、第2の高電圧スイッチ回路9が高速でオンする。ここで、図1に鎖線で示したように静電塗装機の荷電電極11と接地されたワーク11’との間にはストレイキャパシタンスCが存在し、ストレイキャパシタンスCは第1の高電圧スイッチ回路8がオフする寸前ではほぼ−120kVに充電されているが、第2の高電圧スイッチ回路9がオンするのに伴いストレイキャパシタンスCの充電電荷は第2の高電圧スイッチ回路9を通して瞬時に放電され、荷電電極11の電圧は数マイクロ秒以下の短時間でベース電圧である−90kVまで低下する。つまり、第2の高電圧スイッチ回路9は静電塗装機の荷電電極11と接地間のストレイキャパシタンスCの電荷を放電する作用を行い、−90kVまで放電させた後に光駆動信号Bを高レベルにして第2の高電圧スイッチ回路9をオフさせても良い。
【0020】
この理由は、前述のように第2の高電圧スイッチ回路9のアノードAを第2の出力点Yに接続し、そのカソードKを共通出力点Zに接続しているので、図2に示す高電圧スイッチ回路9の各FET21A−21Nが有する各ボデイダイオード(鎖線で示す)が導通するので、共通出力点Zを第2の出力点Yの電圧である−90kVに維持するからである。勿論、図3の光駆動信号aの鎖線で示すように、第1の高電圧スイッチ回路8がオンする寸前まで、第2の高電圧スイッチ回路9をオンさせておいても良い。
【0021】
したがって、第1の高電圧スイッチ回路8がオン、第2の高電圧スイッチ回路9がオフの状態を所定のパルス幅t、例えば100マイクロ秒で周期的に、例えば1kHzで繰り返すことにより、ベース電圧−90kVに数マイクロ秒以下の短い立ち上がりと立ち下がりをもつ小さいパルス幅、例えば100μsの−30kVのパルス電圧を1kHzで重畳した形のパルス重畳型高電圧Qを荷電電極11に加えることができる。
【0022】
この実施例ではベース電圧とそれに重畳されるパルス電圧の時間幅の割合は9;1であり、ピーク電圧を−120kVと高くして短いパルス電圧期間で粒子の帯電を向上させているが、その次の長いベース電圧期間で−90kVと電圧を下げているので、荷電効率が向上するにもかかわらずスパークは発生し難い。このように、荷電効率が向上するにもかかわらずスパークを発生させないためには、各周期において重畳されるパルス電圧の時間幅に比べてベース電圧の時間幅を長くする必要がある。この時間幅の比率は、パルス電圧の印加によって静電塗装機の荷電電極11と被塗装物体であるワーク11’間のイオン量が増大し、ベース電圧印加期間でイオン量がスパークの発生し難いレベルまで減少する値に選定される。なお、前記時間幅の比率は一定にする必要はなく、荷電電極11とワーク11’間の導電度の変化に応じて制御しても良い。
【0023】
図4は本発明の第2の実施例を示す。この例では、高電圧側に制御電源40を設けた。図1、図2と同一の参照記号は相当する部材を示す。制御電源電圧供給用の絶縁トランス41A〜41Dそれぞれの1次巻線、2次巻線は順次縦続接続される。最下段に位置する初段のトランス41Aの1 次巻線は制御電源用インバータ42に接続され、ほぼ接地電位にある。制御電源用インバータ42の出力高周波電圧は絶縁トランス41A〜41Dを介して高電圧側に伝達される。ここで初段のトランス41Aの2次巻線と2段目のトランス41Bの1次巻線は多段縦続型倍電圧整流回路1の2段目、例えば−30kVの点1aに接続される。
【0024】
同様に2段目のトランス41Bの2次巻線と3段目のトランス41Cの1次巻線は、多段縦続型倍電圧整流回路1の4段目の−60kVの点1bに接続される。4段目のトランス41Dの1次巻線と3段目のトランス41Cの2次巻線は、多段縦続型倍電圧整流回路1の6段目の−90kVの点1cに接続される。このように各絶縁トランス41A〜41Dそれぞれの1次、2次巻線は、多段縦続型倍電圧整流回路1の中間段に接地側から順次接続され、それらの電位は多段縦続型倍電圧整流回路1の段階的に上昇する各2段毎の安定な電圧に固定されている。
【0025】
この結果、各トランスは2段分の耐圧、例では−30kVの耐圧に均等分担される。もちろん、1個で−120kV耐圧の絶縁トランスを使用することも可能である。しかしながら、このような、低耐圧のトランスは、−120kV耐圧のトランス1個よりも信頼性が高く、小型化しやすい。なお、トランス41Dだけが整流回路45、46を通して荷電電極11の電位となり、−30kVのパルス電圧で変動する。整流回路45で整流された5〜15V程度の低い電圧VLが光パルス受光回路47の制御電源電圧となる。
【0026】
光パルス発生回路12からの光駆動信号A、Bは光パルス受光回路47で光−電気変換されて電気パルス駆動信号となり、その電気パルス駆動信号は第1の高電圧スイッチ回路8に供給されると共に、反転回路48により反転されてFETのような半導体スイッチ49に供給される。ここで50,51は高電圧スイッチ回路8、9の切り替わり時の同時オン期間が発生した場合の短絡電流制限抵抗である。
【0027】
この実施例では、第1の高電圧スイッチ回路8は図2に示したような従属点孤構成のものであるが、第2の高電圧スイッチ回路9は従属点孤回路ではなく、それぞれ1次巻線と2次巻線を有するパルストランス52A,52B・・・・・52Nを通して駆動されるパルストランス駆動方式とした。第1の高電圧スイッチ回路8の直列接続された各FET21A〜21Nのゲート・ ソースはパルストランス52A〜52Nの2次巻線に接続される。ゲート・ ソース間の抵抗53A〜53Nはパルス整形用である。各FETのドレイン・ ソース間の抵抗54A〜54Nは電圧バランス用である。
【0028】
パルストランス52A〜52Nの各1次巻線は直列接続されており、前述のようにして反転回路48からの反転されたパルス駆動信号により半導体スイッチ49がオンするとき、多段縦続型倍電圧整流回路1の最終段の電圧Vxと電圧Vhとの差の電圧が印加される。これに伴い、パルストランス52A〜52Nには駆動電圧が誘起され、瞬時にFET21A−21Nがターンオンし、第2の高電圧スイッチ回路9はオンする。第2の高電圧スイッチ回路9のオン期間は、反転回路48の反転作用により第1の高電圧スイッチ回路8のオフの期間となる。
【0029】
この実施例では、制御電源40を高電圧側に備えたので、高電圧側のFETの駆動回路の設計自由度が増し、より高速のスイッチングが可能となり、重畳パルスの幅を容易にマイクロ秒オーダーの狭いパルス幅にできる。
【0030】
図5に示す第3の実施例は図4の実施例に似ているが、FETのような半導体スイッチ49に電気駆動パルス電圧を与える制御パルス発生器52を高電圧側に置いたものである。すなわち、実際の静電気応用装置で最適なパルス幅、周波数が決定され、それらを変化させる必要がない場合には、接地側からのパルス信号を伝達する必要が無いので、光ファイバが不要となり、構造上のメリットが大きい。また、パルス重畳型高電圧を使用せずに、従来の一定の直流高電圧を使用する場合には、制御電源用のインバータ42を停止すれば、高電圧側制御電源電圧が消失することにより半導体スイッチ49が高速でオフし、高電圧スイッチ回路8は高速でオフし、同時に高電圧スイッチ回路9は高速でオンするから、高電圧出力端子OTにはベース電圧のみが現出する。
【0031】
ここで、制御パルス発生器52が高レベル信号を発生するとき、高電圧スイッチ回路8がオンし、同時にその高レベル信号は反転回路48で低レベル信号に変換され、半導体スイッチ49を高速でオフにする。したがって、高電圧スイッチ回路9はオフである。次に、制御パルス発生器52が低レベル信号を発生すると、高電圧スイッチ回路8がオフし、反転回路48で反転された高レベル信号は半導体スイッチ49をオンさせ、パルストランス53の1次巻線L1と2次巻線L2を介して高電圧スイッチ回路9をオンさせる。他の部分は図4と同一であるので、説明を省略する。
【0032】
なお、以上述べた実施例では静電塗装装置の場合について説明したが、この発明にかかるパルス重畳型高電圧発生装置は比較的電流容量の小さな他の静電応用機器、例えば空気清浄器、静電分級機、静電植毛装置などにも同様に適用できる。
【0033】
【発明の効果】
以上述べたように、本発明によれば多段縦続型倍電圧整流回路の最終段、中間段と高電圧出力端子間に高電圧スイッチ回路をそれぞれ直列に接続し、交互に重ならないように高速でオン動作させてパルス重畳型高電圧を発生させているので、回路構成が比較的簡単であるのもかかわらず、パルス重畳型高電圧の立ち上がりと立ち下がりに要する時間が非常に短く、したがってパルス幅の狭い高電圧パルスを容易に得ることができ、粒子の帯電効率を向上させることが可能である。
【図面の簡単な説明】
【図1】 本発明に係るパルス重畳型高電圧発生装置の第一の実施例を示す図である。
【図2】 本発明装置に用いる高電圧スイッチ回路の一例を示す図である。
【図3】 図1に示す装置の動作を説明するための波形を示す図である。
【図4】 本発明に係る第2の実施例を示す図である。
【図5】 本発明に係る第3の実施例を示す図である。
【符号の説明】
1・・多段縦続型倍電圧整流回路 2・・高周波高圧トランス
5・・高周波インバータ5 8・・第1の高電圧スイッチ回路
9・・第2の高電圧スイッチ回路 10・・放電防止抵抗
11・・荷電電極 11’・・他方の電極又は負荷
12・・光パルス発生回路 13、14・・光ファイバ
21A−21N・・FET
22A−22N・・ゼナーダイオード
23A−23M・・電圧バランス抵抗17
40・・制御電源
41A−41D・・縦続接続された絶縁トランス
42・・制御電源用インバータ
45、46・・整流回路 47・・光パルス受光回路
48・・反転回路 49・・反転回路
50、51・・短絡電流制限抵抗 52・・制御パルス発生器
53・・パルストランス
[0001]
[Industrial application fields]
The present invention supplies a pulse superposition type high voltage in which a high voltage pulse is superimposed on a normal DC voltage to a charging electrode of an electrostatic application device with a small current such as an electrostatic coating machine, an air cleaner, or an electrostatic classifier. The present invention relates to a high voltage generator.
[0002]
[Prior art]
Electrostatic coating is applied by adsorbing paint to a workpiece with electrostatic force, and has the advantage of relatively high coating efficiency. However, in recent years, it has increased from the viewpoint of environmental protection. It has been demanded to reduce the amount of power energy, the amount of paint used, and the processing cost of unattached paint, and further improvement in coating efficiency is an urgent issue.
[0003]
As one of the measures, one of the applicants in the patent application of Japanese Patent Application No. 11-279141 is a pulse superposition type high voltage in which a high voltage pulse is superimposed on a normal DC high voltage (herein referred to as a base voltage) at a substantially constant level. A method of charging a voltage to a charging electrode of an electrostatic coating apparatus has been proposed. In the case of such a pulse superposition type high voltage, the pulse voltage peak value can be made higher than the conventional charge voltage at a substantially constant level, so that the charging efficiency can be improved, and the width of the pulse voltage is 200 microseconds. There is an advantage that it does not shift to a spark if it restricts to the following. In particular, if a spark is generated by electrostatic coating, the coating operation is interrupted and there is a risk of ignition of the paint, so it is said that no spark should occur.
[0004]
[Problems to be solved by the invention]
Therefore, the present invention can increase the painting or collection efficiency, and can realize the generation of a pulse superimposed high voltage having a steep rise and fall that can suppress the occurrence of spark with a low cost and simple circuit configuration. It is an object of the present invention to provide a pulse superposition type high voltage generator.
[0005]
[Means for Solving the Problems]
[0006]
According to a first aspect of the present invention, in order to solve the above-described problem, the first and the second stages of a multi-stage vertical voltage doubler rectifier circuit in which a plurality of capacitors and a plurality of diodes are cascade-connected are provided The second high voltage switch circuit is connected in series, and the connection point thereof is connected to a high voltage output terminal connected to the charging electrode of the electrostatic application device through a resistor, and the first and second high voltage switch circuits are connected. By alternately operating the voltage switch circuit, when the second high voltage switch circuit connected to the intermediate stage is on, a base voltage corresponding to the voltage of the intermediate stage is output from the high voltage output terminal, and the final stage When the connected first high voltage switch circuit is on, a pulse superposition type high voltage in which a pulse voltage corresponding to the difference between the voltage of the final stage and the intermediate stage is superimposed on the base voltage is output to the high voltage output terminal Pal for electrostatic application equipment In the superposition type high voltage generator, the high voltage switch circuit, which are connected in series a plurality of FET or IGBT, the control voltages of the high voltage switch is supplied through a plurality of isolation transformers in cascade, and the plurality There is provided a pulse superposition type high voltage generator for electrostatic application equipment, in which each of the potentials of the isolation transformers is fixed in stages to the intermediate stage potential of the multistage vertical voltage doubler rectifier circuit.
[0007]
For a second aspect of the present invention is to solve the above problems, according to claim 1, wherein the first ON period of the high voltage switch circuit is set to be shorter than the on period of the second high voltage switch circuit It proposes a pulse superposition type high voltage generator for electrostatic application equipment.
[0008]
According to a third aspect of the present invention, in order to solve the above-mentioned problem, in the first or second aspect , the pulse signal generator is arranged on the high voltage side, and the pulse signal generator is connected to the plurality of insulations connected in cascade. The present invention proposes a pulse superposition type high voltage generator for electrostatic application equipment that operates with the control voltage supplied through a transformer.
[0009]
According to a fourth aspect of the present invention, in order to solve the above problem, a charged electrode connected to the high voltage output terminal of the pulse superposition type high voltage generator for electrostatic application apparatus according to any one of the first to third aspects is provided. The present invention proposes an electrostatic application device characterized by having the above.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The basic idea of the present invention is that a pair of high voltage switch circuits that alternately perform switching operations at high speed are connected to the final stage and the intermediate stage of a multistage cascaded voltage doubler rectifier circuit, and the high voltage switch circuit connected to the final stage The high-voltage pulse is generated by turning on, and then the high-voltage switch circuit connected to the intermediate stage is turned on to thereby charge the floating capacitance formed between the electrostatic application device and the grounded object. Discharge and suddenly drop from a voltage corresponding to the high voltage pulse to a DC constant high voltage (herein referred to as a base voltage) corresponding to a normal charging voltage, and the base voltage is reduced until the next cycle. By holding a pulse superimposed high voltage that periodically superimposes a high voltage pulse with a narrow pulse width with sharp rising and falling edges, the charging electrode of electrostatic application equipment Since it can be supplied, the charging rate of particles is increased and the coating or collection efficiency is improved without generating a spark between the charged electrode of an electrostatic application device such as an electrostatic coating machine and a grounded workpiece. It is to improve.
[0013]
FIG. 1 shows an embodiment of the present invention. Reference numeral 1 denotes an ordinary multi-stage cascaded voltage doubler rectifier circuit such as a Cockcroft-Walton (hereinafter referred to as CW) circuit or a Shunkel circuit having a negative output formed by cascading a plurality of capacitors and diodes. Reference numeral 2 denotes a high-frequency, high-voltage transformer that drives the multistage cascaded voltage doubler rectifier circuit 1, and the secondary high voltage winding 3 is connected to the input of the multistage cascaded voltage doubler rectifier circuit 1, and the winding start is grounded. The The primary winding 4 is connected to the output of the high frequency inverter 5. The first and second high voltage switch circuits 8 between the first output point X of the final stage 7 and the second output point Y of the intermediate stage 6 and the common output point Z of the multistage cascaded voltage doubler rectifier circuit 1. , 9 are connected in series.
[0014]
As will be described in detail later, in the case of the first high-voltage switch circuit 8, its cathode K is connected to the first output point X and its anode A is connected to the common output point Z. In the case of the voltage switch circuit 9, its anode A is connected to the second output point Y, and its cathode K is connected to the common output point Z. The high voltage switch circuits 8 and 9 are connected to the charging electrode 11 of the electrostatic coating machine through the common output point Z and the discharge prevention resistor 10. A workpiece 11 ′, which is an object to be coated that acts as the other electrode for the charged electrode 11, is grounded. The optical pulse generation circuit 12 transmits optical drive signals A and B for driving the high voltage switch circuits 8 and 9 on and off through the optical fibers 13 and 14. The optical drive signals A and B turn on the high voltage switch circuits 8 and 9 alternately with a predetermined pulse width and frequency, but not simultaneously.
[0015]
Next, before describing the operation, an example of a specific configuration of the high-voltage switch circuits 8 and 9 capable of high-speed switching operation that rises and falls in a short time of several microseconds or less will be described with reference to FIG. In this example, the high-voltage switch circuits 8 and 9 have almost the same configuration, and a dependent firing circuit configuration is possible in which the necessary number of FET switches are connected in series and the FET can be driven without using a control power supply. ing. According to this circuit, not only high speed operation but also control of the FET switch on the high voltage side can be realized at low cost.
[0016]
N FETs 21 </ b> A to 21 </ b> N are connected in series between the anode A and the cathode K. Protective Zener diodes 22A-22N are connected between the gate and source electrodes of each FET. Adjacent gates of the FETs 21A to 21N are connected to each other by a voltage balance resistor 23A-23M, and a voltage balance resistor 23N is connected between the gate and drain of the final stage FET 21N located closest to the anode A. Further, the collector and emitter electrodes of the phototransistor 24 are connected between the gate and source electrodes of the first stage FET 21A located closest to the cathode K. It is known that each of the FETs 21A to 21N has a body diode having a polarity indicated by a chain line.
[0017]
These high voltage switch circuits 8 and 9 are generally known dependent firing circuits and will not be described in detail. However, when the optical drive signal A or B is received through the optical fiber 13 or 14, the phototransistor 24 is turned on. Since it is turned on and the gate-source electrode of the FET 21A is short-circuited, the FET 21A is turned off, and the other FETs 21B-21N are also turned off. Next, when the optical drive signal A or B disappears, the phototransistor 24 is turned off, and a voltage is applied between the anode and cathode of each of the FETs 21A to 21N, so that the gate electrode of the FET 21A has an anode voltage through the resistors 23A to 23N. Forward-biased and turns on at high speed. The other FETs 21B-21N also follow and turn on at high speed.
[0018]
Returning to FIG. 1 again, the operation will be described. FIG. 3 shows the waveforms Q of the optical drive signals a and b and the output voltage Q at the common output point Z in this embodiment. The second output point Y of the intermediate stage 6 of the multistage cascaded voltage doubler rectifier circuit 1 generates, for example, a base voltage of −90 kV. The first output point X of the final stage 7 generates a voltage necessary for the superimposed pulse voltage, for example, −120 kV obtained by adding −30 kV to the base voltage. When the optical drive signal A is at a low level and the optical drive signal B is at a high level, the first high voltage switch circuit 8 is turned on at high speed, and the second high voltage switch circuit 9 is turned off. Accordingly, the charging electrode 11 of the electrostatic coating machine has a DC high voltage substantially equal to −120 kV obtained by adding −30 kV to the base voltage −90 kV through the first high-voltage switch circuit 8, the common output point Z, and the resistor 10. A voltage is applied.
[0019]
Next, after about 100 microseconds, when the optical drive signals A and B are inverted and the optical drive signal A becomes high level and the optical drive signal B becomes low level, the first high voltage switch circuit 8 is turned off at high speed, The high voltage switch circuit 9 is turned on at high speed. Here, as indicated by a chain line in FIG. 1, there is a stray capacitance C between the charged electrode 11 of the electrostatic coating machine and the grounded work 11 ′, and the stray capacitance C is the first high-voltage switch circuit. Immediately before 8 is turned off, it is charged to approximately −120 kV, but as the second high voltage switch circuit 9 is turned on, the charge of the stray capacitance C is instantaneously discharged through the second high voltage switch circuit 9. The voltage of the charging electrode 11 drops to the base voltage of −90 kV in a short time of several microseconds or less. That is, the second high-voltage switch circuit 9 performs the action of discharging the charge of the stray capacitance C between the charging electrode 11 of the electrostatic coating machine and the ground. After discharging to -90 kV, the optical drive signal B is set to the high level. The second high voltage switch circuit 9 may be turned off.
[0020]
This is because the anode A of the second high-voltage switch circuit 9 is connected to the second output point Y and the cathode K is connected to the common output point Z as described above. This is because each body diode (indicated by a chain line) included in each FET 21A-21N of the voltage switch circuit 9 becomes conductive, so that the common output point Z is maintained at -90 kV that is the voltage of the second output point Y. Needless to say, the second high voltage switch circuit 9 may be turned on just before the first high voltage switch circuit 8 is turned on, as indicated by the chain line of the optical drive signal a in FIG.
[0021]
Accordingly, by repeating the state in which the first high voltage switch circuit 8 is on and the second high voltage switch circuit 9 is off at a predetermined pulse width t, for example, 100 microseconds, for example, at 1 kHz, the base voltage A small pulse width having a short rise and fall of a few microseconds or less at −90 kV, for example, a pulse superposition type high voltage Q in which a pulse voltage of −30 kV of 100 μs is superposed at 1 kHz can be applied to the charging electrode 11.
[0022]
In this embodiment, the ratio of the time width of the base voltage and the superimposed pulse voltage is 9: 1, and the peak voltage is increased to -120 kV to improve the charging of particles in a short pulse voltage period. Since the voltage is lowered to −90 kV in the next long base voltage period, it is difficult for sparks to occur even though the charging efficiency is improved. Thus, in order not to generate a spark despite the improvement in charging efficiency, it is necessary to make the time width of the base voltage longer than the time width of the pulse voltage superimposed in each cycle. This time width ratio is such that, by applying a pulse voltage, the amount of ions between the charged electrode 11 of the electrostatic coating machine and the workpiece 11 ′, which is the object to be coated, increases, and the amount of ions hardly generates a spark during the base voltage application period. A value that decreases to the level is selected. Note that the ratio of the time widths does not need to be constant, and may be controlled according to a change in conductivity between the charging electrode 11 and the workpiece 11 ′.
[0023]
FIG. 4 shows a second embodiment of the present invention. In this example, the control power supply 40 is provided on the high voltage side. The same reference symbols as those in FIGS. 1 and 2 indicate the corresponding members. The primary windings and secondary windings of the insulating transformers 41A to 41D for supplying the control power supply voltage are connected in cascade. The primary winding of the first-stage transformer 41A located at the lowest stage is connected to the control power source inverter 42 and is substantially at the ground potential. The output high-frequency voltage of the control power inverter 42 is transmitted to the high voltage side via the isolation transformers 41A to 41D. Here, the secondary winding of the first-stage transformer 41A and the primary winding of the second-stage transformer 41B are connected to the second stage of the multi-stage cascaded voltage doubler rectifier circuit 1, for example, the point 1a of −30 kV.
[0024]
Similarly, the secondary winding of the second-stage transformer 41B and the primary winding of the third-stage transformer 41C are connected to the fourth stage −60 kV point 1b of the multi-stage cascaded voltage doubler rectifier circuit 1. The primary winding of the fourth-stage transformer 41D and the secondary winding of the third-stage transformer 41C are connected to the sixth stage −90 kV point 1c of the multi-stage cascaded voltage doubler rectifier circuit 1. In this way, the primary and secondary windings of each of the isolation transformers 41A to 41D are sequentially connected from the ground side to the intermediate stage of the multistage cascaded voltage doubler rectifier circuit 1, and their potentials are multistage cascaded voltage doubler rectifier circuits. It is fixed to a stable voltage for every two stages that rise in steps of one.
[0025]
As a result, each transformer is equally shared with a withstand voltage of two stages, for example, with a withstand voltage of −30 kV. Of course, it is also possible to use a single isolation transformer having a withstand voltage of -120 kV. However, such a low withstand voltage transformer is more reliable than one transformer with a withstand voltage of −120 kV and is easy to miniaturize. Only the transformer 41D becomes the potential of the charged electrode 11 through the rectifier circuits 45 and 46, and fluctuates with a pulse voltage of −30 kV. A low voltage VL of about 5 to 15 V rectified by the rectifier circuit 45 becomes the control power supply voltage of the optical pulse light receiving circuit 47.
[0026]
The optical drive signals A and B from the optical pulse generation circuit 12 are photoelectrically converted by the optical pulse light receiving circuit 47 to become an electrical pulse drive signal, and the electrical pulse drive signal is supplied to the first high voltage switch circuit 8. At the same time, the signal is inverted by the inverting circuit 48 and supplied to the semiconductor switch 49 such as an FET. Here, 50 and 51 are short-circuit current limiting resistors when a simultaneous ON period occurs when the high-voltage switch circuits 8 and 9 are switched.
[0027]
In this embodiment, the first high-voltage switch circuit 8 has a dependent point arc configuration as shown in FIG. 2, but the second high-voltage switch circuit 9 is not a dependent point arc circuit, and each has a primary order. A pulse transformer drive system is used which is driven through pulse transformers 52A, 52B,... 52N having windings and secondary windings. The gates and sources of the FETs 21A to 21N connected in series of the first high voltage switch circuit 8 are connected to the secondary windings of the pulse transformers 52A to 52N. The gate-source resistors 53A to 53N are for pulse shaping. Resistances 54A to 54N between the drain and source of each FET are for voltage balancing.
[0028]
The primary windings of the pulse transformers 52A to 52N are connected in series, and when the semiconductor switch 49 is turned on by the inverted pulse drive signal from the inverting circuit 48 as described above, the multistage cascaded voltage doubler rectifier circuit The voltage of the difference between the final stage voltage Vx and the voltage Vh is applied. Accordingly, a drive voltage is induced in the pulse transformers 52A to 52N, the FET 21A-21N is turned on instantaneously, and the second high voltage switch circuit 9 is turned on. The on period of the second high voltage switch circuit 9 is an off period of the first high voltage switch circuit 8 due to the inversion action of the inversion circuit 48.
[0029]
In this embodiment, since the control power supply 40 is provided on the high voltage side, the degree of freedom in designing the drive circuit for the high voltage side FET is increased, enabling faster switching, and the width of the superimposed pulse is easily on the order of microseconds. Narrow pulse width.
[0030]
The third embodiment shown in FIG. 5 is similar to the embodiment of FIG. 4 except that a control pulse generator 52 for supplying an electric drive pulse voltage to a semiconductor switch 49 such as an FET is placed on the high voltage side. . That is, when the optimum pulse width and frequency are determined by an actual electrostatic application device and there is no need to change them, there is no need to transmit a pulse signal from the ground side, so no optical fiber is required, and the structure The above merit is great. Further, when the conventional constant DC high voltage is used without using the pulse superposition type high voltage, if the control power supply inverter 42 is stopped, the high-voltage side control power supply voltage disappears and the semiconductor Since the switch 49 is turned off at high speed, the high voltage switch circuit 8 is turned off at high speed, and the high voltage switch circuit 9 is turned on at high speed at the same time, only the base voltage appears at the high voltage output terminal OT.
[0031]
Here, when the control pulse generator 52 generates a high level signal, the high voltage switch circuit 8 is turned on. At the same time, the high level signal is converted into a low level signal by the inverting circuit 48 and the semiconductor switch 49 is turned off at high speed. To. Therefore, the high voltage switch circuit 9 is off. Next, when the control pulse generator 52 generates a low level signal, the high voltage switch circuit 8 is turned off, and the high level signal inverted by the inverting circuit 48 turns on the semiconductor switch 49, and the primary winding of the pulse transformer 53 is turned on. The high voltage switch circuit 9 is turned on via the line L1 and the secondary winding L2. The other parts are the same as those in FIG.
[0032]
In the embodiment described above, the case of the electrostatic coating apparatus has been described. However, the pulse superposition type high voltage generator according to the present invention can be applied to other electrostatic application equipment having a relatively small current capacity, such as an air cleaner, a static cleaner. It can be similarly applied to an electric classifier and an electrostatic flocking device.
[0033]
【The invention's effect】
As described above, according to the present invention, the high-voltage switch circuit is connected in series between the final stage, the intermediate stage and the high-voltage output terminal of the multi-stage cascaded voltage doubler rectifier circuit, so that they do not overlap each other at high speed. Since the pulse superposition type high voltage is generated by the ON operation, the time required for the rise and fall of the pulse superposition type high voltage is very short, so the pulse width Narrow high voltage pulses can be easily obtained, and the charging efficiency of the particles can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a pulse superposition type high voltage generator according to the present invention.
FIG. 2 is a diagram showing an example of a high voltage switch circuit used in the device of the present invention.
FIG. 3 is a diagram showing waveforms for explaining the operation of the apparatus shown in FIG. 1;
FIG. 4 is a diagram showing a second embodiment according to the present invention.
FIG. 5 is a diagram showing a third embodiment according to the present invention.
[Explanation of symbols]
1. ・ Multi-stage cascaded voltage doubler rectifier circuit 2. ・ High frequency high voltage transformer 5 ・ ・ High frequency inverter 5 8. ・ First high voltage switch circuit 9 ・ ・ Second high voltage switch circuit 10 ・ ・ Discharge prevention resistor 11 ・・ Charged electrode 11 ′ ・ ・ Other electrode or load 12 ・ ・ Optical pulse generation circuit 13, 14 ・ ・ Optical fiber 21A-21N ・ ・ FET
22A-22N ... Zener diode 23A-23M ... Voltage balance resistor 17
40 .. Control power supply 41A-41D .. Cascaded insulation transformer 42 .. Control power supply inverters 45, 46..Rectifier circuit 47..Optical pulse light receiving circuit 48..Invert circuit 49..Invert circuit 50, 51.・ ・ Short-circuit current limiting resistor 52 ・ ・ Control pulse generator 53 ・ ・ Pulse transformer

Claims (4)

複数のコンデンサと複数のダイオードとを縦属接続してなる多段縦属型倍電圧整流回路の最終段と中間段との間に第1と第2の高電圧スイッチ回路を直列に接続すると共に、それらの接続点を抵抗を介して静電応用機器の荷電電極に接続される高電圧出力端子に接続し、前記第1と第2の高電圧スイッチ回路を交互に動作させることにより、中間段に接続された第2の高電圧スイッチ回路がオンのとき中間段の電圧に相当するベース電圧を前記高電圧出力端子から出力し、最終段に接続された前記第1の高電圧スイッチ回路がオンのとき前記最終段と中間段の電圧の差に相当するパルス電圧を前記ベース電圧に重畳したパルス重畳型高電圧を前記高電圧出力端子に出力する静電応用機器用パルス重畳型高電圧発生装置において、
前記高電圧スイッチ回路は複数のFET又はIGBTを直列接続した回路であり、これら高電圧スイッチの制御電圧は縦続接続された複数の絶縁トランスを通して供給され、かつこれら複数の絶縁トランスの電位の各々を前記多段縦属型倍電圧整流回路の中間段電位に段階的に固定することを特徴とする静電応用機器用パルス重畳型高電圧発生装置。
The first and second high-voltage switch circuits are connected in series between the final stage and the intermediate stage of the multistage longitudinal voltage doubler rectifier circuit formed by cascade-connecting a plurality of capacitors and a plurality of diodes, By connecting these connection points to a high voltage output terminal connected to a charging electrode of an electrostatic application device through a resistor, and operating the first and second high voltage switch circuits alternately, When the connected second high voltage switch circuit is on, a base voltage corresponding to the voltage of the intermediate stage is output from the high voltage output terminal, and the first high voltage switch circuit connected to the final stage is on. in the pulse superposition type electrostatic application pulse superposition type high voltage generator equipment for a high voltage output to the high voltage output terminal of the pulse voltage is superimposed on the base voltage corresponding to a difference between the voltage of the final stage and the intermediate stage when ,
The high voltage switch circuit is a circuit in which a plurality of FETs or IGBTs are connected in series, and the control voltage of these high voltage switches is supplied through a plurality of cascaded isolation transformers, and each of the potentials of the plurality of isolation transformers is supplied. A pulse superposition type high voltage generator for electrostatic application equipment, wherein the multistage longitudinal voltage doubler rectifier circuit is fixed stepwise to an intermediate stage potential.
請求項において、
前記第1の高電圧スイッチ回路のオン期間は前記第2の高電圧スイッチ回路のオン期間よりも短くなるように設定されていることを特徴とする静電応用機器用パルス重畳型高電圧発生装置。
In claim 1 ,
The pulse superposition type high voltage generator for electrostatic applied equipment, wherein the on period of the first high voltage switch circuit is set shorter than the on period of the second high voltage switch circuit .
請求項1又は請求項2において、
パルス信号発生器を高電圧側に配置し、このパルス信号発生器を前記縦続接続された前記複数の絶縁トランスを通して供給される前記制御電圧で動作させることを特徴とする静電応用機器用パルス重畳型高電圧発生装置。
In claim 1 or claim 2 ,
A pulse signal generator for electrostatic application equipment, wherein a pulse signal generator is disposed on a high voltage side and the pulse signal generator is operated with the control voltage supplied through the plurality of cascaded insulating transformers. Type high voltage generator.
請求項1ないし請求項3のいずれかの静電応用機器用パルス重畳型高電圧発生装置の前記高電圧出力端子に接続された荷電電極を有することを特徴とする静電応用機器。An electrostatic application device comprising a charged electrode connected to the high voltage output terminal of the pulse superposition type high voltage generator for electrostatic application device according to any one of claims 1 to 3 .
JP35714199A 1999-12-16 1999-12-16 Pulse superposition type high voltage generator for electrostatic application equipment and electrostatic application equipment Expired - Fee Related JP4245761B2 (en)

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