JP4241700B2 - Detection circuit - Google Patents

Description

  The present invention relates to a receiver circuit for RF communication using AM modulation, such as a radio frequency receiver of a radio timepiece (hereinafter referred to as an RF receiver).

  Circuit diagrams showing specific examples of a conventional variable gain amplifier for auto gain control (hereinafter referred to as AGC) are shown in FIGS. FIG. 7 is a circuit diagram showing an example of the basic configuration of the RF receiver of a conventional radio timepiece.

  In the variable gain amplifier of FIG. 4, the differential amplifier 1 is configured such that the transistors T1 and T2 form a first differential pair, and the sink current of the first differential pair flows to the drain of the transistor T5, and the source is the source. A differential amplifier having a configuration in which a transistor T3 that connects the resistor RS1 and a transistor T4 that connects the source resistor RS2 to the source constitute a second differential pair, and the sink current of the second differential pair flows to the drain of the transistor T6 The positive inputs (gates of the transistors T1 and T3) and the negative inputs (gates of the transistors T2 and T4) are connected to each other so that the inputs and outputs of the differential amplifier 1 and the differential amplifier 2 are connected in parallel (2). Differential amplifier 1 and differential amplifier 2 have the same differential input), and positive phase current outputs (drains of transistors T1 and T3) and negative phase current outputs. (The drains of the transistors T2 and T4) are connected to each other (the differential output currents of the differential amplifier 1 and the differential amplifier 2 are added), and the added positive phase is added to the load resistor RL1 having one end connected to the power supply VDD. An output current is passed to convert it to a negative phase output voltage Vo−, and the added negative phase output current is supplied to a load resistor RL2 having one end connected to the power supply VDD to convert it to a positive phase output voltage Vo +.

  The sources of the sink current transistor T5 of the differential amplifier 1 and the sink current transistor T6 of the differential amplifier 2 are connected to each other, and further connected to a constant current circuit Is that is a sink current circuit. Is configured.

  In the above configuration, Is × M (M is 0 to 1) which is a part of the constant current Is of the constant current circuit Is flows to the transistor T5, and Is (1-M) which is the remaining part of the constant current Is. Flows to transistor T6. This distribution ratio M is arbitrarily changed by a gain control differential voltage Vgc applied between the inputs of the third differential amplifier (between the gates of the transistors T5 and T6).

  Further, in the above configuration, the transfer conductance Gm1 of the differential amplifier 1 is determined by the suction current flowing through the first differential pair, and the transfer conductance Gm2 of the differential amplifier 2 is determined by the suction current flowing through the second differential pair. And the source resistances Rs1 and Rs2, and the gain from the differential input (difference between Vi + and Vi−) to the differential output (difference between Vo + and Vo−) is the combined conductance Gm = (Gm1 + Gm2) It is determined by the load resistances RL1 and RL2.

The currents flowing through the transistors T5 and T6 are I1 and I2, the transfer conductances of the transistors T1 and T2 determined by the current I1 are Gm (I1), and the transfer conductances of the transistors T3 and T4 determined by the current I2 are Gm (I2) and Then
Is = I1 + I2 (I1 = Is * M, I2 = Is (1-M), 0 <M <1)
Gm1 = Gm (I1) / 2
Gm2 = 1 / (Rs1 + Rs2 + (2 / Gm (I2)))
The relationship is established. Therefore, by controlling the current distribution ratio M and appropriately changing the transfer conductances Gm1 and Gm2, the maximum gain is obtained when the constant current Is flows to the differential amplifier 1 (M≈1), and When the constant current Is flows to the differential amplifier 2 (M≈0), the gain can be minimized, that is, the current distribution ratio M flowing to the differential amplifier 1 and the differential amplifier 2 by the gain control differential voltage Vgc. By controlling this, a variable gain amplifier that can obtain an arbitrary gain between the maximum gain and the minimum gain can be obtained.

  The variable gain amplifier circuit of FIG. 5 has transistors T1 to T4 and load resistors RL1 to RL2 that are the same transistors and load resistors RL1 to RL2 as the circuit of FIG. 4, and Rs of FIG. 5 is the sum of Rs1 and Rs2 of FIG. By setting the value (Rs = RS1 + Rs2) and making the size of the sum of T6a and T6b in FIG. 5 the same as T6 in FIG. 4 (T6a size = T6b size, T6 size = T6a size + T6b size), the circuit of FIG. Equivalent operation.

  In the variable gain amplifier circuit of FIG. 6, the sink current flowing through the first differential pair constituted by the transistors T1 and T2 to which the differential input voltages Vi + and Vi− are input, and the differential input voltages Vi + and Vi−. DC bias VB (an equivalent circuit example is shown in FIG. 24. The resistor R or the resistor R or the distribution of the suction current flowing through the second differential pair constituted by the transistors T3 and T4 to which no current is input is connected to the differential input. By changing the potential difference between the gain control voltage Vgc and the transfer conductance Gm1 of the first differential pair related to amplification, the differential input (one of the choke coils L may be omitted) This is a variable gain amplifier that changes the gain from the difference between Vi + and Vi-) to the differential output (difference between Vo + and Vo-). Transistors T3 and T4 The second differential pair is configured, it acts to maintain a constant without changing the output Vo + and Vo- DC bias.

  The DC bias VB may be included in the differential input voltages Vi + and Vi−.

  Although FIGS. 4 to 6 show examples of MOS type transistors, junction field effect type or bipolar type transistors can also be used.

  In Japan, the Communications Research Laboratory transmits a standard radio wave that is a frequency standard at 40 KHz from a transmitting station in Fukushima Prefecture and 60 KHz from a transmitting station in Saga Prefecture day and night.

This standard radio wave is superimposed with time information (Japan Standard Time) based on an AM modulation signal. By receiving this standard radio wave and decoding and decoding the time code, the delay time from radio wave transmission to arrival (several mass) The degree of accuracy can be obtained.
If the timepiece has a function of correcting the time using this, it is possible to realize a timepiece in which the time accuracy is always maintained. This is a so-called radio clock.

  An image of a standard radio wave is shown in FIG. The standard Japanese radio wave is an AM-modulated signal that has the above-mentioned transmission frequency as a carrier and has only two amplitude states with a small amplitude of 0.1 (modulation degree: 90%) with respect to a large amplitude of 1. The communication speed is 1 bit / sec Yes, in the 1-bit length (the large amplitude state is 200 msec and the remaining 800 msec is the small amplitude state) → the sign “M” (mark signal) is expressed, and the large amplitude state is 800 msec and the remaining 200 msec is the small amplitude state) → represents a code “0” (a large amplitude state is 500 msec and the remaining 500 msec is a small amplitude state) → a code “1” is represented. A time code is configured by combining these three values.

  The time code starts with an "M" code, separates minutes, hours, day of the year from the first day, year, day of the week, etc. with "M" and ends with an "M" code. This is a code string as a unit. Therefore, by detecting the position where the “M” code is continuous (the end of the previous code string and the beginning of the next code string), the time code break and the start position can be identified.

  In the radio clock RF receiver circuit of FIG. 7, a bias circuit VB (equivalent circuit example shown in FIG. 24) that tunes the bar antenna L and the tuning capacitor C to the standard radio wave, selectively receives the standard radio wave and inputs it to the preamplifier PA. ) Supplies an input bias to the preamplifier PA.

  The variable gain amplifier GCA uses the output of the preamplifier PA as an input Vi and amplifies it with a gain according to the control from the gain control terminal.

  The band pass filter BPF removes a low-frequency component and a high-frequency component that are noise components outside the necessary band output from the variable gain amplifier GCA.

  A peak detection circuit PDet composed of the first rectifier circuit Rec1, the first peak holding capacitor C1, and the first discharge resistor R1 detects the peak value of the output Vo of the bandpass filter BPF, and calculates the peak value voltage Vp. Output.

  The gain control amplifier DA applies a DC voltage to the gain control terminal of the variable gain amplifier GCA to lower the gain of the variable gain amplifier GCA when the output Vp of the peak detection circuit PDet is higher than the first reference voltage VR1. When the output voltage is small, a DC voltage that increases the gain is output. Thereby, the potential difference between the output Vp of the peak detection circuit PDet and the first reference voltage VR1 is substantially zero (negative feedback control). As a result, the large amplitude side of the bandpass filter BPF output amplitude Vo becomes a substantially constant level.

  The low pass filter LPF inserted and connected to the output of the gain control amplifier DA has a time constant so that the gain control to the variable gain amplifier GCA does not become unstable.

  The envelope detection circuit SDet formed of the second rectifier circuit Rec2, the second peak holding capacitor C2, and the second discharge resistor R2 becomes a peak value envelope of the RF amplitude value of the bandpass filter BPF output Vo. Such a voltage is output (broken line waveform in FIG. 30).

  The comparator Comp compares the output of the envelope detection circuit SDet with the second reference voltage VR2 (set to an intermediate value between the high and low voltages of the envelope detection output), and outputs the output of the envelope detection circuit SDet. Is higher than the second reference voltage VR2, the logic signal “H” is output, and when it is lower, the logic signal “L” is output.

  By identifying the time length of the logic signal “H” or the logic signal “L” with a microcomputer (not shown), it is possible to determine whether the time code string is “M” / “0” / “1”. Identify. This microcomputer recognizes the current time by decoding the received time code, corrects the time, and displays it (radio clock function).

  Since it is sufficient to set the time several times a day, a power supply circuit Reg for controlling the power supply from the external power supply VDD to each of the circuits using the control signal PON (power on / off, constant voltage supply, etc.) is provided, which is useless. It tries to eliminate power consumption.

  In FIG. 7, the band pass filter BPF may be omitted when the output noise of the variable gain amplifier GCA is small. Further, a termination condition of the bandpass filter BPF is satisfied between the bandpass filter BPF and the first rectifier circuit Rec1 and the second rectifier circuit Rec2, and the first rectifier circuit Rec1 and the second rectifier circuit are satisfied. An appropriate buffer circuit that can drive Rec2 is placed. Furthermore, when the gain control amplifier DA includes appropriate low-pass filter characteristics, the low-pass filter LPF may be omitted.

  Since the radio timepiece is required to have an AGC that can handle a wide range of input of approximately 1 uVrms to 100 mVrms, the reception preamplifier PA is also part of the variable gain amplifier (FIG. 7, control indicated by a broken line to the reception preamplifier PA). There is also.

  In the following description, a circuit corresponding to a portion including the variable gain amplifier GCA, the gain control amplifier DA, and the low-pass filter LPF in FIG. 7 may be referred to as a variable gain amplifier block GCAb. A circuit corresponding to a portion to which the pass filter BPF is added may be referred to as a gain control amplifier unit GCA-B. Further, a circuit corresponding to a portion including the gain control amplifier unit GCA-B and the peak detection circuit PDet may be referred to as an auto gain control circuit AGC or an AGC circuit.

  In addition, there are the following documents as examples of a variable gain amplifier that improves the linearity of the output characteristics of the variable gain amplifier, an AM modulation signal reception circuit, and a detection circuit.

Japanese Patent Laid-Open No. 11-225028 Japanese Patent Laid-Open No. 10-209904 JP-A-6-252649

  Since the standard radio wave received by the radio-controlled timepiece is an AM modulation method, the auto gain control circuit AGC is required to have linearity for amplification. In addition, since the number of standard radio wave transmission stations is small, it is necessary to enable reception from directly below the transmission antenna to a very long distance, and a wide AGC range is required. Therefore, it is desired to realize a variable gain amplifier that always ensures linearity and has a wide variable gain range.

  4 and 5 has a minimum gain determined by transfer conductances Gm (Is) and Rs1 and Rs2 (or combined Rs) of the transistors T1 to T4, and the transfer conductances Gm of the transistors T1 to T4. If (Is) cannot be made sufficiently larger than the reciprocal of the source resistance Rs, the variable gain range becomes narrow. In addition, since the differential pair of transistors T1 to T4 and the differential pair of transistors T5 to T6 are connected in series between the power supplies, the minimum operating power supply voltage cannot be reduced, so battery driving (1.5 V power supply) It is not suitable for low power supply voltage operation. It is desired to realize a variable gain amplifier that has a wide variable gain range and can reduce the minimum operating voltage.

  The variable gain amplifier circuit of FIG. 6 is suitable for low power supply voltage operation because there is one differential pair between the power supplies, but increases the gain control voltage Vgc to increase the input voltage and decrease the gain by AGC operation. As the current of the differential pair (transistors T1 and T2) related to the gain decreases (thus lowering the gain), the output dynamic range and the linear input range become smaller, so a large input voltage (low gain) As the operation enters the range, the AGC operation shifts to the limit amplifier operation, and the linearity deteriorates.

  Even in the large input voltage (low gain operation) region, the output dynamic range is maintained, and as the input voltage increases, the linear input range is expanded, and it is desired to realize a variable gain amplifier that can always maintain linearity.

  In the case of a wall clock type radio-controlled timepiece, the direction of the clock changes depending on the installation location, and the direction of the bar antenna of the receiving unit also changes. The antenna reception gain changes depending on the direction of the bar antenna, and a single antenna such as the radio clock receiver shown in FIG. It is desired to realize a bar antenna installation method and reception method that can ensure a certain level of reception level even when the direction of the radio clock changes.

  When the reception preamplifier PA is a differential input amplifier, if the bias circuit VB is connected to both or one of the differential inputs, the noise component generated by each of the bias circuits VB is also differentially amplified. As a result, the S / N ratio (signal-to-noise ratio) of the receiving unit deteriorates. It is desired to realize a reception preamplifier with good minimum reception sensitivity characteristics by suppressing the influence of noise generated by the bias circuit VB and improving the S / N ratio of the reception unit.

  The standard radio wave is an AM modulation system, and is very slow at 1 second for 1-bit information transmission. Therefore, an AGC system is required in which a large and small amplitude level ratio is correctly maintained for a long time. For this reason, it is necessary to increase the holding time constant of the peak detection circuit PDet or the time constant of the low-pass filter LPF. If this time constant is increased, a large time constant capacity is required, the time from the start of reception until the AGC becomes stable becomes longer, and the AGC tracking speed when the reception level fluctuates decreases. Become.

  An increase in time constant capacity can be suppressed, a large and small amplitude level ratio can be maintained correctly for a long time, and the time from the start of reception until the AGC becomes stable is short, and the tracking speed when the reception level fluctuates is fast. Realization of an AGC circuit capable of obtaining an operation is desired.

  In AM modulation wave peak value envelope detection using a rectifier, the detection waveform has a fast rise and a slow fall as shown by the broken line waveform in FIG. 30, and the pulse width accuracy for discriminating the time code is deteriorated. The reception time accuracy decreases. Therefore, it is desired to realize a detection circuit capable of obtaining an output accurately corresponding to the peak value envelope.

  An object of the present invention is to provide an AM modulation signal detection circuit capable of obtaining an output accurately corresponding to a peak value envelope.

  In order to solve the above-described problem, the AM modulation signal detection circuit of the present invention receives the two states of the AM modulation signal Vi of the large amplitude state and the small amplitude state and receives the two states when identifying the two states. A carrier frequency component is extracted from the output signal Vo of the AGC circuit for controlling and amplifying the AM modulation signal to a predetermined amplitude value corresponding to two states of the large amplitude state and the small amplitude state, and the peak of the amplitude of the output signal Vo of the AGC circuit is obtained. A timing extraction unit that outputs a clock pulse CL that is timed to a position, a clock generation unit that receives the clock pulse CL and outputs a sampling clock pulse SCL that is timed to a peak position, and a reference that outputs a reference voltage VR2 When the voltage setting unit and the sampling clock pulse SCL are input, the output Vo of the AGC circuit and the reference voltage VR2 are sampled and compared. It outputs the output signal TCO, and a sampling comparator holding portion for holding up the next sampling clock pulse SCL is input.

  According to the AM modulation signal detection circuit of the present invention, in the AM modulation signal receiving circuit that receives the AM modulation signal Vi in the two states of the large amplitude state and the small amplitude state and identifies the two states, A carrier frequency component is extracted from the output signal Vo of the AGC circuit that is controlled and amplified to a predetermined amplitude value corresponding to two states of the large amplitude state and the small amplitude state, and the timing is set at the peak position of the amplitude of the output signal Vo of the AGC circuit. A timing extraction unit that outputs a clock pulse CL that is combined, a clock generation unit that inputs the clock pulse CL and outputs a sampling clock pulse SCL that is synchronized with the peak position, and a reference voltage that outputs a reference voltage VR2 A setting unit; when the sampling clock pulse SCL is input, the output Vo of the AGC circuit and the reference voltage VR2 Since the sampling comparison holding unit that outputs the output signal TCO by sampling comparison and holds it until the next sampling clock pulse SCL is input, the rising characteristic and falling characteristic of the detection waveform are aligned, and the amplitude Can respond immediately to changes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
[Constitution]
1 to 3 are diagrams showing specific examples of the variable gain amplifier circuit according to the first embodiment of the present invention.

  In the variable gain amplifier circuit of FIG. 1, the gates of transistors T1 and T2 forming a differential pair are connected to inputs Vi + and Vi− (bias VB), and a sink current circuit Is is connected to the sources of the transistors T1 and T2. And the source of each of the differential pair transistors T1 and T2 of a differential amplifier configured by connecting load resistors RL1 and RL2 whose one ends are connected to the power supply VDD to the respective drains of the transistors T1 and T2. And the sink current circuit Is, the drains and sources of the transistors T3 and T4 are inserted and connected, and the gain control voltage Vgc is connected to the gates of the transistors T3 and T4.

  The gate shapes of the transistors T1 and T2 and the transistors T3 and T4 are set so that the MOS transistors T1 and T2 operate in a saturation region, and the MOS transistors T3 and T4 operate in a linear region (a short channel MOS that is difficult to be saturated is desirable). It is set.

[Operation]
Since the MOS transistors T1 and T2 in FIG. 1 operate in the saturation region and the MOS transistors T3 and T4 operate in the linear region, the gate shapes of the transistors T1 and T2 and the transistors T3 and T4 are set. T1 and T2 operate as active amplifying elements of the differential amplifier, and the MOS transistors T3 and T4 operate as negative feedback resistors connected to the sources of the MOS transistors T1 and T2 (inside the broken line in FIG. 1).

The transfer conductance Gm1 and the gate-source voltage VGS1 of the MOS transistors T1 and T2 are determined by their shape and the bias current (1/2 of the suction current Is) flowing through them, and the source potential of the transistors is It is obtained by subtracting the gate-source voltage VGS1 from the gate bias voltage VB, and becomes a fixed voltage Vs1. That is,
Vs1 = VB−VGS1
It is.

On the other hand, the MOS transistors T3 and T4 operate as a linear region, that is, operate as variable resistance elements Rs3 and Rs4 (usually RS3 = Rs4) by setting the gate size so that the potential difference between the drain and the source becomes almost zero. The resistance value Rs3 is determined by its shape and the voltage VGS3 applied between its gate and source. The gate-source voltage VGS3 is a value obtained by subtracting the fixed voltage Vs1 from the gain control voltage Vgc. That is,
VGS3 = Vgc-Vs1 = Vgc- (VB-VGS1) = Vgc-VB + VGS1
It is. Accordingly, the gate-source voltage VGS3 of the transistors T3 and T4 can be changed by changing the gain control voltage Vgc (or the gate bias voltage VB). As a result, the resistances Rs3 and Rs4 of the transistors T3 and T4 are changed. Can be changed.

As described above, the transfer conductance Gm and the differential voltage gain A of the differential circuit including the transistors T1 to T4 are
Gm = 1 / (Rs3 + Rs4 + 2 / Gm1)
A = Gm × (RL1 + RL2) = (RL1 + RL2) / (Rs3 + Rs4 + 2 / Gm1)
Thus, the transfer conductance Gm and the differential voltage gain A can be changed by changing the gain control voltage Vgc (or the gate bias voltage VB), and the differential circuit operates as a variable gain amplifier.

  The variable gain amplifier circuit of FIG. 2 basically has a configuration in which the sink current circuit Is of the circuit of FIG. 1 is divided into two (current value ½) and connected to the respective sources of the transistors T1 and T2. Operates in the same manner as in FIG. In the circuit of FIG. 2, since a bias current does not flow through the transistors T3 and T4, a ± both voltage region can be used as a linear operation region between the source and the drain of the transistor. Good linearity.

  In the variable gain amplifier circuit of FIGS. 1 and 2, when the gate-source voltage VGS3 of the transistors T3 and T4 approaches zero, the resistors Rs3 and Rs4 increase without limit, and the differential voltage gain A becomes extremely zero. As shown in FIG. 3, when a fixed resistor Rs is connected in parallel to the variable resistor formed by the transistors T3 and T4, the combined resistance of the resistor and the transistors T3 and T4 is fixed. Since it does not become smaller than the resistance value Rs, the variable gain amplifier of this configuration has a minimum gain.

  The same effect can be obtained by connecting a fixed resistor Rs between the sources of the transistors T1 and T2 in FIG.

  In a configuration in which variable gain amplifiers are connected in multiple stages so that the total gain and variable gain width can be increased, when the input level of the variable gain amplifier is increased from the minimum level, the gain of each stage is lower than that of lowering the gain uniformly. If the gain is decreased in order from the side, the gain of the first-stage amplifier having a large influence on the noise characteristics can be secured if the gain is decreased, and the signal / noise ratio is improved. For such a configuration, a variable gain amplifier having a minimum gain as shown in FIG. 3 is required.

  The transistors T3 and T4 have been described as operating as variable resistors. However, in an actual MOS transistor, there are capacitance components between the gate and the source and between the gate and the drain, and these capacitances are combined (series connected capacitance). Are connected in parallel to the variable resistor. High frequency peaking occurs with the frequency determined by the capacity and the time constant of the variable resistor as a pole.

  If the gate resistors RG1 and RG2 are connected to the gates of the transistors T3 and T4 as in the variable gain amplifier circuit of FIG. 3, the peaking effect of the combined capacitance between the gate and the source and between the gate and the drain can be reduced.

  The transistors T3 and T4 of the variable gain amplifier circuit of FIGS. 2 and 3 may be replaced with one transistor if the combined values are the same, or conversely, a plurality of three or more may be connected in series or It is good also as a parallel connection. Appropriate selection and setting are made in consideration of the peaking effect of the combined capacitance between the gate and source and between the gate and drain.

  The variable gain amplifier circuit examples of FIGS. 1 to 3 are configured with N-MOS elements, but are configured with P-MOS, mixed P-MOS and N-MOS, and configurations using junction field effect elements. It is also good. The transistors T1 and T2 may be bipolar transistors. Regarding the transistors T3 and T4, an N-MOS element and a P-MOS element may be combined. In addition, when the short channel type is used, the minimum resistance value can be lowered and the saturation characteristic can be weakened or eliminated, so that the area that can be used as a variable resistor is widened.

As described above, according to the first embodiment, the following effects can be obtained.
(1) Since the differential circuit is not stacked between the power supply and the ground, the minimum operating power supply voltage is lowered. (Comparison with the configuration of FIGS. 4 and 5)
(2) Since the total sink current (Is) is always supplied to the differential pair transistors (T1 and T2) that perform the amplifier operation, the output dynamic range is constant and does not decrease even when the gain is reduced. (Comparison with the configuration of FIG. 6)
(3) As the gain is lowered, the input linear input range becomes wider. (Comparison with the configuration of FIG. 6)
(4) If the output dynamic range is determined by the sink current Is and the load resistances RL1 and RL2, the linearity (or uniformity of the magnitude relationship) between the input and output is maintained. (Comparison with the configuration of FIG. 6)
(5) Both a configuration in which the minimum gain is infinitely small and a configuration having a fixed minimum gain can be realized.

[Second Embodiment]
[Constitution]
FIGS. 8A to 8D are diagrams showing specific examples of the AM modulation signal receiving circuit in the second embodiment of the present invention.

The AM modulation signal receiving circuit of FIG. 8A lowers the gain when the input voltage Vp from the peak value input terminal is larger than the built-in reference value, and increases the gain when the input voltage Vp is smaller than the built-in reference value. The gain control amplifier unit GCA-B that amplifies Vi and outputs the output signal Vo, the envelope detection circuit SDet that detects the output signal Vo of the gain control amplifier unit GCA-B, and the envelope detection circuit SDet A comparison circuit Comp that compares the output with the reference voltage VR2 and outputs an output signal TCO, and an output signal in which the output signal of the comparison circuit Comp corresponds to a large amplitude input state with the output signal TCO of the comparison circuit Comp as a control input At this time, the peak value of the output signal Vo of the gain control amplifier unit GCA-B is detected, and the detected peak value Vp is obtained. When the output signal TCO of the comparison circuit Comp changes to an output signal corresponding to the small amplitude input state, the detected peak value Vp immediately before the change is held, The hold detection peak value Vp is constituted by a peak detection circuit PDet for outputting to the peak value input terminal of the gain control amplifier unit GCA-B.

  The aforementioned input AM modulation signal Vi is generated by the bar antenna L, the tuning capacitor C, the preamplifier PA, and the like illustrated in FIG. The configurations of the gain control amplifier unit GCA-B and the envelope detection circuit SDet are the same as those in FIG.

The peak detection circuit PDet in FIG. 8A includes a rectifier circuit Rec1 that rectifies the output signal of the gain control amplifier unit GCA-B, and a discharge path resistor connected between the output of the rectifier circuit Rec1 and the ground (or power supply). One end of the conduction terminal is connected to the output of R1 (or the constant current circuit I1) and the output of the rectifier circuit Rec1, the output signal TCO of the comparison circuit Comp is used as a control input, and the output signal TCO of the comparison circuit Comp is input with a large amplitude A transfer gate TG1 which becomes conductive when the output corresponding to the state changes and becomes non-conductive when the output signal TCO of the comparison circuit Comp changes to an output corresponding to the small amplitude input state, and a conduction terminal of the transfer gate TG1 One end is connected to the peak value input terminal of the end and the gain control amplifier unit GCA-B, and the other end is connected to the ground ( There is more composed and peak holding capacitor C1 connected to the power supply).
FIG. 8B shows that the discharge path resistor R1 in FIG. 8A can be replaced with a discharge path constant current circuit I1.

[Operation]
The AM modulation signal Vi received by the AM modulation signal receiving circuit of FIG. 8A has only two states of a large amplitude state and a small amplitude state in the steady reception state, and when receiving the large amplitude state, The output signal TCO of the comparison circuit Comp is set to the “H” state (or “L” state), and when the small amplitude state is received, the output signal TCO of the comparison circuit Comp is set to the “L” state (or “H” state). And The level of the AM modulation signal Vi to be received varies greatly depending on the distance from the transmitting station.

  As a specific example of the AM modulation signal Vi having only two states of a large amplitude state and a small amplitude state, there is a standard radio wave transmitted from the Communications Research Laboratory described in the description of the conventional circuit.

  In the circuit of FIG. 8A, when the output signal TCO of the comparison circuit Comp is in the “H” state (or “L” state), the transfer gate TG1 in the peak detection circuit PDet becomes conductive, and therefore the peak detection circuit PDet. Operates as a normal peak detection circuit. Accordingly, since the peak detection circuit PDet and the gain control amplifier unit GCA-B operate as a normal AGC amplifier in cooperation, the output amplitude Vo of the gain control amplifier unit GCA-B is controlled to be constant.

  When the output signal TCO of the comparison circuit Comp is in the “L” state (or “H” state), the transfer gate TG1 in the peak detection circuit PDet becomes non-conductive, and immediately before the transfer gate TG1 becomes non-conductive. A fixed voltage based on the charge accumulated in the peak hold capacitor C1 is output as the output Vp of the peak detection circuit PDet.

  In the conventional circuit of FIG. 7, when the output amplitude of the gain control amplifier unit GCA-B is increased, the output response of the peak detection circuit PDet is a small time constant between the on-resistance (small resistance) of the rectifier circuit Rec1 and the peak hold capacitor C1. However, the output response of the peak detection circuit PDet when the output amplitude of the gain control amplifier unit GCA-B is small is larger between the discharge path resistor R1 (large resistance) and the peak hold capacitor C1. Slow response with time constant.

  In order to speed up the response when the output amplitude of the gain control amplifier unit GCA-B is reduced, the time constant between the discharge path resistor R1 (large resistance) and the peak hold capacitor C1 may be reduced. While receiving the small amplitude state of the AM modulated wave, the output Vp of the peak detection circuit PDet rapidly decreases, so the gain of the gain control amplifier unit GCA-B increases rapidly, and the reception time of the small amplitude state Is long (such as “M” in FIG. 35), the output signal Vo of the gain control amplifier unit GCA-B also increases rapidly, and the output of the envelope detection circuit SDet becomes the reference voltage VR2 despite the small amplitude input state. (The threshold voltage of the comparator Comp) is exceeded and the output signal TCO of the comparator Comp is in the “H” state (or “L” corresponding to the large amplitude input state) The malfunction will be inverted to the state).

  In order to prevent such malfunction, in the circuit of FIG. 7, it is necessary to set the hold time constant of the discharge path resistor R1 and the peak hold capacitor C1 to a large time constant corresponding to several bits.

  Since the time code superimposed on the standard radio wave is very slow at 1 bit / sec, it takes a very long time even for several bits.

  In the circuit of FIG. 8A, since the accumulated charge of the peak hold capacitor C1 is zero when the power is turned on, the gain control amplifier unit GCA-B starts reception at the maximum gain state, and the gain control amplifier unit GCA-B The output amplitude Vo always starts from a level that is larger than the amplitude in the AGC stable state. For this reason, since the detection output signal obtained by detecting this output is always greater than the reference voltage VR2, the output signal TCO of the comparator Comp is in the “H” state (or “L” state) corresponding to the large amplitude input state. As a result, the transfer gate TG1 becomes conductive, the output amplitude Vo of the gain control amplifier unit GCA-B is large, and the peak hold capacitor C1 is rapidly charged, and the control voltage of the gain control amplifier unit GCA-B Vp suddenly rises, whereby the gain suddenly falls and the AGC stable state is reached at high speed.

  In the small amplitude input state, the detection output becomes smaller than the reference voltage VR2, the output signal TCO of the comparator Comp becomes the “L” state (or “H” state), the transfer gate TG1 becomes non-conductive, and the peak hold The charge / discharge of the capacitor C1 is stopped, the control voltage Vp of the gain control amplifier unit GCA-B becomes a fixed value, the gain control amplifier unit GCA-B operates in a fixed gain operation, regardless of the duration of the small amplitude input state. A stable small amplitude receiving operation is performed.

  When the large amplitude reception state is entered again, the detection output signal becomes larger than the reference voltage VR2, the output signal TCO of the comparator Comp returns to the “H” state (or “L” state), the transfer gate TG1 returns to conduction, The normal AGC operation for adjusting the output amplitude to a constant value is resumed. Thereafter, the above-described operation is continued.

  Since charging / discharging of the peak hold capacitor C1 is stopped in the small amplitude input state, stable AGC operation can be performed even if the hold time constants of the discharge path resistor R1 and the peak hold capacitor C1 are reduced.

  By reducing this time constant, the time to reach the AGC stable state at the time of reception from power-on can be shortened, and the response to the reception level fluctuation due to fading etc. is quick and the amplitude of the output signal Vo of the gain control amplifier unit GCA-B is Stabilize.

  In the circuit example of FIG. 8A, the resistor R1 is used for the discharge path, but a constant current circuit I1 may be used for the discharge path instead of this resistor (this example is not shown).

  In the circuit example of FIG. 8A, the transfer gate TG1 that turns on / off the charge / discharge operation of the peak hold capacitor C1 is used. However, in FIG. 8C, the discharge current flowing through the discharge path resistor R1 is As the transfer gate TG1 to be turned on / off, the discharge of the peak hold capacitor C1 in the small amplitude input state is stopped, and the same effect as in FIG. 8A is obtained.

  In FIG. 8D, the same effect as FIG. 8A is obtained as a configuration for turning on / off the discharge current I1 flowing through the discharge path constant current circuit I1.

  When the transfer gate is a combination of the N channel type and the P channel type, a change in charge of the peak hold capacitor C1 due to charge / discharge of the capacitance between the gate and the channel when the transfer gate is turned on / off (Vp Can lead to fluctuations).

As described above, according to the second embodiment, the following effects can be obtained.
(1) Since the AGC hold time constant determined by the discharge path resistor R1 (or the constant current I1 of the constant current circuit I1) and the peak hold capacitor C1 does not need to be taken into consideration. The hold time constant can be reduced, and the peak hold capacity C1 can be reduced.
(2) Since the hold time constant for AGC can be reduced, the AGC response in the large amplitude input state can be speeded up.
(3) By (2), the time to reach the AGC stable state at the time of reception from power-on can be shortened, and the response to the reception level fluctuation due to fading etc. is quick and the amplitude of the output Vo of the gain control amplifier unit GCA-B is Stabilize.
(4) Even when the duration of the small amplitude input state is long, the gain of the gain control amplifier unit GCA-B does not increase and the amplitude of the output signal Vo of the gain control amplifier unit GCA-B is fixed. Since the amplitude can be maintained, the malfunction of the output signal TCO of the comparator Comp does not occur even when the duration of the small amplitude input state is long.
(5) Even when the duration of the small amplitude input state is long, the phenomenon that the gain of the gain control amplifier unit GCA-B increases does not occur, so the pulse width error of the output signal TCO of the comparator Comp becomes small.

[Third Embodiment]
[Constitution]
FIGS. 9A to 9E are diagrams showing specific examples of the AM modulation signal receiving circuit according to the third embodiment of the present invention.

The AM modulation signal receiving circuit according to the third embodiment has, as a first configuration, a discharge path resistor R1 in the peak hold capacitor C1 of the peak detection circuit PDet in the AM modulation signal receiving circuit according to the second embodiment. A configuration (FIG. 9A) in which a second discharge path R3 (or constant current I3) for flowing a current smaller than (or the discharge path constant current circuit I1) is added is shown.
FIG. 9B shows that the second discharge path resistor R3 of FIG. 9A can be replaced with the second discharge path constant current circuit I3.

  As a second configuration, a transfer gate is obtained by OR-combining a control signal HS-AGC from a microcomputer (not shown) that performs a clock operation by inputting an output signal TCO of the comparator Comp and an output signal TCO of the comparator Comp. The structure (FIG.9 (c)) which controls conduction | electrical_connection / non-conduction of TG1 is shown.

  As a third configuration, the peak hold capacitor C1 is forcibly discharged by a control signal RESET from a microcomputer (not shown) that performs the clock operation by inputting the output signal TCO of the comparator Comp (FIG. 9 (d)). Indicates.

  As a fourth configuration, when the output signal TCO of the comparator Comp changes to an output state corresponding to large amplitude reception, “0” is immediately output, and after changing to an output state corresponding to small amplitude reception, A timer circuit TM that outputs “1” when a predetermined time has elapsed is provided, and the continuity / conduction of the transfer gate TG1 is obtained by OR-combining the output of the timer circuit TM and the output signal TCO of the comparator Comp. The structure (FIG.9 (e)) which controls non-conduction is shown.

[Operation]
In the AM modulation signal receiving circuit of FIG. 8A, the reception level is greatly reduced when the AGC operation cannot follow, such as the direction of the radio clock is changed during small amplitude reception, and the envelope at the time of large amplitude reception is reduced. When the output of the detection circuit SDet cannot exceed the reference voltage VR2, the transfer gate TG1 remains in a non-conductive state, the AGC operation is not permanently performed, and the gain of the gain control amplifier unit GCA-B is fixed. The Comp output signal TCO is fixed to an output state corresponding to reception of a small amplitude.

  In such a case, in the circuit of FIG. 9A, a minute current flowing through the second discharge path resistor R3 (or the second discharge path constant current circuit I3) causes the accumulated charge of the peak hold capacitor C1 to be accumulated. By discharging, the gain of the gain control amplifier unit GCA-B is slowly increased to return to the normal AGC operation, and the output signal TCO of the comparator Comp is released from the fixed state.

  In the circuit of FIG. 9C, when a microcomputer (not shown) determines that the output signal TCO of the comparator Comp is fixed to the output state corresponding to the small amplitude reception, the transfer gate TG1 is forcibly turned on. The control signal HS-AGC is output, and the control signal HS-AGC passes through the OR combiner to forcibly bring the transfer gate TG1 into the conductive state to return to the normal AGC operation, and the comparator Comp output signal TCO Get out of the fixed state.

  In the circuit of FIG. 9D, a control signal for forcibly discharging the peak hold capacitor C1 when a microcomputer (not shown) determines that the output signal TCO of the comparator Comp is fixed to the output state corresponding to the small amplitude reception. RESET is output, the peak hold capacitor C1 is forcibly discharged to return the gain control amplifier unit GCA-B to the initial large gain state, the normal AGC operation is restored, and the output signal TCO of the comparator Comp is released from the fixed state. To do.

  The control terminal RESET is connected to the control terminal PON of the power circuit Reg described in the conventional circuit (FIG. 7) (broken line in FIG. 9 (d)) to be a PON / RESET terminal, and power supply to each part is turned off. When performing (control from the PON terminal), the peak hold capacitor C1 may be forcibly discharged (control from the RESET terminal).

  In the circuit of FIG. 9 (e), after the output signal TCO of the comparator Comp is changed to an output state corresponding to reception of a small amplitude, the output signal TCO of the comparator Comp is within the predetermined time (for example, within 1 sec). If the output state corresponding to the large amplitude reception changes each time, the output of the timer circuit TM continues to be “0”, and the OR synthesis result is the same as the output signal TCO of the comparator Comp, as shown in FIG. The operation is the same as that described in a).

  When the output signal TCO of the comparator Comp does not become the output state corresponding to the reception of the large amplitude even when the predetermined time is exceeded (falling into the failure state), the output of the timer circuit TM is inverted to “1”, and OR The “1” signal that has passed through the combiner forcibly turns on the transfer gate TG1, and thus the AGC operation similar to that of the conventional circuit is performed, and the output signal TCO of the comparator Comp is released from the fixed state. Until the output state corresponding to the large amplitude reception appears as the output signal TCO of the comparator Comp, the timer circuit TM output “1” state continues and the AGC operation similar to the conventional circuit continues. When an output state corresponding to large amplitude reception appears while the AGC operation similar to that of the conventional circuit continues, the timer circuit TM output immediately becomes “0”, and the operation returns to the same operation as in FIG.

  In the circuits of FIGS. 9C to 9E, the same effect can be obtained even if the transfer gate TG1 and the discharge path resistor R1 are replaced as shown in FIGS. 8B to 8D. Further, the circuit systems shown in FIGS. 9A to 9E may be used in combination.

  25 is a circuit diagram showing that the circuit of the OR circuit and transfer gate TG1 in FIGS. 9C and 9E can be replaced with a parallel circuit of two transfer gates TG1 and TG2. It is an example.

  The circuit diagram shown in FIG. 28 shows a specific example of the timer circuit TM shown in FIG. 9E. When Qi in FIG. 28 is changed to the “H” input, the transistor T1 sets the capacitor C. The battery is rapidly charged, and Qo is rapidly changed to “L”. When Qi changes to the “L” input, the transistor T1 is turned off, the capacitor C is discharged by the constant current Is of the constant current circuit, and Qo sets the discharge time (corresponding to the predetermined time). Change to "H". If Qi changes to the “H” input within the discharge time (predetermined time), the capacitor C is rapidly charged again by the transistor T1, so that Qo is maintained at “L”.

  As described above, according to the third embodiment, in addition to the effects of the second embodiment, during reception, the reception level decreases when the AGC operation cannot follow, and the output of the comparator Comp When the signal TCO is fixed to the output state corresponding to the reception of the small amplitude (malfunction state), it is possible to escape from this state and return to the normal operation.

[Fourth Embodiment]
[Constitution]
FIGS. 10A to 10D are diagrams showing specific examples of the AM modulation signal receiving circuit according to the fourth embodiment of the present invention.

  In the AM modulation signal receiving circuit of the fourth embodiment, in the AM modulation signal receiving circuit of the second or third embodiment, the peak hold capacitance C1 of the peak detection circuit PDet of the AM modulation signal receiving circuit is charged. A function for forcibly stopping the discharge by the external control signal AGCH is added.

  The example of the AM modulation signal receiving circuit shown in FIG. 10A is an AND combination of the output signal TCO of the comparator Comp and the external control signal AGCH in the circuit of FIG. 8A of the second embodiment. An example is shown in which the transfer gate TG1 is controlled by an AND-combined signal.

  The method of AND-combining the output signal TCO of the comparator Comp and the external control signal AGCH, and controlling the transfer gate TG1 with this AND-combined signal can also be applied to FIG. 9D, and FIG. Application in accordance with b) and (d) is also possible. (Not shown)

  The example of the AM modulation signal receiving circuit shown in FIG. 10B is similar to the circuit of FIG. 9A of the third embodiment in that the transfer gate TG1 and the second discharge path resistor R3 (or the second discharge path). The second transfer gate TG2 is inserted at a connection point between the connection of the constant current circuit I3) and the peak hold capacitor C1 terminal serving as the peak hold output, and the conduction / non-conduction of the second transfer gate TG2 is An example is shown in which control is performed using an external control signal AGCH.

  The example of the AM modulation signal receiving circuit shown in FIG. 10C is an OR combination of the output signal TCO of the comparator Comp and the above-described external control signal HS-AGC in the circuit of FIG. 9C of the third embodiment. An example is shown in which the output and the external control signal AGCH are AND-combined and the transfer gate TG1 is controlled by this AND-combined output.

  If the external control signal HS-AGC of FIG. 10C is replaced with the timer circuit TM shown in FIG.

  In the circuit shown in FIG. 26, the AND circuit and the transfer gate TG1 in FIGS. 10A and 10C can be replaced with a series circuit of two transfer gates TG1 and TG2. It is the example of a circuit shown.

  The circuit shown in FIG. 27 is a specific circuit example of FIG. 10B. The variable gain amplifier GCA (one-stage configuration example) and the gain control amplifier DA shown in FIG. ) Gain control amplifier block GCA-B.

[Operation]
While the external control signal AGCH is “L”, the transfer gate TG1 is in the circuits of FIGS. 10A and 10C, and the second transfer gate TG2 is in the circuit of FIG. It becomes non-conductive, the charge / discharge path of the peak hold capacitor C1 is cut off, and the gain control amplifier unit GCA-B can be set to a fixed gain operation.

  In the radio timepiece that drives the hour / minute / second display with a stepping motor or the like, there is a possibility that a large noise may be generated during driving, and the second hold and the AGC response speed are improved by reducing the peak hold capacity C1 for AGC operation. When this noise is superimposed on the AM modulation signal amplification path of the circuit of the third embodiment, the charge amount of the peak hold capacitor C1 becomes abnormal, and the output amplitude of the gain control amplifier unit GCA-B may become abnormal. Can happen.

  Since such noise generation timing can be predicted, if the external control signal AGCH is set to “L” at this timing, the charge charge amount of the peak hold capacitor C1 can be prevented from becoming abnormal, and the gain control amplifier unit GCA− The output amplitude of B can be kept normal.

  In the second to fourth embodiments, examples have been shown in which the transfer gate TG1 and the second transfer gate TG2 are controlled by hardware. However, the clock operation is performed by inputting the output signal TCO of the comparator Comp. If a microcomputer (not shown) or the like having a sufficient operating speed has a sufficient operating speed, when the output signal TCO of the comparator Comp is an output corresponding to the small amplitude reception, the microcomputer or the like All of the control may be performed by the microcomputer or the like, such as making the transfer gate TG1 non-conductive using the control signal AGCH. An example of the AM modulation signal receiving circuit of FIG.

  As described above, according to the fourth embodiment, in addition to the effects of the second and third embodiments, the noise when driving the stepping motor for indicating the hour / minute / second, etc., is large. There is an effect that the influence of the generation timing on the AGC of the predictable noise can be reduced.

[Fifth Embodiment]
[Constitution]
FIGS. 11A and 11B are diagrams showing specific examples of the AM modulation signal receiving circuit according to the fifth embodiment of the present invention.

  In the AM modulation signal receiving circuit in the fifth embodiment shown in FIG. 11A, in the AM modulation signal receiving circuit in the second to fourth embodiments, a delay circuit for delaying the output signal TCO of the comparator Comp. D, a monostable multivibrator MM that outputs a pulse having a predetermined time width from the output signal of the delay circuit D, and the transfer gate by switching between the output of the monostable multivibrator MM and the output signal TCO of the comparator Comp A changeover switch S serving as a control signal for TG1 is added.

  In the AM modulation signal receiving circuit in the fifth embodiment shown in FIG. 11B, in the AM modulation signal receiving circuit in the second to fourth embodiments, a delay circuit for delaying the output signal TCO of the comparator Comp. D, a monostable multivibrator MM that outputs a pulse having a predetermined time width from the output signal of the delay circuit D, and an AND circuit that ANDs the output of the monostable multivibrator MM and the output signal TCO of the comparator Comp And a changeover switch S for switching the output of the AND circuit and the output signal TCO of the comparator Comp to serve as a control signal for the transfer gate TG1.

  The circuit of FIG. 11A is also a diagram showing that the reference voltage VR2 can be generated from the output of the peak detection circuit PDet. As shown in FIGS. 8A to 10D, the independent reference voltage VR2 is generated. It is good. Further, instead of the transfer gate TG1, as in the example of FIG. 8C, the discharge current I1 flowing through the discharge path constant current circuit I1 may be turned on / off.

[Operation]
In the AM modulation signal receiving circuit in the fifth embodiment, in addition to the AGC method in the second to fourth embodiments, a path through the delay circuit D and the monostable multivibrator MM is set by the changeover switch S. Thus, a predetermined pulse width set by the monostable multivibrator MM after a delay time set by the delay circuit D after the output TCO of the comparator Comp changes to an output corresponding to the large amplitude input state. The transfer gate TG1 (or a constant current I1 that can be turned on / off) is in a conductive state only for a period of time, and an AGC operation is performed only during this conductive state. In other time regions, the peak detection circuit PDet holds the previous state. Then, an AGC method for fixing the gain of the gain control amplifier unit GCA-B can be performed.

  The delay circuit D creates a predetermined waiting time, and may be composed of a monostable multivibrator. The change-over switch also enables use of the above-described two methods of AGC, and may be configured using other logic configurations or a plurality of transfer gates. This switching control is performed by a microcomputer attached to the AM modulation signal receiving circuit.

  In the circuit of FIG. 11A, the switch S uses the output signal TCO of the comparator Comp to directly use the control signal TCO for controlling the transfer gate TG1, and the idle reception is started. The output signal TCO of the comparator Comp is "H" / ". When the state of the alternating output of L ″ can be confirmed, the switch S is switched to a connection that becomes a path via the delay circuit D and the monostable multivibrator MM, and the main reception is performed. Accordingly, it is possible to realize the accurate reception of the “H” output duration of the output signal TCO of the comparator Comp (the “L” output duration is also accurate).

  The operation will be described in detail below.

  In an AM modulation signal receiving circuit for a radio clock, a narrow band pass filter BPF with a bandwidth of around 10 Hz is used to remove out-of-band noise and increase the reception sensitivity on the minimum level side. The envelope of the peak value of the output signal of GCA-B is a gradual change corresponding to a narrow band with a bandwidth of about 10 Hz (the change takes time of about 100 msec).

  FIG. 36 schematically shows an input / output waveform example of the band pass filter BPF in the gain control amplifier unit GCA-B. In FIG. 36, the region A changes to the tail portion of the small amplitude input state, the region B changes to the large amplitude input state, and the temporary amplitude increases due to the band limiting characteristic of the bandpass filter BPF (narrow band around 10 Hz). In part C, the large amplitude input continues, and the part in which the output amplitude Vo is stably controlled to a predetermined level (a constant level state) by AGC control, area D changes to the small amplitude input state, and the band limitation of the bandpass filter BPF The part where the amplitude decreases for a while depending on the characteristics, the area E is the initial part of the small amplitude input state, and after a predetermined time from the area E, it is connected to the area A and is repeated.

  The AGC operation of the conventional circuit and the AGC operation (normal AGC operation) in the conduction state of the transfer gate TG1 of the AM modulation signal receiving circuit of each of the second to fourth embodiments are performed by the gain control amplifier unit GCA-B. An operation is performed so that the output amplitude Vo always matches the amplitude indicated in the C region. That is, in a region with a small amplitude other than the C region, the amplitude increases toward the amplitude in the C region at a response speed limited by the time constant of the AGC circuit.

  Accordingly, the output amplitude Vo of the gain control amplifier unit GCA-B in the AGC operation of the conventional circuit is larger in the A region amplitude than the E region amplitude in FIG. 36, and the rise of the B region is the band limitation of the bandpass filter BPF. Although there is a characteristic, it is accelerated by the AGC operation, and the fall of the C region is further decelerated by the AGC operation of the slow fall due to the band limiting characteristic of the bandpass filter BPF. Due to this phenomenon, when the input reference voltage VR2 of the comparator Comp is set to a value corresponding to the middle level of the C region and the level of 1/10 thereof (in the case of Japanese standard radio wave reception), the output of the comparator Comp In the signal TCO, the pulse width on the side corresponding to the large amplitude always extends (td1 <td2).

  As can be seen from FIG. 35, since “M” / “0” / “1” is identified by the pulse width of the output signal TCO corresponding to the large amplitude, the accuracy of the pulse width leads to the accuracy of the identification. To go.

  Also in the AGC operations in the second to fourth embodiments, in the region where the output signal TCO of the comparator Comp is an output corresponding to a small amplitude, the gain control amplifier unit GCA-B has a fixed gain. During this time, the amplitude increase phenomenon of the output amplitude Vo of the gain control amplifier unit GCA-B does not occur, but the output signal TCO of the comparator Comp becomes an output corresponding to a large amplitude in the second half of the region B and the first half of the region D. As a result, the above-described amplitude increase phenomenon occurs, and the pulse width on the side corresponding to the large amplitude always increases although it is greatly improved over the conventional circuit.

  In order to suppress the influence of the amplitude increase phenomenon in the conventional circuit, the time constant of the AGC circuit (the time constant of the peak detection circuit PDet or the time constant of the low-pass filter LPF) during the amplitude increase phenomenon occurs. Therefore, it is necessary to set it sufficiently larger than the gentle rise / fall time due to the band limiting characteristic of the bandpass filter BPF.

  Furthermore, in order to widen the reception range to a very small input, it is necessary to increase the maximum gain of the AGC amplifier and widen the variable gain range. When this improvement is made, the gain change with respect to the change in the output Vp of the peak detection circuit PDet becomes large. Therefore, in order to suppress the amplitude increase phenomenon, it is necessary to further increase the time constant of the AGC circuit.

  In the circuit of FIG. 11A, the delay time of the delay circuit D is set to a time roughly corresponding to the region B, and the pulse width of the monostable multivibrator MM is set to the minimum duration having a large amplitude (“M” in FIG. 35). If the time is set to a time corresponding to a sign, a normal AGC operation is performed for the minimum duration of the C region that is a completely flat level, and the gain control amplifier unit GCA-B is operated at a fixed gain for other times. Since the amplitude increase phenomenon in the previous period can be completely eliminated, the time width between the large amplitude state and the small amplitude state becomes accurate.

  Since the normal AGC operation is performed only for the minimum duration time of the C region at a completely flat level, it is not necessary to increase the AGC time constant even if the maximum gain or variable gain range is increased.

  As described above, the time constant of the peak detection circuit PDet can be significantly reduced, so that the AGC response speed can be increased and the time constant capacity C1 can be reduced.

  In the circuit shown in FIG. 11A, if the main reception is suddenly performed immediately after the receiving circuit is turned on, the AGC operation is performed in the small amplitude input state from the region E to the region A in the previous period. There is a possibility that the gain may be fixed by matching the output amplitude Vo of the gain control amplifier unit GCA-B in the input state with a level corresponding to the region C in FIG. In this state, since the input of the comparator Comp is always equal to or higher than the input level corresponding to the large amplitude input state, the output signal TCO of the comparator Comp is also fixed at the level corresponding to the large amplitude input state ( Malfunction).

  In the idle reception, first, a large amplitude input state is selected, and an AGC state in which the output amplitude Vo in this state is adjusted to a level corresponding to the C region is created. Thereafter, by performing the main reception via the delay circuit D and the like, the pulse width of the output signal TCO of the comparator Comp can be accurately received.

  The reference voltage VR2 is optimally set to an intermediate value between the output peak value and the bottom value of the envelope detection circuit SDet. In the circuit of FIG. 11A, even if the holding capacity of the peak detection circuit PDet is small, the output VP of the peak detection circuit PDet is more stable than the conventional circuit or the second to fourth embodiments. A method of determining the reference voltage VR2 from the peak detection circuit PDet becomes more effective.

  The delay time of the delay circuit D is generally set to a time corresponding to the region B, and prevents an excessive increase in the output amplitude Vo due to an increase in gain during this period. The delay circuit D may be omitted in a configuration in which the amplitude increase of the previous output amplitude Vo due to the gain increase during this period does not become a problem, such as the reference voltage VR2 being a fixed value.

  Further, when the monostable multivibrator MM generates an erroneous pulse for some reason, the AGC operation becomes abnormal. As shown in FIG. 11B, the output of the monostable multivibrator MM and the comparator If the output signal TCO of Comp is AND-combined, it is possible to prevent malfunction when the monostable multivibrator MM generates an erroneous pulse for some reason.

As described above, according to the fifth embodiment, the following effects can be obtained.
(1) The time constant of the peak detection circuit PDet can be significantly reduced, and the AGC response can be speeded up and the time constant capacity C1 can be reduced.
(2) Constant The output amplitude of the gain control amplifier unit GCA-B is stably controlled, and the time width of the large amplitude state and the small amplitude state becomes accurate.
(3) A method of determining the reference voltage VR2 from the peak detection circuit PDet is effective.
(4) An increase in the AGC time constant associated with increasing the maximum gain and variable gain range of the variable gain amplifier can be prevented.
(5) With the above (1) to (4), an AM signal receiving circuit with a wide reception level range and few malfunctions can be realized.

[Sixth Embodiment]
[Constitution]
FIG. 12 is a diagram showing a specific example of an AM modulated signal receiving circuit according to the sixth embodiment of the present invention.

  The AM modulation signal receiving circuit of FIG. 12 is an AM modulation signal receiving circuit capable of simultaneous reception by a plurality of stations, and is composed of an antenna coil L1 that tunes and receives a radio wave having a carrier frequency f1, a tuning capacitor C1, and the like. A second tuning circuit including a tuning circuit, a preamplifier PA1 that amplifies and outputs an output signal of the first tuning circuit, an antenna coil L2 that tunes and receives a radio wave having a carrier frequency f2, a tuning capacitor C2, and the like; The preamplifier PA2 that amplifies and outputs the output signal of the second tuning circuit, the addition circuit Add that outputs the output of the preamplifier PA1 and the preamplifier PA2, and the external DC control voltage Vp rises to decrease the gain. When the signal falls, the gain is increased and the output of the adder circuit Add is amplified as the input signal Vi, and the band signal Vo1 having the center frequency f1 and the bandwidth Δf1 and the middle A gain control amplifier unit GCA-B that extracts and outputs a band signal Vo2 having a bandwidth Δf2 of frequency f2, a rectifier circuit Rec1a that rectifies the band signal Vo1 and charges the peak holding capacitor C1, and a band signal Vo2 The rectifier circuit Rec1b that charges the peak holding capacitor C1 and the discharge resistor R1 that discharges the charged charge of the peak holding capacitor C1 are configured, and the charging voltage of the holding capacitor C1 is supplied to the gain control amplifier unit GCA-B as a DC control voltage. A peak detection circuit PDet that outputs Vp, a rectifier circuit Rec2a that rectifies the band signal Vo1 and charges the peak holding capacitor C2, a rectifier circuit Rec2b that rectifies the band signal Vo2 and charges the peak holding capacitor C2, and a peak holding capacitor C2 Discharging charge of And an output signal TCO by comparing the output of the envelope detection circuit SDet with the reference voltage VR2 and the envelope detection circuit SDet configured to output the charging voltage of the peak holding capacitor C2 as an envelope detection output. And a comparator Comp that outputs.

FIG. 21 shows a specific example of the adder circuit in the present embodiment.
The outputs of the preamplifiers PA1 and PA2 are converted into differential current signals by the circuit within the broken line, the wired current is added, and the added current is converted into a voltage signal by the load resistors RL1 and RL2.

  The gain control amplifier unit GCA-B compares the control voltage Vp with an internal reference voltage VR1 (not shown) to control the gain and amplify the input signal Vi. The gain control amplifier unit GCA-B has a bandwidth Δf1 with a center frequency f1. A band pass filter BPF1 is included as means for extracting the signal Vo1, and a band pass filter BPF2 is included as means for extracting the band signal Vo2 having the center frequency f2 and the bandwidth Δf2.

  As described in the description of the conventional circuit basic configuration example (FIG. 7), the preamplifiers PA1 and PA2 may be variable gain amplifiers and may be incorporated in an AGC operation loop. Also, each bandpass filter BPF and each rectifier circuit Rec There is a buffer circuit that satisfies the termination condition of the bandpass filter BPF and drives each rectifier circuit Rec between them, but it is omitted in FIG. 12 because it can be easily analogized by those skilled in the art.

[Operation]
The antenna coil L1 may have a bar antenna structure or may be connected to an external antenna. The antenna coil L1 receives a radio wave in the vicinity of the carrier frequency f1 and converts it into a voltage (current) signal. C1 is tuned to the carrier frequency f1 and emphasizes the voltage (current) signal of the frequency f1 by resonance operation. The preamplifier PA1 further amplifies the voltage (current) signal and outputs it to the adder circuit Add.

  Similarly to the above, the antenna coil L2, the tuning capacitor C2, and the preamplifier PA2 receive the radio wave of the carrier frequency f2, convert it to a voltage (current) signal, amplify it, and output it to the adder circuit Add.

  The adder circuit Add adds the amplified voltage (current) signals of the carrier frequency f1 and the carrier frequency f2 in an analog manner and outputs the result to the gain control amplifier unit GCA-B.

  The variable gain amplifier block GCAb amplifies the output Vi of the adder circuit Add with a gain that keeps the external DC control Vp constant, and the bandpass filter BPF1 uses a band signal Vo1 having a bandwidth Δf1 with a center frequency f1 from the amplified signal. Is extracted and output. Similarly, the bandpass filter BPF2 extracts a band signal Vo2 having a bandwidth Δf2 having a center frequency f2 from the amplified signal and outputs the extracted signal.

  The band signal Vo1 passes through the rectifier circuit Rec1a, and the band signal Vo2 passes through the rectifier circuit Rec1b, and is rectified and charged in the peak holding capacitor C1, and the DC control Vp is generated by the charged charge.

  This charge operation and the operation of discharging the charge stored in the peak holding capacitor C1 with a time constant of R1 × C1 by the discharge resistor R1 serve as a peak detection circuit PDet.

  Here, since the voltage amplitudes of the band signals Vo1 and Vo2 are generally larger than the other, the output Vp of the peak detection circuit PDet is determined only by the larger amplitude level and does not depend on the smaller amplitude level. .

  The gain control amplifier unit GCA-B and the peak detection circuit PDet perform an AGC operation. Since the output signal Vp of the peak detection circuit PDet depends only on the larger amplitude level of the two band signals, the AGC operation is performed. Operates so as to make the amplitude level on the large side constant, and the level on the small side is amplified by the gain. Therefore, the ratio of the reception amplitude level is maintained as the ratio of the output amplitude.

  In the envelope detection circuit SDet, the band signal Vo1 passes through the rectifier circuit Rec2a, and the band signal Vo2 passes through the rectifier circuit Rec2b and is rectified and charged to the peak holding capacitor C2. This charge operation and the operation of discharging the charge stored in the peak holding capacitor C2 with the time constant of R2 × C2 by the discharge resistor R2 serve as the envelope detection circuit SDet.

  Similar to the description of the peak detection circuit PDet, the output of the envelope detection circuit SDet is a combination of the amplitude levels on the higher voltage amplitude side of the band signals Vo1 and Vo2. The output of the envelope detection circuit SDet and the reference voltage VR2 are compared by a comparator Comp and converted into a comparison signal TCO.

  As standard Japanese radio waves, the same time code is transmitted from Fukushima Prefecture (40 KHz) and Saga Prefecture (60 KHz) with the same AM modulation at the same time. When these two radio signals are received in Japan, there will be a time difference due to the difference in reach to the reception point, which is about several milliseconds, as can be seen from the standard radio wave waveform example of FIG. Since the time width of each bit is on the order of several hundreds msec, it can be ignored. Therefore, even if these two stations are received simultaneously, the time code is not corrupted.

  If the received input level is extremely low, it will be ignored without being amplified to a visible level, and if the received input level is similar, the reception status will always be changed even if the received input level fluctuates individually due to fading. Since the good side is automatically selected and received, stable reception is realized.

As described above, according to the sixth embodiment, the following effects can be obtained.
(1) An input signal having an extremely small reception input level is ignored, and when the reception input level is similar, stable reception is realized even if the reception input level fluctuates due to a fading phenomenon or the like.
(2) Although it is a two-station simultaneous receiving circuit, since there are many shared parts, there is little increase in the number of parts and power consumption.
(3) Compared with a method that employs the result of better reception of two stations individually, reception in a short time is realized.
(4) Compared with the method of receiving two stations individually, the above (2) and (3) reduce the total power consumption.

[Seventh Embodiment]
[Constitution]
FIG. 13 is a diagram showing a specific example of an AM modulated signal receiving circuit according to the seventh embodiment of the present invention.

  The multi-station simultaneous reception AM modulation signal reception circuit of FIG. 13 is the same as the multi-station simultaneous reception AM modulation signal reception circuit in the sixth embodiment described above, but the bandwidth of the gain control amplifier unit GCA-B having the center frequency of f1. A second addition circuit Add2 for adding the outputs of the bandpass filter BPF1 for extracting the band signal Vo1 of Δf1 and the bandpass filter BPF2 for extracting the band signal Vo2 of the center frequency f2 with the bandwidth Δf2 is added. The output of the second addition circuit Add2 is input to the peak detection circuit PDet and the envelope detection circuit SDet.

  Similarly to the description of the conventional circuit basic configuration example (FIG. 7), the preamplifiers PA1 and PA2 may be variable gain amplifiers and may be incorporated in the AGC operation circuit.

  FIG. 21 shows a specific example of the adder circuits Add1 and Add2 in the present embodiment. The outputs of the preamplifiers PA1 and PA2 are converted into differential current signals by a circuit within a broken line, and a wired current is obtained. The added currents are converted into voltage signals by the load resistors RL1 and RL2.

[Operation]
Since the basic operation as the multi-station simultaneous reception AM modulation signal receiving circuit is the same as that of the sixth embodiment, the description thereof will be omitted.

  In the seventh embodiment, the output Vo1 of the bandpass filter BPF1 and the output Vo2 of the bandpass filter BPF2 are added by the second addition circuit Add2.

  Examples of analog addition synthesis of waves having different frequencies are shown in FIGS. FIGS. 37 to 41 are examples in which sine waves having an amplitude value of 0.5 are synthesized by changing the initial phase. The amplitude value of the sum of the amplitude values is approximately the frequency of the difference between the two waves. appear. As a result, the AGC operation is performed so that the synthesized amplitude value becomes a predetermined level, and detection based on the envelope of the peak value of the amplitude value is performed.

  In the sixth embodiment, the input conversion noises of the two preamplifiers PA1 and PA2 are added and appear in the output (noise increases). In the seventh embodiment, the amplitude is approximately the sum of two waves. Therefore, if the variable gain amplifier operates with a low gain, the increase in noise is reduced.

  Also, since the two waves are amplified with the same gain, as in the sixth embodiment, the side where the reception input level is extremely small is not amplified to a visible level and is consequently ignored, and the reception input level is close. In this case, even if the reception input level fluctuates individually due to a fading phenomenon or the like, the reception is always performed with the addition being performed mainly on the side with good reception conditions, so that stable reception is realized.

  Furthermore, although it is a two-station simultaneous reception circuit, since there are many shared parts, the increase in the number of parts and power consumption is small.

  In addition, compared to a method that adopts the result of receiving two stations individually, it can be received in half the time, and when combined with the above, less power is required for all receptions.

  Further, when the second to fifth embodiments are applied, the respective effects appear as they are.

  As for a method for capturing radio waves, the antenna coil may be a bar antenna or may be pulled in from an external antenna with an antenna cable.

  As described above, according to the seventh embodiment, in addition to the effect of the sixth embodiment, there is an effect of reducing noise.

[Eighth Embodiment]
[Constitution]
FIG. 14 is a diagram showing a specific example of an AM modulated signal receiving circuit according to the eighth embodiment of the present invention.

  The AM modulation signal receiving circuit of FIG. 14 is the AM modulation signal receiving circuit of the sixth embodiment, wherein the antenna coil L1 and the antenna coil L2 are bar antennas and are arranged so as to be orthogonal to each other on a horizontal plane. The phase changeover switch S for switching the output phase of the preamplifier PA2 between the positive phase and the reverse phase with the same tuning frequency f as the tuning frequency of the coil L1 and the tuning capacitor C1 and the tuning frequency of the antenna coil L2 and the tuning capacitor C2 It is configured to be inserted between the output of PA2 and the input terminal of the adder circuit Add.

  In this embodiment, since the tuning frequency f is single, the band-pass filter BPF in the AGC circuit of FIG. 14 may be single, and after the AGC circuit, the conventional circuit or the second to fifth embodiments are used. A circuit similar to the circuit can be used.

  Similarly to the description of the conventional circuit basic configuration example (FIG. 7), the preamplifiers PA1 and PA2 are variable gain amplifiers and may be incorporated in the AGC circuit.

  22 and 23 are specific examples of the adder circuit including polarity switching of the preamplifier PA2. In the adder circuit of FIG. 22, either the transfer gate TG1 or TG2 is turned on to make the preamplifier PA2 positive. The output of the phase or reverse phase and the output of the preamplifier PA1 are added. In the adder circuit of FIG. 23, any one of the differential pair of the transistors T3 and T4 or the differential pair of the transistors T1 and T2 is activated by bringing one of the transistors T5 and T6 into a conductive state. In this state, the output of the preamplifier PA2 is added to the output of the preamplifier PA1 in the normal phase or the reverse phase.

[Operation]
A receiving unit including two antenna coils L1 and L2, tuning capacitors C1 and C2, and two preamplifiers PA1 and PA2 receives the same frequency, that is, receives and outputs a transmission radio wave from the same transmitting station.

  If the distance between two orthogonally arranged bar antennas is sufficiently smaller than the wavelength of the transmission radio wave, the received voltage generated in the two antenna coils L1 and L2 is either in-phase or out-of-phase depending on the coil winding direction. Thus, only the reception level changes depending on the angle θ (θ is 0 to 360 degrees, see FIG. 16) with respect to the direction of arrival of the radio wave.

  When the reception level of the antenna coil L1 is V1 = Vo × cos θ, the reception level of the antenna coil L2 is V2 = Vo × sin θ. When simple addition (V = V1 + V2), the magnitude is equal and the phase is reversed and the addition result is Although an angle that becomes zero occurs, if the phase changeover switch S is operated so as to always have the same phase (V = | V1 | + | V2 |), the addition V is always Vo to 1.4Vo. . (See Figure 42)

  In the case of a wall-mounted radio clock, the direction of the bar antenna in the radio clock is determined by the orientation of the installation wall, etc., and if it is a single bar antenna, it cannot be received at all depending on the angle. By using the AM modulation signal receiving circuit, it is possible to obtain a reception sensitivity equal to or higher than a reception level obtained by directing a single bar antenna in the best direction at any angle.

  The operation of switch S is switched for the first reception such as after setting the radio timepiece or after replacing the power supply battery to test the goodness of reception in the normal phase / reverse phase of the preamplifier PA2. If reception is attempted successfully with successful phase, the reception success time code is used, and if it fails, the phase is reversed and reception is attempted.

  Also in this embodiment, when the second to fifth embodiments are applied, the respective effects live as they are.

  As described above, according to the eighth embodiment, the reception sensitivity equal to or higher than the reception level obtained by directing the single bar antenna in the best direction regardless of the direction of the AM modulation signal reception circuit. Is obtained.

[Ninth Embodiment]
[Constitution]
FIG. 15 is a diagram illustrating a specific example of an AM modulated signal receiving circuit according to the ninth embodiment of the present invention.

  The AM modulation signal receiving circuit of FIG. 15 is the AM modulation signal receiving circuit according to the seventh embodiment, in which the antenna coil L1 and the antenna coil L2 are bar antennas and are arranged orthogonally on a horizontal plane. Further, the tuning frequency of the antenna coil L1 and the tuning capacitor C1 and the tuning frequency of the antenna coil L2 and the tuning capacitor C2 are set to the same tuning frequency f1, and the tuning capacitor C3 that can be turned on / off with the switch S1 is connected to the tuning capacitor C1. In addition, a tuning capacitor C4 that can be turned on / off by the switch S2 is added to the tuning capacitor C2, and the tuning frequency of the antenna coil L1 and the tuning capacitors C1 and C3 and the tuning of the antenna coil L2 and the tuning capacitors C2 and C4 are added. The phase changeover switch S for switching the output phase of the preamplifier PA2 between the positive phase and the reverse phase is inserted between the output of the preamplifier PA2 and the input terminal of the adder circuit Add.

  Examples of analog addition synthesis of waves having different frequencies are shown in FIGS. FIGS. 37 to 41 are examples in which sine waves having an amplitude value of 0.5 are synthesized by changing the initial phase. The amplitude value of the sum of the amplitude values is approximately the frequency of the difference between the two waves. appear. As a result, the AGC operation is performed so that the synthesized amplitude value becomes a predetermined level, and detection based on the envelope of the peak value of the amplitude value is performed.

  22 and 23 are specific examples of the adder circuit including polarity switching of the preamplifier PA2. In the adder circuit of FIG. 22, either the transfer gate TG1 or TG2 is turned on to make the preamplifier PA2 positive. The output of the phase or reverse phase and the output of the preamplifier PA1 are added. In the adder circuit of FIG. 23, any one of the differential pair of the transistors T3 and T4 or the differential pair of the transistors T1 and T2 is activated by bringing one of the transistors T5 and T6 into a conductive state. In this state, the output of the preamplifier PA2 is added to the output of the preamplifier PA1 in the normal phase or the reverse phase.

[Operation]
The combination of on / off of the switches S1 and S2, the tuning frequency connected to the preamplifier PA1 and the tuning frequency connected to the preamplifier PA2, both are the tuning frequency f1 or f2, or one is the tuning frequency f1 and the other is The tuning frequency f2 can be freely selected.

  Further, the output phase of the preamplifier PA2 can be freely selected by the switch S between the positive phase and the reverse phase.

  Therefore, both the reception method of the seventh embodiment and the reception method of the eighth embodiment with respect to the tuning frequency f1 or f2 can be realized by a combination of on / off of the switches S and S1 and S2.

  Switch S and S1 and S2 are switched for the first reception, such as after setting the radio clock or after replacing the power supply battery, to test the goodness of reception. When the reception is successful, the reception success time code is used, and when the reception is successful, the on / off combination is changed and the reception is attempted. It is efficient to store the success rate of each combination and give priority to a combination with a high success rate.

  Also in this embodiment, when the above-described second to fifth embodiments are applied, the respective effects live as they are.

  As described above, in the ninth embodiment, the combination of the switches S and S1 and S2 is turned on / off, and the reception method of the seventh embodiment also uses the reception of the eighth embodiment for the tuning frequency f1 or f2. Any method can be used, and the combined effect of the two embodiments can be obtained.

[Tenth embodiment]
[Constitution]
FIG. 17 is a diagram showing a specific example of an AM modulated signal receiving circuit according to the tenth embodiment of the present invention.

  The AM modulation signal receiving circuit in FIG. 17 uses a differential input amplifier as a preamplifier PA. In the AM modulation signal receiving circuit in the conventional circuit and the second to ninth embodiments, the input bias of the preamplifier PA is set as an antenna coil. It is set as the structure supplied from the center tap provided in L.

[Operation]
Since the operation as the AM modulation signal receiving circuit is the same as that of each of the above-described embodiments, the description thereof is omitted. In order to improve the minimum input sensitivity of the AM modulation signal receiving circuit, it is necessary to reduce the noise of the preamplifier PA. As in the conventional circuit, a bias circuit is provided for both differential inputs to supply a bias, or a bias circuit is provided on one side of an operation input and the other is supplied with a bias via an antenna coil. The generated thermal noise or the like is directly amplified by the preamplifier, and this noise is mixed.

  In the method of supplying a bias to the input of the differential input preamplifier PA from the center tap of the antenna coil L, the noise generated by the bias circuit becomes the common mode input noise of the differential input amplifier and appears at the output of the differential input preamplifier PA. Disappear. Accordingly, it is possible to realize an AM modulation signal receiving circuit from which thermal noise generated by the bias circuit is removed.

  As described above, according to the tenth embodiment, in addition to the effects of the second to ninth embodiments, it is possible to realize an AM modulation signal receiving circuit in which thermal noise and the like generated by the bias circuit are removed.

[Eleventh embodiment]
[Constitution]
18A to 18D are diagrams showing specific examples of the AM modulation signal detection circuit in the eleventh embodiment of the present invention.

  The AM modulation signal detection circuit in the eleventh embodiment is a circuit corresponding to the conventional circuit and the detection circuit SDet of the AM modulation signal reception circuit in the second to tenth embodiments.

The AM modulation signal detection circuit of FIG. 18A extracts a carrier frequency component from the output signal Vo of the AGC circuit of the AM modulation signal receiving circuit in the conventional circuit and the second to tenth embodiments. A timing extraction unit that outputs a clock pulse CL of a frequency, a clock generation unit that receives the clock pulse CL from the timing extraction unit and outputs a sampling clock pulse SCL, a reference voltage setting unit that outputs a reference voltage VR2, and a sampling It comprises a sampling comparison holding unit that samples and compares the output signal Vo of the AGC circuit and the reference voltage VR2 when the clock pulse SCL is input, outputs the output signal TCO, and holds it until the next sampling clock pulse SCL is input. .

In the AM modulation signal detection circuit of FIG. 18B, the reference voltage setting unit is configured by a reference voltage generation circuit, the timing extraction unit is a limit amplifier LIM that limits and amplifies the output signal Vo of the AGC circuit, and this The first mono multivibrator MM1 that outputs the clock pulse CL using the output of the limit amplifier LIM as a trigger, and the clock generator generates the sampling clock pulse SCL in response to the clock pulse CL of the first mono multivibrator MM1 And a sampling comparison and holding unit, a holding capacitor C having one end connected to the ground, an output Vo and a holding capacitor C of the AGC circuit of the AM modulation signal receiving circuit when the sampling clock pulse SCL is input. A transfer gate TG for bringing the other end of the gate into a conductive state; It is constituted by a comparator Comp which compares the other end voltage and the reference voltage VR2 of the holding capacitor C.

  The first mono multivibrator MM1 creates a predetermined waiting time for adjusting the timing phase, and may be configured by a delay circuit.

In the AM modulation signal detection circuit of FIG. 18C, the reference voltage setting unit is a voltage dividing circuit that divides the output Vp of the peak detection circuit PDet (not shown) in the AGC circuit and outputs the reference voltage VR2. And a timing extraction unit that delays (advances) the phase of the output Vo1 of the AGC circuit and the phase Vo of the output Vo1 of the AGC circuit. And a limit amplifier LIM that limits the output of the second phase shift circuit PS2 and outputs a clock pulse CL, and the clock generator is configured to output the clock pulse. A delay circuit Dt that inverts and delays CL, and a logic synthesis circuit NOR that performs NOR or AND synthesis of the output of the delay circuit Dt and the clock pulse CL and outputs it as a sampling clock pulse SCL. The sampling comparison holding unit is composed of AND and a hysteresis type comparator Comp that holds the output state immediately before being opened when the output signal TCO is determined according to the differential input and the input is opened, and the sampling clock pulse SCL are inputted. The transfer gate TG is in a conductive state and connects the output Vo1 of the first phase shift circuit PS1 and the reference voltage VR2 to the differential input of the hysteresis type comparator Comp.
The first phase shift circuit PS1 and the second phase shift circuit PS2 are for obtaining a waveform whose phase is shifted by π / 2 as shown in FIG. 29 including the delay of the limit amplifier LIM. When the phase can be shifted by π / 2 by the phase shift (delayed phase) by the second phase shift circuit PS2 and the delay of the limit amplifier LIM, the first phase shift circuit PS1 can be omitted.

  In the AM modulation signal detection circuit of FIG. 18D, the sampling comparison holding unit compares the output Vo1 of the first phase shift circuit PS1 with the reference voltage VR2 and outputs a comparison result signal; The comparator Comp output comprises a data input D, a sampling clock pulse SCL as a clock input CK, and a logic output Q as an output signal TCO of the AM modulation signal detection circuit. In addition, a tank tuning circuit using a crystal resonator or the like is included to stabilize the timing of the output CL.

  18B to 18D have independent functions, and may be interchanged between the drawings.

  The clock CL or the sampling clock pulse SCL can be taken out and used as a reproduction clock from a received signal by a device (not shown).

[Operation]
Waveforms for explaining the operation of the detection circuit in this embodiment are shown in FIG. The AM modulation signal output Vo of the conventional circuit and the AGC circuit of the AM modulation signal receiving circuit in the second to tenth embodiments has only two states, a large amplitude state and a small amplitude state. (Refer to the first waveform in FIG. 29)

  In the basic circuit of FIG. 18A, the reference voltage setting unit is intermediate between the peak value (or bottom value) of the large amplitude state and the peak value (or bottom value) of the small amplitude state of the AM modulation signal output Vo. The voltage is output as the reference voltage value VR2.

  The timing extraction unit adjusts the timing of the rising edge (or falling edge) from the AM modulation signal output Vo to the vicinity of the peak value (or the vicinity of the bottom value) of the AM modulation signal output Vo (phase from the AM modulation signal output Vo). The carrier frequency clock pulse CL is generated.

  The clock generator outputs a sampling clock pulse SCL from the carrier frequency clock pulse CL at a timing near the peak value (or near the bottom value) of the AM modulation signal output Vo.

When the sampling clock pulse SCL is “H” (or “L”), the sampling comparison holding unit samples and compares the AM modulation signal output Vo and the reference voltage value VR2, and outputs the comparison result as the output signal TCO. When the sampling clock pulse SCL is “L” (or “H”), the output signal TCO immediately before the change of the sampling clock pulse SCL is held.

  Through the above operation, the peak value (or bottom value) of the large amplitude state and the peak value (or bottom value) of the small amplitude state of the AM modulation signal output signal Vo are extracted at the timing of the sampling clock pulse SCL, and this envelope A signal corresponding to this state is obtained, and a binary output signal TCO corresponding to this state can be extracted from the AM modulation signal output Vo in two states, a large amplitude state and a small amplitude state.

  In the conventional detection circuit SDet using the rectifier Rec2, the capacitor C2, and the resistor R2, C2 and C2 are used to remove the carrier frequency component of the AM modulation waveform having two states of the large amplitude and the small amplitude of the standard radio wave time code (see FIG. 35). When the time constant determined by the product of R2 is increased, a so-called “sag” is generated in the envelope in the transition from the large amplitude state to the small amplitude state, and as a result, the output signal TCO corresponding to the large amplitude state of the comparator Comp is generated. The time span will spread. (See Figure 30)

  In the detection circuit according to the eleventh embodiment, since the peak value (or bottom value) of each carrier amplitude is sampled one after another, the time width of the output signal TCO corresponding to the large amplitude state of the comparator Comp is obtained. The “sag” as described above does not occur, and an accurate time width of the output signal TCO can be obtained.

  Further, if a sampling comparison / holding unit as shown in FIG. 18C or FIG. 18D is used, a capacitive element such as the capacitor C2 of the detection circuit SDet can be dispensed with, which is suitable for an IC.

  Examples of phase shift circuits that shift the phase by π / 2 from the AM modulation signal output signal Vo are shown in FIGS. Capacitance elements are required for these phase-shift circuits and monostable multivibrators that produce a time width equivalent to π / 2, but these are values related to the time domain of about ¼ of the carrier frequency, and have a small capacitance. Therefore, there is a high possibility that IC can be made.

As described above, according to the detection circuit in the eleventh embodiment, the following effects can be obtained.
(1) When receiving a standard radio wave time code transmitted with a time width of two states of a large amplitude and a small amplitude, a detection output with an accurate time width can be obtained as compared with a conventional envelope detection circuit.
(2) Capacitance elements necessary for the conventional envelope detection circuit can be eliminated.

[Twelfth embodiment]
[Constitution]
FIGS. 19A and 19B are diagrams showing specific examples of the AM modulation signal detection circuit according to the twelfth embodiment of the present invention.

    In the AM modulation signal detection circuit according to the twelfth embodiment, the sampling comparison holding unit according to the eleventh embodiment uses the reference voltage VR2 and the output signal Vo of the AGC circuit (or the output of the first phase shift circuit PS1). A comparator Comp that compares the signal Vo1) and outputs a comparison result signal; an odd-n-bit serial-in-parallel-out shift register SHR that uses the output of the comparator Comp as data D and the sampling clock pulse SCL as the clock CK; When the majority of the "H" / "L" outputs of the parallel outputs Q1 to Qn of the shift register SHR are processed and the number of bits of the "H" output is large, the number of bits of the "H" and "H" outputs is small. The majority circuit is configured to output “L”.

[Operation]
The operation of the detection circuit according to the twelfth embodiment is the same as that of the detection circuit according to the eleventh embodiment except for the majority process, and the description thereof is omitted.

  If noise is superimposed on the AM modulation signal output signal Vo at the timing of the sampling clock pulse SCL, the output of the comparator Comp may be in an erroneous output state (the output signal TCO becomes a so-called tooth loss state). However, taking the average value can prevent or reduce this erroneous output state.

  Further, if the amplitude of the AM modulation signal output Vo is gradually increased or decreased due to the influence of the narrow-band bandpass filter BPF in the AGC circuit, the parallel output “H” / “L” of the shift register SHR The timing at which the majority decision is reversed is exactly delayed by a time obtained by multiplying the number of parallel bits by 1/2 the sampling speed, both at the rise and fall, so even if the number of bits in the shift register SHR is increased, time correction is performed. The time of the change point of the accurate AM modulation signal output Vo is obtained.

  FIG. 33 shows a majority circuit example. In a radio timepiece or the like, the output signal TCO is captured by a microcomputer or the like and converted into time information. If it is assumed that the logic output is taken in by a microcomputer or the like, as shown in FIG. 34, the parallel bit output (or serial bit output) of the shift register SHR may be directly taken in.

  The majority processing of digital bits is also equivalent to analog signal averaging processing, and a resistor R is connected before the capacitor C in FIG. 18B to form an average value circuit by CR (see FIG. 19B). The AM modulation signal output Vo may be averaged and compared with the reference voltage VR2.

  As described above, in the detection circuit according to the twelfth embodiment, when noise is superimposed on the AM modulation signal output Vo, the output of the comparator Comp is prevented from being in an erroneous output state, or Can be reduced.

  The circuit of FIG. 20 is obtained by adding the idea of the receiving circuit in the fifth embodiment to the detection circuit in the eleventh embodiment or the twelfth embodiment, and detecting the peak in the AGC circuit. The circuit PDet does not require the rectifier Rec1 and the discharge path resistor R1, and the peak hold capacitor C1 can be reduced to such an extent that it can be built in the IC.

  The use of the power supply circuit Reg that can control the power supply from the external power supply VDD to each circuit by the control signal PON (creation of an operation on state and a standby standby state, or a constant supply power supply voltage) is described above. It is effective when applied to each of the embodiments 2-12.

5 is a diagram illustrating a specific example of a variable gain amplifier circuit according to the first embodiment. FIG. 5 is a diagram illustrating a specific example of a variable gain amplifier circuit according to the first embodiment. FIG. 5 is a diagram illustrating a specific example of a variable gain amplifier circuit according to the first embodiment. FIG. It is a circuit diagram showing a specific example of a conventional variable gain amplifier for AGC. It is a circuit diagram showing a specific example of a conventional variable gain amplifier for AGC. It is a circuit diagram showing a specific example of a conventional variable gain amplifier for AGC. It is a circuit diagram which shows the basic structural example of RF receiving part of the conventional radio timepiece. It is a figure which shows the specific example of the AM modulation signal receiving circuit in 2nd Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 3rd Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 4th Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 5th Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 6th Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 7th Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 8th Embodiment. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 9th Embodiment. It is the figure which showed angle (theta) of the antenna coil with respect to the electromagnetic wave arrival direction. It is the figure which showed the specific example of the AM modulation signal receiving circuit in 10th Embodiment. It is the figure which showed the specific example of the detection circuit for AM modulation signals in 11th Embodiment. It is the figure which showed the specific example of the detection circuit for AM modulation signals in 12th Embodiment. It is a figure which shows the circuit example which added the idea of the receiving circuit in 5th Embodiment to the detection circuit in 11th Embodiment or 12th Embodiment. It is a figure which shows the specific example of the addition circuit of FIG. 12, FIG. 13 in 6th and 7th embodiment. FIG. 17 is a diagram illustrating a specific example of an adder circuit including polarity switching of the preamplifier PA2 of FIGS. 14 and 15 in the eighth and ninth embodiments. FIG. 17 is a diagram illustrating a specific example of an adder circuit including polarity switching of the preamplifier PA2 of FIGS. 14 and 15 in the eighth and ninth embodiments. It is a figure which shows the example of a bias circuit. FIG. 10 is a diagram in which the OR circuit and the transfer gate TG1 in FIGS. 9C and 9E in the third embodiment are replaced with a parallel circuit of two transfer gates TG1 and TG2. FIG. 10 is a diagram in which the AND circuit and the transfer gate TG1 in FIGS. 10A and 10C in the fourth embodiment are replaced with a series circuit of two transfer gates TG1 and TG2. It is a detailed circuit diagram of FIG.10 (b) in 4th Embodiment. It is a figure which shows the specific example of the timer circuit TM of FIG. 14 in 3rd Embodiment. It is a wave form diagram of each part of a detection circuit. It is the figure which compared the conventional Comp output waveform in a large amplitude state with the Comp output waveform in 11th Embodiment. It is a figure which shows the specific example of the phase shift circuit of FIG.18 (c) in FIG. 18 (d) in 11th Embodiment. It is a figure which shows the specific example of the phase shift circuit of FIG.18 (c) in FIG. 18 (d) in 11th Embodiment. It is a figure which shows the specific example of the majority circuit of FIG. 27 in 12th Embodiment. It is a figure which shows the specific example of the majority circuit of FIG. 27 in 12th Embodiment. It is a waveform diagram of a standard radio wave. It is the figure which showed typically the example of an input / output waveform of the band pass filter BPF in the gain control amplifier part GCA-B in 5th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment. It is the figure which showed the example of a waveform at the time of carrying out the analog addition of 2 waves in 7th Embodiment and 9th Embodiment.

Explanation of symbols

T, T2 differential pair transistor RL1, RL2 additional resistance Is, Is1, Is2 sink current circuit T3, T4 transistor Vgc control voltage GCA-B gain control amplifier part SDet envelope detection circuit Comp comparison circuit PDet peak detection circuit Rec1, Rec1a, Rec1b, Rec2a, REc2b Rectifier circuit TG1, TG2 Transfer gate TM Timer circuit D Delay circuit PA1, PA2 Preamplifier Add addition circuit GCAb Variable gain amplifier BPF1, BPF2 Bandpass filter PS1, PS2 Phase shift circuit LIM Limit amplifier SMR , MM1 Mono multivibrator

Claims (11)

In an AM modulation signal receiving circuit that receives an AM modulation signal Vi in two states of a large amplitude state and a small amplitude state and identifies the two states,
A carrier frequency component is extracted from the output signal Vo of the AGC circuit for controlling and amplifying the received AM modulation signal to a predetermined amplitude value corresponding to the two states of the large amplitude state and the small amplitude state, and the output signal Vo of the AGC circuit is obtained. A timing extractor that outputs a clock pulse CL that is timed to the peak position of the amplitude of
A clock generator that inputs the clock pulse CL and outputs a sampling clock pulse SCL that is timed to the peak position;
A reference voltage setting unit that outputs a reference voltage VR2,
A sampling comparison holding unit that outputs the output signal TCO by sampling and comparing the output Vo of the AGC circuit and the reference voltage VR2 when the sampling clock pulse SCL is input, and holds it until the next sampling clock pulse SCL is input. A detection circuit characterized by comprising. 2. The detection circuit according to claim 1, wherein the reference voltage setting unit is configured by a voltage dividing circuit that outputs a reference voltage VR2 obtained by dividing the output signal Vp of the peak detection circuit (PDet) in the AGC circuit. And a detection circuit.   2. The detection circuit according to claim 1, wherein the timing extraction unit first outputs a clock pulse CL by using a limit amplifier (LIM) for limit amplification of the output Vo of the AGC circuit and a trigger of the output of the limit amplifier (LIM). And a mono multivibrator (MM1). 2. The detection circuit according to claim 1, wherein the timing extraction unit causes the phase of the output signal Vo of the AGC circuit to advance (delay) and outputs the output Vo <b> 1 to the sampling comparison holding unit. (PS1),
A second phase shift circuit (PS2) that outputs the output signal Vo of the AGC circuit with the phase being delayed (advanced), and the output of the second phase shift circuit (PS2) is limited and amplified to generate a clock pulse. A detection circuit comprising a limit amplifier (LIM) that outputs CL.   2. The detection circuit according to claim 1, wherein the clock generation unit includes a second mono multivibrator (MM2) that receives the clock pulse CL and generates a sampling clock pulse SCL.   2. The detection circuit according to claim 1, wherein the clock generation unit performs NOR or AND synthesis on a delay circuit (Dt) that inverts and delays the clock pulse CL, and an output of the delay circuit (Dt) and the clock pulse CL. And a logic synthesis circuit NOR / AND that outputs the sampling clock pulse SCL. 2. The detection circuit according to claim 1, wherein the sampling comparison holding unit includes a holding capacitor C having one end connected to the ground, an output Vo of the AGC circuit and the other end of the holding capacitor C when the sampling clock pulse SCL is input. A transfer gate (TG) that makes the connection between them and a comparator (Co) that compares the other end voltage of the storage capacitor C and the reference voltage VR2.
mp) and a detection circuit.   7. The detection circuit according to claim 4, wherein the sampling comparison holding unit is a hysteresis for holding the logic output state immediately before the release when the output signal TCO is determined according to the differential input and the input is opened. When the sampling clock pulse SCL is input, the comparator is brought into a conducting state and the output Vo1 of the first phase shift circuit (PS1) and the reference voltage VR2 are connected to the hysteresis comparator (Comp). And a transfer gate (TG) connected to the differential input. 2. The detection circuit according to claim 1, wherein the timing extraction unit causes the phase of the output signal Vo of the AGC circuit to advance (delay) and outputs the output Vo <b> 1 to the sampling comparison holding unit. (PS1), a second phase shift circuit (PS2) that delays (advances) the phase of the output signal Vo of the AGC circuit and outputs it to the tank tuning circuit, and the output of the tank tuning circuit is limit amplified. And a limit amplifier (LIM) that outputs a clock pulse CL,
The sampling comparison holding unit includes a comparator (Comp) for comparing the output signal Vo1 of the first phase shift circuit (PS1) and the reference voltage VR2, and an output of the comparator (Comp) as a data input D. A detection circuit comprising: a D-type flip-flop that outputs the sampling clock pulse SCL as a clock input CK and a logic output Q as an output signal TCO of the AM modulation signal detection circuit.   8. The detection circuit according to claim 7, wherein a resistor R is inserted at a connection point between the transfer gate (TG) of the sampling comparison holding unit and the holding capacitor C. 10. The detection circuit according to claim 9, wherein the D-type flip-flop of the sampling comparison holding unit is an odd-numbered n-bit serial having an output of the comparator (Comp) as a data input D and the sampling clock pulse SCL as a clock input CK. In-parallel out shift register (SHR) and "H" / "L" output of parallel outputs Q1-Qn of the shift register (SHR) are majority processed. If the number of bits of "H" output is large, "H" A detection circuit characterized by comprising "" and a majority circuit that outputs "L" when the number of bits of "H" output is small.

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