JP4239830B2 - PLL circuit with self-test function - Google Patents

Description

  The present invention relates to a PLL circuit that outputs a signal that is phase-synchronized with a reference signal, and more particularly to a PLL circuit that has a function of identifying the cause of a conduction failure that has occurred inside the circuit.

  2. Description of the Related Art Conventionally, an IC including a PLL is widely used in an electronic device by being incorporated in a digital circuit using a process such as a discrete (single function semiconductor) component or a C-MOS or a circuit in which digital-analog is mixed.

  The PLL circuit inputs a signal oscillated by the VCO and a reference signal stably oscillated by a crystal or the like to a phase comparator, smooths the output and returns it to the VCO, thereby obtaining a phase characteristic close to that of the reference signal. This is a general-purpose circuit that obtains a VCO oscillation output.

  FIG. 4 shows an example of a conventional PLL circuit. In general, a PLL circuit is a unit having a functional unit excluding a reference signal oscillator that uses a crystal for oscillation of a reference signal and a smoothing circuit that requires a large capacity capacitor to smooth the output signal of the phase comparator. (LSI, IC, circuit board, etc.). Hereinafter, this is expressed as a circuit unit.

  As shown in FIG. 4, the conventional PLL circuit has a configuration in which most of the electronic components constituting the circuit are incorporated in the circuit unit, so that problems due to poor connection are unlikely to occur inside the circuit unit. However, since there is still a possibility that a connection failure will occur at the external connection terminal of the circuit unit, the cause of the failure may be inspected in the manufacturing process of mass-produced electronic devices or when investigating the cause of failure. Need to be analyzed promptly.

  In particular, in recent years when electronic circuits and electronic components have been mounted with high density, small packages, multiple pins, and electrode pitches have been reduced, the conventional method of manually inspecting a probe with a terminal is not used. Have difficulty.

  For this reason, it is required to incorporate a circuit that outputs a signal for detecting whether or not a defect occurs in the connection terminal of the circuit unit into the circuit unit to have a self-test function (BIST). ing.

As an example of a conventional logic circuit having a self-test function, there is a “semiconductor integrated circuit” disclosed in Patent Document 1.
The invention disclosed in Patent Document 1 performs a self-test of a logic circuit using a system clock output from a PLL circuit.
JP 2001-183423 A

  However, as in the invention disclosed in Patent Document 1, the conventional self-test circuit adds a test-dedicated circuit that has nothing to do with the original operation to the logic circuit, which increases the circuit scale. This hinders downsizing and weight reduction of electronic devices.

  In the case of digital signal inspection, it is possible to use connection confirmation between ICs represented by JTAG (boundary scan) defined in IEEE1149.1, but this is also applied to analog signal inspection. I can't do it.

  In general, the PLL circuit can output a signal (lock detector) for detecting lock, but even if this signal alone can detect that there is a defective portion in the PLL circuit, the cause cannot be specified.

  As described above, the conventional PLL circuit applied to the analog circuit or the electronic circuit in which digital / analog is mixed is not capable of specifying the cause of the conduction failure generated at the connection portion between the circuit unit and the smoothing circuit constituting the PLL. It was not easy.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a PLL circuit having a self-test function capable of easily confirming a connection state between a circuit unit constituting the PLL and a smoothing circuit.

To achieve the above object, the present invention provides a phase comparator to which a signal oscillated by a VCO and a reference signal are input, a charge pump for raising and lowering the voltage of an output signal of the phase comparator, A PLL circuit that has a smoothing circuit that smoothes a signal output from a charge pump and inputs the signal to a VCO, and causes the VCO to oscillate a signal having substantially the same phase characteristics as a reference signal. The circuit unit including the pump and the VCO and the smoothing circuit configured separately from the circuit unit are electrically connected via a contact portion included in the circuit unit, and the circuit unit is a capacitive element constituting the smoothing circuit. and discharging means for forcibly discharging device, a charging means for charging the capacitive elements constituting the smoothing circuit, the reference signal is inputted, a counter for counting up in response to the reference signal Based on the count value of the counter, there is provided a PLL circuit having a self-test function, characterized in that it comprises a measurement means for measuring a time required for charging the capacitive element of the smoothing circuit is completed .

In any of the above configurations, after discharging the capacitive element constituting the smoothing circuit by driving the discharging means, the capacitive element constituting the smoothing circuit is charged by driving the charging means, and the circuit unit It is preferable to further include a determination unit that determines an electrical connection state between the contact point and the smoothing circuit based on the time measured by the measurement unit.

  In any of the above configurations, the discharge means outputs a test discharge signal, a means for switching the input signal to the charge pump to the test discharge signal, and the test discharge signal is input to the charge pump. In this case, it is preferable that the smoothing circuit is configured by means for directly or indirectly connecting the capacitive element of the smoothing circuit to the ground.

  In any of the above configurations, the charging means outputs means for outputting a test charge signal, means for switching the input signal to the charge pump to the test charge signal, and the test charge signal is input to the charge pump. In this case, it is preferable that the capacitive element of the smoothing circuit is constituted by means for directly or indirectly connecting the capacitive element of the smoothing circuit to a power source or a constant current source.

  In any of the above configurations, it is preferable that the circuit unit is integrated with the semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, the PLL circuit provided with the self test function which can confirm easily the connection state of the circuit unit which comprises PLL, and a smoothing circuit can be provided.

A preferred embodiment of the present invention will be described. FIG. 1 shows the configuration of a PLL circuit that preferably implements the present invention. The PLL circuit according to the present embodiment includes a circuit unit 10 including a phase comparator 11, a counter 12, a timing control circuit 13, a changeover switch 14, a latch circuit 15, a charge pump 16 and a VCO 17, a reference oscillator 20, and a smoothing circuit 30. And have.
The output signal fin of the VCO 17 and the reference signal fref (rin) from the external reference oscillator 20 are input to the phase comparator 11. The phase comparator 11 compares these phases and outputs the comparison result to the changeover switch 14. The changeover switch 14 inputs either the output result from the phase comparator 11 or the signal from the timing control circuit 13 to the charge pump 16. The charge pump 16 outputs an H pulse or an L pulse to the smoothing circuit 30 according to a signal input from the phase comparator 11 via the changeover switch 14.

  The H pulse or L pulse output from the charge pump 16 charges or discharges the smoothing circuit 30 via the terminal P as a constant current source, and changes the potential of the terminal P. The H pulse or L pulse is also input to the VCO 17 to change its oscillation frequency. This feedback loop is generally known as a PLL, and causes the VCO 17 to oscillate a signal that is phase-synchronized with the reference signal fref.

  The timing control circuit 13 starts an operation for executing a self test when an operation start signal (trigger signal) of the self test circuit is input from a register (not shown). The timing control circuit 13 turns on and off signals output to the changeover switch 14 and the counter 12 according to a predetermined procedure when the self test is executed, and controls a series of operations of the self test. The on / off timing of the signal may be controlled by a command in a register (not shown), or the specified time may be measured by counting the pulses of the reference signal inside the timing control circuit 13.

  The signal A switched by the changeover switch 14 and input to the switch on the low potential side of the charge pump 16 discharges the charge stored in the capacitor C constituting the smoothing circuit 30. On the other hand, the signal B switched by the changeover switch 14 and input to the high potential side switch of the charge pump 16 causes the capacitor C constituting the smoothing circuit 30 to store charges.

  The counter 12 is reset according to the signal input from the timing control circuit 13 and counts up according to the reference signal fref.

  The latch circuit 15 latches the output signal (count value) of the counter 12 in accordance with the frequency comparison result output from the phase comparator 11 and measures the time from reset release.

  The operation of the self test circuit will be described. When the timing control circuit 13 receives an operation start signal of the self-test circuit from a register (not shown), the timing control circuit 13 starts the operation. First, the timing control circuit 13 outputs a signal C as a reset signal at a predetermined timing (FIG. 2a), and resets the counter 12. At the same time, the timing control circuit 13 outputs the signal D to the changeover switch 14 and switches the signal input to the charge pump 16 from the comparison result output from the phase comparator 11 to the output A and output B of the timing control circuit 13. Further, the timing control circuit 13 turns on the signal A, switches on the low potential side switch of the charge pump 16, and discharges the charge of the smoothing circuit 30 connected to the terminal P. As a result, the potential at the point P gradually decreases and reaches 0 V (FIG. 2b).

  After a sufficient time has elapsed for the potential at the point P to drop to 0 (FIG. 2c), the timing control circuit 13 turns off the signal A and turns on the signal B. Further, the timing control circuit 13 stops the output of the signal C that is a reset signal and starts the operation of the counter 12. The signal B that has been turned on is input to the switch on the high potential side of the charge pump 16, and charges are stored in the smoothing circuit 30 connected to the terminal P. Thereby, the potential at the point P gradually increases.

  When the potential at the point P reaches a value corresponding to the frequency that the VCO 17 originally locks (FIG. 2d), the frequency determination output of the phase comparator 11 is inverted, and the latch circuit 15 sets the value of the counter 12 according to the signal. Latch. The latch circuit 15 outputs the value to a register (not shown). This value represents the time required for the capacitive element (capacitor) C constituting the smoothing circuit 30 to be charged. Further, this value is approximately proportional to the capacity of the capacitor C constituting the smoothing circuit 30 and can be calculated based on the current value of the constant current source of the charge pump 16 and the lock range of the VCO 17, so that it is read from a register (not shown). If the elapsed time (count value) is within a predetermined range based on the time corresponding to the calculated value, it can be said that the connection state at point P is normal.

  Next, a case where there is an abnormality in the connection state at point P will be described. When the conduction at the point P becomes poor and the circuit unit 10 and the smoothing circuit 30 are in an insulated state, the point P is electrically separated from the smoothing circuit 30. Therefore, the capacitance at the point P is the terminal of an IC or the like. It becomes capacity only and becomes extremely small. For this reason, the time required for charging is extremely shortened.

  When the point P is short-circuited to the ground for some reason, the frequency does not increase even after the signal A is turned off, the signal B is turned on, and the signal D is stopped. The counter value is not latched within this period.

  When the point P and the power supply are short-circuited, immediately after the signal A is turned off, the signal B is turned on, and the signal D is stopped, the frequency rises instantaneously. Is latched at a timing extremely earlier than the time corresponding to the calculated value.

  The result that the count value is latched at a timing earlier than the calculated value is the same between the case of poor conduction and the case of short-circuiting with the power source. However, in general, in the case of normal operation, in the case of poor continuity, it is locked although it is unstable, but in the case of short-circuiting with the power supply, the oscillation output is fixed at the upper limit, so it is not locked . Therefore, these differences can be identified by monitoring the signal output from the lock detector LD.

  As described above, in the PLL circuit according to the present embodiment, the method of changing the potential at the point P during the self-test operation differs depending on the connection state of the smoothing circuit 30. Therefore, the connection state between the circuit unit 10 and the smoothing circuit 30 constituting the PLL can be easily confirmed without manually applying a probe to the terminal.

In addition, the said embodiment is an example of suitable implementation of this invention, and this invention is not limited to this.
For example, in the above embodiment, the smoothing circuit 30 as shown in FIG. 3A applied to the charge pump in the constant current mode has been described as an example. However, the constant voltage mode as shown in FIG. The smoothing circuit may be applied to the charge pump.
In the above embodiment, the PLL circuit having the basic configuration is taken as an example. However, the PLL circuit having another configuration (for example, outputting an integer multiple of a reference frequency widely used in a local oscillator of a radio circuit) Needless to say, the present invention can also be applied to such a PLL circuit.
As described above, the present invention can be variously modified.

It is a figure which shows the structure of the PLL circuit which implemented this invention suitably. It is a figure which shows the change of the electric potential of P point at the time of a self test operation | movement. It is a figure which shows the structural example of a charge pump. It is a figure which shows the structure of the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit unit 11 Phase comparator 12 Counter 13 Timing control circuit 14 Changeover switch 15 Latch circuit 16 Charge pump 17 VCO
20 Reference oscillator 30 Smoothing circuit

Claims (5)

A phase comparator to which a signal oscillated by a VCO and a reference signal are input; a charge pump for raising and lowering a voltage of an output signal of the phase comparator; and a signal output from the charge pump is smoothed to A PLL circuit for causing the VCO to oscillate a signal having substantially the same phase characteristics as the reference signal,
The circuit unit including the phase comparator, the charge pump, and the VCO, and the smoothing circuit configured separately from the circuit unit are electrically connected via a contact portion included in the circuit unit,
The circuit unit is
Discharging means for forcibly discharging the capacitive element constituting the smoothing circuit;
Charging means for charging the capacitive element constituting the smoothing circuit;
A counter that receives the reference signal and counts up according to the reference signal;
A PLL circuit having a self-test function, comprising: a measuring unit that measures a time required to complete charging of the capacitive element of the smoothing circuit based on a count value of the counter . After the discharging means is driven to discharge the capacitive elements constituting the smoothing circuit, the charging means is driven to charge the capacitive elements constituting the smoothing circuit, and the circuit unit and the smoothing circuit PLL circuit an electrical connection through the contact section, with a self-test function according to claim 1, further comprising a determination means based on the time the measuring means has measured the. The discharging means is
Means for outputting a test discharge signal;
Means for switching the input signal to the charge pump to the test discharge signal;
If the test discharge signal is inputted to the charge pump, the directly or indirectly according to claim 1 or 2, characterized in that it is constituted by means for connecting the capacitive element of the smoothing circuit to ground PLL circuit with self-test function. The charging means is
Means for outputting a test charging signal;
Means for switching the input signal to the charge pump to the test charge signal;
A means for directly or indirectly connecting a capacitive element of the smoothing circuit to a power source or a constant current source when the test charging signal is input to the charge pump. A PLL circuit having a self-test function according to any one of 1 to 3 . It said circuit unit, PLL circuit having a self-test function according to any one of the preceding claims, characterized in that it is formed are integrated into the semiconductor device 4.

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