JP4235047B2 - Memory device with improved safety of stored data and data processing device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device and a data processing device, and is used in, for example, a computer system that requires high reliability for automobiles, security control, and the like, and uses the memory device and the memory device that increase the safety of stored data. Related to the data processing apparatus.
[0002]
[Prior art]
For example, in order to easily realize advanced system functions in automobile engine control, security equipment, and the like, a micro controller unit (MCU) is used. Many of such micro controller units incorporate a memory device. By using such a micro controller unit and appropriately designing a program for operating the micro controller unit, various functions can be easily achieved with a relatively simple device configuration. And the reliability of the system using the micro controller unit can be improved to some extent by devising the program. For example, in an automobile engine control application, if a parameter value deviates from a predetermined range, an adverse effect due to a failure can be prevented by stopping or controlling the operation of the engine by a program. As prior art patent documents, there are JP-A-8-153039 and JP-A-2002-244995.
[0003]
[Problems to be solved by the invention]
However, even in a system using such a conventional micro controller unit (MCU), if the data stored in the memory device built in the MCU or connected to the MCU is destroyed, the system can operate reliably. Can no longer be expected.
[0004]
In general, in an MCU, if an accidental hardware reset sequence such as a watchdog reset occurs during a write operation to the memory, it cannot be guaranteed that the proper memory contents are maintained. Furthermore, if a write sequence that requires a plurality of cycles for writing is interrupted, appropriate memory contents cannot be maintained, and the safety of stored data is threatened.
[0005]
Such safety of the memory contents often does not pose a problem in an MCU having a small capacity memory. This is because in the MCU having such a small capacity memory, the memory contents are written in a short time and can be updated or initialized. However, it takes a long time to initialize an MCU having a large-capacity memory, and therefore the response speed for initialization is slow. For this reason, in an MCU having a large-capacity memory, there is a high possibility that the safety of stored data is threatened by an accidental event as described above.
[0006]
Therefore, an object of the present invention is to provide a memory device that increases the safety of stored data.
[0007]
Another object of the present invention is to ensure that data is accurately written even in a memory device that requires a relatively long time for data writing, such as when multiple cycles are required for data writing. .
[0008]
Still another object of the present invention is to provide a memory device in which the safety of memory contents is not threatened by an accidental reset sequence or interruption of a write operation, and a data processing device using such a memory device. There is.
[0009]
Still another object of the present invention is to provide a memory device having high reliability with respect to the safety of stored data and a data processing device using such a memory device.
[0010]
[Means for Solving the Problems]
According to one aspect of the present invention, a memory device with improved safety of stored data is provided, the memory device including a memory unit for storing data, and a buffer for temporarily storing data to be written to the memory unit. A semaphore register that stores information indicating whether or not data can be written from the buffer to the memory unit. When writing to the memory unit, the semaphore register is set in advance to lock the memory unit. The write data is written into the buffer in a plurality of times, and after the data is stored in the buffer, the memory unit is unlocked from the buffer when the semaphore register is set and the memory unit is unlocked. It is characterized in that data is written at once.
[0011]
In the memory device, the contents of the buffer are advantageously discarded if an accidental reset event occurs that impairs the integrity of data writing to the buffer while the semaphore register is set. It is.
[0012]
In addition, if the write operation to the buffer is interrupted while the semaphore register is set, it is advantageous to discard the contents of the buffer.
[0013]
Furthermore, a data bus for inputting write data to the buffer may be provided, and the transmission capacity of the data bus may be smaller than the capacity of the buffer.
[0014]
Furthermore, data can be read directly from the memory unit.
[0015]
According to another aspect of the present invention, a data processing device is provided, the data processing device comprising: a central processing unit (CPU); and a memory device, a memory unit for storing data, and the memory unit A buffer for temporarily storing data to be written to the memory, and a semaphore register for storing information indicating whether data can be written from the buffer to the memory unit. Set to lock the memory unit, write data to the buffer divided into multiple times, and after the data is stored in the buffer, the semaphore register is unset and the memory unit is unlocked A memory device for writing data from the buffer to the memory unit at a time. Executes a job to be executed by dividing it into a plurality of tasks, checkpoints are provided between the tasks, and checkpoints are recorded by writing checkpoint data to the memory device at the end of each task. In addition, the initial state of the checkpoint is reproduced by reading the checkpoint data from the memory device at the start of each task.
[0016]
The checkpoint recording is performed by sequentially writing checkpoint data necessary for the central processing unit to resume a task at each checkpoint to the buffer of the memory device, and writing data to the buffer during the checkpoint recording. When the checkpoint is recorded by collectively transferring the data written in the buffer to the memory unit when there is no accidental reset event that impairs the integrity of the data or interruption of data writing to the buffer Convenient.
[0017]
If an accidental reset event that impairs the integrity of the data write to the buffer occurs while the semaphore register is set, or if the write operation to the buffer is interrupted halfway, The content can be configured to be discarded.
[0018]
The accidental reset event may be caused by resetting the central processing unit when an abnormal operation of the central processing unit is detected by a watchdog timer.
[0019]
Alternatively, the accidental reset event may be caused by resetting the clock oscillator and the central processing unit in response to detecting the oscillation stop of the clock oscillator.
[0020]
Further, the accidental reset event may be caused by resetting the central processing unit when an instantaneous drop in power supply voltage supplied to the data processing unit is detected.
[0021]
The data processing device may be a micro controller unit (MCU).
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration of a memory device according to an embodiment of the present invention. The memory device shown in FIG. 1 includes a memory unit 11, a buffer 13, an address decoder 15, a selector 17, a semaphore register 19, and the like.
[0023]
The memory unit 11 includes a plurality of memory cells 11a. Each memory cell 11a includes, for example, a flip-flop, a transparent latch, and others. The buffer 13 is provided for temporarily storing data to be written to the memory unit 11, and includes a plurality of bit cells 13a. Each bit cell 13a includes a flip-flop, a transparent latch, and the like, like the memory cell 11a of the memory unit 11. The address decoder 15 decodes the write address input from the address bus 23 and generates a control signal supplied to the control terminal G of each bit cell 13 a of the buffer 13. Further, the selector 17 outputs read data corresponding to the address specified by the address bus 27 in the output from the memory unit 11 to the read data bus 29.
[0024]
A semaphore register 19 is constituted by, for example, a flip-flop, receives a lock instruction signal (LOCK) and a commit signal (COMMIT), that is, a write transfer instruction signal, and an enable signal (ENABLE) according to the logical state of these signals. ) And an internal commit signal. More specifically, the semaphore register 19 receives the lock instruction signal and outputs an internal commit signal to lock the memory unit 11, that is, write prohibition. Further, an enable signal is output and supplied to the address decoder 15, and data writing to the buffer 13 is permitted according to the address data from the address bus 23. The semaphore register 19 further receives an input commit signal, supplies an internal commit signal to the memory unit 11, and allows data writing from the buffer 13 to the memory unit 11.
[0025]
Each memory cell 11a of the memory unit 11 has a data input D that receives the output Q of the corresponding bit cell 13a of the buffer 13, a control terminal G that receives an internal commit signal from the semaphore register 19, and an output terminal that outputs a stored signal. Q is provided. The output terminal Q is connected to the selector 17.
[0026]
Each bit cell 13 a of the buffer 13 includes a data input terminal D, a control terminal G, and an output terminal Q, similarly to the memory cell 11 a of the memory unit 11. The data input terminal D is connected to the write data bus 25, and the control terminal G is connected to the output of the address decoder 15.
[0027]
The memory device having such a configuration is incorporated in a micro controller unit (MCU) as described later, for example, and stores data that requires safety when the central processing unit (CPU) of the MCU executes a program. Used to do.
[0028]
Next, the operation of the memory device shown in FIG. 1 will be described. As described above, when the CPU operates in accordance with a program and attempts to update the memory contents by writing to the memory device, first, a lock signal is supplied to the semaphore register 19 by the program, and the semaphore register 19 is sent to the memory unit 11. Lock the writing of That is, the internal commit signal output from the semaphore register 19 is negated, for example, logic “0”. During this locked state, data writing to the memory unit 11 is not performed, and write data is first written to the buffer 13. However, in reading from the memory device of FIG. 1, the selector 17 selects the stored data in the memory unit 11 in accordance with the address signal supplied from the address bus 27, and the read data can be output to the read data bus 29.
[0029]
In the memory lock state, the semaphore register 19 affirms the enable signal, for example, logic “1”. In response to this, the write address data supplied from the address bus 23 is supplied to the address decoder 15, and the data from the write data bus 25 is written into the selected bit cell 13 a of the buffer 13. In the MCU, the number of bits of the buffer 13, that is, the number of bit cells 13a is often larger than the number of bits of the write data bus 25. In such a case, data writing to the buffer 13 is performed by a plurality of write cycles.
[0030]
During the writing of data to the buffer 13, for example, the CPU may be reset. For example, when it is detected that the CPU has a hardware problem and does not operate normally, the CPU is reset to cope with the failure and protect the system including the CPU. Such a reset corresponds to, for example, a case where a watchdog reset is performed by a time-up of a watchdog timer (not shown) built in the MCU. When such a reset is performed, the program processing of the system using the MCU is interrupted, and the processing is executed again from the beginning of the program.
[0031]
Therefore, when such a reset occurs in the middle of data writing to the buffer 13, the contents of the buffer 13 are discarded, and data transfer from the buffer 13 to the memory unit 11 described later is not performed.
[0032]
When the data writing to the buffer 13 is completed, the CPU releases the lock to the semaphore register 19 and supplies a commit signal. In response to this, the semaphore register 19 affirms the internal commit signal, for example, sets the logic to “1”, and unlocks the writing to the memory unit 11. Therefore, the data stored in each bit cell 13a of the buffer 13 is written into the corresponding memory cell 11a of the memory unit 11 at a time. That is, the commit operation is performed in response to the unlock operation of the semaphore register.
[0033]
In this way, if an accidental reset sequence occurs while the memory is locked, the contents of the buffer are discarded, and therefore the data stored in the memory unit 11 is not changed. Since writing to the memory unit 11 is performed at once by the commit operation, the stored data in the memory unit 11 is updated to appropriate data without being destroyed, and kept in a safe state.
[0034]
FIG. 2 shows an example of a data processing device including a memory device as described above, i.e., a commitable memory device. Such a data processing apparatus can also be configured on, for example, one integrated circuit chip as a micro controller unit (MCU), for example. 2 includes a central processing unit (CPU) 31, a watchdog timer 35, a committable memory 37, a random access memory (RAM) 39, and peripheral devices 41 connected to the CPU 31 by a bus 33. Composed.
[0035]
The watch dog timer 35 detects, for example, that the CPU 31 is causing an abnormal operation by monitoring the operation timing, and resets the CPU 31. As will be described later, the committable memory 37 includes registers, flags, and other checkpoints necessary for resuming the operation of the data processing device at checkpoints provided between tasks of the job executed by the CPU 31. It is used to store data. The RAM 39 stores programs executed by the CPU 31, for example, and processing data. The peripheral device 41 is a peripheral device that is controlled by the MCU, such as an engine control of an automobile, for example, and is often provided outside the MCU.
[0036]
In the data processing apparatus shown in FIG. 2, the CPU 31 executes a predetermined job for controlling the peripheral device 41 in accordance with a program stored in the RAM 39. The predetermined job is sequentially executed by being divided into a plurality of tasks, and checkpoints are provided between the tasks. At each checkpoint, the checkpoint is recorded by storing in the committable memory 37 the status data of each part of the data processing device at the checkpoint, such as registers, flags, and other data necessary for the operation of the data processing device. It is. When starting a task from each checkpoint, the task for reading out necessary data from the committable memory 37 is initialized. This allows the central processing unit to safely execute the job without being affected by disturbances, as will be described in more detail later. Note that the watchdog timer 35 in FIG. 2 detects an abnormality when the CPU 31 is executing a task and the CPU 31 is not executing a program to be executed due to an abnormal operation of the CPU 31, and the CPU 31 detects the abnormality. Is reset asynchronously, that is, irrespective of the operation of the CPU 31.
[0037]
FIG. 3 shows another configuration example of the data processing apparatus in which the committable memory is used. 3 replaces the watchdog timer 35 in the data processing apparatus of FIG. 2 or in addition to the watchdog timer 35, the clock oscillator 45 having the crystal unit 43 and the oscillation state of the clock oscillator are monitored. The clock monitor 47 is provided. The other parts may be the same as in FIG. 2 and are indicated with the same reference numerals.
[0038]
In the central processing unit of FIG. 3, for example, when the crystal resonator or the crystal oscillator 43 stops oscillating due to a disturbance or starts abnormal oscillation, the clock monitor 47 detects such an abnormal state, and the clock Asynchronous with the oscillator 45 and the CPU 31, that is, regardless of the operation of the CPU, is reset and restarted.
[0039]
FIG. 4 shows another configuration example of the data processing apparatus using the committable memory according to the present invention. The data processing apparatus in FIG. 1 includes a stabilized power supply 49 that generates a power supply voltage for operating the data processing apparatus from a commercial power supply, and an instantaneous power failure detection unit 51 that detects an instantaneous drop in the commercial power supply. . Other parts may be the same as those of the data processing apparatus of FIG. 2, and the same parts are denoted by the same reference numerals.
[0040]
In the data processing apparatus shown in FIG. 4, when the data processing apparatus is operating with a commercial power supply, for example, when an instantaneous power reduction of the commercial power supply is detected, the CPU 31 is reset to an unstable state. Stop safely before it becomes. In this case, the system of the data processing apparatus cuts off the power to the other parts of the system while holding the memory data with a backup power source (not shown) and waits for the power to be restored. In this case, resetting is performed asynchronously for the purpose of safely stopping the CPU 31.
[0041]
2, 3, and 4, only the circuit portion that performs reset by the watchdog timer 35, reset by the clock monitor 47, and reset by the instantaneous power failure detection circuit 51 is shown. However, it is clear that a plurality of types of circuit parts may be provided in the data processing device in any combination of these circuit parts.
[0042]
Next, in the data processing apparatus as described above, how to execute a highly reliable job in which stored data is kept safe by providing a committable memory will be described in detail.
[0043]
As an example, when there is a job with a long calculation time, if this job is executed under a bad environment such as a lot of noise, the execution of the job may be interrupted due to the influence of noise during the execution. For example, as shown in FIG. 5, when there is no disturbance due to noise or the like, even a job having a long calculation time can be executed without being interrupted from the start to the end of the job. On the other hand, when there is a disturbance, important data may be destroyed by the disturbance after the job starts, and the job may be interrupted. In particular, the longer the time from the start to the end of the job, the more susceptible to disturbances, and if the job is interrupted, it is necessary to start over from the beginning, and the overall job processing time is exponential It will be long.
[0044]
In order to eliminate such inconvenience, the job is divided into a plurality of tasks, and checkpoints are provided between the tasks. When the job is interrupted, a method of restarting the job from the checkpoint immediately before the interruption is used. That is, as shown in FIG. 6, the job is divided into a plurality of tasks and executed sequentially by checkpoints CP1, CP2, CP3, CP4, and the like. In each task, the initial state is reproduced, that is, initialized from the checkpoint at the start of the task, and the checkpoint is recorded at the end of each job. In the checkpoint recording, parameters necessary for the data processing apparatus to execute a task or job are recorded in the memory. These parameters hold, for example, each register, flag, and other data of the data processing system. At the start of each task, each piece of data is read from the memory, set in a register, etc., and the initial state is reproduced, and then the task is executed. This increases the overhead of replaying the initial state from the checkpoint and recording the checkpoint, but the interrupted job is reliably executed.
[0045]
That is, in FIG. 6, when a job interruption such as an accidental reset of the CPU occurs during the execution of the task after the checkpoint CP2, the task is resumed from the checkpoint CP2. Further, when an interruption occurs in a task after the checkpoint CP4, the task can be restarted again from the checkpoint CP4 and the job can be surely terminated.
[0046]
However, even in such a processing method, if the process is interrupted in the “checkpoint recording” phase, there is a possibility that the initial state of the task to be executed next cannot be reproduced. That is, as shown in FIG. 7, each task has a task body portion for executing processing and a checkpoint recording phase for recording necessary data as checkpoints after execution of the processing is completed. For example, it is assumed that information necessary as a checkpoint is A, B, C, D, and E, and all these data must be recorded at the end of the task. In this case, if the process is interrupted before recording the data D and E due to an accidental reset during the recording of the checkpoint, the checkpoint becomes unusable because the data is broken. For this reason, it is necessary to redo the entire normal job.
[0047]
In such a case, by using the committable memory according to the present invention for the checkpoint recording, the task can be executed safely and quickly without maintaining the consistency of the checkpoint and re-doing the entire job. Can be terminated.
[0048]
For example, as shown in FIG. 8, in the data processing apparatus according to the present invention, data A, B, C, D required as checkpoints in the checkpoint recording phase after the task main body in each task. , E are sequentially written to the buffer (13 in FIG. 1) of the committable memory. When the checkpoint recording is performed without interruption and the data writing to the buffer is completely performed, the semaphore register (19, FIG. 1) is released after the writing to the buffer is completed. Then, data is transferred from the buffer to the memory unit (11, FIG. 1) at a time, that is, a commit operation is performed. As a result, the checkpoint data is updated to a new value.
[0049]
On the other hand, as shown in FIG. 9, for example, when the processing is interrupted by resetting the CPU during the recording of the checkpoint, the “commit” operation does not occur, so the checkpoint is not updated. In this case, the contents of the buffer are discarded and the checkpoint is not updated with the contents of the buffer. For this reason, if processing is interrupted in the checkpoint recording phase, the task is re-executed, and the initial state of the task can be correctly reproduced by the data previously stored in the committable memory. it can. Therefore, the data necessary for the checkpoint is destroyed and there is no need to restart the job from the beginning, and the job can be completed quickly.
[0050]
【The invention's effect】
As is apparent from the above, according to the present invention, even if the CPU is accidentally reset, the stored data in the memory unit is stored in a safe state without being destroyed. In addition, since data is written to the memory unit at a time from the buffer, the possibility that inappropriate data is written to the memory unit is extremely low. Therefore, according to the memory device of the present invention, the safety of stored data can be improved, and the reliability of a data processing device using such a memory device can be greatly increased to prevent a reduction in processing speed. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a schematic configuration of a central processing unit using a memory device according to the present invention.
FIG. 3 is a block diagram showing another configuration example of the data processing apparatus using the memory device according to the present invention.
FIG. 4 is a block diagram showing still another configuration example of the data processing apparatus using the memory device according to the present invention.
FIG. 5 is an explanatory diagram showing an influence due to a disturbance of a job executed by the central processing unit.
FIG. 6 is an explanatory diagram showing processing for dividing a job into a plurality of tasks and executing the job.
FIG. 7 is an explanatory diagram showing a state in which processing is interrupted during recording of task checkpoints.
FIG. 8 is an explanatory diagram showing a procedure for recording checkpoints using the memory device according to the present invention;
FIG. 9 is an explanatory diagram showing a state of processing when a check point is recorded using the memory device according to the present invention and there is an interruption in processing during check point recording;
[Explanation of symbols]
11 Memory part
11a memory cell
13 buffers
13a bit cell
15 Address decoder
17 Selector
19 Semaphore register
31 Central processing unit (CPU)
33 Bus
35 Watchdog timer
37 Commitable memory
39 Random Access Memory (RAM)
41 Peripheral devices
43 Crystal oscillator
45 clock oscillator
47 Clock monitor
49 Stabilized power supply
51 Instantaneous power failure detection circuit

Claims (12)

A memory unit for storing data;
A buffer for temporarily storing data to be written to the memory unit;
A semaphore register that stores information indicating whether data can be written from the buffer to the memory unit;
When the writing to the memory unit is performed, the semaphore register is set in advance to lock the memory unit, and the write data is written into the buffer in multiple times, and the data is stored in the buffer A memory device with improved safety of stored data, wherein after the semaphore register is released and the memory unit is unlocked, data is written from the buffer to the memory unit at a time. 2. The buffer contents are discarded if an accidental reset event occurs that impairs the integrity of data writing to the buffer while the semaphore register is set. The memory device described. 2. The memory device according to claim 1, wherein if a write operation to the buffer is interrupted while the semaphore register is set, the contents of the buffer are discarded. 2. The memory device according to claim 1, further comprising a data bus for inputting write data to the buffer, wherein a transmission capacity of the data bus is smaller than a capacity of the buffer. 2. The memory device according to claim 1, wherein data is read directly from the memory unit. A data processing device:
A central processing unit (CPU); and a memory unit, a memory unit for storing data, a buffer for temporarily storing data to be written to the memory unit, and whether data can be written from the buffer to the memory unit A semaphore register for storing information, and when writing to the memory unit, the semaphore register is set in advance and the memory unit is locked, and the write data is written to the buffer in a plurality of times, A memory device for writing data from the buffer to the memory unit at a time when the semaphore register is released and the memory unit is unlocked after data is stored in the buffer;
The central processing unit divides a job to be executed into a plurality of tasks, executes checkpoints between the tasks, and writes checkpoint data to the memory device at the end of each task. A data processing apparatus for performing checkpoint recording by reading the checkpoint data and reading the checkpoint data from the memory device at the start of each task. The checkpoint recording is performed by sequentially writing checkpoint data necessary for the central processing unit to resume a task at each checkpoint to the buffer of the memory device, and writing data to the buffer during the checkpoint recording. When the accidental reset event that impairs the integrity of the data or the interruption of the data writing to the buffer does not occur, the checkpoint is recorded by collectively transferring the data written in the buffer to the memory unit The data processing apparatus according to claim 6. If an accidental reset event that impairs the integrity of the data write to the buffer occurs while the semaphore register is set, or if the write operation to the buffer is interrupted halfway, 8. The data processing apparatus according to claim 6, wherein the contents are discarded. 9. The data processing apparatus according to claim 7, wherein the accidental reset event is generated by resetting the central processing unit when an abnormal operation of the central processing unit is detected by a watch dog timer. 9. The data processing apparatus according to claim 7, wherein the accidental reset event is generated by resetting the clock oscillator and the central processing unit in response to detecting the oscillation stop of the clock oscillator. . 9. The accidental reset event is generated by resetting the central processing unit when an instantaneous decrease in power supply voltage supplied to the data processing unit is detected. Data processing equipment. The data processing apparatus according to any one of claims 6 to 11, wherein the data processing apparatus is a micro controller unit (MCU).

Images