JP4231881B2 - Device apparatus and manufacturing method thereof - Google Patents

Device apparatus and manufacturing method thereof Download PDF

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JP4231881B2
JP4231881B2 JP2006212903A JP2006212903A JP4231881B2 JP 4231881 B2 JP4231881 B2 JP 4231881B2 JP 2006212903 A JP2006212903 A JP 2006212903A JP 2006212903 A JP2006212903 A JP 2006212903A JP 4231881 B2 JP4231881 B2 JP 4231881B2
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resin
device chip
functional surface
wiring
periphery
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JP2008041857A (en
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修 島田
充教 ▲高▼杉
博史 土屋
哲夫 山田
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Dai Nippon Printing Co Ltd
Ube Corp
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Dai Nippon Printing Co Ltd
Ube Industries Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

本発明は、表面に空間を必要とする機能面領域を有するデバイスチップがフェイスダウンで搭載されるデバイス装置及びその製造方法 The present invention Lud vice apparatus and a method for manufacturing the device chip having a functional surface area in need of space on the surface is mounted in a face-down

例えばSAW(Surface acoustic wave)チップ等においては、通常の半導体装置と同様に外界の影響から素子を保護するために封止構造が用いられている。ただし、SAWチップ等はその特性から素子の機能面領域上方を中空状態に保持しなければならないため、中空状態を保持し得る封止構造を適用する必要がある。このような封止構造としては、従来から適用されているカンタイプのパッケージが知られているが、パッケージの大型化が避けられないことから、近年の小型化要求には到底対応することができない。   For example, in a SAW (Surface Acoustic Wave) chip or the like, a sealing structure is used to protect an element from the influence of the outside world as in a normal semiconductor device. However, since the SAW chip or the like must hold the functional area above the element in a hollow state due to its characteristics, it is necessary to apply a sealing structure that can hold the hollow state. As such a sealing structure, a can-type package that has been conventionally used is known, but since it is unavoidable to increase the size of the package, it is difficult to meet the recent demand for downsizing. .

このような点に対して、デバイスチップの機能面領域上方が中空状態となるようにデバイスチップの周囲を感光性樹脂で中空封止した構造が知られている(例えば、特許文献1参照。)。また、機能面領域が中空内に保持されるように高粘度のNCP(Non Conductive Polymer)樹脂等で封止した構造が知られている(例えば、特許文献2参照。)。
特開2001−298102号公報 特開2005−110017号公報
For such a point, a structure is known in which the periphery of the device chip is hollow-sealed with a photosensitive resin so that the functional area of the device chip is hollow (see, for example, Patent Document 1). . Further, a structure in which a functional surface region is sealed with a high-viscosity NCP (Non Conductive Polymer) resin or the like so as to be held in the hollow is known (for example, see Patent Document 2).
JP 2001-298102 A JP 2005-110017 A

しかしながら、従来の封止構造のうち、デバイスチップの外周を感光性樹脂で中空封止した構造では、用いる感光性樹脂の流動性が高く、塗布時に樹脂が半導体チップの機能面領域周辺にまで侵入し素子特性を劣化させ易くするという難点を有していた。一方、高粘度のNCP樹脂等を適用した構造では、デバイスチップ上に塗布する際の樹脂が100〜200Pa・sという高粘度であるため、塗布出しに時間を要し作業性の悪化を招く傾向にあった。   However, among the conventional sealing structures, in the structure in which the outer periphery of the device chip is hollow-sealed with a photosensitive resin, the photosensitive resin used has high fluidity, and the resin penetrates to the periphery of the functional surface area of the semiconductor chip during application. However, it has a drawback of easily degrading element characteristics. On the other hand, in a structure using a high-viscosity NCP resin or the like, since the resin when applied on the device chip has a high viscosity of 100 to 200 Pa · s, it takes time to apply and tends to deteriorate workability. It was in.

本発明は、このような課題に対処するためになされたもので、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造可能にしたデバイス装置及びその製造方法を提供することを目的とする。 The present invention, such a problem in which has been made in order to cope, on having improved sealing reliability, easy and devices that enables manufacturing a device device sealed good yield hollow resin molding An object is to provide an apparatus and a method for manufacturing the same.

本発明に係るデバイス装置は、表面に空間を必要とする機能面領域の周囲に複数の電気的接続部が形成されたデバイスチップと、前記デバイスチップが、前記機能面領域及び前記電気的接続部が配線基板側に向くように配置され、表面から突出する凸状の配線パターンが形成された配線基板であって、前記配線パターンが、前記機能面領域と対向する対向領域の外側から、前記電気的接続部との接続位置に向けて直線的に延在し、かつ、当該電気的接続部との接続位置と前記対向領域との間に終端部を有するように形成され、かつ、前記電気的接続部に対応して設けられた配線パターンの前記機能面領域に向かった前記終端部によって前記デバイスチップの下側に位置する段部が形成されている配線基板とを具備し、前記デバイスチップと前記配線基板との間が、前記機能面領域との間に空間が形成されるように樹脂により封止され、少なくとも前記デバイスチップと対向する領域の前記配線パターン上に前記樹脂が存在していることを特徴とする。 The device device according to the present invention includes a device chip in which a plurality of electrical connection portions are formed around a functional surface region that requires space on the surface, and the device chip includes the functional surface region and the electrical connection portion. there are disposed such that the wiring substrate side a wiring substrate convex a wiring pattern is formed to protrude from the surface, the wiring pattern, from the outside of the opposing region that faces the functional surface region, the electric Extending linearly toward the connection position with the electrical connection portion, and having a terminal portion between the connection position with the electrical connection portion and the opposing region , and the electrical ; and a wiring board stepped portion positioned on the lower side of the device chip by the end edge portion toward the functional surface area of the wiring pattern provided in correspondence with the connecting portion is formed, the device chip And before Sealed with resin so that a space is formed between the wiring board and the functional surface region, and the resin exists on the wiring pattern in a region facing at least the device chip. It is characterized by.

上記構成のデバイス装置では、表面から突出する凸状の配線パターンが、機能面領域と対向する対向領域の外側から、当該対向領域に延在することがないようにし、配線パターンの上部を通って、機能面領域の部分に樹脂が急速に進入することを防止する。これとともに、デバイスチップの電気的接続部に対応する配線パターンの端部によって段部を形成することにより、樹脂の進入を一時的にこの部分で遅らせる。これによって、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造することができる。   In the device device having the above configuration, the convex wiring pattern protruding from the surface does not extend from the outside of the facing area facing the functional surface area to the facing area, and passes through the upper part of the wiring pattern. This prevents the resin from rapidly entering the functional surface area. At the same time, by forming the step portion by the end portion of the wiring pattern corresponding to the electrical connection portion of the device chip, the entry of the resin is temporarily delayed at this portion. As a result, it is possible to manufacture a device device in which the resin is sealed in the hollow easily and with high yield, while improving the sealing reliability.

上記のデバイス装置において、配線パターンは、表面から10μm以上突出する高さとすることが好ましい。これによって、樹脂の進入を遅らせる十分な効果を得ることができる。また、隣接する配線パターンの間隔が広くなる場合は、対向領域の周囲に沿って、配線パターンの間に位置するように、表面から突出する凸状のダミーパターンを形成することが好ましい。これによって、より確実に樹脂の進入状態を制御することができる。このようなダミーパターンは、表面から10μm以上突出し、かつデバイスチップと直接接触しない高さとすることが好ましい。また、このようなデバイス装置では、樹脂が、隣接する配線パターン同士、又は隣接する配線パターンとダミーパターンの間で外側方向に向かって凹んだ形状となる。   In the above-described device apparatus, the wiring pattern preferably has a height protruding from the surface by 10 μm or more. Thereby, it is possible to obtain a sufficient effect of delaying the entry of the resin. When the interval between adjacent wiring patterns becomes wide, it is preferable to form a convex dummy pattern protruding from the surface so as to be positioned between the wiring patterns along the periphery of the opposing region. Thereby, the approach state of the resin can be controlled more reliably. Such a dummy pattern preferably protrudes from the surface by 10 μm or more and has a height that does not directly contact the device chip. Moreover, in such a device apparatus, resin becomes a shape dented toward the outer side between adjacent wiring patterns or between adjacent wiring patterns and dummy patterns.

本発明に係る他のデバイス装置は、表面に空間を必要とする機能面領域の周囲に複数の電気的接続部が形成されたデバイスチップと、前記機能面領域及び前記電気的接続部が配線基板側に向くように配置され、前記機能面領域と対向する対向領域の周囲を囲むように、前記デバイスチップの下側で前記機能面領域より外側に位置する部位に段部が形成されている配線基板を具備し、前記デバイスチップと前記配線基板との間が、前記機能面領域との間に空間が形成されるように前記デバイスチップの周囲から前記段部まで樹脂により封止され、中空に閉じ込めされていることを特徴とするデバイス装置。 Another device device according to the present invention includes a device chip in which a plurality of electrical connection portions are formed around a functional surface region that requires space on the surface, and the functional surface region and the electrical connection portion are wiring boards. Wiring in which a step portion is formed at a portion located on the lower side of the device chip and outside the functional surface region so as to surround the periphery of the opposing region facing the functional surface region. A substrate is provided, and the space between the device chip and the wiring substrate is sealed with resin from the periphery of the device chip to the step portion so that a space is formed between the functional surface region, and is hollow. A device apparatus characterized by being confined .

上記構成のデバイス装置では、機能面領域と対向する対向領域の周囲を囲むように、デバイスチップの下側に位置する部位に形成された段部により、樹脂の進入を一時的にこの部分で遅らせることができる。これによって、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造することができる。このような段部は、表面を凹陥するように形成された凹部によって形成することができる。   In the device device having the above-described configuration, the step of the resin is temporarily delayed at this portion by the step portion formed at the lower part of the device chip so as to surround the periphery of the facing region facing the functional surface region. be able to. As a result, it is possible to manufacture a device device in which the resin is sealed in the hollow easily and with high yield, while improving the sealing reliability. Such a stepped portion can be formed by a recess formed so as to be recessed in the surface.

本発明に係るデバイス装置の製造方法は、上記したデバイス装置の製造方法であって、前記デバイスチップの周囲に沿って樹脂を供給し、当該樹脂が前記機能面領域と前記配線基板との間に流入する前に前記デバイスチップの周囲全周に樹脂を供給し、前記デバイスチップと前記配線基板との間を前記機能面領域との間に空間が形成されるように前記デバイスチップの周囲全周を樹脂により封止することを特徴とする。 The device device manufacturing method according to the present invention is a device device manufacturing method described above, wherein a resin is supplied along the periphery of the device chip, and the resin is interposed between the functional surface region and the wiring board. said supplying resin to the entire circumference around the device chip prior to entering, the entire periphery of the device chip such that a space is formed circumferentially between the between the wiring substrate and the device chip the functional surface area Is sealed with resin.

上記構成のデバイス装置の製造方法では、樹脂が機能面領域と配線基板との間に流入する前にデバイスチップの周囲全周に樹脂を供給することにより、空隙部分の内圧で、樹脂の進入を止めることができる。これによって、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造することができる。このような樹脂の供給は、デバイスチップの周囲に沿って、樹脂を供給するためのディスペンサを移動させながら供給する方法、又は、デバイスチップに対応した開口部を有するマスクを介して樹脂を供給する方法等によって行うことができる。   In the manufacturing method of the device device having the above-described structure, the resin is supplied to the entire periphery of the device chip before the resin flows between the functional surface region and the wiring board, thereby allowing the resin to enter with the internal pressure of the gap portion. Can be stopped. As a result, it is possible to manufacture a device device in which the resin is sealed in the hollow easily and with high yield, while improving the sealing reliability. Such a resin is supplied by moving a dispenser for supplying the resin along the periphery of the device chip, or through a mask having an opening corresponding to the device chip. It can be performed by a method or the like.

本発明によれば、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造可能にしたデバイス装置及びその製造方法を提供することができる。 According to the present invention, after improving the sealing reliability can be provided easily and the device and a manufacturing method thereof allowing manufacturing a device device sealed good yield hollow resin.

以下、本発明の詳細を実施の形態について、図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1,2は、本発明の第1の実施形態に係る配線基板の構造を模式的に示すもので、図1は縦断面図であり、図2は上方から見た構成を示す透視図である。これらの図において、1は配線基板を示している。この配線基板1としては、樹脂基板、セラミック基板、Si基板等その材質はどのようなものでも良い。   1 and 2 schematically show the structure of a wiring board according to a first embodiment of the present invention. FIG. 1 is a longitudinal sectional view, and FIG. 2 is a perspective view showing a configuration viewed from above. is there. In these drawings, reference numeral 1 denotes a wiring board. The wiring substrate 1 may be made of any material such as a resin substrate, a ceramic substrate, or a Si substrate.

上記配線基板1には、その表面から所定高さ(例えば10μm〜20μm程度)突出するように配線パターン2が複数形成されている。また、配線基板1上には、デバイスチップ3が設けられている。このデバイスチップ3は、中央部に機能面領域4を有し、この機能面領域4の周囲に、電気的接続部としての電極パッド(図示せず。)及びこの電極パッドと接続されたAuバンプ5が設けられている。そして、配線パターン2とデバイスチップ3の電極パッドとはAuバンプ5を介して電気的及び機械的に接続されている。すなわち、デバイスチップ3は、機能面領域4、電極パッド、Auバンプ5が配線基板1側を向くように、配線基板1にフェイスダウンで搭載されている。   A plurality of wiring patterns 2 are formed on the wiring substrate 1 so as to protrude from the surface thereof to a predetermined height (for example, about 10 μm to 20 μm). A device chip 3 is provided on the wiring board 1. The device chip 3 has a functional surface region 4 in the center, and an electrode pad (not shown) as an electrical connection portion and an Au bump connected to the electrode pad around the functional surface region 4. 5 is provided. The wiring pattern 2 and the electrode pads of the device chip 3 are electrically and mechanically connected via Au bumps 5. That is, the device chip 3 is mounted face down on the wiring board 1 such that the functional surface area 4, electrode pads, and Au bumps 5 face the wiring board 1 side.

デバイスチップ3の機能面領域4は、その表面に空間を必要とする。すなわち、デバイスチップ3は、例えばSAW(Surface Acoustic Wave)デバイスないしFBAR(Film Bulk Acoustic Resonator)等からなり、機能面領域4には櫛歯状電極(図示せず。)等が設けられており、その表面に空間を必要とする構成となっている。このため、機能面4と配線基板1との間には、空隙6が形成されている。   The functional surface area 4 of the device chip 3 requires a space on its surface. That is, the device chip 3 is composed of, for example, a SAW (Surface Acoustic Wave) device or an FBAR (Film Bulk Acoustic Resonator), and the functional surface area 4 is provided with comb-like electrodes (not shown). The surface requires a space. For this reason, a gap 6 is formed between the functional surface 4 and the wiring board 1.

上記の空隙6を形成するため、配線パターン2は、機能面領域4と対向する対向領域の外側から、当該対向領域に延在することのないように形成され、かつ、少なくともデバイスチップ3のAuバンプ5に対応した位置に形成されている。なお、本実施形態では、図1,2に示すように、配線基板1の機能面領域4と対向する対向領域には配線パターン2が形成されていない。しかし、対向領域の外側から対向領域内に延在するものでなく、単に対向領域内に孤立して配置されたもの(島状に配置されたもの)であれば、対向領域内に配線パターン2があっても良い。   In order to form the gap 6, the wiring pattern 2 is formed so as not to extend from the outside of the facing area facing the functional surface area 4 to the facing area, and at least the Au of the device chip 3. It is formed at a position corresponding to the bump 5. In the present embodiment, as shown in FIGS. 1 and 2, the wiring pattern 2 is not formed in the facing region facing the functional surface region 4 of the wiring substrate 1. However, if the wiring pattern 2 does not extend from the outside of the opposing area but is simply arranged in the opposing area (is arranged in an island shape), the wiring pattern 2 is provided in the opposing area. There may be.

また、上記の配線パターン2は、配線基板1の表面から10μm以上突出していることが好ましい。これは、配線基板1の表面と配線パターン2の段部により、封止用の樹脂7の流れを制御するためである。この配線パターン2の高さとしては、例えば前記した10μm〜20μm程度が好ましい。この場合、配線パターン2の上面とデバイスチップ3との間隔が10μm〜20μm程度となり、配線パターン2以外の配線基板1の上面とデバイスチップ3との間隔が20μm〜40μm程度となる。   The wiring pattern 2 preferably protrudes from the surface of the wiring board 1 by 10 μm or more. This is because the flow of the sealing resin 7 is controlled by the surface of the wiring substrate 1 and the stepped portion of the wiring pattern 2. The height of the wiring pattern 2 is preferably about 10 μm to 20 μm, for example. In this case, the distance between the upper surface of the wiring pattern 2 and the device chip 3 is about 10 μm to 20 μm, and the distance between the upper surface of the wiring substrate 1 other than the wiring pattern 2 and the device chip 3 is about 20 μm to 40 μm.

また、上記の配線パターン2は、デバイスチップ3の周囲に沿って適宜の間隔で配置されることが好ましく、隣接する配線パターン2の間隔が広く空く場合は、図3に示すようにこれらの配線パターン2の間にダミーパターン8を設けて、隣接するパターン同士の間隔を一定以下とすることが好ましい。なお、このようなダミーパターン8は、配線パターン2と同様に銅、アルミニウム、金等の金属導体、あるいは、絶縁樹脂やガラス等の絶縁性材料等どのようなもので形成してもよい。さらに、配線基板1から突出する構造の配線パターン2を有しない場合は、全てダミーパターン8によって構成することもできる。このようにダミーパターン8を使用した場合、ダミーパターン8とデバイスチップ3とが直接接触しないことが好ましく、ダミーパターン8の高さは、配線パターン2の場合と同様に、10μm〜20μm程度とすることが好ましい。   The wiring patterns 2 are preferably arranged at appropriate intervals along the periphery of the device chip 3, and when the intervals between the adjacent wiring patterns 2 are wide, these wiring patterns are arranged as shown in FIG. It is preferable to provide a dummy pattern 8 between the patterns 2 so that the interval between adjacent patterns is not more than a certain value. Such a dummy pattern 8 may be formed of any material such as a metal conductor such as copper, aluminum, or gold, or an insulating material such as an insulating resin or glass, like the wiring pattern 2. Further, in the case where the wiring pattern 2 having a structure protruding from the wiring substrate 1 is not provided, the wiring pattern 2 can be entirely constituted by the dummy pattern 8. Thus, when the dummy pattern 8 is used, it is preferable that the dummy pattern 8 and the device chip 3 do not contact directly, and the height of the dummy pattern 8 is about 10 μm to 20 μm as in the case of the wiring pattern 2. It is preferable.

上記構成の配線基板1では、デバイスチップ3を搭載した後、デバイスチップ3の周囲を樹脂7で封止する。この際に、デバイスチップ3の周囲に沿って樹脂7を供給する。すなわち、例えば図4,5に示すように、樹脂7を供給するディスペンサ20をデバイスチップ3の周囲に沿って移動させながら樹脂7を供給する。なお、樹脂7の粘度はある程度高いことが好ましく、例えば20Pa・s以上とすることが好ましい。   In the wiring substrate 1 having the above configuration, after the device chip 3 is mounted, the periphery of the device chip 3 is sealed with the resin 7. At this time, the resin 7 is supplied along the periphery of the device chip 3. That is, for example, as shown in FIGS. 4 and 5, the resin 7 is supplied while moving the dispenser 20 for supplying the resin 7 along the periphery of the device chip 3. The viscosity of the resin 7 is preferably high to some extent, for example, 20 Pa · s or more is preferable.

この時、図6(a),(b)に示すように、一般にデバイスチップ3と配線基板1(配線パターン2)との間隔dが狭いほど(図6の場合(b)の方)、毛細管現象により樹脂7の内側への進入速度が速い。この進入速度は、デバイスチップ3と配線基板1(配線パターン2)との間隔dに反比例して増加する。このため配線基板1上では、配線パターン2上の方が配線パターン2の無い部分よりも樹脂7の進入速度が速くなる。例えば、配線パターン2の配線基板1表面からの突出高さが10μm、配線パターン2上面とデバイスチップ3との距離が10μm、配線基板1上の配線パターン2が無い部分とデバイスチップ3との距離が20μmであると、この場合、配線パターン2上の方が2倍速く樹脂7が進入する。このため、本実施形態では、配線パターン2が、機能面領域4と対向する対向領域の外側から、当該対向領域に延在することのないようにしている。   At this time, as shown in FIGS. 6A and 6B, generally, the narrower the distance d between the device chip 3 and the wiring board 1 (wiring pattern 2) (in the case of FIG. 6B), the capillary tube. Due to the phenomenon, the speed of entering the inside of the resin 7 is fast. This approach speed increases in inverse proportion to the distance d between the device chip 3 and the wiring board 1 (wiring pattern 2). For this reason, on the wiring board 1, the entry speed of the resin 7 is faster on the wiring pattern 2 than on the portion without the wiring pattern 2. For example, the protruding height of the wiring pattern 2 from the surface of the wiring substrate 1 is 10 μm, the distance between the upper surface of the wiring pattern 2 and the device chip 3 is 10 μm, and the distance between the portion without the wiring pattern 2 on the wiring substrate 1 and the device chip 3 In this case, the resin 7 enters the wiring pattern 2 twice as fast. For this reason, in the present embodiment, the wiring pattern 2 does not extend from the outside of the facing area facing the functional surface area 4 to the facing area.

そして、図7に示すように、樹脂7が配線パターン2の端部(段部)まで到達すると、樹脂7の進入速度が遅くなる。ここで、重力を除いた樹脂7に働くデバイスチップ3の外周方向への力(A)(図7中黒色の矢印で示す。)は、
(1)樹脂の自己凝集力
(2)表面張力(樹脂自体の形状保持)
(3)中空空間による内部圧力
である。また、内部へ進入する方向に働く力(B)(図7中白抜きの矢印で示す。)は、
(4)樹脂と各材料間の界面張力(濡れ性)
(5)毛細管現象
である。
As shown in FIG. 7, when the resin 7 reaches the end portion (step portion) of the wiring pattern 2, the entry speed of the resin 7 becomes slow. Here, the force (A) in the outer peripheral direction of the device chip 3 acting on the resin 7 excluding gravity (indicated by a black arrow in FIG. 7) is:
(1) Resin self-cohesive force (2) Surface tension (maintenance of resin itself)
(3) Internal pressure due to the hollow space. Moreover, the force (B) (indicated by a white arrow in FIG. 7) acting in the direction of entering the inside is
(4) Interfacial tension (wetting) between resin and each material
(5) Capillary phenomenon.

樹脂7を塗布した直後は、上記の(B)の合計した力の方が、(A)の合計した力よりも大きいので、樹脂7は、デバイスチップ3の内側に徐々に侵入していく。そして、デバイスチップ3と配線基板1との間隙における樹脂7の量が多くなるにつれて(1)の自己凝集力が大きくなり、樹脂7の進入速度は徐々に遅くなっていく。配線パターン2の先端の段部に樹脂7が到達すると、図8,9に示す樹脂7と配線パターン2との接触角度θが変わるため、図9(a)に示す状態から図9(b)に示す状態となるようにその接触角度が変わるまで樹脂7の進入位置が保持される。この間にデバイスチップ3の周囲を樹脂7で覆い中空に閉じ込めてしまえば、(3)の内部圧力によって、樹脂7の進入は止まる。一方、この間に中空に閉じ込めを行わない場合は、配線パターン2上の樹脂7が配線基板1表面にまで到達し、その後はデバイスチップ3と配線基板1との距離とそこまでの樹脂7の進入量に応じて樹脂7が徐々に内側に進入する。   Immediately after the resin 7 is applied, the total force in (B) above is greater than the total force in (A), so that the resin 7 gradually enters the inside of the device chip 3. Then, as the amount of the resin 7 in the gap between the device chip 3 and the wiring substrate 1 increases, the self-cohesion force of (1) increases and the entry speed of the resin 7 gradually decreases. When the resin 7 reaches the stepped portion at the tip of the wiring pattern 2, the contact angle θ between the resin 7 and the wiring pattern 2 shown in FIGS. 8 and 9 changes, so that the state shown in FIG. The approach position of the resin 7 is held until the contact angle changes so that the state shown in FIG. During this time, if the periphery of the device chip 3 is covered with the resin 7 and confined in the hollow, the ingress of the resin 7 is stopped by the internal pressure of (3). On the other hand, if the confinement is not performed in the hollow space, the resin 7 on the wiring pattern 2 reaches the surface of the wiring board 1, and thereafter, the distance between the device chip 3 and the wiring board 1 and the resin 7 entering there. Resin 7 gradually enters the inside according to the amount.

このため、図4,5に示すように、樹脂7を供給するディスペンサ20をデバイスチップ3の周囲に沿って移動させながら樹脂を供給する場合、樹脂7が配線パターン2の端部で止まっている間に、デバイスチップ3の全周に亘って樹脂7を供給し中空に閉じ込めを行う。なお、この樹脂7の供給開始から終了までの時間は、例えば1mm角のSAWチップの場合、1秒以下程度とすることが好ましい。これによって、図2,3に示すように、機能面領域4の部分に樹脂7が進入しない状態に確実に樹脂封止を行うことができる。なお、樹脂7の供給方法としては、上記のようなディスペンサ20を用いた方法に限られず、例えば、図10に示すように、デバイスチップ3に対応した形状の開口部(図示せず。)を有するマスク30とスキージ31等を用いた印刷工程による方法でもよい。このような方法によれば、より短時間でデバイスチップ3の周囲の全周に亘って樹脂7を供給することができ、また、一度に複数のデバイス装置に対して樹脂7を供給できるので工程時間の短縮を図ることができる。さらに、デバイスチップ全体を封止でき、信頼性が増すとともに、形成後の封止樹脂表面が平らになり、取り扱いが容易となる。   Therefore, as shown in FIGS. 4 and 5, when the resin is supplied while moving the dispenser 20 that supplies the resin 7 along the periphery of the device chip 3, the resin 7 stops at the end of the wiring pattern 2. In the meantime, the resin 7 is supplied over the entire circumference of the device chip 3 and confined in the hollow. The time from the start to the end of the supply of the resin 7 is preferably about 1 second or less in the case of a 1 mm square SAW chip, for example. As a result, as shown in FIGS. 2 and 3, resin sealing can be reliably performed in a state where the resin 7 does not enter the functional surface region 4. The method for supplying the resin 7 is not limited to the method using the dispenser 20 as described above. For example, as shown in FIG. 10, an opening (not shown) having a shape corresponding to the device chip 3 is provided. A method using a printing process using the mask 30 and the squeegee 31 may be used. According to such a method, the resin 7 can be supplied over the entire circumference of the device chip 3 in a shorter time, and the resin 7 can be supplied to a plurality of device devices at a time. Time can be shortened. Furthermore, the entire device chip can be sealed, the reliability is increased, and the surface of the sealing resin after formation is flattened so that handling is easy.

上記のようにデバイスチップ3の周囲に樹脂7を供給した後、配線基板1ごと例えばオーブンに投入し、所定温度で所定時間(例えば150℃程度で30分)加熱し、塗布された樹脂7を熱硬化させる。加熱してから熱硬化反応が起こる100℃になるまでの間に樹脂7が低粘度になり流動化し易くなるが、封止空間の内圧が高くなるため機能面領域4周辺に流れ込む恐れはない。なお、オーブンの代わりにホットステージを用いてもよい。デバイスチップ3が実装された配線基板1をホットステージに載置することで、配線基板1側に直に熱を供給できるため、150℃に加熱した場合5分程度で熱硬化させることができる。   After the resin 7 is supplied to the periphery of the device chip 3 as described above, the entire wiring board 1 is put in, for example, an oven, and heated at a predetermined temperature for a predetermined time (for example, about 150 ° C. for 30 minutes). Heat cure. The resin 7 has a low viscosity and easily fluidizes during the period from the heating until the thermosetting reaction occurs at 100 ° C., but the internal pressure of the sealing space increases, so there is no risk of flowing into the periphery of the functional surface region 4. A hot stage may be used instead of the oven. By placing the wiring board 1 on which the device chip 3 is mounted on the hot stage, heat can be supplied directly to the wiring board 1 side, so that when it is heated to 150 ° C., it can be thermally cured in about 5 minutes.

以上のように、本実施形態では、封止信頼性を向上させた上で、容易にかつ収率よく中空に樹脂封止したデバイス装置を製造することができる。実際に、1mm角のSAWチップの場合について、周囲からSAWチップの下に樹脂7が入り込む幅を測定したところ、従来は300μm以上であったのに対して、上記の実施形態によれば150μm以下とすることができた。なお、上記のようにして樹脂封止を行ったデバイス装置の場合、樹脂7は、図2,3に示すように、隣接する配線パターン2同士又は配線パターン2と隣接するダミーパターン8との間において、外側方向に凹んだ形状となっている。   As described above, according to the present embodiment, it is possible to manufacture a device device that is easily and efficiently sealed with a resin while improving the sealing reliability. Actually, in the case of a 1 mm square SAW chip, when the width of the resin 7 entering from the periphery under the SAW chip was measured, it was 300 μm or more in the related art, but according to the above embodiment, 150 μm or less. And was able to. In the case of a device device that has been resin-sealed as described above, as shown in FIGS. 2 and 3, the resin 7 is between the adjacent wiring patterns 2 or between the adjacent wiring patterns 2 and the adjacent dummy pattern 8. In FIG. 2, the shape is recessed in the outer direction.

次に、図11を参照して第2の実施形態について説明する。第2の実施形態にかかる配線基板1aは、図11に示すように、デバイスチップ3の機能面領域4と対向する対向領域の周囲を囲むように、デバイスチップ3の下側に位置する部位に段部9aが形成されている。すなわち、配線基板1aには、矩形状の機能面領域4より面積の広い矩形状の凹部9が形成されており、この凹部9の縁部によって段部9aが形成されている。このように構成された第2の実施形態では、前述した配線パターン2の端部の場合と同様に、段部9aによって樹脂7の進入が抑制されるので、前記した実施形態と同様な効果を得ることができる。   Next, a second embodiment will be described with reference to FIG. As shown in FIG. 11, the wiring substrate 1 a according to the second embodiment is disposed at a portion located below the device chip 3 so as to surround the periphery of the facing region facing the functional surface region 4 of the device chip 3. A step portion 9a is formed. That is, a rectangular recess 9 having a larger area than the rectangular functional surface region 4 is formed in the wiring board 1 a, and a step portion 9 a is formed by an edge of the recess 9. In the second embodiment configured as described above, since the step of the resin 7 is suppressed by the step portion 9a as in the case of the end portion of the wiring pattern 2 described above, the same effect as the above-described embodiment can be obtained. Obtainable.

なお、段部9aを形成するためには、上記のように全体を凹陥した形状の凹部9に限らず例えば周囲のみを凹陥したロ字状の凹部としても良く、或いは凹陥する代わりに周囲を突出させたと凸部を形成しても良い。また、図12に示す参考例のように、配線基板1bには段部を設けず、デバイスチップ3側を凹陥して凹部10を形成し、デバイスチップ3側の電極部分と機能面領域4の間に段部10aを設けても良い。 In order to form the stepped portion 9a, it is not limited to the concave portion 9 having a concave shape as a whole as described above. For example, a square-shaped concave portion having a concave shape only around the periphery may be used. If it is made, you may form a convex part. Further, as in the reference example shown in FIG. 12, the wiring substrate 1 b is not provided with a step portion, but the device chip 3 side is recessed to form the recess 10, and the electrode portion on the device chip 3 side and the functional surface region 4 are formed. You may provide the step part 10a in between.

なお、上述した実施形態では、樹脂封止デバイスとしてSAWデバイスを例に挙げて説明しているが、これに限定されるものではなく、素子の機能面上方に封止空間を必要とするFBAR、MEMSデバイス、光学デバイス等であっても適用することができる。   In the above-described embodiment, the SAW device is described as an example of the resin-encapsulated device. However, the present invention is not limited to this, and an FBAR that requires a sealed space above the functional surface of the element, Even a MEMS device, an optical device, or the like can be applied.

本発明の第1の実施形態に係るデバイス装置の模式的な縦断面図。1 is a schematic longitudinal sectional view of a device device according to a first embodiment of the present invention. 図1のデバイス装置を透視して示す模式的な平面図。FIG. 2 is a schematic plan view showing the device device of FIG. 1 in perspective. 図1のデバイス装置の変形例の構成を透視して示す模式的な平面図。The typical top view which shows through the structure of the modification of the device apparatus of FIG. 本発明の実施形態に係る製造方法を模式的に示す図。The figure which shows typically the manufacturing method which concerns on embodiment of this invention. 図4の縦断面構成を模式的に示す図。The figure which shows typically the longitudinal cross-section structure of FIG. 配線基板とデバイスチップとの間隔と樹脂の進入状態の関係を説明するための図。The figure for demonstrating the relationship between the space | interval of a wiring board and a device chip, and the approach state of resin. 樹脂の進入状態を説明するための図。The figure for demonstrating the approach state of resin. 樹脂の接触角度を説明するための図。The figure for demonstrating the contact angle of resin. 樹脂の接触角度と樹脂の進入状態の関係を説明するための図。The figure for demonstrating the relationship between the contact angle of resin, and the approach state of resin. 樹脂の供給方法の他の例を説明するための図。The figure for demonstrating the other example of the supply method of resin. 本発明の第2の実施形態に係るデバイス装置の模式的な縦断面図。The typical longitudinal section of the device device concerning a 2nd embodiment of the present invention. 本発明の参考例に係るデバイス装置の模式的な縦断面図。The typical longitudinal section of the device concerning the reference example of the present invention.

符号の説明Explanation of symbols

1……配線基板、2……配線パターン、3……デバイスチップ、4……機能面領域、5……Auバンプ、6……空隙、7……樹脂、8……ダミーパターン、9,10……凹部、9a,10a……段部。   DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Wiring pattern, 3 ... Device chip, 4 ... Functional surface area, 5 ... Au bump, 6 ... Air gap, 7 ... Resin, 8 ... Dummy pattern, 9, 10 ... recesses, 9a, 10a ... steps.

Claims (10)

表面に空間を必要とする機能面領域の周囲に複数の電気的接続部が形成されたデバイスチップと、
前記デバイスチップが、前記機能面領域及び前記電気的接続部が配線基板側に向くように配置され、表面から突出する凸状の配線パターンが形成された配線基板であって、前記配線パターンが、前記機能面領域と対向する対向領域の外側から、前記電気的接続部との接続位置に向けて直線的に延在し、かつ、当該電気的接続部との接続位置と前記対向領域との間に終端部を有するように形成され、かつ、前記電気的接続部に対応して設けられた配線パターンの前記機能面領域に向かった前記終端部によって前記デバイスチップの下側に位置する段部が形成されている配線基板とを具備し、
前記デバイスチップと前記配線基板との間が、前記機能面領域との間に空間が形成されるように樹脂により封止され、少なくとも前記デバイスチップと対向する領域の前記配線パターン上に前記樹脂が存在していることを特徴とするデバイス装置。
A device chip in which a plurality of electrical connection portions are formed around a functional surface area that requires space on the surface;
The device chip is a wiring board in which the functional surface area and the electrical connection portion are arranged to face the wiring board side, and a convex wiring pattern protruding from the surface is formed. It extends linearly from the outside of the facing area facing the functional surface area toward the connection position with the electrical connection section, and between the connection position with the electrical connection section and the facing area. to be formed with a terminal end, and a stepped portion positioned on the lower side of the device chip by the end edge portion toward the functional surface area of the wiring pattern provided corresponding to the electrical connection section A wiring board on which is formed,
The space between the device chip and the wiring board is sealed with a resin so that a space is formed between the functional surface region, and the resin is placed on the wiring pattern in a region facing at least the device chip. A device device that exists.
前記配線パターンが、表面から10μm以上突出するように設けられていることを特徴とする請求項記載のデバイス装置。 The wiring pattern, the device according to claim 1, wherein a is provided so as to protrude from the surface 10μm or more. 前記対向領域の周囲に沿って、前記配線パターンの間に位置するように、表面から突出する凸状のダミーパターンが前記配線パターンとは独立して形成されていることを特徴とする請求項又は記載のデバイス装置。 Along the periphery of the opposite region so as to be positioned between the wiring patterns, claim convex dummy pattern projecting from the surface, characterized in that it is formed independently of the wiring pattern 1 Or the device apparatus of 2 . 前記ダミーパターンが、表面から10μm以上突出し、かつ前記デバイスチップと直接接触しない高さとされていることを特徴とする請求項記載のデバイス装置。 4. The device apparatus according to claim 3 , wherein the dummy pattern protrudes from the surface by 10 [mu] m or more and has a height that does not directly contact the device chip. 前記樹脂が、隣接する前記配線パターン同士、又は隣接する前記配線パターンと前記ダミーパターンの間で外側方向に向かって凹んだ形状とされていることを特徴とする請求項乃至いずれか1項記載のデバイス装置。 The resin is the wiring pattern between the adjacent, or characterized in that said wiring patterns adjacent said there is a recessed outward direction between the dummy patterns claims 1 to 4 any one The device apparatus as described. 表面に空間を必要とする機能面領域の周囲に複数の電気的接続部が形成されたデバイスチップと、
前記機能面領域及び前記電気的接続部が配線基板側に向くように配置され、前記機能面領域と対向する対向領域の周囲を囲むように、前記デバイスチップの下側で前記機能面領域より外側に位置する部位に段部が形成されている配線基板を具備し、
前記デバイスチップと前記配線基板との間が、前記機能面領域との間に空間が形成されるように前記デバイスチップの周囲から前記段部まで樹脂により封止され、中空に閉じ込めされていることを特徴とするデバイス装置。
A device chip in which a plurality of electrical connection portions are formed around a functional surface area that requires space on the surface;
The functional surface area and the electrical connection portion are arranged so as to face the wiring substrate side, and are outside the functional surface area below the device chip so as to surround a periphery of the facing area facing the functional surface area. A wiring board having a step portion formed in a portion located at
The space between the device chip and the wiring board is sealed with resin from the periphery of the device chip to the step portion so that a space is formed between the functional surface region and confined in a hollow space. A device device.
前記段部が、表面を凹陥するように形成された凹部によって形成され、前記樹脂が前記凹部内に入り込んでいないことを特徴とする請求項記載のデバイス装置。 The device according to claim 6 , wherein the step portion is formed by a recess formed so as to be recessed in the surface, and the resin does not enter the recess. 請求項乃至のいずれか1項記載のデバイス装置の製造方法であって、
前記デバイスチップの周囲に沿って樹脂を供給し、当該樹脂が前記機能面領域と前記配線基板との間に流入する前に前記デバイスチップの周囲全周に樹脂を供給し、前記デバイスチップと前記配線基板との間を前記機能面領域との間に空間が形成されるように前記デバイスチップの周囲全周を樹脂により封止することを特徴とするデバイス装置の製造方法。
A device manufacturing method according to any one of claims 1 to 7 ,
Resin is supplied along the periphery of the device chip, and the resin is supplied to the entire periphery of the device chip before the resin flows between the functional surface region and the wiring board. A device device manufacturing method, wherein the entire periphery of the device chip is sealed with a resin so that a space is formed between the wiring substrate and the functional surface region.
前記デバイスチップの周囲に沿って、前記樹脂を供給するためのディスペンサを移動させながら前記樹脂を供給することを特徴とする請求項記載のデバイス装置の製造方法。 9. The method of manufacturing a device apparatus according to claim 8, wherein the resin is supplied while moving a dispenser for supplying the resin along the periphery of the device chip. 前記デバイスチップに対応した開口部を有するマスクを介して前記樹脂を供給することを特徴とする請求項記載のデバイス装置の製造方法。 9. The method of manufacturing a device apparatus according to claim 8, wherein the resin is supplied through a mask having an opening corresponding to the device chip.
JP2006212903A 2006-08-04 2006-08-04 Device apparatus and manufacturing method thereof Expired - Fee Related JP4231881B2 (en)

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