JP4230439B2 - Semiconductor application equipment - Google Patents

Semiconductor application equipment Download PDF

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Publication number
JP4230439B2
JP4230439B2 JP2004274745A JP2004274745A JP4230439B2 JP 4230439 B2 JP4230439 B2 JP 4230439B2 JP 2004274745 A JP2004274745 A JP 2004274745A JP 2004274745 A JP2004274745 A JP 2004274745A JP 4230439 B2 JP4230439 B2 JP 4230439B2
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wiring
application device
semiconductor application
semiconductor
auxiliary wiring
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JP2006093278A (en
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万寿夫 古賀
徹夫 溝尻
幸昌 林田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To determine an overcurrent leading to failure of a semiconductor chip easily from appearance. <P>SOLUTION: A pair of parts 5 and 3 including a semiconductor chip 5 are connected through main current wiring 6 and auxiliary wiring 11 parallel with the main current wiring 6 such that the auxiliary wiring 11 can be viewed through the window 13 of a case 12. Current capacity of the auxiliary wiring 11 is set lower than that of the main current wiring 6. When a current flowing through the semiconductor chip 5 exceeds a predetermined level, the auxiliary wiring 11 melts before the main current wiring 6 and it can be viewed externally through the window 13 of a case 12. A decision can thereby be made whether a semiconductor application device require replacement or not without inspecting the electrical characteristics. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、少なくとも一の半導体チップを備える半導体応用装置に関するものである。   The present invention relates to a semiconductor application device including at least one semiconductor chip.

電鉄等に使用されるインバータ回路を始めとした半導体応用装置において、システム構成時には大電流・高耐圧等の必要性のため、数個から数十個の半導体チップを使用して１ユニットを形成することが多い。   In semiconductor application devices such as inverter circuits used for electric railways, etc., one unit is formed using several to several tens of semiconductor chips because of the necessity of high current and high withstand voltage during system configuration. There are many cases.

この半導体応用装置に使用する半導体チップが１つでも異常になるとシステム全体に影響が出ることになるため、個々の半導体チップが正常であるかどうかを定期的に電気特性で検査し、異常なものは交換することが行なわれている。   If even one semiconductor chip used in this semiconductor application device becomes abnormal, the entire system will be affected. Therefore, whether each semiconductor chip is normal or not is checked regularly with its electrical characteristics. Are being exchanged.

しかし、このようなユニットでは半導体チップの周辺を外部ブスバ、制御基板、平滑コンデンサ等の部品が取り囲んでおり、これらを取り外して半導体チップの電気特性を一つ一つ検査することは、多大な作業量と時間を要する。   However, in such a unit, parts such as an external bus bar, a control board, and a smoothing capacitor surround the periphery of the semiconductor chip, and removing these components to inspect the electrical characteristics of the semiconductor chip one by one Requires amount and time.

また、この検査においても半導体チップがその電流容量を超えた過電流を受けているかどうかまでは十分に確認できず、過電流履歴により破壊直前まで疲労が進んでいる半導体チップが良品と判断されて再度ユニットに組み込まれ、再稼動後すぐに破壊してしまうおそれがある。   Also in this inspection, it is not possible to fully check whether the semiconductor chip has received an overcurrent exceeding its current capacity, and a semiconductor chip whose fatigue has progressed to just before breakdown due to the overcurrent history is judged as a good product. There is a risk that it will be re-installed in the unit and destroyed immediately after re-operation.

そこで、従来においては、例えば特許文献１のように、ワイヤを半導体チップと外部導出端子との間に配線し、半導体チップの故障が基で過電流が流れた際には、このワイヤが速やかに溶断して半導体チップへの過電流の通流を絶つ技術が開示されている。   Therefore, conventionally, as in Patent Document 1, for example, when a wire is wired between the semiconductor chip and the external lead-out terminal and an overcurrent flows due to a failure of the semiconductor chip, the wire is quickly A technique for cutting off the overcurrent flow to the semiconductor chip by fusing is disclosed.

特開平０７−０７８９３３号公報Japanese Patent Application Laid-Open No. 07-078933

従来の技術では、ワイヤを溶断して半導体チップへの過電流の通流を絶つことにより、半導体チップの破壊を防止することができる。   In the conventional technique, the breakage of the semiconductor chip can be prevented by cutting the wire to cut off the overcurrent flow to the semiconductor chip.

しかしながら、ワイヤが溶断することにより半導体応用装置が停止してしまい、その故障を未然に防ぐことができなかった。   However, when the wire is blown, the semiconductor application device is stopped, and the failure cannot be prevented.

そこで、本発明の課題は、半導体チップの故障につながる過電流の有無を外観によって容易に判別できるようにすることで、半導体チップの電気特性を一つ一つ検査する必要性をなくすとともに、過電流の要因となる外部ノイズや定常電流の抑制などの適切な処置を行なうことで、半導体応用装置の故障を未然に防ぐことにある。   Therefore, an object of the present invention is to make it possible to easily determine the presence or absence of an overcurrent that leads to a failure of a semiconductor chip by its appearance, thereby eliminating the need to inspect the electrical characteristics of the semiconductor chip one by one. By taking appropriate measures such as suppression of external noise that causes current and steady-state current, it is possible to prevent failure of the semiconductor application device.

上記課題を解決すべく、この発明は、少なくとも一の半導体チップと、前記半導体チップを含む一対の部位の間に形成されて当該部位同士を接続する主電流配線と、前記主電流配線よりも電流容量が小さく設定され、前記一対の部位同士の間に形成されて、前記主電流配線に並列に前記部位同士を接続する補助配線と、前記一対の部位、前記主電流配線及び前記補助配線を収納するとともに、前記補助配線を外部から目視可能に形成された目視窓が形成されたケースとを備えるものである。 In order to solve the above-described problems, the present invention provides at least one semiconductor chip, a main current wiring formed between a pair of parts including the semiconductor chip and connecting the parts, and a current more than that of the main current wiring. A capacity is set to be small, and is formed between the pair of parts, and accommodates the auxiliary wiring that connects the parts in parallel to the main current wiring, and the pair of parts, the main current wiring, and the auxiliary wiring. And a case in which a viewing window is formed so that the auxiliary wiring is visible from the outside .

この発明の半導体応用装置では、補助配線の電流容量が主電流配線よりも小さく設定されているので、半導体チップに流れる電流が所定の規定値を越えると、主電流配線より先に補助配線が溶断する。このように、補助配線の溶断有無を外観で調べることが可能であるので、主電流配線に規定値以上の電流が加わっているかどうかを判別でき、電気特性の検査を行うことをせずに半導体応用装置の交換が必要であるといった判断を行うことができる。この場合、補助配線が溶断しても、主電流配線が溶断しなければ、半導体応用装置の動作は正常に行なわれるため、例えば定期点検時に補助配線が溶断しているか否かを確認し、補助配線が溶断している半導体応用装置だけを交換するなどの取り扱いが可能となる。したがって、補助配線が形成されていない場合に比べると、主電流配線が突然に溶断し半導体応用装置の動作を停止してしまったり、半導体応用装置内の半導体チップ等に電流が集中して破壊を起こしたりする事態を未然に防止できるという効果がある。   In the semiconductor application device of the present invention, since the current capacity of the auxiliary wiring is set smaller than that of the main current wiring, if the current flowing through the semiconductor chip exceeds a predetermined specified value, the auxiliary wiring is blown before the main current wiring. To do. In this way, it is possible to visually check whether the auxiliary wiring is blown or not, so it is possible to determine whether or not a current exceeding the specified value is applied to the main current wiring, and it is possible to determine the semiconductor without having to inspect the electrical characteristics. It can be determined that the application device needs to be replaced. In this case, even if the auxiliary wiring is blown, if the main current wiring is not blown, the operation of the semiconductor device is performed normally. For example, it is confirmed whether or not the auxiliary wiring is blown during the periodic inspection. It is possible to handle such as exchanging only the semiconductor application device in which the wiring is melted. Therefore, compared to the case where the auxiliary wiring is not formed, the main current wiring suddenly melts and stops the operation of the semiconductor application device, or the current concentrates on the semiconductor chip in the semiconductor application device and breaks down. There is an effect that it is possible to prevent a situation that occurs.

｛実施の形態１｝
図１は本発明の実施の形態１に係る半導体応用装置の構造を示す平面図、図２は同じくその等価回路を示す概略回路図、図３は同じくその外観を示す平面図、図４は同じくその断面図である。 {Embodiment 1}
1 is a plan view showing the structure of a semiconductor application device according to Embodiment 1 of the present invention, FIG. 2 is a schematic circuit diagram showing the equivalent circuit, FIG. 3 is a plan view showing the appearance, and FIG. FIG.

この半導体応用装置は、図１の如く、絶縁基板１上に、コレクタパターン２、エミッタパターン３及びゲートパターン４が形成され、コレクタパターン２上に半導体チップ５が搭載されている。この半導体チップ５の上面とエミッタパターン３の上面とは、複数の主電流配線６によって接続され、また半導体チップ５の上面からゲートパターン４の上面にかけては、ゲート配線７が形成されている。さらに、コレクタパターン２、エミッタパターン３及びゲートパターン４のそれぞれの上面には、コレクタ接合部８、エミッタ接合部９及びゲート接合部１０がそれぞれ形成されている。   In this semiconductor application device, as shown in FIG. 1, a collector pattern 2, an emitter pattern 3, and a gate pattern 4 are formed on an insulating substrate 1, and a semiconductor chip 5 is mounted on the collector pattern 2. The upper surface of the semiconductor chip 5 and the upper surface of the emitter pattern 3 are connected by a plurality of main current wirings 6, and the gate wiring 7 is formed from the upper surface of the semiconductor chip 5 to the upper surface of the gate pattern 4. Further, a collector junction 8, an emitter junction 9 and a gate junction 10 are formed on the upper surfaces of the collector pattern 2, the emitter pattern 3 and the gate pattern 4, respectively.

そして、この半導体応用装置では、図１及び図２の如く、半導体チップ５の上面からエミッタパターン３の上面との間に、上記の主電流配線６と電気的に並列に補助配線１１が形成されており、この補助配線１１の電流容量が主電流配線６より小さく設定されている。これにより、半導体チップ５とエミッタパターン３との間に流れる電流がある規定値を越えると、主電流配線６より先に補助配線１１が溶断するように設定される。   In this semiconductor application device, as shown in FIGS. 1 and 2, the auxiliary wiring 11 is formed in parallel with the main current wiring 6 between the upper surface of the semiconductor chip 5 and the upper surface of the emitter pattern 3. The current capacity of the auxiliary wiring 11 is set smaller than that of the main current wiring 6. Thereby, when the current flowing between the semiconductor chip 5 and the emitter pattern 3 exceeds a predetermined value, the auxiliary wiring 11 is set to be blown before the main current wiring 6.

ここで、主電流配線６がＮ本で構成され、この主電流配線６が最大電流Ａまで耐久する場合、１本あたりの主電流配線６の電流容量がＡ／Ｎで表されることから、１本の補助配線１１の電流容量Ｘは「Ｘ＜Ａ／Ｎ」に設定される。例えば、この１本の補助配線１１の電流容量Ｘは、上記の「Ａ／Ｎ」に対して５０％程度に設定される。   Here, when the main current wiring 6 is composed of N pieces and the main current wiring 6 is durable up to the maximum current A, the current capacity of the main current wiring 6 per line is represented by A / N. The current capacity X of one auxiliary wiring 11 is set to “X <A / N”. For example, the current capacity X of the single auxiliary wiring 11 is set to about 50% with respect to the “A / N”.

また、補助配線１１の電流容量Ｘを各主電流配線６より小さくする方法としては、補助配線１１の直径や断面積を各主電流配線６よりも小さくしたり、補助配線１１の材料としてＡｌ化合物等の融点の低い（ただし電気伝導率は主電流配線６とほぼ同じ）材料を用いたりする方法を採用する。   In addition, as a method of making the current capacity X of the auxiliary wiring 11 smaller than each main current wiring 6, the diameter and cross-sectional area of the auxiliary wiring 11 are made smaller than each main current wiring 6, or the material of the auxiliary wiring 11 is an Al compound. For example, a method using a material having a low melting point (however, the electrical conductivity is substantially the same as that of the main current wiring 6) is employed.

ここで、補助配線１１として例えばアルミニウム製のワイヤを使用する場合、直径が４００μｍと仮定すると、「長さ／電流」は「１５ｍｍ／２４Ａ」「２５ｍｍ／１７Ａ」「３５ｍｍ／１３Ａ」等となる。また、補助配線１１の溶断電流は、断面積の２乗に反比例し、例えば直径が２００μｍの場合は４００μｍの場合に比べて１／４の電流で溶断される。これらのことを考慮して、補助配線１１の径や長さ等が設定される。   Here, for example, when an aluminum wire is used as the auxiliary wiring 11, assuming that the diameter is 400 μm, the “length / current” is “15 mm / 24 A”, “25 mm / 17 A”, “35 mm / 13 A”, and the like. Further, the fusing current of the auxiliary wiring 11 is inversely proportional to the square of the cross-sectional area. For example, when the diameter is 200 μm, the fusing current is blown by 1/4 of the current compared to 400 μm. Considering these, the diameter, length, etc. of the auxiliary wiring 11 are set.

また、補助配線１１をアルミニウムで形成することで、補助配線１１を安価に形成できる利点がある。   Moreover, there is an advantage that the auxiliary wiring 11 can be formed at low cost by forming the auxiliary wiring 11 from aluminum.

さらに、図３及び図４の如く、この半導体応用装置はケース１２を備えており、このケース１２には目視窓１３が形成されており、この目視窓１３を通して、補助配線１１が溶断したか否かを装置外部から視認することが可能となっている。尚、目視窓１３は、例えば透明のアクリル等の樹脂またはガラス等を用いて例えばケース１２と別部品のものとして形成されており、ケース１２に形成された窓孔に填め込まれるなどして設置される。   Further, as shown in FIGS. 3 and 4, the semiconductor application apparatus includes a case 12, and a visual window 13 is formed in the case 12, and whether or not the auxiliary wiring 11 is blown through the visual window 13. Can be visually recognized from the outside of the apparatus. The visual window 13 is formed, for example, as a separate part from the case 12 using, for example, a resin such as transparent acrylic or glass, and is installed by being inserted into a window hole formed in the case 12. Is done.

尚、ケース１２内は、図４の如く、例えば下層に透明のシリコンゲル１３ａが封入され、上層に例えば黒色のエポキシ樹脂１３ｂ等が封入されて、目視窓１３の下方に透明のシリコンゲル１３ａまでを中空状に保つための筒体１３ｃを形成するなど、補助配線１１の溶断の有無を目視窓１３で目視することが可能なようにしておく。あるいは、透明のシリコンゲル１３ａのみが封入されても差し支えない。   In the case 12, as shown in FIG. 4, for example, a transparent silicon gel 13a is sealed in the lower layer, for example, a black epoxy resin 13b is sealed in the upper layer, and the transparent silicon gel 13a is placed below the viewing window 13. The presence or absence of fusing of the auxiliary wiring 11 is made visible through the visual window 13, such as by forming a cylindrical body 13c for keeping the wire 13 hollow. Alternatively, only the transparent silicon gel 13a may be encapsulated.

以上の構成の半導体応用装置では、半導体チップ５が動作すると、半導体チップ５とエミッタパターン３との間に、複数の主電流配線６を通って電流が流れるとともに、補助配線１１にも電流が流れる。   In the semiconductor application device having the above configuration, when the semiconductor chip 5 is operated, a current flows through the plurality of main current wirings 6 between the semiconductor chip 5 and the emitter pattern 3, and a current also flows through the auxiliary wirings 11. .

ここで、この電流が主電流配線６の持つ容量を超えて大きくなると、主電流配線６に過電流が流れるとともに、補助配線１１にも過電流が流れる。   Here, when this current increases beyond the capacity of the main current wiring 6, an overcurrent flows through the main current wiring 6 and an overcurrent also flows through the auxiliary wiring 11.

そして、半導体チップ５とエミッタパターン３との間の電流が所定の規定値を越えると、主電流配線６より先に補助配線１１が溶断する。かかる補助配線１１の溶断は、半導体応用装置のケース１２に形成された目視窓１３を通して外部から視認することができる。   When the current between the semiconductor chip 5 and the emitter pattern 3 exceeds a predetermined specified value, the auxiliary wiring 11 is blown before the main current wiring 6. The fusing of the auxiliary wiring 11 can be visually recognized from the outside through the viewing window 13 formed in the case 12 of the semiconductor application device.

このように、補助配線１１の溶断有無を外観で調べることにより、主電流配線６に規定値以上の電流が加わっているかどうかを判別でき、電気特性の検査を行うことをせずに半導体応用装置の交換が必要であるといった判断を行うことができる。   In this manner, by examining the presence or absence of fusing of the auxiliary wiring 11, it is possible to determine whether or not a current exceeding the specified value is applied to the main current wiring 6, and it is possible to determine the semiconductor application apparatus without performing an inspection of electrical characteristics. It is possible to make a determination that replacement is necessary.

この場合、補助配線１１が溶断しても、主電流配線６が溶断しなければ、半導体応用装置の動作は正常に行なわれるため、例えば定期点検時に補助配線１１が溶断しているか否かを確認し、補助配線１１が溶断している半導体応用装置だけを交換するという取り扱いが可能である。   In this case, even if the auxiliary wiring 11 is blown, if the main current wiring 6 is not blown, the operation of the semiconductor application device is normally performed. For example, it is confirmed whether the auxiliary wiring 11 is blown during the periodic inspection. However, it is possible to handle only the semiconductor application device in which the auxiliary wiring 11 is melted.

また、目視窓１３を通じて補助配線１１の溶断を発見した場合には、半導体応用装置に加わる外部ノイズを減らしたり、半導体チップ５とエミッタパターン３との間の電流の値を下げるなどの処置を行なうことにより、半導体応用装置の停止や破壊を未然に防ぐことができる。   When the fusing of the auxiliary wiring 11 is found through the visual window 13, measures such as reducing external noise applied to the semiconductor application device or lowering the current value between the semiconductor chip 5 and the emitter pattern 3 are taken. As a result, the semiconductor application device can be prevented from being stopped or destroyed.

以上のことから、補助配線１１が形成されていない場合に比べると、主電流配線６が異常に加熱して突然に溶断し半導体応用装置の動作を停止してしまったり、半導体応用装置内の半導体チップ５等に電流が集中して破壊を起こしたりする事態を防止できる。   From the above, as compared with the case where the auxiliary wiring 11 is not formed, the main current wiring 6 is abnormally heated and suddenly melts and stops the operation of the semiconductor application device, or the semiconductor in the semiconductor application device. It is possible to prevent a situation in which current concentrates on the chip 5 or the like and causes destruction.

｛実施の形態２｝
図５は本発明の実施の形態２に係る半導体応用装置の一部の構造を示す平面図である。なお、図５では実施の形態１と同様の機能を有する要素については同一符号を付している。 {Embodiment 2}
FIG. 5 is a plan view showing a partial structure of the semiconductor application device according to the second embodiment of the present invention. In FIG. 5, elements having the same functions as those in the first embodiment are denoted by the same reference numerals.

この実施の形態の半導体応用装置は、図５の如く、エミッタパターン３とゲートパターン４とが、コレクタパターン２が形成された絶縁基板１上に形成されるのではなく、ケース１２に内蔵された構成となっている。   In the semiconductor application device of this embodiment, as shown in FIG. 5, the emitter pattern 3 and the gate pattern 4 are not formed on the insulating substrate 1 on which the collector pattern 2 is formed, but are built in the case 12. It has a configuration.

その他の構成は、実施の形態１と同様である。特に、半導体チップ５とエミッタパターン３との間に、主電流配線６に並列に補助配線１１を形成している点、及びこの補助配線１１がケース１２（図３）の目視窓１３で目視できる点が、実施の形態１と同様である。   Other configurations are the same as those in the first embodiment. In particular, the auxiliary wiring 11 is formed in parallel with the main current wiring 6 between the semiconductor chip 5 and the emitter pattern 3, and the auxiliary wiring 11 can be visually observed through the viewing window 13 of the case 12 (FIG. 3). The point is the same as in the first embodiment.

かかる実施の形態でも、実施の形態１と同様の利点がある。   This embodiment has the same advantages as those of the first embodiment.

｛実施の形態３｝
図６は本発明の実施の形態３に係る半導体応用装置の構造を示す平面図である。なお、図６では実施の形態１と同様の機能を有する要素については同一符号を付している。 {Third embodiment}
FIG. 6 is a plan view showing the structure of a semiconductor application device according to Embodiment 3 of the present invention. In FIG. 6, elements having the same functions as those in the first embodiment are denoted by the same reference numerals.

この実施の形態の半導体応用装置は、図６の如く、半導体チップ５とエミッタパターン３との間に、主電流配線６に並列に複数の補助配線１１が形成されたものである。この複数の補助配線１１は、ケース１２（図３）の目視窓１３で目視できる点は、実施の形態１と同様である。   In the semiconductor application apparatus of this embodiment, as shown in FIG. 6, a plurality of auxiliary wirings 11 are formed in parallel with the main current wiring 6 between the semiconductor chip 5 and the emitter pattern 3. The plurality of auxiliary wirings 11 are the same as in the first embodiment in that they can be seen through the viewing window 13 of the case 12 (FIG. 3).

この実施の形態では、複数の補助配線１１のうちの何本が溶断したかを目視窓１３で目視して調べることで、過電流の大小を知ることができる。   In this embodiment, it is possible to know the magnitude of the overcurrent by visually checking how many of the plurality of auxiliary wirings 11 are blown out with the visual window 13.

｛実施の形態４｝
本発明の実施の形態４に係る半導体応用装置は、図６に示した実施の形態３の構造と基本的には類似しているが、複数の補助配線１１のワイヤ径が異なるなどして、各補助配線１１の電流容量が異なって設定されている。 {Embodiment 4}
The semiconductor application device according to the fourth embodiment of the present invention is basically similar to the structure of the third embodiment shown in FIG. 6, but the wire diameters of the plurality of auxiliary wirings 11 are different. The current capacity of each auxiliary wiring 11 is set differently.

この場合において、半導体チップ５とエミッタパターン３との間に過電流が流れると、相対的にワイヤ径の細い補助配線１１が、相対的にワイヤ径の太い補助配線１１よりも先に溶断する。したがって、どのワイヤ径の補助配線１１が溶断したかを調べることで、過電流の大小を詳細に目視窓１３で目視することができる。   In this case, when an overcurrent flows between the semiconductor chip 5 and the emitter pattern 3, the auxiliary wiring 11 having a relatively small wire diameter is blown before the auxiliary wiring 11 having a relatively large wire diameter. Therefore, by checking which wire diameter of the auxiliary wiring 11 is melted, the magnitude of the overcurrent can be observed in detail with the viewing window 13.

｛実施の形態５｝
図７は本発明の実施の形態５に係る半導体応用装置の構造を示す平面図、図８は同じくその外観を示す平面図である。なお、図７及び図８では実施の形態１と同様の機能を有する要素については同一符号を付している。 {Embodiment 5}
FIG. 7 is a plan view showing the structure of a semiconductor application device according to Embodiment 5 of the present invention, and FIG. 7 and 8, elements having the same functions as those in the first embodiment are denoted by the same reference numerals.

この実施の形態の半導体応用装置は、図７及び図８の如く、ケース１２内に発光素子１４が設置され、この発光素子１４の一端が補助配線１１ａを通じて半導体チップ５に接続され、他端が補助配線１１ｂを通じてエミッタパターン３に電気的に接続されている。即ち、半導体チップ５とエミッタパターン３との間に、主電流配線６と並列に発光素子１４が接続されていることになる。   7 and 8, the semiconductor application device of this embodiment has a light emitting element 14 installed in a case 12, one end of the light emitting element 14 is connected to the semiconductor chip 5 through an auxiliary wiring 11a, and the other end is connected. The emitter pattern 3 is electrically connected through the auxiliary wiring 11b. That is, the light emitting element 14 is connected in parallel with the main current wiring 6 between the semiconductor chip 5 and the emitter pattern 3.

そして、発光素子１４は、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されない限り、半導体チップ５とエミッタパターン３との間に電流が流れることで点灯し、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されたときに発光素子１４が消灯する。   The light emitting element 14 is turned on when a current flows between the semiconductor chip 5 and the emitter pattern 3 unless at least one of the auxiliary wirings 11a and 11b is melted, and at least one of the auxiliary wirings 11a and 11b is turned on. When 11b is fused, the light emitting element 14 is turned off.

また、ケース１２の目視窓１３は、発光素子１４に対応する位置に形成されている。   The viewing window 13 of the case 12 is formed at a position corresponding to the light emitting element 14.

したがって、例えば半導体チップ５の通電時において、目視窓１３を通して発光素子１４が消灯していることを目視することにより、半導体チップ５とエミッタパターン３との間に過電流が流れていることを容易に認識できる。   Therefore, for example, when the semiconductor chip 5 is energized, it is easy for an overcurrent to flow between the semiconductor chip 5 and the emitter pattern 3 by visually observing that the light emitting element 14 is turned off through the viewing window 13. Can be recognized.

｛実施の形態６｝
本発明の実施の形態６に係る半導体応用装置は、目視窓１３が、透明度の高い樹脂を使用して、ケース１２に対して二色成型で形成されており、これにより目視窓１３とケース１２とが別部品でなく単一部品として構成されている。 {Sixth embodiment}
In the semiconductor application device according to the sixth embodiment of the present invention, the viewing window 13 is formed by two-color molding with respect to the case 12 using a resin having high transparency, whereby the viewing window 13 and the case 12 are formed. Are configured as a single part rather than a separate part.

具体的に、この半導体応用装置では、ひとつの金型に２つの射出装置を備えた金型成形装置を用いて、一方からケース１２用の黒色ＰＰＳ（ポリフェニレンサルファイド樹脂）等を射出すると共に、目視窓１３用の透明ＰＣ（ポリカーボネート樹脂）等を射出して、ケース１２と目視窓１３とを同時に成形すればよい。   Specifically, in this semiconductor application apparatus, a black mold PPS (polyphenylene sulfide resin) or the like for the case 12 is injected from one side using a mold forming apparatus provided with two injection apparatuses in one mold, and visually observed. The case 12 and the viewing window 13 may be molded simultaneously by injecting transparent PC (polycarbonate resin) or the like for the window 13.

ケース１２の内部の構成は、上記の実施の形態１〜５のいずれかと同様である。   The internal configuration of case 12 is the same as that of any of the first to fifth embodiments.

この実施の形態でも、上記の実施の形態１〜５と同様の利点があるとともに、目視窓１３を安価に製造できる利点がある。   This embodiment has the same advantages as those of the first to fifth embodiments, and also has the advantage that the viewing window 13 can be manufactured at a low cost.

尚、上記の実施の形態５では、発光素子１４は、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されない限り、半導体チップ５とエミッタパターン３との間に電流が流れることで点灯し、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されたときに発光素子１４が消灯するようになっていたが、逆に、発光素子１４が、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されない限り消灯し、少なくともいずれか一方の補助配線１１ａ，１１ｂが溶断されたときに点灯するようにしてもよい。   In the fifth embodiment, the light-emitting element 14 is turned on when a current flows between the semiconductor chip 5 and the emitter pattern 3 unless at least one of the auxiliary wirings 11a and 11b is blown. The light emitting element 14 is turned off when either one of the auxiliary wirings 11a and 11b is melted. Conversely, as long as at least one of the auxiliary wirings 11a and 11b is not melted, the light emitting element 14 is turned off. The light may be turned off and turned on when at least one of the auxiliary wirings 11a and 11b is melted.

例えば図９の如く、補助配線１１が溶断されていないときには、この補助配線１１によりトランジスタ１５のベースが接地されるなどしてオフすることで、発光素子１４に流れる電流が遮断される一方、補助配線１１が溶断されたときには、トランジスタ１５のベースがハイ状態になってオンとなり、発光素子１４に電流が流れて点灯する構成であれば、正常状態で発光素子１４が消灯し、補助配線１１が溶断したときに始めて発光素子１４を点灯させることが可能となる。   For example, as shown in FIG. 9, when the auxiliary wiring 11 is not melted, the auxiliary wiring 11 is turned off by grounding the base of the transistor 15 or the like, whereby the current flowing through the light emitting element 14 is cut off. When the wiring 11 is blown, if the base of the transistor 15 is turned on and turned on and a current flows through the light emitting element 14, the light emitting element 14 is turned off in a normal state, and the auxiliary wiring 11 is turned on. It becomes possible to turn on the light emitting element 14 only after the fusing.

本発明の実施の形態１に係る半導体応用装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor application apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体応用装置の等価回路を示す概略回路図である。It is a schematic circuit diagram which shows the equivalent circuit of the semiconductor application apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体応用装置の外観を示す平面図である。It is a top view which shows the external appearance of the semiconductor application apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体応用装置の外観を示す断面図である。It is sectional drawing which shows the external appearance of the semiconductor application apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体応用装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor application apparatus which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体応用装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor application apparatus which concerns on Embodiment 3 of this invention. 本発明の実施の形態５に係る半導体応用装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor application apparatus which concerns on Embodiment 5 of this invention. 本発明の実施の形態５に係る半導体応用装置の外観を示す平面図である。It is a top view which shows the external appearance of the semiconductor application apparatus which concerns on Embodiment 5 of this invention. 本発明の他の実施例に係る半導体応用装置の一部を示す等価回路図である。It is an equivalent circuit diagram which shows a part of semiconductor application apparatus based on the other Example of this invention.

符号の説明Explanation of symbols

１ 絶縁基板，２ コレクタパターン，３ エミッタパターン，４ ゲートパターン，５ 半導体チップ，６ 主電流配線，７ ゲート配線，８ コレクタ接合部，９ エミッタ接合部，１０ ゲート接合部，１１， １１ａ，１１ｂ 補助配線，１２ ケース，１３ 目視窓，１３ａ シリコンゲル，１３ｂ エポキシ樹脂，１３ｃ 筒体，１４ 発光素子，１５ トランジスタ。
1 Insulating substrate, 2 Collector pattern, 3 Emitter pattern, 4 Gate pattern, 5 Semiconductor chip, 6 Main current wiring, 7 Gate wiring, 8 Collector junction, 9 Emitter junction, 10 Gate junction, 11, 11a, 11b Auxiliary Wiring, 12 cases, 13 viewing window, 13a silicon gel, 13b epoxy resin, 13c cylinder, 14 light emitting element, 15 transistor.

Claims (6)

少なくとも一の半導体チップと、
前記半導体チップを含む一対の部位の間に形成されて当該部位同士を接続する主電流配線と、
前記主電流配線よりも電流容量が小さく設定され、前記一対の部位同士の間に形成されて、前記主電流配線に並列に前記部位同士を接続する補助配線と、
前記一対の部位、前記主電流配線及び前記補助配線を収納するとともに、前記補助配線を外部から目視可能に形成された目視窓が形成されたケースとを備えることを特徴とする、
半導体応用装置。 At least one semiconductor chip;
A main current wiring that is formed between a pair of parts including the semiconductor chip and connects the parts;
A current capacity is set smaller than the main current wiring, formed between the pair of parts, an auxiliary wiring for connecting the parts in parallel to the main current wiring ,
A case in which the pair of parts, the main current wiring, and the auxiliary wiring are housed and a viewing window formed so that the auxiliary wiring is visible from the outside is formed.
Semiconductor application equipment. 請求項１に記載の半導体応用装置であって、The semiconductor application device according to claim 1,
前記補助配線が複数設けられたことを特徴とする半導体応用装置。A semiconductor application device comprising a plurality of the auxiliary wirings. 請求項２に記載の半導体応用装置であって、The semiconductor application device according to claim 2,
複数の前記補助配線の電流容量が異なって設定されたことを特徴とする半導体応用装置。A semiconductor application device, wherein the plurality of auxiliary wirings have different current capacities. 請求項１に記載の半導体応用装置であって、The semiconductor application device according to claim 1,
前記補助配線が溶断したか否かによって点灯状態と消灯状態とを変化させる発光素子をさらに備える半導体応用装置。A semiconductor application device further comprising a light emitting element that changes between a lighting state and a lighting state depending on whether or not the auxiliary wiring is blown. 請求項１に記載の半導体応用装置であって、The semiconductor application device according to claim 1,
前記補助配線がアルミニウム製である、半導体応用装置。A semiconductor application device, wherein the auxiliary wiring is made of aluminum. 請求項１に記載の半導体応用装置であって、The semiconductor application device according to claim 1,
前記ケースと前記目視窓とが同時成形で一体形成された単一部品である、半導体応用装置。A semiconductor application device, wherein the case and the viewing window are a single part integrally formed by simultaneous molding.
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