JP4228167B2 - CCD charge transfer drive circuit - Google Patents

Description

【００５４】
表１に示すように、デコーダ回路ＤＥに入力されたデータｂ₀からｂ₃までのデータの組み合わせにより、デコーダ回路ＤＥの１０本の出力端子ＥＮ０からＥＮ９までのうち、いずれの出力端子に接続されているチャネルを選択するかを決定する。
【００５５】
表１では、"１"が出力される出力端子に接続されているチャネルが選択され、"０"が出力される出力端子に接続されているチャネルが非選択となる。
【００５６】
尚、４つのデータが"０"と"１"との２つの状態を取りうるので、４つのデータの組み合わせとしては、２⁴の１６通りの組み合わせが可能となる。複数のチャネルについて同時に同じ状態を選択する場合があるため、組み合わせの数はチャネル数よりも多くしている。
【００５７】
上記の１０本の出力端子が、１０本のチャネルを動作させるための信号を出力する。
【００５８】
例えば実際の回路では、１０本の出力信号端子のうちＥＮ０からＥＮ３を４本の２値用チャネルに、ＥＮ４からＥＮ９を６本の３値用チャネルに割り当てている。以下においては、簡単のため２値用チャネルと３値用チャネルとを各１本ずつ有している場合について説明するが、実際の回路例では２値用チャネルと３値用チャネルとは例えば４チャネルと６チャネルの構成となっている。
【００５９】
制御クロック信号付与許可回路３は、２値用チャネルＢＤ１の制御クロック信号を付与するための２入力ＡＮＤ回路１１−１と、３値用チャネルＴＤ１に制御クロック信号を付与するための２入力ＡＮＤ回路１５−１とを有している。
【００６０】
２値用及び３値用の２入力ＡＮＤ回路１１−１、１５−１は、２つの入力端子と１つの出力端子とを有している。２値用及び３値用の２入力ＡＮＤ回路１１−１、１５−１の一方の入力端子は、デコーダ回路ＤＥの出力端子の１つ、例えば出力端子ＥＮ０、ＥＮ４と接続されている。
【００６１】
２値用及び３値用の２入力ＡＮＤ回路１１−１、１５−１の入力端子の他方には、タイミング発生回路ＴＧから出力される制御クロック信号ＣＫが入力される。
【００６２】
３値用チャネル用の２入力ＡＮＤ回路１５−１の出力端子は、それぞれ各１組の第４及び第５のラッチ回路２１、２５の制御クロック入力端子ＣＫ２１、ＣＫ２５と接続されている。
【００６３】
許可信号出力回路２の出力端子ＥＮ０からＥＮ９までのうちいずれかの出力信号が選択状態、すなわち"１"の場合には、許可信号出力回路２の出力端子と接続されている２入力ＡＮＤ回路１１−１又は１５−１の他方の入力端子から入力される信号、すなわち制御クロック信号ＣＫが２入力ＡＮＤ回路１１−１又は１５−１からそのまま出力される。
【００６４】
許可信号出力回路２の出力端子ＥＮ０からＥＮ９までのうちいずれかの出力信号が非選択状態、すなわち"０"の場合には、その出力端子と接続されている２入力ＡＮＤ回路１１−１又は１５−１の他方の入力端子から入力される信号、すなわち制御クロック信号ＣＫには関係なく入力ＡＮＤ回路１１−１又は１５−１からは"０"が出力される。
【００６５】
すなわち、制御クロック信号付与許可回路３内の２入力ＡＮＤ回路１１−１，１５−１は、許可信号出力回路２からの許可信号"１"を受けた場合にのみ制御クロック信号ＣＫを出力する回路である。
【００６６】
第２のラッチ回路部４は、第３のラッチ回路１７−１と、第４のラッチ回路２１−１と、第５のラッチ回路２５−１とを有する。
【００６７】
第３のラッチ回路１７−１は、符号化回路ＣＯにより符号化された例えば４ビットのデータ信号ＤＩ_0,3（第１から第４までの４つのバイナリデータｂ₀からｂ₃までを含む）のうちｂ₀が入力される入力端子Ｄ１７を有する。第３のラッチ回路１７−１のクロック入力端子ＣＫ１７は、２入力ＡＮＤ回路１１−１の出力端子と接続される。
【００６８】
第４のラッチ回路２１−１は、符号化回路ＣＯにより符号化された例えば４ビットのデータ信号ＤＩ_0,3（第１から第４の４つのバイナリデータｂ₀からｂ₃までを含む）のうちｂ₀が入力される入力端子Ｄ２１を有する。第４のラッチ回路２１−１のクロック入力端子ＣＫ２１は、２入力ＡＮＤ回路１５−１の出力端子と接続される。
【００６９】
第５のラッチ回路２５−１は、符号化回路ＣＯにより符号化された例えば４ビットのデータ信号ＤＩ_0,3（第１から第４までの４つのバイナリデータｂ₀からｂ₃までを含む）のうちｂ₁が入力される入力端子Ｄ２５を有する。第５のラッチ回路２５−１のクロック入力端子ＣＫ２５は、２入力ＡＮＤ回路１５−１の出力端子と接続される。
【００７０】
すなわち、第４のラッチ回路２１と第５のラッチ回路２５との２つのラッチ回路の制御クロック入力端子ＣＫ２１−１とＣＫ２５−１とは共通に結線されている。
【００７１】
許可信号を受けたチャネルに属する第２のラッチ回路部４中の第２から第４までのラッチ回路１７−１、２１―１，２５−１のクロック信号入力端子ＣＫ１７、ＣＫ２１及びＣＫ２５に制御クロック信号ＣＫが入力する。
【００７２】
加えて、第２から第４までのラッチ回路１７−１，２１−１、２５−１の入力端子Ｄ１７、Ｄ２１、Ｄ２５にも、タイミング発生回路ＴＧから出力され符号化されたデータ信号ＤＩ_0,3も入力されている。制御クロック信号ＣＫによりデータ信号をラッチする。
【００７３】
【表２】

【００７４】
ラッチされたデータＤＩ_0,3の値に応じて、例えば表２に示すように３値のチャネルからの出力状態ＶＬ、ＶＭ、またはＶＨのいずれかの出力状態が決定される。２値のチャネルからの出力状態も決定される。
【００７５】
より詳細には、許可信号を受けて選択されたチャネルに対応する第２から第４までのラッチ回路１７−１、２１−１、２５−１は、図４に示すように、第２のタイミング、例えば制御クロック信号ＣＫの立ち上がり時ｔ２において、データ信号ＤＩ_0,3のデータをラッチする。第２のラッチ回路１７−１は、データｂ₀を、第３のラッチ回路２１−１はデータｂ₀を、第４のラッチ回路２５−１はデータｂ₁をラッチする。
【００７６】
選択されたチャネル、例えば２値用チャネルＢＤ１と３値用チャネルＴＤ１とのにデータ信号ＤＩ_0,3（ｂ₀又はｂ₀及びｂ₁）が供給される。
【００７７】
ドライバー回路部５は、２値用チャネルＢＤ１と３値用チャネルＴＤ１とを含む。
【００７８】
３値用チャネルＴＤ１は、第１の比較器３１ａ、第２の比較器３１ｂと３値のスイッチ回路３３ａとを含む。
【００７９】
２値用チャネルＢＤ１は、第３の比較器３１ｃと２値のスイッチ回路３３ｂとを含む。
【００８０】
接地電位ＧＮＤ（０Ｖ）と電源電圧ＶＤＤ（３．３Ｖ）との間に２つの直列抵抗Ｒ１、Ｒ２が接続されており、２つの直列抵抗Ｒ１，Ｒ２の間に存在する節点ｘにおける分割電圧が１．６５Ｖになるように抵抗値Ｒ１、Ｒ２の値が設定されている。
【００８１】
節点ｘにおける約１．６５Ｖに設定された電圧は、第１から第３までの比較器３１ａ、３１ｂ、３１ｃのそれぞれの反転入力端子（−）４１ａ、４３ａ、４５ａに供給される。
【００８２】
第５のラッチ回路２５−１の出力端子Ｑ２５が第１の比較器３１ａの非反転入力端子（＋）４１ｂに接続され、３値チャネル用の電荷転送用タイミングパルス入力端子ＴＩｍを形成している。
【００８３】
第４のラッチ回路２１−１の出力端子Ｑ２１が第２の比較器３１ｂの非反転入力端子（＋）４３ｂに接続され、読み出し用タイミングパルス入力端子ＰＧｍを形成している。
【００８４】
第３のラッチ回路１７−１の出力端子Ｑ１７が第３の比較器３１ｃの非反転入力端子（＋）４５ｂに接続され、２値チャネル用の電荷転送用タイミングパルス入力端子ＢＩｎを形成している。
【００８５】
第１の比較器３１ａは、第１の電源端子４１ｃと第２の電源端子４１ｄとの２つの電源端子を有している。第２の比較器３１ｂは、第３の電源端子４３ｃと第４の電源端子４３ｄとの２つの電源端子を有している。第３の比較器３１ｃは、第５の電源端子４５ｃと第６の電源端子４５ｄとの２つの電源端子を有している。
【００８６】
第１、第３、第５の電源端子４１ｃ、４３ｃ、４５ｃに対して高電圧電源ＶＨが接続され、例えば＋１６Ｖの電圧が印加されている。第２、第４、第６の電源用端子４１ｄ、４３ｄ、４５ｄに対して低電圧電源ＶＬが接続され、例えば−８Ｖの電圧が印加されている。
【００８７】
第１及び第２の比較器３１ａ、３１ｂの出力端子４１ｅ、４３ｅは、３値のスイッチ回路３３ａの２つの入力端子５１ａ、５１ｂにそれぞれ接続されている。
【００８８】
第３の比較器３１ｃの出力端子４５ｅは、２値のスイッチ回路３３ｂの入力端子５３ａとに接続されている。
【００８９】
３値用のチャネルＴＤ１に含まれる第１の比較器３１ａは、３値チャネル用の電荷転送用タイミングパルス入力端子ＴＩｍの電位と接地電圧ＧＮＤ（０Ｖ）と電源電圧（３．３Ｖ）との中間の電位１．６５Ｖとを比較し、３値チャネル用の電荷転送用タイミングパルス入力端子ＴＩｍの電位の方が高ければ高電圧ＶＨ（＋１６Ｖ）を、低ければ低電圧ＶＬ（−８Ｖ）を３値のパルス発生回路３３ａの一方の入力端子５１ａに出力する。
【００９０】
第２の比較器３１ｂは、読み出し用タイミングパルス入力端子ＰＧｍの電位と１．６５Ｖとを比較し、読み出し用タイミングパルス入力端子ＰＧｍの電位の方が高ければ高電圧ＶＨを、低ければ低電圧ＶＬを３値のパルス発生回路３３ａの他方の入力端子５１ｂに出力する。
【００９１】
第３の比較器３１ｃは、２値チャネル用の電荷転送用タイミングパルス入力端子ＢＩｎの電位と１．６５Ｖとを比較し、２値チャネル用の電荷転送用タイミングパルス入力端子ＢＩｎの電位の方が高ければ高電圧ＶＨ（＋１６Ｖ）を、低ければ低電圧ＶＬ（−８Ｖ）を２値のパルス発生回路３３ｂの入力端子５３ａに出力する。
【００９２】
３値のスイッチ回路３３ａは、３つの電源端子５１ｃ、５１ｄ、５１ｅを有している。３つの電源端子５１ｃ、５１ｄ、５１ｅは、それぞれ、高電圧端子ＶＨ、中間電圧端子ＶＭ、低電圧端子ＶＬに接続され、順に＋１６Ｖ、０Ｖ、−８Ｖの電圧が印加される。３値のスイッチ回路３３ａの出力端子５１ｆが３値チャネル用の出力端子ＴＯｍを形成している。
【００９３】
２値のスイッチ回路３３ｂは、２つの電源端子５３ａ、５３ｃを有している。２つの電源端子５３ａ、５３ｃは、それぞれ、中間電圧端子ＶＭ、低電圧端子ＶＬに接続され、０Ｖ及び−８Ｖの電圧が印加されている。２値のスイッチ回路３３ｂの反転出力端子５３ｄが２値チャネル用の出力端子ＢＯｎを形成している。
【００９４】
図５及び図６をも参照して、ドライバー回路部５の動作について説明する。
【００９５】
図５（ａ）は３値スイッチ回路３３ａの入力端子５１ａに入力される信号電圧を、図５（ｂ）は３値スイッチ回路３３ａの入力端子５１ｂに入力される信号電圧を、図５（ｃ）は３値スイッチ回路３３ａの出力端子５１ｆから出力される出力信号を示す。
【００９６】
図６（ａ）は２値スイッチ回路３３ｂの入力端子５３ａに入力される信号電圧を、図６（ｂ）は２値スイッチ回路３３ｂの出力端子５３ｄから出力される出力信号を示す。
【００９７】
図５（ａ）から（ｃ）までに示すように、３値のスイッチ回路３３ａは、第１の比較器３１ａと第２の比較器３１ｂとから出力された２つの信号電圧（ＶＨ、ＶＬ）の入力の組み合わせパターンにより、ＶＨ（＋１６Ｖ）、ＶＭ（０Ｖ）、ＶＬ（−８Ｖ）のうちのいずれかの電圧信号を３値チャネル用の出力端子ＴＯｍに出力する。
【００９８】
ｂ₀がＬｏｗの場合には、３値チャネル用の出力端子ＴＯｍにおける出力信号は、ｂ₁のＬｏｗ、Ｈｉｇｈによって決まる。ｂ₁がＬｏｗであれば出力信号はＶＬであり、ｂ₁がＨｉｇｈであれば出力信号はＶＭとなる。ｂ₀がＨｉｇｈの場合には、３値チャネル用の出力端子ＴＯｍにおける出力信号は、ｂ₁の値によらずＶＨとなる。
【００９９】
すなわち、３値のスイッチ回路３３ａの入力端子５１ｂに入力される信号電圧がＶＬの間、入力端子５１ａにＶＬが入力されると出力信号はＶＬ（−８Ｖ）となり、ＶＨが入力されると出力信号はＶＭ（０Ｖ）となる。
【０１００】
入力端子５１ｂに入力される信号電圧がＶＨの間は、入力端子５１ａに入力される信号電圧値にかかわらず、出力信号がＶＨ（＋１６Ｖ）となる。
【０１０１】
２値のパルス発生回路３３ｂは、第３の比較器３１ｃから出力された１つの入力信号により、ＶＭ（０Ｖ）、ＶＬ（−８Ｖ）のうちのいずれかを２値チャネル用の出力端子ＢＯｎに出力する。
【０１０２】
図６（ａ）及び図６（ｂ）に示すように、２値のスイッチ回路３３ｂは、入力端子に信号電圧ＶＨが入力されると出力信号がＶＭに、入力端子に信号電圧ＶＬが入力されると、出力信号がＶＬになる。
【０１０３】
２値チャネル用の出力端子ＢＯｎの出力信号は、ｂ₀のＬＯＷ、ＨＩＧＨのみによって決定される。
【０１０４】
３値用チャネルの出力端子ＴＯｍ及び２値用チャネルの出力端子ＢＯｎに出力された信号は、例えばＣＣＤ固体撮像素子の垂直電荷転送路における電荷転送電極に印加される。光電変換素子から垂直電荷転送路への電荷の読み出し及び垂直電荷転送路内の電荷の転送を行うことができる。
【０１０５】
図４に示すように、時間ｔ３、すなわち制御クロック信号ＣＫの立ち下がり時に、データＤＩ_0,3が読み出され、読み出されたデータＤＩ_0,3に応じて、復号化回路ＤＥの出力端子のうちのいずれか（例えばＥＮｙで表す）の電圧信号がＨｉｇｈになり、ＥＮｙに繋がるチャネルが選択状態となる。逆にＥＮｘの電圧はＬｏｗになって、ＥＮｘに繋がるチャネルの選択が解除される。
【０１０６】
チャネルは、例えば表１に示すように選択される。
【０１０７】
チャネルＥＮｙが選択状態になっている時間内に、例えば時間ｔ４において制御クロック信号ＣＫが立ち上がると、データＤＩ_0,3が再び読み出され、読み出されたデータＤＩ_0,3に応じて、例えば表２に示すように出力状態がＶＬ、ＶＭ又はＶＨが再び決定される。
【０１０８】
以上の動作により、所望のタイミングで所望のチャネルを所望の出力状態にすることができる。
【０１０９】
以上に説明したように、本実施の形態による電荷転送用駆動回路は、タイミング発生回路において符号化された駆動信号を電荷転送用駆動回路内において復号化して用いる。
【０１１０】
従って、タイミング発生回路からの信号を入力するための入力端子数を大幅に減らすことができる。加えて、タイミング発生回路の出力端子数及びタイミング発生回路と電荷転送用駆動回路とを接続する配線の本数も減らすことができる。
【０１１１】
付加されるコーダ回路、デコーダ回路自体は非常に簡単な回路であり、回路全体の集積度もそれほど高くはならない。むしろパッケージの端子数を減らすことができる効果の方が大きい。
【０１１２】
尚、上記の実施の形態においては、データバスを４ビットとしているが、チャネル数を増加させたい場合や、チャネルの選択方法の組み合わせが多い場合などには、データバスの本数を増やせば良い。
【０１１３】
以上、本実施の形態により固体撮像装置について例示的に説明したが、その他、種々の変更、改良、組み合わせ等が可能なことは当業者には自明あろう。
【０１１４】
【発明の効果】
電荷転送用駆動回路の入力端子数を減らすことができる。加えて、電荷転送用駆動回路と接続されるタイミング発生器の出力端子数を減らすことができる。
【図面の簡単な説明】
【図１】 本発明の一実施の形態によるＣＣＤ固体撮像素子とその周辺回路の機能ブロック図である。
【図２】 本発明の一実施の形態による電荷転送用駆動回路の機能ブロック図である。
【図３】 図２に示す電荷転送用駆動回路の、より詳細な回路図である。
【図４】 図３に示す電荷転送用駆動回路の動作を示すタイミングチャート図である。
【図５】 ３値のチャネルの動作を示すタイミングチャート図である。
【図６】 ２値のチャネルの動作を示すタイミングチャート図である。
【符号の説明】
ＣＣＤ１ ＣＣＤ固体撮像素子
ＡＳＰ アナログ信号処理回路
ＤＳＰ デジタル信号処理回路
ＴＧ タイミング発生回路
ＤＲＶ１ 電荷転送用駆動回路
ＴＤ１ ３値用チャネル
ＢＤ１ ２値用チャネル
１ 第１のラッチ回路部
２ 許可信号出力回路
３ 制御クロック信号付与許可回路
４ 第２のラッチ回路部
５ ドライバー回路部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge transfer drive circuit for applying a drive voltage for transferring charges in a vertical charge transfer path to a vertical charge transfer electrode of a CCD solid-state imaging device.
[0002]
[Prior art]
Peripheral circuits for the CCD solid-state imaging device include an analog signal processing circuit (Analog Signal Processor), a digital signal processing circuit (Digital Signal Processor), a timing generation circuit (TimingGenerator), and a charge transfer drive circuit (Driver Circuit). including.
[0003]
In general, the analog signal processing circuit, the digital signal processing circuit, and the timing generation circuit are driven with a relatively low voltage such as 3.3V as a power supply voltage. Therefore, the above circuit can be manufactured using a normal submicron CMOS process.
[0004]
In order to drive a vertical charge transfer path that is included in a CCD solid-state imaging device and transfers charges from a photoelectric conversion device in the vertical direction, generally three types of voltage signals including a negative voltage are required. There are three types of voltage signals, for example, a + 16V signal used for reading out charges from the photoelectric conversion element to the vertical charge transfer path, and a 0V and -8V signal used for transferring charges in the vertical charge transfer path. Including voltage signals. As a power supply voltage of the charge transfer drive circuit for generating a drive signal for transferring charges in the vertical charge transfer path, a high voltage as high as 24 V is required as a potential difference.
[0005]
Since the power supply voltage is high, the charge transfer driving circuit needs to be manufactured using a high-breakdown-voltage transistor. Manufactured using a high voltage CMOS process instead of a submicron CMOS process.
[0006]
On the other hand, the driving circuit for binary driving outputs, for example, two kinds of voltage pulse signals of 0V and −8V.
[0007]
In the case of ternary driving, two input terminals are provided for one output terminal. In the case of binary driving, one input terminal is provided for one output terminal.
[0008]
[Problems to be solved by the invention]
The total number of drive circuits for charge transfer is increasing due to the megapixels of the solid-state imaging device. For example, in a charge transfer drive circuit used in a recent megapixel CCD, a configuration having six ternary channels and four binary channels is common. A total of 16 input terminals are provided, 12 for the value channel and 4 for the binary channel.
[0009]
The same number of output terminals are required for the timing generator corresponding to each input terminal. Since the CCD transfer electrode drive circuit chip and the timing generator chip are mounted in a package, the number of terminals required for each package increases, leading to an increase in cost.
[0010]
A means for reducing the number of terminals of the package by integrating the timing generation circuit and the charge transfer drive circuit on the same chip is also conceivable. However, in order to manufacture a 3.3 V drive sub-micron CMOS and a CMOS transistor that requires a high breakdown voltage on the same substrate, process complexity is inevitable and the manufacturing cost increases.
[0011]
An object of the present invention is to reduce the number of input terminals of a CCD transfer electrode driving circuit connected to a timing generator.
[0012]
[Means for Solving the Problems]
According to one aspect of the present invention, a driver circuit unit including two or more channels that can be switched and output at least two states, and decoded channel selection information are decoded, and the driver circuit unit includes A channel selection circuit for selecting one or more included channels, and a channel selected by the channel selection circuit, receiving the encoded output state determination information, and determining the output state of the channel There is provided a CCD charge transfer driving circuit including a state determining circuit.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
As used herein, a channel means a single signal path or control path in a device or system having many signals or control circuits. More specifically, a ternary or binary signal output circuit for outputting a ternary or binary signal is included.
[0014]
A CCD charge transfer driving circuit according to an embodiment of the present invention will be described below with reference to FIGS.
[0015]
FIG. 1 shows a functional block diagram of a CCD solid-state imaging device and its peripheral circuits.
[0016]
As shown in FIG. 1, the peripheral circuit for the CCD solid-state imaging device 1 includes an analog signal processor ASP, a digital signal processor DSP, and a timing generator TG. And a charge transfer driving circuit (Driver Circuit) DRV.
[0017]
The analog signal processing circuit ASP reduces the reset noise included in the analog signal output from the CCD solid-state image pickup device 1 by using a correlated double sampling circuit, and then provides an appropriate gain for A / D conversion. To do.
[0018]
The digital signal processing circuit DSP processes the obtained digital image signal.
[0019]
The timing generation circuit TG generates a timing signal for driving the CCD solid-state imaging device 1 and its charge transfer driving circuit DRV, generates a timing pulse for the analog signal processing circuit ASP, and further generates a digital signal processing circuit. A timing pulse for synchronizing with the DSP is generated.
[0020]
The charge transfer drive circuit DRV is a circuit that applies a drive pulse to the vertical charge transfer electrode of the CCD solid-state imaging device 1.
[0021]
The analog signal processing circuit ASP, the digital signal processing circuit DSP, and the timing generation circuit TG are generally driven by a relatively low power supply voltage such as 3.3V.
[0022]
In order to drive a vertical charge transfer path included in the CCD solid-state imaging device 1 for transferring charges from the photoelectric conversion device in the vertical direction, two types of drive circuits of ternary driving and binary driving are mainly required. It becomes.
[0023]
A three-value driving circuit generally requires three types of voltage signals including a negative voltage. The voltage signal is, for example, +16 V used for reading out charges from the photoelectric conversion element to the vertical charge transfer path, and 0 V and -8 V used in total for transferring charges in the vertical charge transfer path. The drive circuit for binary driving outputs, for example, two kinds of voltage pulses of 0V and −8V used for charge transfer.
[0024]
FIG. 2 shows a functional block diagram of the charge transfer drive circuit. FIG. 2 also shows a timing generation circuit.
[0025]
As shown in FIG. 2, the charge transfer drive circuit DRV1 includes a first latch circuit unit 1, a permission signal output circuit 2, a control clock signal application permission circuit 3, a second latch circuit unit 4, and a driver. Circuit portion 5.
[0026]
In the timing generation circuit TG, an encoding circuit (coder circuit) CO for encoding and outputting a data signal is incorporated in advance.
[0027]
The timing generation circuit TG forms a reference clock signal that defines a reference timing for controlling the circuit operation and a data signal for selecting a channel and determining an output state. Is encoded.
[0028]
A control clock signal CK and, for example, a 4-bit data signal DI encoded by the coder circuit CO from the timing generation circuit TG to the charge transfer drive circuit DRV1._0,3(Four binary data b from the first to the fourth₀To b_ThreeAre output via the control clock signal line CL and the data bus line DBL, respectively.
[0029]
The channel selection circuit includes a first latch circuit unit 1, a permission signal output circuit 2, and a control clock signal application permission circuit 3. The state determination circuit includes a second latch circuit unit 4. The driver circuit unit 5 includes, for example, binary and ternary channels.
[0030]
The first latch circuit section 1 has a control clock signal CK and a 4-bit data signal DI._0,3Are entered. The first latch circuit unit 1controlThe data signal DI at the first timing of the clock signal CK_0,3Latch. Latched data signal DI_0,3Is input to the permission signal output circuit 2 as an output signal from the first latch circuit section 1.
[0031]
The permission signal output circuit 2 includes a decoding circuit (decoder) DE for decoding the data signal encoded by the encoding circuit CO and latched and output by the first latch circuit unit 1.
[0032]
The output signal (permission signal) decoded by the decoding circuit DE in the permission signal output circuit 2 is output to the control clock signal addition permission circuit 3 through the output terminals (ENn, ENm) of the permission signal output circuit 2.
[0033]
The control clock signal addition permission circuit 3 also receives the control clock signal CK from the timing generation circuit TG. The control clock signal CK is output via the control clock signal addition permission circuit 3 only to the channel to which the permission signal from the permission signal output circuit 2 is input. The control clock signal CK is input to the second latch circuit unit 4.
[0034]
The second latch circuit section 4 has a data signal DI from the timing generator TG._0,3Is also entered. The second latch circuit unit 4 latches the input 1-bit signal (for binary channel) and 2-bit signal (for ternary channel) at the second timing, and these signals are included in the driver circuit unit 5. Output for each channel.
[0035]
The driver circuit unit 5 has, for example, at least one ternary channel TD1 and two binary channels TD2. Two or more ternary channels TD1 or binary channels BD1 may be provided.
[0036]
The binary channel BD1 has a binary channel charge transfer timing pulse input terminal BIn and a binary channel output terminal BOn.
[0037]
The ternary channel TD1 has a charge transfer timing pulse input terminal TIm and a read timing pulse input terminal PGm of the ternary channel, and an output terminal TOm for the ternary channel.
[0038]
Further, the driver circuit unit 5 includes a ground terminal GND and a power supply terminal V._DDhave.
[0039]
The output signal of the second latch circuit unit 4 is the charge transfer timing pulse input terminal TIm for the ternary channel of the driver circuit unit 5, the read timing pulse input terminal PGm, and the charge transfer timing pulse input for the binary channel. A binary or ternary signal is output from the terminal BIn and output from the binary channel output terminal BOn and the ternary channel output terminal TOm.
[0040]
Since information for selecting a channel and state determination information for determining a signal output from the channel are transferred by a signal encoded in the charge transfer drive circuit, a large number of channels can be obtained with a small number of input terminals. Can be operated.
[0041]
Hereinafter, a more detailed configuration and operation of the charge transfer drive circuit DRV1 will be described with reference to FIGS.
[0042]
FIG. 3 is a more detailed circuit diagram of the charge transfer drive circuit DRV1 shown in FIG. FIG. 3 also shows the timing signal generation circuit TG.
[0043]
FIG. 4 is a timing chart showing the operation of the charge transfer device clock driver circuit transfer drive circuit shown in FIG. FIG. 5 is a timing chart showing the operation of the ternary channel, and FIG. 6 is a timing chart showing the operation of the binary channel.
[0044]
As shown in FIG. 3, the first latch circuit unit 1 is, for example, a 4-bit data signal b₀To b_ThreeHave four first latch circuits 1-0 to 1-3.
[0045]
The first latch circuits 1-0 to 1-3 receive the data signal b₀To b_ThreeInput terminals D0 to D3 to which any one data signal selected from among them is input, and one clock input terminal CK0 to CK3 (input in common) per latch circuit. ing. Further, each of the first latch circuits 1-0 to 1-3 has one output terminal Q0 to Q3 for each latch circuit.
[0046]
Data signal DI output from the timing generation circuit TG_0,3Are input to the four input terminals D0 to D3 of the first latch circuits 1-0 to 1-3 in the first latch circuit section 1, respectively. More specifically, b₀Is D0, b₁Is D1 and b₂Is D2 and b_ThreeIs input to D3.
[0047]
The control clock signal CK is input to the control clock signal input terminals CK0 to CK3 of the four first latch circuits 1-0 to 1-3.
[0048]
As shown in FIG. 4, the first latch circuit 1-0 receives the data b at the first timing t1 and at the falling time t1 of the control clock signal CK.₀Latch. Latched data b₀Is output from the output terminal Q0. The output signal is input to the decoder circuit DE in the permission signal output circuit 2.
[0049]
Similarly, in the other first latch circuits 1-1 to 1-3, the data b at the falling edge t1 of the control clock signal CK.₁, Data b₂, Data b_ThreeAre latched, and the latched signal is input to the decoder circuit DE in the permission signal output circuit 2.
[0050]
The permission signal output circuit 2 includes a decoder circuit DE. The decoder circuit DE has an output signal b from the output terminals Q0 to Q3 of the first latch circuits 1-0 to 1-3.₀To b_ThreeInput terminals DE0 to DE3 are provided.
[0051]
The decoder circuit DE decodes a 4-bit input signal and generates an output signal at a corresponding output terminal among, for example, ten output terminals from EN0 to EN9.
[0052]
More specifically, the output signal from the first latch circuit 1 is input to the decoder circuit DE in the permission signal output circuit 2. 4-bit binary data signal b₀To b_ThreeThe processes up to are decoded in the decoder circuit DE.
[0053]
[Table 1]

[0054]
As shown in Table 1, the data b input to the decoder circuit DE₀To b_ThreeDepending on the combination of the above data, it is determined which of the ten output terminals EN0 to EN9 of the decoder circuit DE is to be used to select a channel connected to the output terminal.
[0055]
In Table 1, a channel connected to an output terminal that outputs “1” is selected, and a channel connected to an output terminal that outputs “0” is not selected.
[0056]
Since the four data can take two states, “0” and “1”, the combination of the four data is 2^Four16 combinations are possible. Since the same state may be selected for a plurality of channels at the same time, the number of combinations is larger than the number of channels.
[0057]
The ten output terminals output signals for operating the ten channels.
[0058]
For example, in an actual circuit, among ten output signal terminals, EN0 to EN3 are assigned to four binary channels, and EN4 to EN9 are assigned to six ternary channels. In the following, a case will be described in which there is one binary channel and one ternary channel for simplicity, but in an actual circuit example, the binary channel and the ternary channel are, for example, 4 It has a configuration of channels and 6 channels.
[0059]
The control clock signal giving permission circuit 3 is a two-input AND circuit 11-1 for giving a control clock signal for the binary channel BD1, and a two-input AND circuit for giving a control clock signal to the ternary channel TD1. 15-1.
[0060]
The binary and ternary 2-input AND circuits 11-1 and 15-1 have two input terminals and one output terminal. One input terminal of the binary and ternary 2-input AND circuits 11-1 and 15-1 is connected to one of the output terminals of the decoder circuit DE, for example, the output terminals EN0 and EN4.
[0061]
The control clock signal CK output from the timing generation circuit TG is input to the other input terminal of the binary and ternary 2-input AND circuits 11-1 and 15-1.
[0062]
The output terminal of the 2-input AND circuit 15-1 for the ternary channel is connected to the control clock input terminals CK21 and CK25 of the fourth and fifth latch circuits 21 and 25, respectively.
[0063]
When one of the output terminals EN0 to EN9 of the enable signal output circuit 2 is in a selected state, that is, “1”, the 2-input AND circuit 11 connected to the output terminal of the enable signal output circuit 2 -1 or 15-1, the signal inputted from the other input terminal, that is, the control clock signal CK is outputted as it is from the 2-input AND circuit 11-1 or 15-1.
[0064]
When one of the output terminals EN0 to EN9 of the enable signal output circuit 2 is in a non-selected state, that is, “0”, the 2-input AND circuit 11-1 or 15 connected to the output terminal. "0" is output from the input AND circuit 11-1 or 15-1 regardless of the signal input from the other input terminal of -1, that is, the control clock signal CK.
[0065]
That is, the two-input AND circuits 11-1 and 15-1 in the control clock signal addition permission circuit 3 output the control clock signal CK only when the permission signal “1” is received from the permission signal output circuit 2. It is.
[0066]
The second latch circuit unit 4 includes a third latch circuit 17-1, a fourth latch circuit 21-1, and a fifth latch circuit 25-1.
[0067]
The third latch circuit 17-1 is, for example, a 4-bit data signal DI encoded by the encoding circuit CO._0,3(Four binary data b from the first to the fourth₀To b_ThreeB)₀Are input terminals D17. The clock input terminal CK17 of the third latch circuit 17-1 is connected to the output terminal of the 2-input AND circuit 11-1.
[0068]
The fourth latch circuit 21-1 is, for example, a 4-bit data signal DI encoded by the encoding circuit CO._0,3(First to fourth binary data b₀To b_ThreeB)₀Are input terminals D21. The clock input terminal CK21 of the fourth latch circuit 21-1 is connected to the output terminal of the 2-input AND circuit 15-1.
[0069]
The fifth latch circuit 25-1 is, for example, a 4-bit data signal DI encoded by the encoding circuit CO._0,3(Four binary data b from the first to the fourth₀To b_ThreeB)₁Are input terminals D25. The clock input terminal CK25 of the fifth latch circuit 25-1 is connected to the output terminal of the 2-input AND circuit 15-1.
[0070]
That is, the control clock input terminals CK21-1 and CK25-1 of the two latch circuits of the fourth latch circuit 21 and the fifth latch circuit 25 are connected in common.
[0071]
Control clocks are supplied to the clock signal input terminals CK17, CK21, and CK25 of the second to fourth latch circuits 17-1, 21-1, and 25-1 in the second latch circuit unit 4 belonging to the channel that has received the permission signal. The signal CK is input.
[0072]
In addition, the encoded data signal DI output from the timing generation circuit TG is also input to the input terminals D17, D21, D25 of the second to fourth latch circuits 17-1, 21-1, 25-1._0,3Is also entered. The data signal is latched by the control clock signal CK.
[0073]
[Table 2]

[0074]
Latched data DI_0,3For example, as shown in Table 2, the output state VL, VM, or VH from the ternary channel is determined according to the value of. The output state from the binary channel is also determined.
[0075]
More specifically, as shown in FIG. 4, the second to fourth latch circuits 17-1, 21-1, and 25-1 corresponding to the channel selected in response to the permission signal receive the second timing. For example, at the rising edge t2 of the control clock signal CK, the data signal DI_0,3Latch the data. The second latch circuit 17-1 receives data b₀The third latch circuit 21-1 receives the data b₀The fourth latch circuit 25-1 receives the data b.₁Latch.
[0076]
The data signal DI is transmitted to the selected channel, for example, the binary channel BD1 and the ternary channel TD1._0,3(B₀Or b₀And b₁) Is supplied.
[0077]
The driver circuit unit 5 includes a binary channel BD1 and a ternary channel TD1.
[0078]
The ternary channel TD1 includes a first comparator 31a, a second comparator 31b, and a ternary switch circuit 33a.
[0079]
The binary channel BD1 includes a third comparator 31c and a binary switch circuit 33b.
[0080]
Two series resistors R1 and R2 are connected between the ground potential GND (0V) and the power supply voltage VDD (3.3V), and the divided voltage at the node x existing between the two series resistors R1 and R2 is The resistance values R1 and R2 are set to 1.65V.
[0081]
The voltage set to about 1.65 V at the node x is supplied to the inverting input terminals (−) 41 a, 43 a, and 45 a of the first to third comparators 31 a, 31 b, and 31 c.
[0082]
The output terminal Q25 of the fifth latch circuit 25-1 is connected to the non-inverting input terminal (+) 41b of the first comparator 31a to form a charge transfer timing pulse input terminal TIm for the ternary channel. .
[0083]
The output terminal Q21 of the fourth latch circuit 21-1 is connected to the non-inverting input terminal (+) 43b of the second comparator 31b to form a read timing pulse input terminal PGm.
[0084]
The output terminal Q17 of the third latch circuit 17-1 is connected to the non-inverting input terminal (+) 45b of the third comparator 31c to form a charge transfer timing pulse input terminal BIn for a binary channel. .
[0085]
The first comparator 31a has two power supply terminals, a first power supply terminal 41c and a second power supply terminal 41d. The second comparator 31b has two power terminals, a third power terminal 43c and a fourth power terminal 43d. The third comparator 31c has two power terminals, a fifth power terminal 45c and a sixth power terminal 45d.
[0086]
A high voltage power supply VH is connected to the first, third, and fifth power supply terminals 41c, 43c, and 45c, and a voltage of, for example, + 16V is applied. A low voltage power supply VL is connected to the second, fourth, and sixth power supply terminals 41d, 43d, and 45d, and a voltage of, for example, -8V is applied.
[0087]
The output terminals 41e and 43e of the first and second comparators 31a and 31b are respectively connected to the two input terminals 51a and 51b of the ternary switch circuit 33a.
[0088]
The output terminal 45e of the third comparator 31c is connected to the input terminal 53a of the binary switch circuit 33b.
[0089]
The first comparator 31a included in the ternary channel TD1 is an intermediate between the potential of the charge transfer timing pulse input terminal TIm for the ternary channel, the ground voltage GND (0V), and the power supply voltage (3.3V). The potential of the charge transfer timing pulse input terminal TIm for the ternary channel is higher, the higher voltage VH (+16 V) is lower, and the lower voltage VL (−8 V) is lower if the potential is lower. Output to one input terminal 51a of the pulse generation circuit 33a.
[0090]
The second comparator 31b compares the potential of the read timing pulse input terminal PGm with 1.65V, and if the potential of the read timing pulse input terminal PGm is higher, the high voltage VH is lower, and if lower, the low voltage VL is lower. Is output to the other input terminal 51b of the ternary pulse generation circuit 33a.
[0091]
The third comparator 31c compares the potential of the binary channel charge transfer timing pulse input terminal BIn with 1.65V, and the potential of the binary channel charge transfer timing pulse input terminal BIn is greater. The high voltage VH (+ 16V) is output to the input terminal 53a of the binary pulse generation circuit 33b if the voltage is high and the low voltage VL (−8V) is output if the voltage is low.
[0092]
The ternary switch circuit 33a has three power supply terminals 51c, 51d, and 51e. The three power supply terminals 51c, 51d, and 51e are connected to a high voltage terminal VH, an intermediate voltage terminal VM, and a low voltage terminal VL, respectively, and voltages of + 16V, 0V, and -8V are sequentially applied. The output terminal 51f of the ternary switch circuit 33a forms an output terminal TOm for a ternary channel.
[0093]
The binary switch circuit 33b has two power supply terminals 53a and 53c. The two power supply terminals 53a and 53c are connected to the intermediate voltage terminal VM and the low voltage terminal VL, respectively, and voltages of 0V and −8V are applied thereto. The inverting output terminal 53d of the binary switch circuit 33b forms a binary channel output terminal BOn.
[0094]
The operation of the driver circuit unit 5 will be described with reference to FIGS.
[0095]
5A shows the signal voltage input to the input terminal 51a of the ternary switch circuit 33a, FIG. 5B shows the signal voltage input to the input terminal 51b of the ternary switch circuit 33a, and FIG. ) Indicates an output signal output from the output terminal 51f of the ternary switch circuit 33a.
[0096]
6A shows a signal voltage input to the input terminal 53a of the binary switch circuit 33b, and FIG. 6B shows an output signal output from the output terminal 53d of the binary switch circuit 33b.
[0097]
As shown in FIGS. 5A to 5C, the ternary switch circuit 33a has two signal voltages (VH, VL) output from the first comparator 31a and the second comparator 31b. Depending on the input combination pattern, any one of the voltage signals VH (+16 V), VM (0 V), and VL (−8 V) is output to the output terminal TOm for the ternary channel.
[0098]
b₀Is low, the output signal at the output terminal TOm for the ternary channel is b₁Of Low and High. b₁Is low, the output signal is VL, b₁If is high, the output signal is VM. b₀Is high, the output signal at the output terminal TOm for the ternary channel is b₁VH regardless of the value of.
[0099]
That is, while the signal voltage input to the input terminal 51b of the ternary switch circuit 33a is VL, the output signal becomes VL (−8V) when VL is input to the input terminal 51a, and the output is output when VH is input. The signal becomes VM (0 V).
[0100]
While the signal voltage input to the input terminal 51b is VH, the output signal is VH (+ 16V) regardless of the signal voltage value input to the input terminal 51a.
[0101]
The binary pulse generation circuit 33b uses either one of VM (0V) and VL (−8V) as a binary channel output terminal BOn in response to one input signal output from the third comparator 31c. Output.
[0102]
As shown in FIGS. 6A and 6B, in the binary switch circuit 33b, when the signal voltage VH is input to the input terminal, the output signal is input to VM, and the signal voltage VL is input to the input terminal. Then, the output signal becomes VL.
[0103]
The output signal of the output terminal BOn for the binary channel is b₀Only LOW and HIGH.
[0104]
Signals output to the output terminal TOm of the ternary channel and the output terminal BOn of the binary channel are applied to, for example, charge transfer electrodes in the vertical charge transfer path of the CCD solid-state imaging device. It is possible to read out charges from the photoelectric conversion element to the vertical charge transfer path and transfer charges in the vertical charge transfer path.
[0105]
As shown in FIG. 4, at time t3, that is, at the falling edge of the control clock signal CK, the data DI_0,3Is read and the read data DI_0,3In response to this, the voltage signal of any one of the output terminals of the decoding circuit DE (for example, represented by ENy) becomes High, and the channel connected to ENy is selected. On the contrary, the voltage of ENx becomes Low, and the selection of the channel connected to ENx is released.
[0106]
The channel is selected as shown in Table 1, for example.
[0107]
If the control clock signal CK rises at the time t4, for example, during the time that the channel ENy is in the selected state, the data DI_0,3Is read again, and the read data DI_0,3Accordingly, for example, as shown in Table 2, the output state VL, VM, or VH is determined again.
[0108]
 With the above operation, a desired channel can be brought into a desired output state at a desired timing.
[0109]
As described above, the charge transfer drive circuit according to the present embodiment uses the drive signal encoded in the timing generation circuit after being decoded in the charge transfer drive circuit.
[0110]
Therefore, the number of input terminals for inputting a signal from the timing generation circuit can be greatly reduced. In addition, the number of output terminals of the timing generation circuit and the number of wirings connecting the timing generation circuit and the charge transfer drive circuit can be reduced.
[0111]
The added coder circuit and decoder circuit itself are very simple circuits, and the degree of integration of the entire circuit is not so high. Rather, the effect of reducing the number of terminals of the package is greater.
[0112]
In the above embodiment, the data bus is 4 bits. However, the number of data buses may be increased when it is desired to increase the number of channels or when there are many combinations of channel selection methods.
[0113]
As described above, the solid-state imaging device has been exemplarily described according to the present embodiment. However, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like are possible.
[0114]
【The invention's effect】
The number of input terminals of the charge transfer drive circuit can be reduced. In addition, the number of output terminals of the timing generator connected to the charge transfer drive circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of a CCD solid-state imaging device and its peripheral circuits according to an embodiment of the present invention.
FIG. 2 is a functional block diagram of a charge transfer drive circuit according to an embodiment of the present invention.
3 is a more detailed circuit diagram of the charge transfer drive circuit shown in FIG. 2;
4 is a timing chart showing the operation of the charge transfer drive circuit shown in FIG. 3;
FIG. 5 is a timing chart showing the operation of a ternary channel.
FIG. 6 is a timing chart showing the operation of a binary channel.
[Explanation of symbols]
CCD1 CCD solid-state image sensor
ASP analog signal processing circuit
DSP digital signal processing circuit
TG timing generator
DRV1 charge transfer drive circuit
TD1 ternary channel
BD1 binary channel
1 1st latch circuit part
2 Enable signal output circuit
3 Control clock signal granting circuit
4 Second latch circuit section
5 Driver circuit

Claims (3)

A driver circuit unit including at least two channels capable of switching and outputting at least two states;
A channel selection circuit that decodes the encoded channel selection information and selects one or more channels included in the driver circuit unit;
A CCD charge transfer drive circuit including a state determination circuit that receives an encoded output state determination information for a channel selected by the channel selection circuit and determines an output state of the channel. The channel selection circuit includes a first latch circuit unit that latches a plurality of data input signals at a first timing;
The CCD charge transfer circuit according to claim 1, further comprising: a permission signal output circuit that outputs a permission signal for selecting one or more channels to be operated based on an output from the first latch circuit unit. Driving circuit. The state determination circuit receives output state determination information encoded for the channel selected by the permission signal, and latches this at a second timing after the first timing. 3. The CCD charge transfer drive circuit according to claim 2, further comprising a latch circuit unit.

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