JP4041101B2 - Timing generator, solid-state imaging device, and camera system - Google Patents

Description

  The present invention relates to a timing generator for generating timing pulses used for driving a solid-state imaging device.

  Video cameras and digital still cameras using a solid-state imaging device such as a CCD (Charge Coupled Device) are known. The development period of these cameras is getting shorter and the price is getting lower. Of course, there are many similar requests for the parts used for it, and it is necessary to shorten the development period and reduce the cost.

  A timing generator (timing generator) is an important component for generating a large number of timing pulses used for driving a solid-state imaging device. In order to realize the camera shake prevention function and the electronic zoom function of the camera, a timing pulse corresponding to the vertical high-speed transfer mode of the solid-state imaging device is required.

  Patent Document 1 discloses a memory for storing time-series data representing timing pulse patterns, and a counter for sequentially giving read addresses to the memory so that the specification change can be easily dealt with. There is disclosed a timing generator comprising:

  Patent Document 2 discloses a timing generator in which a timing pulse that repeats in the horizontal direction and a timing pulse that repeats in the vertical direction are obtained from separate memories for the purpose of reducing the memory capacity.

  Patent Document 3 discloses a timing generator including a decoder for decoding a rising pulse and a decoder for decoding a falling pulse so that the timing pulse can be set programmable by a microcomputer.

Patent Document 4 discloses a timing generator that can reduce the amount of data to be stored in a timing generator with a built-in memory for generating timing pulses used to drive a solid-state imaging device and realize a flexible function. Has been.
JP-A-63-61560 Japanese Patent Laid-Open No. 9-205591 Japanese Patent Laid-Open No. 10-257398 JP 2002-512270 A

  According to the timing generator described in Patent Document 4, it is possible to easily generate timing pulses having a number of complicated waveforms used for driving a solid-state imaging device. However, the pulse timing cannot be changed after the LSI is implemented as the timing generator. For this reason, when there is a change in the specification, etc., it is easy to change the pulse timing.

  The present invention can easily generate the pulse timing required for driving the solid-state imaging device using the timing generation information stored in the memory, and can rewrite the timing generation information from the outside. An object is to provide a timing generator.

In order to solve the above problems, a timing generator according to the present invention includes a first storage circuit that stores timing generation information, a first register that holds the timing generation information of the first storage circuit, and A first external input unit for accessing the first register to rewrite data; and the first storage circuit or the first external input unit for writing data to the first register. A selector that selects any one of the above, a second external input unit that supplies a selection signal of the selector, and a pulse timing corresponding to the timing generation information held in the first register to generate one or more a pulse generator for outputting a pulse, and a second register for holding control function information as the timing generator, the input data from the first external input unit the An input control unit that selects output to either the rectifier or the second register, and the selector selects data to be input to the first register in accordance with data of the second external input unit Then, the pulse generator is initialized during a period of selecting data from the first memory circuit and the input control unit and writing the data of the first external input unit to the first register .

According to the timing generator of the present invention, the timing generation information is set in the first memory circuit, so that the pulse timing required for driving the solid-state imaging device and signal processing can be easily generated. In addition, since the timing generation information can be rewritten from the outside, it is not necessary to re-create the LSI again for a specification change or the like after the LSI is formed as the timing generator.

Further, in the case of a programmable timing generation device that does not have a storage circuit and inputs timing generation information from the outside, the time for inputting all timing generation information at the time of power activation increases compared to the present invention. Since the timing generation information is set in the first memory circuit, it is not necessary to input the timing generation information in addition to the timing change, and the startup time from the camera power input is shortened.
Further, the data input unit for rewriting the data of the first and second registers from the outside is made common, and the timing is generated except for the first memory circuit and the first register during the data input period to the first register. It is possible to initialize the device. Further, the data input from the first external input unit can be rewritten to the first and second registers by the data input to the third external input unit and the data of the second external input unit. .

In the configuration of the timing generator of the present invention , preferably, a third external input unit that supplies a selection signal of the input control unit, and an output that is triggered by an edge of a pulse input from the third external input unit are used. The counter further includes a counting circuit that inverts and holds from the initial state and returns to the initial state after counting for a predetermined period, and the input control unit receives data input from the first external input unit according to the output of the counting circuit, Output to either the selector or the second register.

  According to this configuration, the data input unit for rewriting the data of the first and second registers from the outside is made common, and the pulse input to the third external input unit and the data of the second external input unit are used. Data in the first and second registers is rewritten by data input from the first external input unit, and timing is generated except for the first memory circuit and the first register during the data input period to the first register. It is possible to initialize the device.

  A solid-state imaging device or a camera system including the timing generator having any one of the above configurations can be configured.

  Hereinafter, a timing generator, a solid-state imaging device, and a camera system according to an embodiment of the present invention will be specifically described with reference to the drawings.

(Embodiment 1)
First, the configuration and operation of a solid-state imaging device to which the timing generator in Embodiment 1 is applied will be described. FIG. 1 is a block diagram illustrating a schematic configuration example of a CCD camera which is a solid-state imaging device. In FIG. 1, reference numeral 1 denotes, for example, an interlace scan type solid-state imaging device (CCD), and its output is subjected to CDS (correlated double sampling) and ADC (analog / digital conversion) processing by a preprocessing LSI 2. The output of the preprocessing LSI 2 is subjected to pixel interpolation, luminance / color difference processing, and the like by a digital signal processing (DSP) LSI 3 and output as a video signal. The timing generator (TG) LSI 4 generates timing pulses H1, H2, V1 to V4 and CH1, CH2 used for driving the solid-state imaging device 1. The clock driver (DR) LSI 5 supplies drive pulses φV1 to φ4 generated from V1 to V4 and CH1 and CH2 to the solid-state imaging device 1.

  The timing generator 4 receives the pulses of the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and the clock signal MCK from the digital signal processing LSI 3, and generates the timing pulses H1, H2, V1 to V4, and CH1, CH2, The signal processing pulse PROC is supplied to the preprocessing LSI 2 and the digital signal processing LSI 3. However, there is a case where the timing generator 4 generates a pulse of the horizontal and vertical synchronization signals.

  FIG. 2 shows a gate configuration example of the solid-state imaging device 1 in FIG. In FIG. 2, 6 is a photodiode (PD), 7 is a vertical transfer unit composed of four-phase gates GV1, GV2, GV3, and GV4, 8 is a horizontal transfer unit composed of two-phase gates GH1 and GH2, and 9 is a charge. Each detection unit is shown. In FIG. 2, the photodiode 6 and the vertical transfer unit 7 are illustrated in a simplified manner, but in the actual solid-state imaging device 1, combinations of the photodiode 6 and the vertical transfer unit 7 are arranged by the number of horizontal pixels. . The gates of the vertical transfer unit 7 are arranged by repeating the order of GV3, GV2, GV1, and GV4 from the horizontal transfer unit 8 side. The drive pulses φV1 to φV4 shown in FIG. 1 are supplied to the gates GV1 to GV4 of the vertical transfer unit 7, respectively. The timing pulses H1 and H2 shown in FIG. 1 are supplied to the gates GH1 and GH2 of the horizontal transfer unit 8, respectively.

  The reading method of the solid-state imaging device 1 in FIG. 2 is as follows. That is, charges are read from the photodiode 6 to the vertical transfer unit 7 by applying high voltage (about 15 V) drive pulses φV1 and φV3 to GV1 and GV3 in the vertical transfer unit 7, respectively. After the GV1 readout charge is mixed with the readout charge of the GV3 adjacent to the horizontal transfer unit 8 side to form a signal charge for one stage, or the GV3 readout charge is combined with the readout charge of the GV1 adjacent to the horizontal transfer unit 8 side. After mixing to make signal charges for one stage, drive pulses φV1 to φV4 are inputted to the gates of GV1 to GV4 of the vertical transfer unit 7. Thereby, the charges of two rows of the photodiodes 6 are simultaneously transferred to the horizontal transfer unit 8 once in one horizontal scanning period. In the horizontal transfer unit 8, timing pulses H 1 and H 2 are applied to transfer charges in the horizontal transfer unit 8, and a signal is output from the charge detection unit 9.

  FIG. 3 shows a waveform example (near the VD pulse) of the main signal in FIG. V1 and CH1 in FIG. 3 are timing pulses output from the timing generator 4 and are ternarized and voltage-converted by the clock driver 5 to become a driving pulse φV1. Timing pulses V2 to V4 (not shown) are converted into voltages by the clock driver 5 to become φV2 to φV4. The waveform example of FIG. 3 shows a case where the normal transfer mode and the vertical high-speed transfer mode are mixed in one vertical scanning period in order to realize the camera shake prevention function and the electronic zoom function. Specifically, the charges are read from the photodiode 6 to the vertical transfer unit 7 by applying φV1 and φV3 of about 15 V on the 17th line (number 17 scanning line). The charges are read out, and vertical high-speed transfer is continuously performed by φV1 to φ4, and then normal transfer is performed. Next, normal transfer is performed by φV1 to φ4 until a VD pulse is input, and then vertical high-speed transfer is started again. The driving mode in the timing chart of FIG.

  FIG. 4 shows a waveform example (near the VD pulse) of the main signal in FIG. 1 in the driving mode 2 as in FIG. The difference from the drive mode 1 in FIG. 3 is that the normal transfer unit for vertical transfer is one-stage transfer in the drive mode 1 but two-stage transfer in the drive mode 2.

  The waveform details of the normal transfer unit in the drive mode 1 are shown in FIG. 5, and the waveform details of the normal transfer unit in the drive mode 2 are shown in FIG. 5 and 6, T represents the period of the clock signal MCK. Further, the length of a period from a change point of a certain pulse to the next pulse change point, that is, a logical change unit is expressed as one step. The waveform of the normal transfer unit in the drive mode 1 shown in FIG. 5 has a logical change unit of 12T, a pulse change period of V1 to V4, that is, the number of steps for one vertical transfer is 8, and the vertical transfer is one stage. Note that the cycle of one stage of vertical transfer is 96 clocks. The waveform of the normal transfer unit in the drive mode 2 shown in FIG. 6 has a logical change unit of 10T, the number of steps for one stage of vertical transfer, and two stages of vertical transfer.

  FIG. 7 shows the configuration of the timing generator in the first embodiment. In the present embodiment, the configuration and operation in the case of being adapted to the timing generator 4 of FIG. 1 will be described. In FIG. 7, reference numeral 10 denotes a first storage circuit that stores timing generation information, and reference numeral 11 denotes a first register that holds information of the first storage circuit 10. The first register 11 can be rewritten from the outside by the first external input unit 12. The selector 13 selects from the first memory circuit 10 and the output of the first external input unit 12 as write data to the first register 11. The pulse generator 14 generates a timing pulse corresponding to the timing generation information of the first register 11, and the pulse output unit 15 outputs the output of the pulse generator 14 as the output of the timing generator.

  An operation for generating a timing pulse from the pulse generator 14 based on the timing generation information stored in the first memory circuit 10 will be described with reference to FIG. The configuration shown in FIG. 8 is an arrangement in which the functions of the first register 11 and the pulse generator 14 in FIG. 7 are disassembled so that the operation can be easily understood. Accordingly, the substantial configuration and operation are the same as the combination of the first register 11 and the pulse generator 14. Here, only the generation operation of V1 to V4 will be described.

  The apparatus shown in FIG. 8 includes a counting unit 30, a drive mode control unit 31, and a time series data ROM 32. The counting unit 30 includes a first ROM 33, a first counter 34, a first comparator 35, a second ROM 36, a second counter 37, a second comparator 38, a third ROM 39, a third counter 40, and a third comparator. 41, and the MCK pulse multiple count is executed on condition that the HD pulse is input to the first counter 34 as a trigger. Control values are stored in the first, second, and third ROMs 33, 36, and 39, respectively.

  The first counter 34 starts counting the MCK pulse in response to the HD pulse, initializes the count value in response to the initialization pulse CP1, and stops counting in response to the stop pulse CP3. The first comparator 35 compares the control value DT1 read from the first ROM 33 with the count value CNT1 of the first counter 34, and outputs the control pulse CP1 at the timing of the next MCK pulse each time they match. The control pulse CP1 is supplied to the second counter 37 and is supplied to the first counter 34 as an initialization pulse.

  The second counter 37 counts the control pulse CP1 output from the first comparator 35, and initializes the count value in response to the initialization pulse CP2. The second comparator 38 compares the control value DT2 read from the second ROM 36 with the count value CNT2 of the second counter 37, and outputs the control pulse CP2 at the timing of the next CP1 pulse each time they match. The control pulse CP2 is supplied to the third counter 40 and is supplied to the second counter 37 as an initialization pulse.

  The third counter 40 counts the control pulse CP2 output from the second comparator 38 and initializes the count value in response to the initialization pulse CP3. The third comparator 41 compares the control value DT3 read from the third ROM 39 with the count value CNT3 of the third counter 40, and outputs a control pulse CP3 at the timing of the next CP2 pulse when they match. The control pulse CP3 is supplied to the third counter 40 as an initialization pulse and to the first counter 34 as a stop pulse.

  The first, second, and third counters 34, 37, and 40 continue to stop operating until an HD pulse is input, start operating after the HD pulse is input, and operate until a CP3 pulse is output from the third comparator 41 Continue. When the CP3 pulse is output from the third comparator 41, the first, second, and third counters 34, 37, and 40 are reset to initial values, and the operation is stopped until the HD pulse is input again. Note that the initial values of the first, second, and third counters 34, 37, and 40 in the present embodiment are each "1".

  The drive mode control unit 31 supplies addresses so as to switch the control values read from the first, second, and third ROMs 33, 36, and 39 depending on whether the normal transfer mode or the vertical high-speed transfer mode is selected. . Here, address 1 represents the vertical high-speed transfer mode, and address 2 represents the normal transfer mode.

  The time-series data ROM 32 is a memory for storing time-series data representing a repetition pattern of the logic level of the output pulse. The time-series data ROM 32 receives the count value CNT2 of the second counter 37 as a read address, and converts it into time-series data. The output pulse based on is supplied as a pulse of V1-4.

  FIG. 9 shows timing generation information stored in the first ROM 33, the second ROM 36, the third ROM 39, and the time series data ROM 32 of FIG. 8, and V1 to V4 of the normal transfer unit of the vertical transfer shown in FIGS. This corresponds to data for generating pulse timing. Regarding the pulse timings of V1 to V4 in the driving mode 1 of FIG. 5, the logical change unit is 12T, so 12 (decimal number) is stored as the timing generation information of the first ROM 33 shown in FIG. Since the number of steps for one stage of vertical transfer is 8, 8 (decimal number) is stored as the timing generation information of the second ROM 36 shown in FIG. 9B. Since the vertical transfer is one stage, 1 (decimal number) is stored as the timing generation information of the third ROM 39 shown in FIG. The vertical transfer waveform patterns of the time series data ROM 32 of FIG. 9D are stored as the vertical transfer waveform patterns of V1 to V4.

  Next, for the pulse timings of V1 to V4 in the driving mode 2 of FIG. 6, since the logical change unit is 10T, 10 (decimal number) is stored as the timing generation information of the first ROM 33 shown in FIG. 9A. ing. Since the number of steps for one stage of vertical transfer is 8, 8 (decimal number) is stored as the timing generation information of the second ROM 36 shown in FIG. 9B. Since vertical transfer has two stages, 2 (decimal number) is stored as timing generation information of the third ROM 39 shown in FIG. 9C. The vertical transfer waveform patterns of the time series data ROM 32 of FIG. 9D are stored as the vertical transfer waveform patterns of V1 to V4. The above is the description of the pulse generation operation based on the timing generation information.

  Next, FIG. 10 shows a specific circuit configuration of the timing generator according to this embodiment. In FIG. 10, the first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, and the pulse output unit 15 correspond to those elements shown in FIG. .

  In the pulse generator 14 of FIG. 10, the first counter 34, the first comparator 35, the second counter 37, the second comparator 38, the third counter 40, and the third comparator 41 correspond to those shown in FIG. The functions and operations are the same as in FIG. On the other hand, in the pulse generator 14 of FIG. 10, the first ROM 33, the second ROM 36, and the third ROM 39 of FIG. 8 are deleted. Data corresponding to the data supplied from these ROMs is supplied from the first register 11 to the first comparator 35, the second comparator 38, and the third comparator 41, respectively. 8 is changed to a time series data RAM 32A that also has a function of writing a vertical transfer waveform pattern from the first register 11.

  The drive mode control unit 31A controls the operation of providing timing generation information corresponding to the drive mode from the first register 11 to the first comparator 35, the second comparator 38, the third comparator 41, and the time-series data RAM 32A. To do.

  Hereinafter, the operation of the timing generator is performed in the case of timing generation based on the timing generation information stored in the first storage circuit 10 and the timing generation based on the timing generation information input from the first external input unit 12. Each case will be described.

  First, the case of timing generation based on the timing generation information stored in the first memory circuit 10 will be described with reference to the timing generation information of the first memory circuit 10 shown in FIG. 11 generates the pulse timings of V1 to V4 of the normal transfer unit in the drive mode 1 shown in FIG. 5 and the pulse timings of V1 to V4 of the normal transfer unit in the drive mode 2 shown in FIG. The timing generation information is for the numerical values and data to be the same as those shown in FIG. That is, for the pulse timings of V1 to V4 of the normal transfer unit in the drive mode 1, 12 (decimal number) is stored as a logical change unit, 8 (decimal number) is stored as the number of steps for one stage of vertical transfer, and vertical 1 (decimal number) is stored as the number of transfer stages. In addition, V1-V4 vertical transfer waveform patterns are stored. Similarly, for the pulse timings of V1 to V4 in the driving mode 2, 10 (decimal number) is stored as the logical change unit, 8 (decimal number) is stored as the number of steps for one vertical transfer, and 2 as the number of vertical transfer stages. (Decimal number) is stored. In addition, V1-V4 vertical transfer waveform patterns are stored.

  When the selector 13 selects the first memory circuit 10, the timing generation information of the first memory circuit 10 is written into the first register 11 as it is. That is, the timing generation information written in the first register 11 is the same as that shown in FIG. 11, and will be described with reference to FIG.

  Of the timing generation information written in the first register 11, data in logical change units is sent to the first comparator 35, data for the number of steps for one vertical transfer is sent to the second comparator 38, and data for the number of vertical transfer stages is The vertical transfer waveform patterns V1 to V4 are input to the third comparator 41, respectively, to the time series data RAM 32A. Note that the timing generation information of the driving mode 1 or the driving mode 2 is selectively input by the control from the driving mode control unit 31A.

  With these timing generation information, the pulse timings V1 to V4 of the normal transfer unit in the driving mode 1 in FIG. 5 and the pulse timings V1 to V4 of the normal transfer unit in the driving mode 2 in FIG. 6 can be generated. The operation of the pulse generator 14 is the same as that in FIG.

  Next, the case of timing generation based on the timing generation information input from the first external input unit 12 will be described. In this case, the first external input unit 12 is selected by the selector 13, and desired timing generation information can be arbitrarily written to the first register 11.

  FIG. 12 shows the timing when the logical change unit in the V1 to V4 pulses in drive mode 1 is rewritten from 12 (decimal number) to 5 (decimal number) in the timing generation information of the first register 11 shown in FIG. Indicates generation information.

  FIG. 13 shows pulse timings V1 to V4 of the normal transfer unit in the driving mode 1 obtained from the timing generation information shown in FIG.

  According to this timing generation information, the pulse timing of V1 to V4 of the normal transfer unit in the driving mode 1 is 5 (decimal number) in the logical change unit, for example, the change from the H level to the L level of the V3 pulse is 5T. Thereafter, the output logic of the pulses V1 to V4 changes every 5T.

  As described above, according to the present embodiment, the pulse timing based on the timing generation information of the first memory circuit 10 can be easily generated, and the timing generation information is rewritten from the first external input unit 12. Therefore, it is possible to cope with a change in the specification of pulse timing even after the LSI is implemented.

  Note that the data formats of the first memory circuit 10 and the first register 11 are not particularly limited.

(Embodiment 2)
FIG. 14 shows the configuration of the timing generator in the second embodiment. The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, and the pulse output unit 15 are the same as those in the timing generation device shown in FIG. The configuration is the same. In the present embodiment, a second external input unit 16 that controls the selector 13 is provided. Write data to the first register 11 is selected from the first memory circuit 10 and the first input unit 12 according to the logic of the second external input unit 16.

  According to the present embodiment, the pulse timing based on the timing generation information of the first memory circuit 10 can be easily generated, and the first data is input according to the logic of the data input from the second external input unit 16. The timing generation information can be easily rewritten by inputting data from the external input unit 12. Therefore, it is possible to easily cope with a change in the specification of the pulse timing even after the LSI is formed.

(Embodiment 3)
FIG. 15 shows the configuration of the timing generator in the third embodiment. The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, and the pulse output unit 15 are the same as those in the timing generation device shown in FIG. The configuration is the same. In the present embodiment, a selector control unit 17 that controls the selector 13 is provided. Data to be written to the first register 11 is selected from the first storage circuit 10 and the first input unit 12 by the data of the first external input unit 12 input to the selector control unit 17. The data to be written to the first register 11 is timing generation information. For example, the MSB is divided into MSB and lower data, and the MSB is used as the control logic of the selector 13, and the lower data is used as timing generation information. it can.

  According to the present embodiment, the pulse timing based on the timing generation information of the first memory circuit 10 can be easily generated, and the first external input unit 12 is based on the data of the first external input unit 12. Since the timing generation information can be easily rewritten by inputting the data from the above, it is possible to easily cope with the change in the specification of the pulse timing even after the LSI is implemented.

  In addition, the second external input unit 16 that controls the selector 13 is not required for the timing generator according to the second embodiment, and the number of terminals can be reduced.

(Embodiment 4)
FIG. 16 shows the configuration of the timing generator in the fourth embodiment. The first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, and the selector control unit 17 are the same as the configuration of the timing generation device according to the third embodiment shown in FIG.

  In the present embodiment, the first storage circuit 10A for storing timing generation information has a data format different from that of the first storage circuit 10 in FIG. The first register 11A for storing timing generation information also has a data format different from that of the first register 11 in FIG.

  The first storage circuit 10A stores timing generation information corresponding to N (N is a natural number) drive modes, and a data area COM10Aa in which data COM, which is data common to the N drive modes, is stored. The data area (1 to N) 10Ab stores different data (1 to N) for each of the N modes. The first register 11A includes a register COM for data COM and a register A that holds any one of data (1 to N).

  When the selector 13 selects the first memory circuit 10A, the timing generation information of the data area COM10Aa of the first memory circuit 10A is written to the register COM of the first register 11A, and the data area (1 to N) 10Ab In the timing generation information, any one of the data (1 to N) is written in the register A of the first register 11A according to the driving mode.

  In this embodiment, there are two ways of generating the pulse timings V1 to V4 of the normal transfer unit in the drive mode 1 of FIG. 5 and the pulse timings V1 to V4 of the normal transfer unit of the drive mode 2 of FIG. The case will be described. FIG. 17 shows timing generation information of the first memory circuit 10A. Further, the timing generation information of the driving mode 1 and the timing generation information of the driving mode 2 in the first register 11A are shown in FIGS. 18 and 19, respectively.

  In the first memory circuit 10A shown in FIG. 17, a vertical transfer waveform pattern, which is common timing generation information for the two drive modes, is stored as data COM in the data area COM10Aa. The timing generation information is different between the driving mode 1 and the driving mode 2, and the logical change unit and the number of vertical transfer stages are the same as those in the driving mode 1 and the driving mode 2, but the number of steps for one vertical transfer is the same. Data (1-N) (N = 2) is stored in the data area (1-N) 10Ab.

  In contrast to the timing generation information of the first memory circuit 10A, the timing generation information of the first register 11A in the driving mode 1 is as shown in FIG. In the register area COM, a vertical transfer waveform pattern which is timing generation information common to the driving mode 1 and the driving mode 2 is written. A register A (1) for storing a logical change unit, a register A (3) for storing the number of vertical transfer stages, and a register A (2) for storing the number of steps for one vertical transfer stage are one drive of timing generation information. The registers for the modes are provided, and the timing generation information of the driving mode 1 of the first memory circuit 10A is written in each.

  FIG. 19 shows timing generation information of the first register 11 </ b> A in the driving mode 2. When the driving mode 1 is changed to the driving mode 2, the logical change unit of the register A (1), the number of vertical transfer stages of the register A (3), and the number of steps of one vertical transfer stage of the register A (2) The timing generation information is updated. At this time, the timing generation information of the register COM is not updated.

  As described above, according to the present embodiment, the pulse timing based on the timing generation information of the first memory circuit 10A can be easily generated, and the timing generation information is rewritten from the first external input unit 12. Is possible. Further, for the first register 11A, the data (1 to N) of the data area (1 to N) is different from the data area (1 to N) which is a different data area for each of the N modes as the timing generation information of the first storage circuit 10A. By using the register A that holds any one of them, the number of registers can be reduced, which is advantageous in terms of chip size and cost.

  In the present invention, the control mode of the selector 13 is not particularly limited.

  In this embodiment, the register A constituting the first register 11A holds any one of the data (1 to N), but holds a plurality of data. It doesn't matter.

(Embodiment 5)
FIG. 20 shows the configuration of the timing generator in the fifth embodiment. The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, and the second external input unit 16 are implemented as shown in FIG. It is the same as that of the structure of the timing generator in the form 2. In the present embodiment, a second register 18 is provided and stores setting data for functions controlled by the user such as an electronic shutter function of a video camera or the like. In contrast, the first register 11 mainly stores circuit data as a timing generator. The pulse generator 14 generates timing pulses based on data supplied from the first register 11 and the second register 18.

  The second register 18 is connected to the first external input unit 12, and function setting information is written from the outside. That is, the first external input unit 12 is connected to both the selector 13 and the second register 18. The addresses of the first register 11 and the second register 18 are independent of each other. For this reason, when the selector 13 selects the first external input unit 12 and data input from the first external input unit 12 is input to both the first register 11 and the second register 18. In addition, it is possible to write to any one of the first register 11 and the second register 18 by address designation.

  As described above, according to the present embodiment, data is input to the first register 11 and the second register 18 by providing the addresses of the first register 11 and the second register 18 independently of each other. Therefore, it is possible to share an external input unit for the purpose, and the number of terminals can be reduced. At the same time, the number of external control signals from a microcomputer or the like connected to the external input unit can be reduced.

(Embodiment 6)
FIG. 21 shows the configuration of the timing generator in the sixth embodiment. The apparatus of FIG. 21 has a configuration in the case where the idea of the present embodiment is applied to the timing generator of the fifth embodiment shown in FIG.

  The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, the second external input unit 16, and the second register 18 are shown in FIG. 20 is the same as the configuration of the timing generator in the fifth embodiment shown in FIG. In the present embodiment, a pulse output control unit 19 is provided. The output pulse of the pulse generation unit 14 is input to the pulse output unit 15 via the pulse output control unit 19.

  The pulse output control unit 19 can output any one of the output logic equivalent to the output logic of the pulse generation unit 14 or an H level, L level, or high impedance state. As one embodiment, during the data write period to the first register 11, the pulse output control unit 19 outputs a desired logic to the pulse output unit 15 in the H, L, or high impedance state, After the data write to the register 11 of 1 is completed, the pulse output control unit 19 outputs a logic equivalent to the output logic of the pulse generation unit 14 to the pulse output unit 15.

  According to the present embodiment, the output logic of the pulse generator 14 is indefinite until the timing generation information is written in the first register 11, but the pulse output controller 19 controls the H level, L level, and high impedance. It is possible to fix the desired output of the state. As a result, the timing generation information is written in the first register 11 and the cause of the malfunction to the digital signal processing unit 3 connected to the pulse output unit 15 during the period until the output logic of the pulse generation unit 14 is determined. It becomes possible to suppress the input of the indefinite pulse. Thereby, for example, the reliability as a camera system is improved.

(Embodiment 7)
FIG. 22 shows the configuration of the timing generator in the seventh embodiment. The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, the second external input unit 16, and the second register 18 are shown in FIG. 20 is the same as the configuration of the timing generator in the fifth embodiment shown in FIG. In the present embodiment, an input control unit 20 and a third external input unit 21 for inputting data for controlling the input control unit 20 are provided.

  The input control unit 20 switches the data input from the first external input unit 12 according to the data of the third external input unit 21 and outputs the data to either the selector 13 or the second register 18. Data input from the first external input unit 12 includes timing generation information for writing to the first register 11 and function setting information controlled by the user such as an electronic shutter function for writing to the second register 18. Including.

  When writing the timing generation information to the first register 11, the input control unit 20 uses the H or L level data input from the third external input unit 21 to input the data input from the first external input unit 12. Is output to the selector 13. The selector 13 uses the data input from the first external input unit 12 via the input control unit 20 as the timing generation information based on the H or L level data input from the second external input unit 16. 1 to the register 11. Next, when the function setting information is written to the second register 18, the input control unit 20 is input from the first external input unit 12 by H or L level data input from the third external input unit 21. Data is output to the second register 18 as function setting information.

  According to the present embodiment, by controlling the input control unit 20 and the third external input unit 21, a common external input unit for inputting data to the first register 11 and the second register 18 is used. It is possible to reduce the number of terminals when inputting timing generation information and function setting information. At the same time, the number of external control signals such as a microcomputer connected to the external input unit can be reduced.

  By the way, the purpose of the timing generator in the fifth embodiment is the same as that of the present embodiment, but in the fifth embodiment, the data input from the first external input unit 12 is the first by the address designation. Writing to the register 11 and the second register 18 is controlled. On the other hand, in this embodiment, writing to the first register 11 and the second register 18 is controlled by the input control unit 20 and the third external input unit 21 instead of the address.

  In the present embodiment, a third external input unit 21 is further required with respect to the timing generator of the fifth embodiment. However, in the timing generator of the fifth embodiment, a malfunction occurs when an address is not correctly input due to noise or the like during data input from the first external input unit 12. In particular, when function setting information is written to the second register 18, there is a possibility that normal operation will not be restored until the camera is turned off once, for example, when the function setting information is erroneously written to the first register 11 that stores timing generation information. Is expensive.

  In the present embodiment, by controlling the input control unit 20 and the third external input unit 21, it is possible to reduce writing errors to the first register 11 and the second register 18 as much as possible. Therefore, the reliability of data input of timing generation information and function setting information is improved as compared with the fifth embodiment.

  In addition, the number of terminals can be reduced by using a common data input unit for timing generation information and function setting information.

  Furthermore, since the timing generator of the fifth embodiment distinguishes the first register 11 and the second register 18 by address, the bit length becomes long, and the memory capacity and communication time increase. According to the present embodiment, the first register 11 and the second register 18 can be set without increasing the memory capacity and communication time.

(Embodiment 8)
FIG. 23 shows the configuration of the timing generator in the eighth embodiment. First memory circuit 10, first register 11, first external input unit 12, selector 13, pulse generation unit 14, pulse output unit 15, second external input unit 16, second register 18, input control Unit 20 and third external input unit 21 have the same configuration as the timing generator in the seventh embodiment shown in FIG. In the present embodiment, the H (or L) level data of the third external input unit 21 is transmitted not only to the input control unit 20 shown in the seventh embodiment, but also to the pulse generation unit 14 and the second register 18. Are also supplied.

  When L (or H) level data is input to the third external input unit 21, the input control unit 20 receives data input from the first external input unit 12 according to the L (or H) level. Is output to the selector 13. Then, the selector 13 converts the data input from the first external input unit 12 via the input control unit 20 into the timing generation information using the H (or L) level data input from the second external input unit 16. To the first register 11.

  In addition, during a period in which L (or H) level data is input to the third external input unit 21, the pulse generation unit 14 and the second register 18 are initialized.

  When H (or L) level data is input to the third external input unit 21, the input control unit 20 uses the data input from the first external input unit 12 as function setting information for the second Output to the register 18.

  In addition, during a period in which H (or L) level data is input to the third external input unit 21, the pulse generation unit 14 generates a pulse based on the timing generation information stored in the first register 11. The operation state becomes. The second register 18 is in a writable state.

  According to the present embodiment, as in the seventh embodiment, the first register 11 and the second register 18 can be set without increasing the memory capacity and communication time. Further, since the pulse generation unit 14 is initialized during the period when data is input to the first register 11 as the timing generation information, the timing generation information is written into the first register 11 and the output of the pulse generation unit 14 is output. During the period until the logic is determined, similarly to the sixth embodiment, it is possible to suppress the input of an indefinite pulse that causes a malfunction to the digital signal processing unit 3 or the like connected to the pulse output unit 15.

  Furthermore, the data input to the third external input unit 21 can be used as a reset signal as a timing generator, that is, can also be shared as a reset signal input unit.

  In each of the above embodiments, the first storage circuit 10 and the first register 11 are connected during the writing period from the first storage circuit 10 or the first external input 12 to the first register 11. It is possible to configure so that the elements to be removed are initialized, and thereby the same effect as in the present embodiment can be obtained.

(Embodiment 9)
FIG. 24 shows the configuration of the timing generator in the ninth embodiment. First memory circuit 10, first register 11, first external input unit 12, selector 13, pulse generation unit 14, pulse output unit 15, second external input unit 16, second register 18, input control The unit 20 and the third external input unit 21 have the same configuration as the timing generator in the eighth embodiment shown in FIG.

  In the present embodiment, an edge detection circuit 22 that detects an edge of a pulse input to the third external input unit 21 and a counting circuit 23 that performs counting using the output of the edge detection circuit 22 as a trigger are further provided. . The output of the counting circuit 23 is configured to perform the same operation as that of the third external input unit 21 in the eighth embodiment.

  That is, the edge of the pulse input to the third external input unit 21 is detected by the edge detection circuit 22, and the output of the edge detection circuit 22 is used as a trigger, so that the counting circuit 23 receives at least data to the first register 11. It changes to the L (or H) level and is held until the input is completed. As a result, the pulse generator 14 and the second register 18 are initialized.

  If there is no problem in the system, the block to be initialized may be arbitrarily selected. Further, as the counting period of the counting circuit 23, an arbitrary counting period longer than the writing period to the first register 11 may be set.

  Next, the counting circuit 23 changes to the L (or H) level after the data input to the first register 11 is completed, and the pulse generator 14 is based on the timing generation information stored in the first register 11. The operation state for generating a new pulse is obtained. The second register 18 is in a writable state.

  As described above, according to the present embodiment, as in the eighth embodiment, the pulse generator 14 is initialized during a period in which data is input to the first register 11 as timing generation information. For this reason, the timing generation information is written in the first register 11 and the output logic of the pulse generator 14 is determined. This causes indefinite operation that causes malfunctions in the digital signal processor connected to the pulse output unit 15. It is possible to suppress pulse input.

  The period for initializing the pulse generation unit 14 and the second register 18 is a period sufficient to suppress the input of indefinite pulses that cause malfunctions to the digital signal processing unit connected to the pulse output unit 15. If so, it is not necessary to be a period until the data input to the first register 11 is completed. For example, the initialization may be canceled a predetermined period before the completion of data input.

  Furthermore, according to the configuration of the present embodiment, the timing generator automatically transfers to the first register 11 by detecting the pulse edge without controlling the L (or H) period input to the third external input unit 21. It is possible to determine the completion of data input. As a result, it is possible to generate a pulse based on the timing generation information without outputting an indefinite pulse, and thus it is possible to reduce the load on the control side.

(Embodiment 10)
FIG. 25 shows the configuration of the timing generator in the tenth embodiment. In the present embodiment, the first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, the first external input unit 16, the first The second register 18, the input control unit 20, and the third external input unit 21 have the same configurations as those in the eighth embodiment shown in FIG.

  This embodiment is characterized in how to use the timing generator. That is, a first data generation unit 24, a second data generation unit 25, and a third data generation unit 26 are provided outside the timing generation device, and supply data to the timing generation device. The first data generation unit 24 generates timing generation data to be written to the first register 11. The second data generator 25 generates function setting data to be written to the second register 18. The third data generation unit 26 controls the output states of the first data generation unit 24 and the second data generation unit 25.

  The first data generator 24 outputs data to be input to the first register 11 or enters a high impedance state in response to data input from the third data generator 26. The second data generation unit 25 outputs data to be input to the second register 18 by the data input of the third data generation unit 26 or enters a high impedance state.

  The output of the first data generation unit 24 and the output of the second data generation unit 25 are supplied to the first external input unit 12. When the first data generation unit 24 outputs data to be input to the first register 11, the second data generation unit 25 is in a high impedance state. When the second data generation unit 25 outputs data to be input to the second register 18, the first data generation unit 24 is in a high impedance state.

  As described above, according to the present embodiment, the first data generating unit 24 that generates data for the first register 11 and the second data generating unit 25 that generates data for the second register 18 are used. Even if these are separate output units, the data input unit for rewriting the data of the first register 11 and the second register 18 from the outside can be shared as the first external input unit 12.

  In the case where a register is further provided in addition to the first register 11 and the second register 18 and three or more data generation units are provided, the data input unit is also commonly used as the first external input unit 12. Is possible.

(Embodiment 11)
FIG. 26 shows the configuration of the timing generator in the eleventh embodiment. The first memory circuit 10, the first register 11, the first external input unit 12, the selector 13, the pulse generation unit 14, the pulse output unit 15, the first external input unit 16, and the second register 18 are shown in FIG. 20 is the same as the configuration of the timing generator in the fifth embodiment shown in FIG.

  In the present embodiment, a second memory circuit 27 and a data comparator 28 for comparing data in the second register 18 and the second memory circuit 27 are further provided. In the second register 18, there may be a test setting or a setting that makes the operation indefinite due to the circuit configuration as a function setting. In order to prevent this from being supplied to the pulse generator 14, the second storage circuit 27 stores logical information that should not be set in the second register 18 as a function setting. Data comparison with the register 18 is executed by the data comparator 28.

  When logical information that should not be set in the second register 18 is written by mistake, the data comparator 28 outputs a matching result as a result of the data comparison with the second memory circuit 27, and the output is the first. 2 to invert the corresponding logic. In this way, it is avoided that defective data is set as the address data of the second register 18.

  In the above configuration, the logical information that should not be set in the second register 18 as the function setting is stored in the second storage circuit 27. However, the logical information may be stored in the first storage circuit 10. . Further, the information stored in the second memory circuit 27 can be rewritten from the outside.

  In each of the above embodiments, the timing pulse output from the pulse generator 14 is not limited to a single sequence, and can be output as a plurality of sequences. The same applies to input / output of signals in the timing generator.

  Further, in each of the above embodiments, an apparatus having an independent configuration as a timing generation apparatus has been described. However, a configuration having an equivalent function as a solid-state imaging device or a camera system may be possible.

  The timing generator of the present invention can easily generate pulse timing and can rewrite timing generation information from the outside. In addition, there is an advantage that it is not necessary to re-create the LSI again, which is useful for driving a solid-state imaging device and signal processing.

1 is a block diagram showing a schematic configuration example of a CCD camera which is a solid-state imaging device in an embodiment of the present invention. FIG. 1 is a conceptual diagram illustrating an example of a gate configuration of a solid-state imaging device (CCD) in FIG. FIG. 1 is a timing chart showing a waveform example of a main signal drive mode 1 in FIG. FIG. 1 is a timing chart illustrating an example of a waveform of a main signal drive mode 2 in FIG. Detailed timing chart showing a waveform example of the normal transfer unit in FIG. Detailed timing chart showing a waveform example of the normal transfer unit in FIG. FIG. 3 is a block diagram illustrating a timing generator in the first embodiment. Block diagram for explaining the operation of the timing generator Table showing timing generation information stored in each ROM in FIG. Block diagram specifically illustrating the configuration of the pulse generator in FIG. Table showing data of timing generation information stored in the first storage circuit 10 of FIG. A table showing an example of data when the data of FIG. 11 written in the first register in FIG. 10 is rewritten from the outside. Detailed timing chart showing waveform example of normal transfer unit in drive mode 1 based on timing generation information of FIG. FIG. 3 is a block diagram illustrating a timing generator in the second embodiment. Block diagram showing a timing generator according to Embodiment 3 Block diagram showing a timing generator according to Embodiment 4 A table showing timing generation information stored in the first memory circuit 10A of FIG. A table showing the timing generation information of the driving mode 1 stored in the first register 11A of FIG. A table showing the timing generation information of the driving mode 2 stored in the first register 11A of FIG. FIG. 7 is a block diagram showing a timing generator in the fifth embodiment. Block diagram showing a timing generator according to Embodiment 6 FIG. 9 is a block diagram illustrating a timing generator in a seventh embodiment. Block diagram showing a timing generator according to Embodiment 8 FIG. 9 is a block diagram illustrating a timing generator in a ninth embodiment. FIG. 10 is a block diagram illustrating a timing generator in the tenth embodiment. FIG. 12 is a block diagram showing a timing generator in an eleventh embodiment.

Explanation of symbols

1 Solid-state image sensor (CCD)
2 Preprocessing (CDS / ADC) LSI
3 Digital signal processing (DSP) LSI
4 Timing generator (TG) LSI
5 Clock driver (DR) LSI
6 Photodiode (PD)
7 vertical transfer unit 8 horizontal transfer unit 9 charge detection unit 10 storage circuit 11 first register 12 first external input unit 13 selector 14 pulse generation unit 15 pulse output unit 16 second external input unit 18 second register 19 Pulse output control unit 20 Input control unit 21 Third external input unit 22 Edge detection circuit 23 Count circuit 24 First data generation unit 25 Second data generation unit 26 Third data generation unit 27 Second storage circuit 28 Data comparator 30 Counting unit 31, 31A Drive mode control unit 32 Time series data ROM
32A Time-series data RAM
33 1st ROM
34 First counter 35 First comparator 36 Second ROM
37 Second counter 38 Second comparator 39 Third ROM
40 Third counter 41 Third comparator

Claims (4)

A first storage circuit storing timing generation information;
A first register holding the timing generation information of the first memory circuit;
A first external input unit for accessing the first register and rewriting data;
A selector for selecting either the first memory circuit or the first external input unit for writing data to the first register;
A second external input section for supplying a selection signal of the selector;
A pulse generator for generating a pulse timing corresponding to the timing generation information held in the first register and outputting a single pulse or a plurality of pulses;
A second register holding control function information as a timing generator;
An input control unit that selects to output input data from the first external input unit to either the selector or the second register;
The selector selects data to be input to the first register from outputs of the first storage circuit and the input control unit according to data of the second external input unit,
A timing generator for initializing the pulse generator during a period in which data of the first external input unit is written to the first register. A third external input unit for supplying a selection signal of the input control unit;
The counter further includes a counting circuit that inverts and holds the output from the initial state triggered by the edge of the pulse input from the third external input unit, and returns to the initial state after counting for a predetermined period,
2. The timing generation according to claim 1 , wherein the input control unit outputs the data input from the first external input unit to either the selector or the second register in accordance with an output of the counting circuit. apparatus. A solid-state imaging apparatus having a timing generator according to claim 1 or 2. Camera system comprising a timing generator according to claim 1 or 2.

Images