JP4223702B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus such as a digital still camera.
[0002]
[Prior art]
In recent years, digital still cameras have functions such as voice recording and music playback, communication with a personal computer (mainly USB communication), and support for video output in the PAL format as well as the NTSC format. It is installed as a basic function. For these functions, an IC that realizes these functions basically needs to be fitted with an oscillator or an oscillator.
[0003]
In the past, the frequency used by video encoders was often divided into the basic clock of the timing generator that drives the CCD as a solid-state image sensor, but this has increased the number of pixels and increased autofocus speed. Therefore, it has come to have an oscillator or an oscillator for CCD driving and signal processing independent of the DSP (Digital Signal Processor) side.
[0004]
Many video encoder units have a PLL circuit in a DSP, and are capable of realizing NTSC and PAL fundamental waves with a single oscillator. In many cases, the clock from the video encoder unit is multiplied to be the source signal of the CPU.
[0005]
[Problems to be solved by the invention]
The digital still camera often requires three to four oscillators or oscillators to realize the above functions. This increases the cost, increases the mounting area, and can be fatal in the current situation of downsizing.
[0006]
The present invention aims to provide a compact, Ki out to achieve reduction and power consumption costs, the imaging apparatus can determine the update rate monitoring frame in making the user.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is directed to a solid-state imaging device for imaging a subject, a timing generator for driving the solid-state imaging device, a sample hold of a signal from the solid-state imaging device, and A means for performing A / D conversion, a DSP for processing and outputting a signal from the means, a memory for temporarily storing data processed by the DSP, and a clock having a predetermined frequency required for the DSP The clock generator has an oscillation source of the timing generator, outputs a clock having a frequency of the oscillation source to the timing generator, and outputs a clock frequency to the timing generator. a structure capable of changing a deflection during monitoring is set by the user The beam update speed is intended to change the frequency of the clock to the timing generator from the clock generator.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of the present invention. This embodiment is a form of a digital still camera as an imaging apparatus. Light received by the CCD 1 as a solid-state imaging device from the subject via the imaging lens is photoelectrically converted by the CCD 1 and sent to the sampling (CDS) / analog / digital (A / D) conversion unit 2. The CDS / A / D converter 2 samples the output signal of the CCD 1 while removing noise components by correlated double sampling, sequentially A / D converts it into 10-bit data, and sends it to the DSP 3.
[0013]
The DSP 3 performs processing such as interpolation, aperture enhancement, and white balance processing of the signal sent from the CDS / A / D conversion unit 2, and further converts it into a luminance signal Y and color difference signals Cb and Cr to form a frame as a memory. Temporarily store in buffer 4. This operation is repeated during monitoring, and the data stored in the frame buffer 4 is sequentially read out to the video encoder 5 in the DSP 3 and converted into a video signal by the video encoder 5 and then displayed on an external television receiver or the like. It is output to the device 6.
[0014]
The CCD 1 is driven by a horizontal drive pulse output from the timing generator (TG) 7 to the CCD 1 and a vertical drive pulse output from the vertical driver (VDr) 8 to the CCD 1 and an electronic shutter pulse. The CPU 9 as the control means controls the timing generator 7, the CDS / A / D converter 2 and the clock generator 10 by the electronic shutter pulse. The timing generator 7 outputs the vertical drive pulse of the CCD 1 to the VDr 8 and the CDS / A / D. A clock is output to the conversion unit 2.
[0015]
The source signal of the timing generator 7 is a CCD driving pulse output from the clock generator 10, and this CCD driving pulse is frequency-divided by a frequency divider 7 a in the timing generator 7 and sent to the DSP 3. On the other hand, the DSP 3 has a built-in counter that counts the CCD driving pulses from the timing generator 7, and when the count number of the counter reaches a predetermined count number, a horizontal reset signal, A vertical reset signal is output.
[0016]
Here, the CCD driving pulse is output from the clock generator 10, and this is a circuit that divides the clock of the oscillation frequency of the CCD driving crystal oscillator 11 attached to the clock generator 10 inside the clock generator 10. This is because it can be built in relatively easily. Thus, by dividing the CCD driving pulse, it becomes possible to reduce the power consumption of monitoring.
[0017]
In this embodiment, the clock generator 10 includes a CCD driving pulse 1 based on a source signal (clock generated by a crystal oscillation circuit using the CCD driving crystal oscillator 11) and a clock obtained by dividing the source signal by two by a frequency divider. 2 is selectively output. Of course, a plurality of stages of frequency dividers that divide the clock generated by the crystal oscillation circuit using the CCD drive crystal oscillator 11 may be prepared. The slower the frame is (the lower the frequency is), the slower the monitoring frame update speed is. Therefore, a frequency divider that divides the clock by two is used in consideration of practicality.
[0018]
The remarkable effects of low power consumption obtained by actually dividing the CCD drive pulse are the low power consumption of the logic system inside the timing generator 7, the horizontal and vertical drive output buffers of the CCD 1. The power consumption is reduced, and if the CCD driving pulse is divided by two, the power consumption is halved, and is proportional to the frequency division ratio of the frequency divider that divides the CCD driving pulse. In addition, although not as effective as the above-described block (logic system, horizontal and vertical drive output buffers of CCD 1), the power consumption of the CDS / A / D converter 2 is also reduced.
[0019]
The above is the operation at the time of recording (monitoring). When the recorded image is reproduced, the clock generator 10 completely stops the oscillation of the crystal oscillator 11 for driving the CCD by the control signal from the CPU 9. As a result, the power consumption of the output buffer of the clock generator 10, the crystal oscillation circuit using the crystal oscillator 11 for driving the CCD, the frequency divider of the timing generator 7, and the image processing block of the DSP 3 can be reduced to zero. it can. The frequency selection of the CCD driving pulse of the clock generator 10, the output stop, and the oscillation stop of the crystal oscillation circuit using the CCD driving crystal oscillator 11 are performed by the control of the clock generator 10 by the CPU 9.
[0020]
On the other hand, the clock generator 10 generates a USB clock and an audio sampling clock based on a clock from a crystal oscillation circuit using the CCD drive crystal oscillator 11 by an internal PLL circuit and outputs the generated clock to the DSP 3. . Of course, the clock generator 10 can also generate a clock for the CPU and a clock for the video encoder (for DSP), but the CPU 9 is configured to control the output of the clock generator 10, and Because the encoder clock requires high accuracy and the clock generator 10 generates all the clocks, the number of pins increases and the number of control lines for controlling the output increases. A crystal oscillator 12 for CPU is attached, and a crystal oscillator 13 for DSP is attached to DSP 3.
[0021]
The DSP 3 exchanges image data and audio data with a personal computer via the USB driver 14. The CODEC 15 has an A / D conversion / D / A conversion function. Audio data recording / reproduction is performed between the CPU 9 and the CODEC 15, and when the data is reproduced by a personal computer, it is sent to the personal computer as audio data via the USB driver 14, or the personal computer using a medium such as a card. Will be moved to.
[0022]
The USB clock and the audio sampling clock generated by the PLL circuit in the clock generator 10 are characterized in that they may be used only in a limited case. Therefore, the PLL circuit that generates the USB clock and the audio sampling clock in the clock generator 10 is turned on / off by a control signal from the CPU 9. For this reason, depending on the version, it may be assumed that there is no USB function or no audio function. Even in such a case, by sharing a board from a full-spec camera to a low-cost camera, wasted space Can be minimized.
[0023]
As described above, in this embodiment, the clock generator 10 has the CCD driving crystal oscillator 11 as the oscillation source of the timing generator 7, and outputs the clock having the frequency of the CCD driving crystal oscillator 11 to the timing generator 7. In addition, since the clock frequency output to the timing generator 7 can be changed, the size and cost can be reduced, and the power consumption can be reduced by changing the driving frequency of the CCD 1. In addition, it can flexibly respond to camera version changes.
[0024]
In this embodiment, the CPU 9 keeps the clock (CCD driving pulse) from the clock generator 10 to the timing generator 7 at a low frequency in the monitoring state, and uses the first release signal to start the recording operation. The clock generator 10 is controlled so that the frequency of the clock (CCD driving pulse) from the generator 10 to the timing generator 7 becomes a high frequency.
[0025]
For this reason, in the normal use state, it is possible to reduce the power consumption in the monitoring operation, and at the time of recording where the speed is required, the drive frequency of the CCD 1 is increased by the first release signal to reduce the time required for autofocus. By making it as short as possible, the release time lag can be reduced without the user having to worry about setting the drive frequency of the CCD 1.
[0026]
In this embodiment, the CPU 9 preferentially sends a low-frequency clock (CCD driving pulse) from the clock generator 10 to the timing generator 7 when the subject is dark, based on the detection result of the detecting means for detecting the brightness of the subject. ) And the clock generator 10 is controlled so that a high-frequency clock (CCD driving pulse) is preferentially output from the clock generator 10 to the timing generator 7 when the subject is relatively bright.
[0027]
For this reason, even when the subject is dark, by increasing the accumulation time of the CCD 1, it is possible to obtain effective distance measurement information by the distance measuring device, and the subject is bright and sufficiently effective distance measurement even at a normal frame rate. When information is obtained by a distance measuring device, the drive frequency of the CCD 1 is automatically switched to a high frequency, so that the time lag during actual recording can be reduced and low power consumption can be achieved without the user's awareness. realizable.
[0028]
In the present embodiment, the user has an operation unit for arbitrarily setting the updating speed of the monitoring frame, and the CPU 9 controls the clock generator 10 by an input signal from the operation unit to control the timing generator from the clock generator 10. Change the frequency of the clock to 7 (CCD driving pulse). For this reason, the user can arbitrarily determine the update speed of the monitoring frame at the user's intention when the update speed of the monitoring frame is inevitably slow.
[0029]
In the present embodiment, the CPU 9 controls the clock generator 10 so that data is recorded in the memory 4 at a constant frame rate regardless of the setting value of the monitoring frame update speed during moving image recording. Then, the frequency of the clock (CCD driving pulse) from the clock generator 10 to the timing generator 7 is switched. For this reason, it becomes possible to provide a certain quality to a user.
The present invention is not limited to the above-described embodiment, and can be applied to, for example, a digital video camera.
[0030]
【The invention's effect】
As described above, according to the present invention , downsizing, cost reduction, and low power consumption can be achieved , and the monitoring frame update speed can be arbitrarily determined by the user.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
[Explanation of symbols]
1 CCD
2 CDS / A / D converter 3 DSP
4 Frame buffer 5 Video encoder 7 Timing generator 8 VDr
9 CPU
DESCRIPTION OF SYMBOLS 10 Clock generator 11 Crystal oscillator for CCD drive 12 Crystal oscillator for CPU 13 Crystal oscillator for DSP

Claims (1)

A solid-state imaging device for imaging a subject;
A timing generator for driving the solid-state imaging device;
Means for performing sample hold and A / D conversion of a signal from the solid-state imaging device;
A DSP that processes and outputs signals from this means;
A memory for temporarily storing data processed by the DSP;
A clock generator that generates a clock having a predetermined frequency required by the DSP;
The clock generator has an oscillation source of the timing generator, outputs a clock having a frequency of the oscillation source to the timing generator, and can change a frequency of the clock to be output to the timing generator,
An imaging apparatus, wherein a frequency of a clock from the clock generator to the timing generator is changed according to a frame update speed during monitoring set by a user .

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