JP4221474B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine in which a player plays a game using a gaming medium.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are played as prize balls. Is paid out to the person. Further, a variable display device capable of changing the display state is provided, and is configured to give a predetermined game value to a player when a display result on the variable display device becomes a predetermined specific display mode There is.

  That the display result in the variable display device that displays the special symbol is a combination of specific display modes determined in advance is usually referred to as “big hit”. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate.

  When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  The game progress in the gaming machine is controlled by game control means such as a microcomputer. The identification information displayed on the variable display device is controlled by display control means including a display control microcomputer different from the game control microcomputer of the game control means. Furthermore, in the gaming machine, sound generating means such as a speaker is provided, and various sound effects and sounds are emitted from the speaker as the game progresses in order to enhance the gaming effect. In addition, light emitters such as lamps and LEDs are provided on the game board and the frame side, and these light emitters are turned on and off as the game progresses in order to enhance the game effect. And in order to control the sound generating means and the light emitter, a sound control board equipped with a sound control means is provided separately from the game control means, or a light emitter control board equipped with the light emitter control means is a game control means. A separately provided configuration may be employed.

  When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the game control board on which the game control means is mounted, the progress of the game is controlled by the game control mounted on the game control board. Since it is controlled by the means, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board. On the other hand, the rental of game media is irrelevant to the progress of the game, and is generally controlled by the payout control means without going through the game control means.

  As described above, various control means are mounted on the gaming machine in addition to the game control means. Then, the game control means for controlling the progress of the game transmits each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the control means provided in the gaming machine may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

In the gaming machine as described above, it is desirable that the game shop clerk can easily perform initialization work of the gaming machine such as RAM clearing when the power supply to the gaming machine is started.

Accordingly, an object of the present invention is to provide a gaming machine that can easily execute an initialization process by starting power supply to the gaming machine while turning on a clear switch .

A gaming machine according to the present invention is a gaming machine in which a player can play a predetermined game, and has a game control variation data storage means for storing variation data generated when control is performed . A game control microcomputer for controlling the progress, a storage content holding means capable of holding the storage contents of the game control variation data storage means for a predetermined period even when power supply to the gaming machine is stopped, and a game medium A power supply monitoring means for detecting a voltage drop of a predetermined power supply voltage higher than the voltage supplied to the game medium detecting means for detecting the power supply, and outputting a detection signal when the occurrence of power interruption is detected, and depending on the operation And an initialization operation means for outputting an operation signal, and the game control microcomputer sets a backup flag in the game control variation data storage means in response to the input of the detection signal. Performs game control power supply stop processing including check data creation processing used to determine whether or not the stored contents of the game control variation data storage means are normal, and initializes operation when power supply is started It is determined whether an operation signal is input from the means, and if an operation signal is input from the initialization operation means, it is determined whether the backup flag is set in the game control variation data storage means. The stored contents of the game control variation data storage means are initialized without being executed, and when it is determined that no operation signal is input from the initialization operation means, a backup flag is set in the game control variation data storage means. If it is determined that the backup flag is not set in the game control variation data storage means, the check data is The memory contents of the game control variation data storage means are initialized without determining whether the memory contents of the game control variation data storage means are normal, and the backup flag is set in the game control variation data storage means. When it is determined that the stored content of the game control variation data storage means is normal based on the check data, the storage content of the game control variation data storage means is not normal. When the determination is made, the storage contents of the game control variation data storage means are initialized, and the game control variation data storage means is stored on the condition that the storage contents of the game control variation data storage means are determined normal. Based on the stored contents, the game control state return control is executed to restore the control state to the state when the game control power supply stop process was started. Determining whether or not the operation signal from the initialization operation means is input in a request detection determination period shorter than the game medium detection determination period in which the signal output from the game medium detection means is determined to be valid. Features.
Another aspect of the gaming machine according to the present invention is a gaming machine in which a player can play a predetermined game, and has payout control variation data storage means for storing variation data generated when the control is performed. The memory contents that can hold the memory contents of the payout control microcomputer for controlling the game media payout and the payout control variation data storage means for a predetermined period even when the power supply to the gaming machine is stopped A power supply monitor that detects a voltage drop of a predetermined power supply voltage higher than a voltage supplied to a holding means and a game medium detection means for detecting a game medium, and outputs a detection signal when the occurrence of a power supply interruption is detected. Means for outputting an operation signal according to the operation, and the payout control microcomputer stores the backup flag in accordance with the input of the detection signal. When the power supply is started after executing the process for setting out to the power supply stop for the payout control including the process of creating the check data used to determine whether the stored contents of the fluctuation data storage means for payout control are normal or not Whether the operation signal is input from the initialization operation means, and if the operation signal from the initialization operation means is input, is the backup flag set in the payout control variation data storage means? The storage flag of the payout control variable data storage means is initialized without executing the determination of whether or not, and when it is determined that the operation signal is not input from the initialization operation means, the backup flag is set to the payout control variable data. It is determined whether or not the storage unit is set, and when it is determined that the backup flag is not set in the payout control variation data storage unit, The storage contents of the payout control variable data storage means are initialized without determining whether the storage contents of the payout control fluctuation data storage means based on the check data are normal, and the backup flag is used for the payout control fluctuation data storage means. When it is determined that the storage content of the payout control variation data storage means is normal based on the check data, the storage content of the payout control variation data storage means is normal. If it is determined that the stored data in the payout control variation data storage means is initialized, the payout control variation data storage is determined on the condition that the storage content in the payout control variation data storage means is determined to be normal. The state for payout control that restores the control state to the state when the power supply stop for payout control was started based on the stored contents stored in the means A request detection determination period shorter than the game medium detection determination period in which the signal output from the game medium detection means is determined to be valid whether or not the operation signal from the initialization operation means is input by executing the return control. It is characterized by determining by.

According to the present invention, the request detection determination period shorter than the game medium detection determination period in which the signal output from the game medium detection means is determined to be valid, whether or not the operation signal from the initialization operation means is input. since it is configured so to determine in, by starting the power supply to the gaming machine while the initializing operation means to the oN state, there is an effect that it is possible to easily perform the initialization process.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board with the glass door frame removed. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be, for example, a slot machine. It can also be applied to image-type gaming machines.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided. Further, a start memory display 18 having four display units for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number, is provided at the bottom of the variable display device 9. In this example, with the upper limit being four, every time there is an effective start winning, the start memory display 18 increases the number of lit display sections one by one. Then, each time the variable display of the variable display device 9 is started, the lit display portion is reduced by one.

  When a game ball wins the gate 32, variable display of the display of the normal symbol display 10 by 7 segment LED is started. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having four display units for displaying the number of winning balls that have entered the gate 32 is provided. In this example, with the upper limit of four, every time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of display units that are lit one by one. Each time the opening control of the variable winning ball apparatus 15 is performed, the number of lit display units is reduced by one.

  The game board 6 is provided with a plurality of winning holes 24, 29, 30, 33, and winning of game balls to the winning holes 24, 29, 30, 33 is performed by winning port switches 24a, 29a, 30a, 33a, respectively. Detected. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7.

  In this example, a prize ball lamp 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on in the vicinity of the top frame lamp 28a when the supply ball is cut. A cut lamp 52 is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the hit ball enters the start winning opening 14 and is detected by the start opening switch 14a, the variable display device 9 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state.

  When the hit ball wins the gate 32, the display number as the normal symbol on the normal symbol display 10 is continuously changed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, a game control board (main board) 31 on which a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control microcomputer, and the like are mounted. Is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Further, various decoration LEDs provided on the game board 6, special symbol start memory display 18 and normal symbol start memory display 41, decoration lamp 25, top frame lamp 28a provided on the frame side, left frame lamp 28b. , A lamp control board 35 on which lamp control means for controlling lighting of the right frame lamp 28c, the winning ball lamp 51 and the off-ball lamp 52 is mounted, and a sound control board on which sound control means for controlling sound generation from the speaker 27 is mounted 70 is also provided. Further, a power supply board 910 and a launch control board 91 on which a power supply circuit for creating DC30V, DC21V, DC12V, and DC5V is mounted are provided.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  Furthermore, for clearing backup data stored in storage content holding means (for example, a backup RAM capable of holding the contents even when power supply is stopped) included in each board (main board 31 and payout control board 37). A switch board 190 on which a clear switch 921 as initialization operation means is mounted is provided. The switch board 190 is provided with a clear switch 921 and a connector 922 connected to another board such as the main board 31.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG. 4, reach the ball payout device covered with the prize ball case 40A through the curve rod 186. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  The ball break switch 187 is locked at a position where it can be detected that about 27 to 28 game balls are present in the payout ball passage leading to the ball payout device. That is, the ball break switch 187 has a maximum payout amount per unit of prize balls (15 in this embodiment) and a maximum payout amount per unit of ball lending (100 yen: 25 in this embodiment). It is installed in a position where it can be confirmed that it is secured.

  The game ball paid out from the ball payout device is guided to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45.

  A large number of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full, and finally game balls are paid out after the game balls reach the contact port 45. The game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. That is, it is detected by the full switch 48 that the storage amount in the surplus ball receiving tray 4 as the player side storage means exceeds the storage allowable amount. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the drive of the launching device also stops.

  As shown in FIG. 4, a ball removal passage 191 is formed on the side of the ball payout device from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is an exploded perspective view showing a configuration example of the ball dispensing device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, 142 as the prize ball case 40A. The upper portions of the cases 140 and 141 are provided with holes 170 and 171 communicating with the lower ball passage of the ball break switch 187, and the game balls flow into the ball dispensing device 97 through the holes 170 and 171.

  The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a drive source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted to the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

  The ball passage 293 is provided with a sorting member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when the winning ball is paid out, the game ball falls down so that the game ball flows down one flow path in the ball passage 293, and when the ball is lent, the game ball flows down the other flow path in the ball passage 293. To fall down. The payout motor 289 and the solenoid 310 are controlled by a payout control CPU mounted on the payout control board 37. The payout control CPU controls the payout motor 289 and the solenoid 310 in accordance with a command from the game control CPU mounted on the main board 31.

  A prize ball sensor (prize ball count switch) 301A for detecting a game ball paid out by the ball payout device is provided below the flow path selected at the time of paying out the winning ball, and below the flow path selected at the time of lending the ball. Is provided with a ball lending sensor (ball lending count switch) 301B for detecting a game ball paid out by the ball paying device. The detection signal of the winning ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on these detection signals.

  FIG. 6 is a block diagram illustrating an example of a circuit configuration in the main board 31. 6 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a symbol control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 24a, 29a, 30a, 33a, A switch circuit 58 for supplying signals from the tongue switch 48, the ball break switch 187, the prize ball count switch 301A and the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball apparatus 15, and a solenoid for opening and closing the opening and closing plate 20. 21 and a solenoid circuit 59 for driving a solenoid 21A for switching a route in the special winning opening in accordance with a command from the basic circuit 53 is mounted.

  Although not shown in FIG. 6, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 24a, 29a, 30a and 33a, the full switch 48, the ball running switch 187, the winning ball count switch 301A, etc. Also, what is called a sensor may be used. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (means for storing variation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  Further, a part or all of the RAM (may be a CPU built-in RAM) 55 is a backup RAM that is backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory display 18, the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board. In addition, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the ball-out lamp 52 provided on the frame side is performed. In addition, display control of the variable display device 9 for variably displaying the special symbol and the normal symbol display 10 for variably displaying the normal symbol is performed by display control means mounted on the symbol control board 80.

  FIG. 7 shows the circuit configuration in the symbol control board 80. The LCD (liquid crystal display device) 82, the normal symbol display 10, and the output port (ports 0 and 2) of the main board 31 are examples of realization of the variable display device 9. It is a block diagram shown with 570,572 and output buffer circuit 620,62A. Command data constituting an 8-bit display control command is output from the output port (output port 2) 572, and a 1-bit strobe signal (INT signal) is output from the output port 570. The INT signal is a capture signal for instructing capture of command data.

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  7 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105A and 105B can pass signals only in the direction from the main board 31 toward the symbol control board 80. Therefore, there is no room for signals to be transmitted from the symbol control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input ports. Even if the tampering is added to the circuit in the symbol control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added between the substrates due to the presence of the noise filter 107, the influence is eliminated. . A noise filter may also be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

  FIG. 8 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, various decoration LEDs provided on the game board 6, the special symbol start memory display 18 and the normal symbol start memory display 41, the decoration lamp 25, the top frame lamp 28a provided on the frame side, A lamp control command indicating whether the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51, and the ball-out lamp 52 are turned on / off is output from the main board 31 to the lamp control board 35.

  As shown in FIG. 8, the lamp control command related to the lamp control is output from the output ports (output ports 0 and 3) 570 and 573 of the I / O port unit 57 in the basic circuit 53. The output port (output port 3) 573 outputs command data constituting an 8-bit lamp control command, and the output port 570 outputs a 1-bit INT signal. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

  In the lamp control board 35, the lamp control CPU 351 has various decoration LEDs, decoration lamps 25, ceiling frame lamps 28a, left frame lamps 28b, and right frame lamps provided on the frame side defined according to each control command. A lighting / extinguishing signal is output to 28c. The on / off signal is output to each lamp / LED. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  In the main board 31, the CPU 56 outputs a lamp control command for instructing the lighting of the prize ball lamp 51 when there is an unpaid prize ball remaining in the stored contents of the RAM 55, and is installed in the supply ball passage on the back of the game board. When the off-ball switch 187 (see FIG. 4) stops detecting a game ball, a lamp control command for instructing lighting of the off-ball lamp 52 is output. In the lamp control board 35, each lamp control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  Further, the lamp control CPU 351 outputs a light on / off signal to the start memory display 18 and the normal symbol start memory display 41 in accordance with the lamp control command.

  As the input buffer circuits 355A and 355B, for example, 74HC540 and 74HC14 which are general-purpose CMOS-ICs are used. The input buffer circuits 355A and 355B can pass signals only in the direction from the main board 31 toward the lamp control board 35. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, the signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

  In the main board 31, buffer circuits 620 and 63A are provided outside the output ports 570 and 573. As the buffer circuits 620 and 63A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

  FIG. 9 is a block diagram showing a configuration example of the sound control command signal transmission part of the main board 31 and the sound control board 70. In this embodiment, a sound control command for instructing the sound output of the speaker 27 provided outside the game area 7 is output from the main board 31 to the sound control board 70 as the game progresses.

  As shown in FIG. 9, the sound control command is output from the output ports (output ports 0 and 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53. The output port (output port 4) 574 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the sound control board 70, each signal from the main board 31 is input to the sound control CPU 701 via the input buffer circuits 705A and 705B. When the sound control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the sound control CPU 701.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the sound control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the sound control CPU 701 to a level corresponding to the set volume and outputs it to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

  As the input buffer circuits 705A and 705B, for example, 74HC540 and 74HC14, which are general-purpose CMOS-ICs, are used. The input buffer circuits 705A and 705B can pass signals only in the direction from the main board 31 toward the sound control board 70. Therefore, there is no room for signals to be transmitted from the sound control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the sound control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

  In the main board 31, buffer circuits 620 and 67A are provided outside the output ports 570 and 574. As the buffer circuits 620 and 67A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal to the main board 31 from the sound control board 70 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

  FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full switch 48 is input to the I / O port portion 57 of the main board 31 via the relay board 71. The detection signal from the ball break switch 187 is also input to the I / O port portion 57 of the main board 31 through the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 should stop paying out when the detection signal from the ball-off switch 187 indicates a ball-out state, or when the detection signal from the full-tan switch 48 indicates a full-up state. The payout control command instructing that is sent. When receiving a payout control command instructing that payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, the detection signal from the prize ball count switch 301A is input to the I / O port portion 57 of the main board 31 via the relay board 72 and the relay board 71, and also from the payout control board 37 via the relay board 72. Input to the input port 372b. The prize ball count switch 301A is provided in a payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

  When there is a winning, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the payout control command to perform prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 via the output port 372c. Further, an error signal is output to the error display LED 374 via the output port 372d.

  Further, a detection signal from the payout motor position sensor for detecting the rotational position of the ball lending count switch 301B and the payout motor 289 is input to the input port 372b of the payout control board 37 via the relay board 72. . The ball lending count switch 301B is provided in a payout mechanism portion of the ball payout device 97, and detects a lending ball actually paid out. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the drive signal to the sorting solenoid 310 is transmitted. Is transmitted to the sorting solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372b and the output port 372e.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to a non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, at least a part of the RAM (may be a CPU built-in RAM) present on the payout control board 37 is backed up by a backup power source created on the power board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 11 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of the electric part control boards such as the main board 31, the symbol control board 80, the sound control board 70, the lamp control board 35, and the payout control board 37, and each electric part control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. Further, a capacitor 916 serving as a backup power source, that is, a memory holding means, is charged from a line of power source for driving DC + 5V, that is, an IC on each substrate. Note that VSL is generated by rectifying and boosting AC24V with a rectifier element in the rectifier circuit 912. VSL is a solenoid driving power source.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 includes one or a plurality of converter ICs 922 (only one is shown in FIG. 11), generates + 21V, + 12V, and + 5V based on VSL and outputs the generated voltages to the connector 915. A relatively large capacitor 923 is connected to the input side of the converter IC 922. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as + 30V, + 12V, + 5V, etc., decreases relatively slowly. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board. Further, in FIG. 11, one connector 915 is representatively shown, but the connector is provided for each electric component control board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 has a storage state with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is stopped (a RAM that is backed up by power, that is, a backup storage unit that can be in a storage content holding state even when the power supply is stopped). It becomes a backup power supply that supplies power so that it can be maintained. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line. In this embodiment, +5 V for backup is supplied to the main board 31 and the payout control board 37.

  The power supply board 910 is equipped with a power supply monitoring IC 902 as a power supply monitoring circuit. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. A power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 provide power supply, which is a process for protecting the stored contents of the backup RAM in response to the input of the power-off signal. Execute stop processing.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output becomes on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage, which decreases faster than + 12V, and the power supply is stopped, the switch output is turned on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 that is separate from the electrical component control board, a power-off signal can be supplied from the power monitoring circuit to the plurality of electrical component control boards. Even if there are any number of electrical component control boards that require a power-off signal, it is only necessary to provide one power supply monitoring means. Therefore, even if each electrical component control means in each electrical component control board performs recovery control described later. The cost of the gaming machine does not increase so much.

  In the configuration shown in FIG. 11, the detection signal (power cut-off signal) of the power monitoring IC 902 is sent to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. For example, a configuration may be adopted in which one detection signal is transmitted to the relay board, and the same signal is distributed from the relay board to each electrical component control board. Further, a buffer circuit corresponding to the number of substrates that require a power-off signal may be provided. Further, regarding the power-off signal output to the main board 31 and the payout control board 37, the monitoring voltage of the power supply monitoring circuit that outputs the power-off signal may be different.

  12 and 13 are explanatory diagrams showing output port assignment in this embodiment. As shown in FIG. 12, the output port 0 is an output port for an INT signal of a control command transmitted to each electrical component control board. The 8-bit data of the payout control command transmitted to the payout control board 37 is output from the output port 1, and the 8-bit data of the display control command transmitted to the symbol control board 80 is output from the output port 2. The 8-bit data of the lamp control command transmitted to the lamp control board 35 is output from the output port 3. As shown in FIG. 13, 8-bit data of the sound control command transmitted to the sound control board 70 is output from the output port 4.

  Further, various information output signals from the output port 5 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output. Then, a drive signal from the output port 6 to the solenoid 16 for opening and closing the variable winning ball apparatus 15, the solenoid 21 for opening and closing the opening / closing plate 2 of the big winning opening, and the solenoid 21A for switching the path in the big winning opening. Is output.

  As shown in FIG. 13, each INT signal (payout control signal INT, display control signal INT, lamp control signal INT) output to the payout control board 37, the symbol control board 80, the lamp control board 35, and the sound control board 70. And output port (output port 0) for outputting the sound control signal INT), payout control signals CD0 to CD7 as command data for payout control commands, display control signals CD0 to CD7 as command data for display control commands, and lamp control The output ports (output ports 1 to 4) that output the lamp control signals CD0 to CD7 as the command data of the command and the sound control signals CD0 to CD7 as the command data of the sound control command are different ports.

  Therefore, when outputting the INT signal, the possibility that the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, and the sound control signals CD0 to CD7 are erroneously changed is reduced. Further, when outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, or the sound control signals CD0 to CD7, the possibility of erroneously changing the INT signal is reduced. As a result, a command for each electric component control board is more reliably transmitted from the game control means of the main board 31. Furthermore, since all the INT signals are output from the output port 0, the burden of the INT signal output process of the game control means is reduced.

  FIG. 14 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 14, bits 0 to 7 of the input port 0 detect the winning port switches 33a, 24a, 29a and 30a, the start port switch 14a, the count switch 23, the V winning switch 22 and the gate switch 32a, respectively. A signal is input. In addition, the award ball count switch 301A, the full switch 48, the ball break switch 187 detection signal, the count switch short-circuit signal, and the clear switch 921 detection signal are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. Thus, the detection signal of the clear switch 921 is input to the same input port as the input port (8 bits) to which the switch detection signal for detecting the game ball is input.

  Next, the operation of the gaming machine will be described. FIG. 15 is a flowchart showing main processing executed by game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts main processing after step S1. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set in an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request outputs an RST instruction (1 byte) or a CALL instruction (3 bytes) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is in the high level (see FIG. 14). Further, for example, the game store clerk can easily execute the initialization process by starting the power supply to the gaming machine while the clear switch 921 is turned on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped (step S10). ). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  In this way, it is possible to accurately return the gaming state to the state when the power supply is stopped by checking whether the data in the backup RAM area is stored using the backup flag and check data such as a checksum. it can. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the state recovery process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol process flag, a payout command storage pointer, a winning ball flag, a ball out flag, a payout Work area setting setting processing for setting an initial value to a flag such as a stop flag for selectively performing processing according to the control state is performed (step S12). Further, a process of transmitting a payout stop cancellation command (payable state designation command) instructing that payout from the ball payout device 97 is possible to the payout control board 37 is performed (step S13). Further, a process of transmitting an initialization command for initializing other sub boards (lamp control board 35, sound control board 70, symbol control board 80) to each sub board is executed (step S14). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the extinction of the prize ball lamp 51 and the ball-out lamp 52 (to the lamp control board 35) Etc).

  In the initialization process, a payout enable state designation command is always transmitted to the payout control board 37. Even if the state of the gaming machine is a state in which a payout from the ball payout device 97 is not possible, the fact is detected in the game control process executed immediately after that and an instruction is given that the payout is not possible. There is no problem because a payout stop command (payout stop state designation command) is transmitted. In the process of transmitting the payable state designation command and the initialization command to other sub-boards, for example, the address of the table (ROM area) in which each command is set is set in the pointer, and the command setting process described later is performed. Call the appropriate processing routine.

  Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S15). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

When the execution of the initialization process (steps S11 to S15) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is
This is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a jackpot (a jackpot determining random number generation counter). In a game control process to be described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process described later, and thus conflicts with the process in the timer interrupt process. This is to avoid that. That is, if the timer interrupt is generated during the process of step S17 and the counter value for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  When the timer interrupt occurs, the CPU 56 performs the register saving process (step S20), and then executes the game control processes of steps S21 to S32 shown in FIG. In the game control process, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 33a, 24a, 29a, and 30a via the switch circuit 58. These state determinations are performed (switch processing: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs processing for setting a display control command related to the special symbol in a predetermined area of the RAM 55 and transmitting the display control command (special symbol command control processing: step S28). In addition, a process for transmitting a display control command by setting a display control command related to the normal symbol in a predetermined area of the RAM 55 is performed (normal symbol command control process: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, starting information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21, and 21A in response to a drive command in order to open or close the variable winning ball device 15 or the opening / closing plate 20, or to switch the game ball passage in the special winning opening. To do.

  Then, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals of the prize opening switches 33a, 24a, 29a, 30a (step S32). Specifically, a payout control command indicating the number of winning balls is output to the payout control board 37 in response to detection of winning based on the winning opening switch 33a, 24a, 29a, 30a being turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of prize balls. Thereafter, the contents of the register are restored (step S33), and the interrupt permission state is set (step S34).

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 17 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 17 is a specific process of step S26 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs any one of steps S300 to S309 according to the internal state after performing the fluctuation shortening timer subtraction process (step S310). The variation shortening timer is a timer for setting the variation time when the variation time of the special symbol is shortened.

  Special symbol change waiting process (step S300): The start winning opening 14 is hit and the start opening switch 17 is awaited. When the start opening switch 14 is turned on, if the start winning memorized number is not full, the starting win memorized number is incremented by 1 and a jackpot determining random number or the like is extracted.

  Special symbol determination process (step S301): When variable symbol special display can be started, the number of start winning memories is confirmed. If the start winning memorized number is not 0, it is determined whether to win or not according to the extracted value of the big hit determination random number.

  Stop symbol setting process (step S302): The stop symbol of the middle left and right symbols is determined.

  Reach operation setting process (step S303): It is determined whether or not to perform a reach operation based on a combination of left and right stop symbols, and when it is determined to reach, depending on the value of the random number for determining the variation pattern Determine the time of change at reach.

  All symbol variation start processing (step S304): Control is performed so that the variation display unit 9 starts variation of all symbols. At this time, the left / right middle final stop symbol and information for instructing the variation mode are transmitted to the symbol control board 80. When the process is finished, the internal state (process flag) is updated to shift to step S305.

  All symbol stop waiting process (step S305): When a predetermined time (the time indicated by the fluctuation shortening timer in step S310) elapses, all symbols displayed on the variable display unit 9 are stopped. If the stop symbol is a combination of jackpot symbol, the internal state (process flag) is updated to shift to step S306. If not, the internal state is updated to shift to step S300.

  Big winning opening opening process (step S306): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. When the process is finished, the internal state (process flag) is updated to shift to step S307.

  Processing for opening a special prize opening (step S307): A process for transmitting a display control command for displaying a special prize round to the symbol control board 80, a process for confirming establishment of a closing condition for the special prize opening, and the like are performed. If the final closing condition of the big prize opening is satisfied, the internal state is updated to shift to step S308.

  Specific area valid time process (step S308): The presence / absence of passing of the V winning switch 22 is monitored, and the process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S306. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S309.

  Big hit end process (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated to shift to step S300.

  FIG. 18 is a flowchart showing an example of a normal symbol process processing program executed by the CPU 56. The normal symbol process shown in FIG. 18 is a specific process of step S27 in the flowchart of FIG. When performing normal symbol process processing, the CPU 56 performs gate switch passage confirmation processing (step S75) and then selects one of steps S70 to S74 according to the internal state (normal symbol process flag in this example). Perform the process.

  The gate switch passage confirmation process is a process for detecting the passage of the game ball through the gate 32, which is a condition for starting the normal symbol fluctuation. In the gate switch passage confirmation process, when the CPOU 56 confirms that the gate switch 32a is turned on, it acquires and stores a predetermined random value (random 5 in this example). In addition, the fact that the gate switch 32a is turned on can be stored in a maximum of four as normal symbol starting memories.

  In steps S70 to S74, the following processing is performed.

  Normal symbol normal processing (step S70): The normal symbol start memory number is confirmed. If the normal symbol start memory number is not 0, the value of the normal symbol process flag is changed so as to proceed to step S71.

  Normal symbol determination process (step S71): The contents of the buffer for storing the random number stored when the game ball passes through the gate 32 are shifted. As a result of the shift, whether or not to win is determined based on the contents of the buffer pushed out. Thereafter, the value of the special symbol process flag is changed so as to proceed to step S72. In this embodiment, if the value of the random number that can take a value in the range of 3 to 13 is any of 3 to 12, it is determined to be a hit, and if the value of the random number is 13, it is determined to be out of place. The Further, when the winning symbol is determined, the stop symbol after the variation of the normal symbol fluctuating in the normal symbol display 10 becomes a winning symbol, and when it is determined to be off, the stopping symbol is controlled to be a missing symbol.

  Normal symbol variation processing (step S72): It is confirmed whether or not the variation time of the regular symbol has elapsed. If it has elapsed, the value of the normal symbol process flag is changed so as to proceed to step S73.

  Normal symbol stop process (step S73): If it is determined to win, the value of the normal symbol process flag is changed so as to proceed to step S74. Otherwise, the value of the normal symbol process flag is changed so as to proceed to step S70.

  Ordinary electric accessory operating process (step S74): A process of releasing the variable winning ball apparatus 15 for a predetermined time is performed a predetermined number of times. The solenoid 16 is driven to open the variable winning ball device 15. Then, the value of the normal symbol process flag is changed so as to proceed to step S70.

  FIG. 19 is an explanatory diagram showing an example of a command form of a control command transmitted from the main board 31 to another electrical component control board. In this embodiment, the command data of the control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”. As described above, the control command transmitted to the electrical component control board is composed of a plurality of command data and can be distinguished from each other by the first bit. Note that the command form shown in FIG. 19 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  FIG. 20 is a timing chart showing a relationship between 8-bit control signals CD0 to CD7 (command data) and an INT signal (capture signal) that constitute a control command for each electric component control means. As shown in FIG. 20, after the MODE or EXT data is output to the output port (any one of the output port 1 to the output port 4), when the period indicated by A elapses, the CPU 56 outputs the data. The INT signal, which is a signal indicating the above, is set to a high level (ON data). Further, when the period indicated by B elapses thereafter, the INT signal is set to low level (off data). Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the second byte of data is output to the output port after a period indicated by C. Regarding the second byte data, the periods A and B are the same as in the first byte. In this way, the capture signal is output for each of the MODE and EXT data.

  The period A is a period required for the CPU 56 to prepare for command transmission, that is, a process for setting a control command in the buffer, and a period for stabilizing data in the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, the INT signal as the capture signal is output after a predetermined period (period A: part of the off output period) has elapsed. The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the off-output period) is a period set so that the electrical component control means can reliably capture data. During the period of B and C, the data on the signal line does not change. That is, the data output is maintained until the period of B and C elapses.

  In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are the same command. It is transmitted using a transmission processing routine (common module). Therefore, the period of B and C, that is, the period from when the INT signal related to the first byte rises to the start of data transmission of the second byte is longer than the reception processing time in the electrical component control means that takes the longest time for command reception processing. Is set to be longer.

  Each electrical component control means detects that the INT signal has risen, and starts a 1-byte data capture process, for example, by an interrupt process.

  Since the period of B and C is longer than the reception processing time in the electrical component control means that takes the longest time for command reception processing, even if the game control means controls the command transmission processing for each electrical component control means with the common module Any electric component control means can reliably receive a control command from the game control means.

  The CPU 56 can transmit the next data when a predetermined period elapses after executing the INT signal output process. During the predetermined period (B and C periods), the data is transmitted before the INT signal output process. Is longer than the period (period A) from when the INT signal starts to be output. As described above, the period A is a stabilization period in the command signal line, and the periods B and C are periods for securing a time required for the receiving side to capture data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain the effect that the electric component control means on the receiving side can reliably receive the command, and the transmission of one command is completed. This also has the effect of shortening the time required for.

  FIG. 21 is an explanatory diagram showing an example of the contents of a display control command transmitted to the symbol control board 80 of the electric component control board. As shown in FIG. 22, the display control command has a 2-byte configuration. In the example shown in FIG. 21, commands 8000 (H) to 8031 (H) are display control commands for designating a special symbol variation pattern in the variable display device 9 that variably displays the special symbol. Note that a command for specifying a variation pattern (variation pattern command) also serves as a variation start instruction.

  The command 88XX (X = any value of 4 bits) is a display control command relating to a variation pattern of a normal symbol variably displayed on the normal symbol display 10. The command 89XX is a display control command for designating a normal symbol stop symbol. Command 8AXX (X = any value of 4 bits) is a display control command for instructing stop of variable symbol display.

  Commands 91XX, 92XX, and 93XX are display control commands for designating a stop symbol in the middle left of the special symbol. The command A0XX is a display control command for instructing to stop the special symbol variable display. The command BXXX is a display control command transmitted from the start of the big hit game to the end of the big hit game. The commands C000 to EXXXX are display control commands relating to the display state of the variable display device 9 that is not related to the variation of the special symbol and the big hit game.

  The display control command is transmitted to the display control means as a command indicating the control state after the change in the special symbol command control processing or the normal symbol command control processing in the game control processing (see FIG. 16). Whether or not the control state has changed is determined by a special symbol process or a normal symbol process. When the display control means of the symbol control board 80 receives the display control command described above from the game control means of the main board 31, the display state of the variable display device 9 and the normal symbol display 10 is changed according to the contents shown in FIG. Control to change.

  FIG. 22 is an explanatory diagram showing an example of the content of the lamp control command. The lamp control command also has a 2-byte configuration of MODE and EXT. In the example shown in FIG. 22, commands 8000 (H) to 8031 (H) are lamp control commands for designating a lamp / LED display control pattern corresponding to a special symbol variation pattern in the variable display device 9. The command A0XX (X = any value of 4 bits) is a lamp control command for instructing a lamp / LED display control pattern when the variable symbol special display is stopped. The command BXXX is a lamp control command for instructing a lamp / LED display control pattern from the start of the jackpot game to the end of the jackpot game. The command C000 is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration.

  The commands 8XXX, AXXX, BXXX and CXXX are ramp control commands transmitted from the game control means in accordance with the game progress status. When the lamp control means receives the lamp control command described above from the game control means of the main board 31, the lamp / LED display state is changed according to the contents shown in FIG.

  The command E0XX is a lamp control command indicating the number of lighting of the start memory display 18. For example, the lamp control means turns on the number of displays designated by “XX” in the start memory display 18. The command E1XX is a lamp control command indicating the number of lighting of the normal symbol start memory display 41. For example, the lamp control means turns on the number of displays designated by “XX” in the normal symbol start memory display 41. That is, these commands are commands for instructing control of the light emitters that are provided in order to notify information about the number of reserves. In addition, the command regarding the number of lighting of the start memory | storage display 18 and the normal symbol start memory | storage display 41 may be comprised so that increase / decrease in the number of lighting may be shown.

  The commands E200 and E201 are lamp control commands related to the display state of the winning ball lamp 51, and the commands E300 and E301 are lamp control commands related to the display state of the ball-out lamp 52. When the lamp control means receives the lamp control command of “E201” from the game control means of the main board 31, the lamp control means sets the display state of the prize ball lamp 51 as a predetermined display state when there is a prize ball remaining, and “E200” When the lamp control command is received, the display state of the prize ball lamp 51 is set to a display state determined in advance as a case where no prize ball remains.

  When the lamp control command “E300” is received from the game control means of the main board 31, the display state of the ball break lamp 52 is changed to the display state with a ball, and when the lamp control command “E301” is received, the ball break lamp 52 is displayed. The display state of is set to the display state when the ball is out. That is, commands E200 and E201 are commands indicating control of a light-emitting body provided for notifying a player or the like that there is a non-prize ball, and commands E300 and E301 are supply balls. This is a command indicating that a light-emitting body provided for notifying a player or a game clerk that the game has expired is controlled.

  The command E400 is changed from a special gaming state (high probability state or short time state, high probability state in this example) to a normal state (low probability state or non-time short state, low probability state in this example) when the gaming machine is turned on. This is a lamp control command for instructing a lamp / LED display control pattern at the time of transition. The command E401 is a lamp / LED display when a transition is made from a normal state (low probability state or non-time-short state, low probability state in this example) to a special game state (high probability state or time-short state, high probability state in this example). This is a lamp control command for designating a control pattern. The command E402 is a lamp control command for instructing a lamp / LED display control pattern when an error occurring during the big hit game is canceled. The command E403 is a lamp control command for instructing a lamp / LED display control pattern when an error of the count switch 23 occurs.

  The lamp control command is transmitted to the lamp control means as a command indicating the control state after the change in, for example, a special symbol process or a prize ball process in the game control process (see FIG. 16). Whether the control state has changed is determined by special symbol process processing, prize ball processing, or the like.

  FIG. 23 is an explanatory diagram showing an example of the contents of a sound control command. The sound control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 23, a command 8XXX (X = any value of 4 bits) is a sound control command for designating a sound generation pattern in a special symbol variation period. The command BXXX (arbitrary value of X = 4 bits) is a sound control command for designating a sound generation pattern from the start of the big hit game to the end of the big hit game. The other commands are sound control commands that are not related to special symbol changes and jackpot games. When the sound control means mounted on the sound control board 70 receives the above-described sound control command from the game control means of the main board 31, the sound output state is changed according to the contents shown in FIG.

  For example, in the special symbol process in the game control process (see FIG. 16), the sound control command is transmitted to the sound control means as a command indicating the control state after the change. Whether or not the control state has changed is determined by special symbol process processing or the like.

  FIG. 24 is an explanatory diagram showing an example of the contents of the payout control command. In the example shown in FIG. 24, the command FF00 (H) with MODE = FF (H) and EXT = 00 (H) is a payout control command (payout enable state designation command) for instructing that payout is possible. is there. A command FF01 (H) with MODE = FF (H) and EXT = 01 (H) is a payout control command (payout stop state designation command) for instructing that payout should be stopped. A command F0XX (H) with MODE = F0 (H) is a payout control command for designating the number of winning balls. “XX”, which is EXT, indicates the number of payouts.

  When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout payout and ball lending are stopped, and when the payout control command of FF00 (H) is received, the payout ball payout And you can rent a ball. When a payout control command for designating the number of prize balls is received, prize ball payout control is performed according to the number designated by the received command.

  The display control command, the lamp control command, the sound control command, and the payout control command are in a common command form. In other words, each control command is composed of 8-bit command data and a 1-bit INT signal (strobe signal) for instructing the capture of the command data. Therefore, the command creation routine and the transmission routine in the game control means can be made common for each control command. As a result, the program capacity for command creation and transmission is reduced. In this embodiment, the command data is composed of 2-byte command data composed of MODE data representing the classification of the command and EXT data representing the command type, but the command data is composed of 1 byte or 3 bytes or more. It may be. Moreover, each control command shown in FIGS. 21 to 24 is an example, and the control content and the method of assigning the control command are arbitrary.

  Further, regarding the display control command, the lamp control command, and the sound control command, commands 8XXX, AXXX, BXXX, and CXXX are transmitted from the game control means at the same time according to the game progress status. For example, when the variation of the symbol is started in the variable display device 9 with the variation pattern 1, the same command 8000 (H) is transmitted to the symbol control board 80, the lamp control board 35, and the sound control board 70. That is, the game control means need only transmit one type of control command to the plurality of electrical component control boards. Thus, in this embodiment, the same command can be transmitted to a plurality of electrical component control boards when the control state changes according to the progress of the game. As a result, the number of types of control commands can be reduced.

  The change in the control state means, for example, that the electrical component control means changes the operation to be controlled (for example, the display state of the variable display device 9, the lighting pattern of various lamps / LEDs, the sound generation pattern from the speaker 27). It is to judge that it is necessary to do.

  Each control command is transmitted only once so that the electric component control means mounted on the electric component control board can be recognized. In this example, “recognizable” means that the level of the INT signal changes. In this example, “recognizable to be transmitted only once” corresponds to each of the first and second bytes of command data. Thus, the INT signal is output in a pulse shape (rectangular wave shape) only once.

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an ON state. As shown in FIG. 25, the switch timer is provided for the number N of detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 12. Further, in the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (from top to bottom shown in FIG. 14).

  FIG. 26 is a flowchart illustrating a processing example of the switch process in step S21 in the game control process. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs data input to the input port 0 (step S101). Next, “8” is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

  FIG. 27 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, the switch timer pointed to by the pointer (switch timer address is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S124). Data of input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S125), that is, if the detection signal of the winning opening switch 33a is on, the switch timer value is incremented by 1 (step S127). If the value after addition is not 0, the addition value is returned to the switch timer (steps S128 and S129). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0”, that is, if the detection signal of the winning opening switch 33a is in the OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S130) and subtracts 1 from the number of processes (step S131). If the number of processes is not 0, the process returns to step S122. Then, the processes of steps S122 to S132 are repeated.

  The processes in steps S122 to S132 are repeated for the number of processes, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially checked to determine whether it is on or off. If it is ON, the value of the corresponding switch timer is incremented by one.

  The CPU 56 inputs the data input to the input port 1 in step S105 of the switch process. Next, “4” is set as the processing number (step S106), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S107). Then, a switch check processing subroutine is called (step S108).

  In the switch check processing subroutine, since the above-described processing is executed, the processing in steps S122 to S132 is repeated for the number of processing, that is, four times, and the detection signal of the switch input to the 4 bits of the input port 1 during that time. Then, a check process is sequentially performed to determine whether the state is on or off. If the state is on, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

  28 to 30 are flowcharts showing an example of the prize ball process in step S32 in the game control process. In this embodiment, in the prize ball processing, it is determined whether or not the prize opening switches 33a, 24a, 29a, 30a, the count switch 23, and the start opening switch 14a to be paid out are surely turned on. When it is turned on, control is performed so that a payout control command indicating the number of winning balls is transmitted to the payout control board 37, and it is determined whether or not the full tank switch 48 and the ball shortage switch 187 are turned on. Processing such as control to transmit a predetermined payout control command to the payout control board 37 is performed.

  In the prize ball process, the CPU 56 sets “1” as the offset of the input determination value table (step S150), and sets “9” as the offset of the address of the switch timer (step S151). The offset “1” in the input determination value table (see FIG. 32) means that the second data “50” in the input determination value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “9” designates the switch timer corresponding to the full switch 48. Means. Then, a switch-on check routine is called (step S152).

  The input determination value table is a ROM area in which a determination value for determining that the switch has been turned on when it is detected how many times it is continuously turned on is set for each switch. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 32, the input determination value table includes “2”, “50”, “250”, “30”, “250”, “1” in order from the top, that is, in order from the smallest address value. The judgment value is set. In the switch-on check routine, the judgment value set at the address determined by the head address and the offset value in the input judgment value table is compared with the value of the switch timer determined by the head address and the offset value of the switch timer. If they match, for example, a switch-on flag is set.

  An example of a switch-on check routine is shown in FIG. In the switch-on check routine, if the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch on determination value “50”, the switch on flag is set (step S153), so the full tank flag is set. (Step S154). Although not explicitly shown in FIG. 28, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

  Further, the CPU 56 sets “2” as the offset of the input determination value table (step S156), and sets “0A (H)” as the offset of the switch timer address (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the switch timer address offset “0A (H)” is designated by the switch timer corresponding to the ball break switch 187. Means that Then, a switch-on check routine is called (step S158).

  In the switch-on check routine, if the value of the switch timer corresponding to the ball-out switch 187 matches the ball-out switch-on determination value “250”, the switch-on flag is set (step S159). It is set (step S160). Although not explicitly shown in FIG. 28, a switch-off timer corresponding to the ball-out switch 187 is prepared, and when the value becomes 50, the ball-out flag is reset.

  Then, the CPU 56 confirms whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command which is a payout control command for instructing the payout control board 37 that payout should be stopped is transmitted. If it is not in the payout stop state, it is confirmed whether or not the above-described ball-out state flag or full tank flag is turned on (step S202).

  When either of them changes to the on state, a command transmission table related to the payout stop state designation command is set (step S203), and command set processing is called (step S206). In step S203, the head address of the command transmission table (ROM) storing the payout control command of the payout stop state designation command is set as the address of the command transmission table. In the command transmission table relating to the payout stop state designation command, INT data described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set. In step S202, when one of the flags is already in the on state and the other flag is in the on state, the command transmission control process (step S203) is not performed.

  If it is in the payout stop state, it is checked whether both the ball-out state flag and the full tank flag are turned off (step S204). When both are turned off, the command transmission table relating to the payable state designation command is set (step S205), and the command setting process is called (step S207). In step S205, the head address of the command transmission table (ROM) in which the payout control command of the payable state designation command is stored is set as the address of the command transmission table. In the command transmission table related to the payout enable state designation command, INT data, data of the first byte of the payout control command, and data of the second byte of the payout control command, which will be described later, are set.

  Further, the CPU 56 sets “0” as the offset of the input determination value table (step S221), and sets “0” as the offset of the switch timer address (step S222). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the switch timer address offset “0” designates the switch timer corresponding to the winning port switch 33a. Means. Also, “4” is set as the number of repetitions (step S223). Then, a switch-on check routine is called (step S224).

  In the switch-on check routine, the CPU 56 sets the head address of the input determination value table (see FIG. 32) (step S281). Then, an offset is added to the address (step S282), and a switch-on determination value is loaded from the address after the addition (step S283).

  Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the address after the addition (step S286). Since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the value of the switch timer corresponding to the switch is loaded.

  Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, a switch-on flag is set (step 128).

  In this case, in the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value “2” (step S225). The switch check-on routine is executed for the number of repetitions initially set (step S228, S229) while the offset of the switch timer address is updated (step S230). For 24a, 29a and 30a, the value of the corresponding switch timer is compared with the switch-on determination value “2”.

  When the switch-on flag is set, “10” as the number of prize balls to be paid out is set in the ring buffer (step S226). Then, 10 is added to the stored value of the total winning ball number storage buffer (step S227). When data is written to the ring buffer, the write pointer is incremented. When data is written to the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

  The total winning ball number storage buffer is a buffer for storing a cumulative value of the number of winning balls instructed to the payout control means (however, subtracted when paying out), and is formed in the backup RAM. In this embodiment, when data is written to the ring buffer, an addition process is performed on the stored value of the total prize ball number storage buffer, but a payout control command for instructing the number of prize balls to be paid out is output to the output port. At the time of output, the number of prize balls corresponding to the payout control command to be output may be added to the value stored in the total prize ball number storage buffer.

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S231), and sets “4” as the offset of the switch timer address (step S232). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 14, the switch timer address offset “4” designates the switch timer corresponding to the start port switch 14a. Means. Then, a switch-on check routine is called (step S233).

  In the switch-on check routine, if the value of the switch timer corresponding to the start port switch 14a matches the switch-on determination value “2”, the switch-on flag is set (step S234). When the switch-on flag is set, “6” as the number of prize balls to be paid out is set in the ring buffer (step S235). Further, 6 is added to the stored value of the total winning ball number storage buffer (step S236).

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S241), and sets “5” as the offset of the switch timer address (step S242). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports shown in FIG. 15, the switch timer address offset “5” indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, a switch-on check routine is called (step S243).

  In the switch-on check routine, if the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, “15” as the number of prize balls to be paid out is set in the ring buffer (step S245). Further, 15 is added to the stored value of the total winning ball number storage buffer (step S246).

  If data exists in the ring buffer (step S247), the contents of the ring buffer pointed to by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (next area of the ring buffer). (Step S249), a command transmission table relating to the number of winning balls is set (Step S250), and command set processing is called (Step S251). The operation of the command set process will be described in detail later.

  In step S250, the head address of the command transmission table (ROM) in which the payout control command relating to the number of winning balls is stored is set as the address of the command transmission table. In the command transmission table relating to the number of winning balls, INT data (01 (H)) described later, data of the first byte of the payout control command (F0 (H)), and data of the second byte of the payout control command are set. ing. However, “80 (H)” is set as the second byte data.

  As described above, when the game control means tries to output a payout control command for instructing the number of prize balls to the payout control board 37, the command transmission table address setting and the transmission buffer setting regarding the number of prize balls are performed. . Then, a payout control command is transmitted to the payout control board 37 based on the command transmission table regarding the number of winning balls and the setting contents of the transmission buffer by the command set process. In step S247, whether or not there is data can be confirmed by the difference between the write pointer and the read pointer. However, a counter indicating the number of unprocessed data in the ring buffer is provided, and there is data by the count value. It may be confirmed whether or not.

  Then, when the content of the total prize ball number storage buffer is not 0, that is, when there is still a prize ball remaining, the CPU 56 turns on a prize ball paying-in flag (steps S252 and S253).

  Further, when the winning ball payout flag is on (step S254), the CPU 56 monitors the number of winning balls actually paid out from the ball paying device 97 and subtracts the stored value of the total winning ball number storage buffer. The number of winning balls to be subtracted is performed (step S255). When the winning ball paying flag changes from on to off, a lamp control command for instructing lighting of the winning ball lamp 51 is transmitted to the lamp control board 35.

  As described above, in this embodiment, even when a shortage of game balls to be paid out is detected (at the time of running out of balls), even when the game balls should not be paid out when the lower plate is full, A payout stop state designation command as a command is notified from the game control means to the payout control means (see FIG. 28). That is, even if the conditions for stopping payout are different, a common command is transmitted from the game control means to the payout control means. In other words, it is instructed that the payout control means is not in a state where payout is not possible by a common control command even when any of the plurality of payout stop conditions different from the completion of payout of the game medium is satisfied. The When the payout control means receives the payout stop state designation command, the payout control means stops paying out the game balls.

  Even when any payout stop condition is satisfied, a common control command can be used to instruct that the payout control means is not in a payable state, so that a load related to information transmission from the game control means to the payout control means is reduced. As a result, there is an advantage that the program capacity in the game control means is reduced and the program capacity that can be used for game control is increased.

  As will be described later, when the payout control means receives the payout stop state designation command, it stops both the ball payout as the winning ball and the ball payout as the ball lending. In addition, when a payout enabled state designation command is received, a ball payout as a winning ball and a ball payout as a ball lending are both enabled. However, the game control means gives the payout control means a separate payout control command for stopping or restarting the payout of the ball as a prize ball, and a payout control command for stopping or restarting the payout of the ball as a ball rental. May be transmitted.

  In this embodiment, even if the payout is stopped (steps S201 and S204), the processing of steps S221 to S251 is executed. That is, the game control means can transmit a payout control command for instructing the number of winning balls even when the payout is stopped. That is, a command for instructing the number of prize balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is canceled, the payout of the prize balls can be started early. Further, the game control means does not require a large storage area for storing the number of winning balls based on winning in the payout stop state.

  Next, a transmission method of control commands from the game control means to each electric component control means will be described. When a control command is to be output from the game control means to another electrical component control board (sub board), the head address of the command transmission table is set. FIG. 33A is an explanatory diagram showing a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, the EXT data of the second byte of the control command is set in the command data 2 of the third byte.

  Although the EXT data itself may be set in the area of the command data 2, the command data 2 may be set with data for designating the address of the table storing the EXT data. . For example, if bit 7 (work area reference bit) of command data 2 is 0, it indicates that EXT data itself is set in command data 2. If bit 7 (work area reference bit) of command data 2 is 1, data stored in an area indicated by an address in a predetermined address table (command extended data address table) is used as EXT data. It shows that. For example, in the case of a payout control command, the work area reference bit is 1, and the contents of the transmission buffer are used as EXT data.

  FIG. 33 (B) is an explanatory diagram showing a configuration example of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be transmitted to the payout control board 37. If bit 0 is “1”, it indicates that a payout control command should be transmitted.

  In this embodiment, a command transmission table is prepared for each control command transmitted to each electric component control main board, and the address of the command transmission table to be used is set before transmitting the control command. A plurality of command transmission tables may be prepared as one table. For example, as shown in FIG. 33C, one table including a plurality of command transmission tables capable of storing a plurality of control commands is prepared. In that case, for example, in the display control command control process, the CPU 56 sets INT data, command data 1 and command data 2 from the command transmission table pointed to by the pointer, and transmits the display control command. Then, the pointer is updated. Thereafter, the display control command transmission process is repeated until the command transmission table designated by the pointer indicates the end code.

  FIG. 34 is a flowchart illustrating an example of command set processing. The command set process is a process including a command output process and an INT signal output process. In the command set process, the CPU 56 first saves the address of the command transmission table in a stack or the like (step S331). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 becomes input information for a command transmission process to be described later. Also, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1.

  Next, the CPU 56 reads the command data 1 and sets it to the argument 2 (step S334). The argument 2 is also input information for a command transmission process to be described later. Then, the command transmission processing routine is called (step S335).

  FIG. 35 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set as the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of port 1 is set to the IO address (step S353). In this embodiment, the port 1 address is an output port address for outputting payout control command data, and the ports 2 to 4 output display control commands, lamp control command data, and sound control command data. This is the output port address.

  Next, the CPU 56 shifts the comparison value to the right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether or not the carry bit has become 1 (step S355). When the carry bit becomes 1, it means that the rightmost bit in the INT data is “1”. In this embodiment, four shift processes are performed. For example, when it is specified that a display control command should be transmitted, the carry bit is set to 1 in the second shift process.

  When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S 356). When the second shift process is performed, the port 2 address is set as the IO address. At this time, the MODE data of the display control command is output to the port 2.

  Next, the CPU 56 adds 1 to the IO address (step S357) and subtracts 1 from the number of processes (step S358). If port 2 is indicated before addition, the address of port 3 is set as the IO address by the addition processing for the IO address. Port 3 is a port for outputting a lamp control command. Then, the CPU 56 confirms the value of the number of processes (step S359), and if the value is not 0, returns to step S354. In step S354, the shift process is performed again.

  In the second shift process, the value of bit 1 in the INT data is pushed out, and the carry flag is set to “1” or “0” depending on the value of bit 1. Therefore, it is checked whether or not it is specified that the display control command should be transmitted. Similarly, it is checked whether the lamp control command and the sound control command should be transmitted by the third and fourth shift processes. Thus, when each shift process is performed, an IO address corresponding to a command (payout control command, display control command, lamp control command, sound control command) checked by the shift process is set in the IO address. Has been.

  Therefore, when the carry flag becomes “1”, the control command is transmitted to the corresponding output port (port 1 to port 4). That is, a command transmission process (output process) to each electrical component control unit can be performed by one common module.

  Further, since it is determined to which electrical component control means the control command should be output only by the shift process, the process for determining to which electrical component control means the control command should be output is simplified. It has become.

  Next, the CPU 56 reads the content of the argument 1 in which the INT data before the start of the shift process is stored (step S360), and outputs the read data to the port 0 (step S361). In this embodiment, the address of port 0 is a port for outputting an INT signal for each control signal, and bits 0 to 4 of port 0 are a payout control INT signal, a display control INT signal, and a ramp, respectively. This is a port for outputting a control INT signal and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 is “1”. It has become. Therefore, the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 is turned off (low level).

  Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and subtracts one by one until the value becomes 0 (steps S363 and S364). When the value of the wait counter becomes 0, clear data (00) is set (step S365), and the data is output to port 0 (step S366). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S362), and 1 is subtracted one by one until the value becomes 0 (steps S368 and S369).

  As described above, the MODE data of the first byte of the control command is transmitted. Therefore, the CPU 56 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the command data 2 area of the third byte is designated. The CPU 56 loads the contents of the indicated command data 2 into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S338). If not 0, the head address of the command extended data address table is set in the pointer (step S339), and the value of bit 6 to bit 0 of the command data 2 is added to the pointer to calculate the address (step S340). Then, the data of the area indicated by the address is loaded into the argument 2 (step S341).

  In the command extended data address table, EXT data that can be transmitted to the electrical component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extended data address table corresponding to the contents of the command data 2 is loaded into the argument 2 and the work area reference bit If the value is “0”, the contents of the command data 2 are loaded into the argument 2 as they are. Even when EXT data is read from the command extension data address table, bit 7 of the data is “0”.

  Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, the EXT data is transmitted at the same timing as the transmission of MODE data. Thereafter, the CPU 56 restores the address of the command transmission table (step S343) and updates the value of the read pointer indicating the command transmission table (step S344). If there is another command to be transmitted (step S345), the process returns to step S331.

  As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte configuration is transmitted to the corresponding electrical component control means. When the level change of the INT signal is detected in the electrical component control means, the control command capturing process is started. However, any electrical component control means receives a new signal from the game control means before the capturing process is completed. It is not output to the signal line. That is, reliable command reception processing is performed in each electrical component control means such as a display control means. The polarity of the INT signal may be reversed from that shown in FIG.

  As described above, the command set process is a common module used when transmitting any of the display control commands, lamp control commands, sound control commands, and payout control commands. Therefore, the program capacity of the game control program executed by the game control means can be saved.

  Furthermore, since the forms of the display control command, the lamp control command, the sound control command, and the payout control command are common, the process of creating each control command can be easily modularized. In this embodiment, the command transmission table (see FIG. 33A) for each control command is set in the ROM in advance, but can be created when each control command is transmitted. For example, after creating a command transmission table as shown in FIG. 33A in the RAM, the command set process shown in FIG. 34 may be called.

  Since the command transmission table for any of the display control commands, lamp control commands, sound control commands, and payout control commands is composed of INT data and command data 1 and 2, it is a common module for creating control commands. 33. If the common module is called by using INT data in which any bit is “1” and data to be set in the command data 1 and 2 as input data, any control command is shown in FIG. A common module for creating a control command can be configured so that a command transmission table as described above is created.

  Next, the operation of display control means (display control CPU 101 and its peripheral circuits) will be described as an example of electrical component control means. FIG. 36 is a flowchart showing main processing executed by the display control means. In the main process, the display control CPU 101 first executes an initialization process for initializing a register, a RAM including a work area, an output port, and the like (step S401). Next, a process for updating a counter value for generating a random number is performed (step S402). Then, it is confirmed whether or not a display control command has been received from the main board 31 (step S403: command confirmation processing). Further, a command execution process, such as a process for changing process data to be used (data for setting a timer for progressing display control or display contents), is performed according to the received display control command (step S404). ). The display control command from the main board 31 is taken in by an interrupt process activated in response to the input of the INT signal, and stored in a reception command buffer formed in the RAM.

  Thereafter, in this embodiment, the display control CPU 101 monitors the timer interrupt flag (step S405). Then, as shown in FIG. 37, when a timer interrupt occurs, the display control CPU 101 sets a timer interrupt flag (step S411). If the timer interrupt flag is set in the main processing, the display control CPU 101 clears the flag and performs display control process processing and port output processing (steps S406 and S407).

  Next, display control command reception processing from the main board 31 will be described. FIG. 38 is an explanatory diagram showing a configuration example of a command reception buffer for storing a display control command received from the main board 31. In this example, a command reception buffer of a ring buffer format capable of storing six display control commands having a 2-byte configuration is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

  FIG. 39 is a flowchart showing display control command reception processing by interrupt processing. An INT signal for display control from the main board 31 is input to an interrupt terminal of the CPU 101 for display control. For example, when the level of the INT signal from the main board 31 changes, the display control CPU 101 is interrupted. Then, the display control command reception process shown in FIG. 39 is started.

  If the interrupt is generated at the level change timing (edge) of the pulsed (rectangular wave) INT signal as the capture signal, the edge may be a rising edge or a falling edge. Good. In any case, the interrupt is generated at the level change timing (edge) of the pulsed (rectangular wave) INT signal as the capture signal. By doing so, it becomes possible to receive a command promptly at the stage where command fetch is instructed. Since the output of the INT signal is on standby until the period A (FIG. 35) elapses, the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output. Therefore, the display control command is favorably received by the display control means.

  In the display control command reception process, the display control CPU 101 first saves each register to the stack (step S670). When an interrupt occurs, the display control CPU 101 automatically sets the interrupt prohibited state. However, if a CPU that does not automatically enter the interrupt prohibited state is used, before executing the process of step S670. It is preferable to issue an interrupt prohibition instruction (DI instruction). Next, data is read from an input port assigned to input of display control command data (step S671). And it is confirmed whether it is the 1st byte of the display control command of 2 bytes composition (Step S672).

  Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is “1”. The first bit is “1”, which should be MODE data (first byte) in the display control command having a 2-byte configuration (see FIG. 19). Therefore, if the first bit is “1”, the display control CPU 101 stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area, assuming that the first valid byte has been received (step S1). S673).

  If it is not the first byte of the display control command, it is confirmed whether or not the first byte has already been received (step S674). Whether or not it has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

  If the first byte has already been received, it is confirmed whether or not the first bit of the received 1 byte is “0”. If the first bit is “0”, it is determined that a valid second byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S675). The first bit of “0” is supposed to be EXT data (second byte) in the display control command having a 2-byte configuration (see FIG. 19). If the confirmation result in step S674 indicates that the first byte has already been received, the process ends unless the first bit of the data received as the second byte is “0”.

  In step S675, when the command data of the second byte is stored, 2 is added to the command reception number counter (step S676). Then, it is confirmed whether or not the command reception counter is 12 or more (step S677), and if it is 12 or more, the command reception number counter is cleared (step S678). Thereafter, the saved register is restored (step S679), and interrupt permission is set (step S680).

  The display control command has a two-byte configuration, and the first byte (MODE) and the second byte (EXT) are configured to be immediately distinguishable on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

  As described above, the symbol control board 80 is provided with a reception buffer area as a storage area capable of simultaneously storing a plurality of received display control commands, and the display control commands are stored in the reception command buffer in the reception buffer area. When stored, the command reception number counter corresponding to the storage address is updated. When the display control command is stored in the last received command buffer in the receive buffer area, the value of the command reception number counter is returned to zero. That is, the storage address is set to point to the start address of the reception buffer area.

  The display control CPU 101 reads the display control command in the reception buffer area based on the read address in the reception buffer area. When one display control command is read, the read address is updated. That is, it is updated to point to the next received command buffer. For example, in the command recognition process in the main process described above, when it is detected that a display control command is stored in the reception buffer area, the display control process instructed by the read display control command in the command execution process To start. Therefore, the display control means reads the display control command from the specific reception command buffer indicated by the read address according to the reception order, and starts the display control process corresponding to the read display control command.

  As described above, the display control means can receive the display control command transmitted from the main board 31 and can perform the display control process according to the received display control command. Here, the display control means is taken as an example of the electrical component control means. However, when the lamp control means and the sound control means receive a control command from the main board 31, the same as in the case of the display control means. Can be received by control.

  Next, the operation of payout control means (payout control CPU 371 and peripheral circuits such as ROM and RAM), which is another example of the electrical component control means, will be described. FIG. 40 is an explanatory diagram showing assignment of output ports in this embodiment. As shown in FIG. 40, the output port C (address 00H) is an output port for a drive signal or the like output to the payout motor 289. The output port D (address 01H) is an output port for a display control signal output to the error display LED 374 which is a 7 segment LED. The output port E (address 02H) is an output port for outputting a drive signal output to the sorting solenoid 310 and an EXS signal and a PRDY signal for the card unit 50.

  FIG. 41 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 41, the input port A (address 06H) is an input port for taking in an 8-bit payout control signal of the payout control command transmitted from the main board 31. In addition, detection signals of the winning ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 are supplied with a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 detection signal from the card unit 50. When the clear switch 921 is not used in the payout control means, it is not necessary to input the detection signal.

  FIG. 42 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a payout control process is executed.

  Further, another channel (channel 2 in this embodiment) of the built-in CTC is used as an interrupt generation channel for receiving a payout control command from the game control means, and this channel is used in the counter mode. Used in. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to the counter mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set.

  The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on the count-up of the CTC channel 2 (CH2) is an interrupt that occurs when the value of the timer counter register CLK / TRG2 described above becomes “0”. Therefore, for example, in step S705, the initial value “1” is set in the timer counter register CLK / TRG2 as the specific register. Further, the count value of the timer counter register CLK / TRG2 as the specific register is decremented by 1 at the rise or fall of the signal input to the CLK / TRG2 terminal. Decrease selection can be made. In this embodiment, setting is made such that the count value of the timer counter register CLK / TRG2 is -1 at the rising edge of the signal input to the CLK / TRG2 terminal.

  An interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Used as an interrupt. Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, the CH3 register is set to a value corresponding to 2 ms as an initial value.

  Interrupts based on CTC CH2 count-up have a higher priority than interrupts based on CH3 count-up. Therefore, when the count-up occurs simultaneously, the interrupt based on the CH2 count-up, that is, the interrupt that triggers the execution of the command reception interrupt process is given priority.

  Next, the payout control CPU 371 checks the state of the output signal of the clear switch 921 input via the input port B (see FIG. 41) only once (step S707). In the confirmation, when ON is detected, the payout control CPU 371 executes normal initialization processing (steps S711 to S713). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Note that in the input port 372, the ON state of the clear switch signal is at a high level. Further, the payout control means does not have to make the determination in step S707.

  As with the CPU 56 of the main board 31, the payout control CPU 371 also determines that the switch detection signal is on, for example, when the on state is at least 2 ms (the first process of the process activated every 2 ms). If the detection signal is turned on immediately before the detection in (1), the switch is not considered to be turned on unless it is continued. However, when the clear switch 921 is detected to be turned on, on / off is determined by a single on determination. That is, the initialization request detection determination period for the payout control CPU 371 to determine whether or not the clear switch 921 as the initialization operation means is in a predetermined operation state is a prize ball count switch as the game medium detection means or the like Is a period different from the game medium detection determination period for determining that the game medium has been detected.

  If the clear switch 921 is not in the ON state, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S708). For example, as with the processing of the CPU 56 of the main board 31, whether or not backup data exists is confirmed by whether or not the backup flag that is set when power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

  After confirming that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area. If the power supply is restored after a power outage such as an unexpected power failure, the data in the backup RAM area should have been stored, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of stopping the power supply, and therefore the initialization process that is executed at the time of power-on is executed instead of the recovery from an insufficient power failure.

  If the check result is normal (step S709), the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power supply is stopped (step S710). Then, it returns to the address indicated by the PC (program counter) stored in the backup RAM area.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated every 2 ms (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713).

  In this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, a timer interrupt flag indicating that a timer interrupt has occurred is set as shown in FIG. 43 (step S772). If it is detected in the main process that the timer interrupt flag is set (step S714), the timer interrupt flag is reset (step S751), and the payout control process (steps S751 to S760) is executed. The

  In the timer interrupt, as shown in FIG. 43, the interrupt permission state is first set (step S771). Therefore, the interrupt is permitted during the timer interrupt process, and the payout control command receiving process based on the input of the INT signal can be preferentially executed.

  In the payout control process, the payout control CPU 371 first determines whether or not a switch such as the prize ball count switch 301A or the ball lending count switch 301B input to the input port 372b is turned on (switch process: step S752). .

  Next, the payout control CPU 371 sets the payout stop state when the payout stop state designation command is received from the main board 31, and cancels the payout stop state when the payout possible state designation command is received (payout stop state). State setting process: Step S753). Also, the received payout control command is analyzed, and processing according to the analysis result is executed (command analysis execution processing: step S754). Further, a prepaid card unit control process is performed (step S755).

  Next, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756). At this time, the payout control CPU 371 sets the ball sorting member 311 to the ball lending side by the sorting solenoid 310.

  Further, the payout control CPU 371 performs prize ball control processing for paying out the number of prize balls stored in the total number memory (step S757). At this time, the payout control CPU 371 sets the ball sorting member 311 to the prize ball side by the sorting solenoid 310. Then, a drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of rotations is performed. (Step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control them. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing for outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

  Note that the output port C shown in FIG. 40 is accessed in the payout motor control process (step S758) in the payout control process. The output port D is accessed by error processing (step S759) in the payout control processing. The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

  FIG. 43 is an explanatory diagram showing an example of use of the RAM built in the payout control CPU 371. In this example, a total number storage (for example, 2 bytes) and a lending ball number storage are formed in the backup RAM area. The total number storage stores the total number of prize balls paid out instructed from the main board 31 side. The rented ball number storage stores the number of balls that have not been paid out. Note that all RAM areas in which data used in the payout control process are stored may be backed up.

  Then, when the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means, for example, in the prize ball control process (step S757), the content is increased in the total number memory by the indicated number. . In addition, in the ball lending control process (step S756), every time a ball lending request signal is received from the card unit 50, the content is increased in the lending ball number storage by the number of one unit (for example, 25). Further, the payout control CPU 371 reduces the value of the total number memory by 1 when the prize ball count switch 301A detects one prize ball payout in the prize ball control process, and one ball rental count switch 301B in the ball rental control process. When the lending ball payout is detected, the value of the lending ball number storage is reduced by one.

  Therefore, the number of unpaid prize balls and the number of rented balls are stored in a backup RAM area capable of holding the contents for a predetermined period. Therefore, even if an unexpected power supply stop such as a power failure occurs, the award ball processing and the ball lending processing can be resumed based on the stored contents of the backup RAM area if the power supply is restored within a predetermined period. That is, even if the power supply to the gaming machine is stopped, if the power supply is restarted, the payout is performed based on the number of unpaid prize balls and the number of rented balls at the time of the power supply stop, and given to the player The disadvantage can be reduced.

  FIG. 45 is an explanatory diagram showing a configuration example of a reception buffer for storing a payout control command received from the main board 31. In this example, a ring buffer type reception buffer capable of storing six 2-byte payout control commands is used. Therefore, the reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

  Thus, the payout control board 37 is provided with a reception buffer area as a storage area capable of simultaneously storing a plurality of received payout control commands, and the payout control command is stored in the reception command buffer in the reception buffer area. When stored, the command reception number counter corresponding to the storage address is updated. When a payout control command is stored in the last received command buffer in the receive buffer area, the value of the command reception number counter is returned to zero. That is, the storage address is set to point to the start address of the reception buffer area.

  The payout control CPU 371 reads out the payout control command in the reception buffer area based on the read address in the reception buffer area. When one payout control command is read, the read address is updated. That is, it is updated to point to the next received command buffer. For example, when it is detected that a payout control command is stored in the reception buffer area in a payout stop state setting process or a command analysis execution process, which will be described later, the control process indicated by the read payout control command is started. To do. Accordingly, the payout control means reads the payout control command from the specific reception command buffer indicated by the read address in accordance with the order of reception, and starts control processing according to the read payout control command.

  In this embodiment, the payout control command received from the main board 31 is stored as it is in the reception buffer area, but only a part of the received payout control command data is stored in the reception buffer area. Also good. For example, only data indicating the number of payout control commands indicating the number of winning balls may be stored in the reception buffer area.

  FIG. 46 is a flowchart showing a payout control command reception process by an interrupt process. The payout control INT signal from the main board 31 is input to the CLK / TRG2 terminal of the payout control CPU 371. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 46 is started. The payout control CPU 371 is a CPU having a structure such that when an interrupt occurs, a maskable interrupt does not occur unless the interrupt is permitted by software.

  In this embodiment, the initial setting is made such that the value of the timer counter register CLK / TRG2 is set to -1 when the input of the CLK / TRG2 terminal rises. That is, an interrupt is generated at the rise of the INT signal. However, the initial setting may be performed such that the value of the timer counter register CLK / TRG2 is set to -1 when the input of the CLK / TRG2 terminal falls. In other words, initial settings may be made such that an interrupt occurs at the falling edge of the INT signal.

  In other words, if an interrupt is generated at the level change timing (edge) of a pulsed (rectangular wave) INT signal as an acquisition signal, the edge may be a rising edge or a falling edge. Good. In any case, the interrupt is generated at the level change timing (edge) of the pulsed (rectangular wave) INT signal as the capture signal. By doing so, it becomes possible to receive a command promptly at the stage where command fetch is instructed. Since the output of the INT signal is on standby until the period A (FIG. 35) elapses, the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output. Therefore, the payout control means receives the payout control command satisfactorily.

  In the payout control command reception process, the payout control CPU 371 first saves each register in the stack (step S850). Next, data is read from the input port 372a (see FIG. 10) assigned to input of the payout control command data (step S851). Then, it is confirmed whether or not it is the first byte of the 2-byte payout control command (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is “1”. The first bit “1” should be the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 19). Therefore, if the first bit is “1”, the payout control CPU 371 determines that the valid first byte has been received, and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step S31). S853).

  If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not it has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

  If the first byte has already been received, it is confirmed whether or not the first bit of the received 1 byte is “0”. If the first bit is “0”, it is determined that the valid second byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The leading bit “0” should be the EXT byte (second byte) of the payout control command having a 2-byte configuration (see FIG. 19). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends unless the first bit of the data received as the second byte is “0”. If “N” is determined in step S854, the process in step S856 is not performed, so the next received command is stored in the buffer area where the command received this time should have been stored. The

  When the second byte of command data is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether or not the command reception counter is 12 or more (step S857). If it is 12 or more, the command reception number counter is cleared (step S858). Thereafter, the saved register is restored (step S859), and finally, interrupt permission is set (step S859).

  Interrupts are disabled during command reception interrupt processing. As described above, since the interrupt is enabled during the 2 ms timer interrupt processing, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt processing is executed with priority. The Even if a 2 ms timer interrupt occurs during command reception interrupt processing, the interrupt processing is awaited. Thus, in this embodiment, the processing priority of command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during command reception processing, the maximum time required for command reception processing is determined. If the configuration is such that another interrupt process can be executed during the command reception process, it is difficult to estimate the longest time required for the command reception process. Since the longest time required for the command reception process is determined, it is possible to accurately determine how long the period C (see FIG. 20) in the command transmission process of the game control means should be.

  The payout control command has a 2-byte configuration, and the first byte (MODE) and the second byte (EXT) can be immediately distinguished on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

  In this embodiment, in the command reception interrupt process, the received command is controlled to be stored in the reception buffer. However, the payout stop state setting process (see FIG. 48) and the command analysis execution process (FIG. 49) described later are performed. May be executed in the command reception interrupt process. As such, in the case of executing the command reception interrupt process up to the command determination process for determining the command in the reception buffer, the determination of the command is also executed quickly.

  FIG. 47 is a flowchart illustrating an example of the switch process in step S751. In the switch process, the payout control CPU 371 checks whether or not the prize ball count switch 301A indicates the on state (step S751a). If the on state is indicated, the payout control CPU 371 increments the prize ball count switch on counter by 1 (step S751b). The prize ball count switch on counter is a counter for counting the number of times the on state of the prize ball count switch 301A is detected.

  Then, the value of the prize ball count switch-on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. If it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number memory) by −1 (step S751d).

  When it is confirmed in step S751a that the prize ball count switch 301A is not in the on state, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, it is checked whether or not the ball lending count switch 301B indicates the on state (step S751f). If the on state is indicated, the payout control CPU 371 increments the ball lending count switch on counter by 1 (step S751g). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B is turned on.

  Then, the value of the ball lending count switch-on counter is checked (step S751h). If the value is 2, it is determined that one lending ball has been paid out. When it is determined that one lending ball has been paid out, the payout control CPU 371 decrements the lending ball unpaid-out number counter (the number of lending balls stored in the lending ball number storage) (step S751i). ).

  When it is confirmed in step S751f that the ball lending count switch 301B is not in the on state, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

  FIG. 48 is a flowchart showing an example of the payout stop state setting process in step S753. In the payout stop state setting process, the payout control CPU 371 checks whether or not there is a reception command in the reception buffer (step S753a). If there is a reception command in the reception buffer, it is checked whether or not the received payout control command is a payout stop state designation command (step S753b). If it is a payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S753c).

  If it is confirmed in step S753b that the received command is not a payout stop state designation command, it is confirmed whether or not the received payout control command is a payout enable state designation command (step S753d). If it is a payout enable state designation command, the payout stop state is canceled (step S753e).

  When the payout stop state is set, for example, driving of the payout motor 289 is stopped and an internal flag indicating that payout is stopped is set. When releasing the payout stop state, the driving of the payout motor 289 is resumed and an internal flag indicating that payout is stopped is reset.

  When the payout stop state is set, the payout motor 289 may be stopped immediately. However, the payout motor 289 may be stopped at a place where the cut is good instead of being controlled as such. For example, the game balls may be paid out in units of 25, and when the payout of one unit is completed, the payout motor 289 may be stopped and the internal state may be set to the payout stop state. As described above, the ball break switch 187 is installed at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage. Even if detected, at least 25 payouts are possible from that point. Accordingly, there is no problem even if the payout is stopped when one unit of payout is completed. Further, if the payout is stopped in units of one unit, control at the time of restarting payout becomes easy.

  FIG. 49 is a flowchart illustrating an example of the command analysis execution process in step S754. In the command analysis execution process, the payout control CPU 371 checks whether or not there is a reception command in the reception buffer (step S754a). If there is a received command, it is checked whether or not the received payout control command is a payout control command for designating the number of winning balls (step S754b). The payout control CPU 371 determines in step S754b for the received command stored at the address in the receiving buffer pointed to by the read pointer as the command instruction means. Further, after the determination, the value of the read pointer is incremented by one. When the address pointed to by the read pointer exceeds the address of the reception command buffer 12 (see FIG. 45), the value of the read pointer is updated to indicate the reception command buffer 1.

  If the received payout control command is a payout control command for designating the number of winning balls, the number instructed by the payout control command is added to the total number memory (step S754c). That is, the payout control CPU 371 stores the number of prize balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number memory).

  The payout control CPU 371 performs subtraction of the command reception number counter and reception command shift processing in the reception buffer, if necessary. Further, the payout stop state setting process and the command analysis execution process may be repeated until the value of the read pointer matches the latest command storage position in the reception buffer. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is “3”, there are three unprocessed received commands, but the process is repeated until they match. , There are no outstanding received commands. That is, all received commands stored in the reception buffer are read and processed in a single process.

  FIG. 50 is a flowchart showing an example of the prepaid card unit control process in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not a VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Also, the payout control CPU 371 checks whether or not the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CPU 371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S755d).

  If the VL signal is detected to be off 125 times (2 ms × 125 = 250 ms) continuously by the above processing, the ball firing prohibited state is set.

  If the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the discharge control CPU 371 stops outputting the firing control signal (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to enable the drive motor 94 (step S755g). .

  51 and 52 are flowcharts showing an example of the ball lending control process in step S756. In this embodiment, the maximum value of the continuous payout number is set as one unit (for example, 25) of the lending ball, but the maximum value of the continuous payout number may be another number.

  In the ball lending control process, the payout control CPU 371 first confirms whether or not payout is stopped (step S510). If the payout is stopped, the process is terminated. If the payout is not stopped, it is checked whether or not the ball is being paid out (step S511). If the ball is being paid out, the process proceeds to the ball lending process shown in FIG. Whether or not the lending ball is being paid out is determined by the state of a ball lending process flag which will be described later. If the rental ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout, the payout control CPU 371 checks whether or not a ball lending request has been received from the card unit 50 (step S513). If there is a request, the ball lending process flag is turned on (step S514), and 25 (number of ball lending units: here 100 yen) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S518), and the process proceeds to the ball lending process shown in FIG.

  Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized acceptance. The ball lending process flag is set in the backup RAM area.

  FIG. 52 is a flowchart showing a ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch processing in step S751, it is confirmed whether or not a game ball has been paid out based on the detection signal from the ball lending count switch 301B. Is not done.

  In the ball lending control process, the payout control CPU 371 checks whether or not it is during the lending ball passage waiting time (step S519). If it is not during the lending ball passage waiting time, the lending ball is paid out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be finished (whether the payout operation of one unit has been finished) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522) and sets the lending ball passage waiting time (step S523).

  If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 checks whether or not the lending ball passage waiting time has ended (step S524). The rental ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all lending balls of one unit have been paid out, so that the card unit 50 can accept the next lending request. The EXS signal is turned off (step S525). Further, the distribution solenoid is turned off (step S526), and the ball lending process flag is turned off (step S527). If the last payout ball does not pass the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. In this embodiment, the winning ball and the lending are performed by the same payout device.

  After turning off the EXS signal indicating acceptance of a ball lending request, if the BRQ signal, which is a ball lending request signal, is turned on again within a predetermined period, the ball lending process is continued without turning off the sorting solenoid and the dispensing motor. You may make it do. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be executed continuously.

  The contents of the rental ball number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Accordingly, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

  53 and 54 are flowcharts showing an example of the prize ball control process in step S757. In this example, the maximum value of the continuous payout number is the same as the unit of the lending ball (for example, 25), but the maximum value of the continuous payout number may be another number.

  In the prize ball control process, the payout control CPU 371 first checks whether or not payout is stopped (step S530). If the payout is stopped, the process is terminated. If the payout is not stopped, it is confirmed whether or not the rental ball is paying out (step S531). Whether or not the ball lending is being paid out is determined by the state of the ball lending process flag. If the ball is not paid out, it is confirmed whether or not the prize ball is being paid out (step S532). If the prize ball is being paid out, the process proceeds to the processing in the prize ball shown in FIG. Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout is found, the payout control CPU 371 checks whether or not there is a ball lending preparation request from the card unit 50 (step S533). Whether or not there is a ball lending preparation request is determined by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

  If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of winning balls (the number of unpaid winning balls) stored in the total number memory is 0 (step S534). . If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on a prize ball processing flag (step S535), and whether or not the value of the total number memory is 25 or more. Confirmation is made (step S536). The prize ball processing flag is set in the backup RAM area.

  When the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate the payout motor 289 until paying out 25 game balls. In order to output 25, the payout operation of 25 is set (step S537). If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate until all the game balls stored in the total number memory are paid out. In order to output the total number delivery operation (step S538). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is in the off state, the ball distribution member below the ball dispensing device 97 is set to the prize ball side. Then, the process proceeds to a process during payout of prize balls in the prize ball control process shown in FIG.

  FIG. 54 is a flowchart showing an example of a process during a prize ball in the payout control process by the payout control CPU 371. In the winning ball control process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch process of step S751, it is confirmed whether or not a game ball has been paid out based on the detection signal of the prize ball count switch 301A. Therefore, in the prize ball control process, the total number memory is subtracted. Is not done.

  In the processing during the winning ball, the payout control CPU 371 checks whether or not it is during the waiting time for winning ball passing (step S540). If it is not during the waiting time for passing the prize ball, the prize ball is paid out (step S541), and whether or not the driving of the payout motor 289 should be terminated (whether a predetermined number of payout operations of 25 or less than 25 has been completed). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the award ball passage waiting time (step S544). The award ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

  If it is during the winning ball passage waiting time in step S540, the payout control CPU 371 checks whether or not the winning ball passage waiting time has ended (step S545). When the prize ball passing waiting time ends, all the prize balls set in step S537 or step S538 have been paid out. Therefore, the payout control CPU 371 turns off the award ball processing flag if the award ball passage waiting time has ended (step S546). If the last payout ball does not pass the prize ball count switch 301A before the prize ball passage waiting time elapses, a prize ball path error is determined.

  In this embodiment, the ball lending is prioritized over the winning ball processing according to the determinations in steps S511 and S531, but the winning ball processing may be prioritized over the ball lending.

  The contents of the total number storage and the rented ball number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the payout process based on the contents of the total number storage.

  The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but may manage each prize ball number (for example, 15, 10, or 6). Good. For example, a number counter corresponding to each award ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When a prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, a subtraction process is performed in the payout control process). Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored during a predetermined period, the payout control CPU 371 can continue the prize ball payout process based on the contents of each number counter.

  As described above, in this embodiment, the control command transmitted from the game control means to the electrical component control means (in the above example, the display control means, the lamp control means, the sound control means) and the payout control means. The form is the same. That is, there is a 1-bit INT signal, and 8-bit control signals CD0 to CD7 are valid command data. Therefore, it becomes possible to share a program related to the creation and transmission of control commands to the display control means, lamp control means, sound control means and payout control means, and the program capacity of the game control program can be reduced. In addition, the number of commands transmitted from the main board 31 to other boards can be reduced.

  In addition, in the main board 31, output sections (output ports and output buffer circuits) for control commands output to the symbol control board 80, the sound control board 70, the lamp control board 35, and the payout control board 37 are provided separately. ing. Therefore, the game control means can also output a control command for each board in parallel.

  Further, in this embodiment, even when a shortage of game balls to be paid out is detected (when a ball is out), the payout stop is the same command both when the game ball should not be paid out when the lower plate is full. A state designation command is notified from the game control means to the payout control means (see FIG. 28). That is, a common command is transmitted from the game control means to the payout control means even if the conditions for stopping the prize ball payout are different. In other words, even if any winning ball stop condition is satisfied, a common control command instructs the payout control means that the winning ball payout is not possible.

  Furthermore, when a game ball can be paid out, a prize ball can be paid out to the payout control means by a common payout enable state designation command even if the prize ball payout is stopped under any payout stop condition. Command that it has reached the correct state. As a result, there is an advantage that the load related to information transmission from the game control means to the payout control means is reduced, the program capacity in the game control means is reduced, and the program capacity that can be used for game control is increased. In addition, the number of commands transmitted from the main board 31 to the payout control board 37 can be reduced.

  In addition, with regard to ball lending, when a shortage of game balls to be paid out is detected (when the ball is out of play), even when the game ball should not be paid out when the lower plate is full, the payout stop state is the same command. The designated command is notified from the game control means to the payout control means. That is, a common command is transmitted from the game control means to the payout control means even if the conditions for stopping lending are different. In other words, even when any of the ball lending stop conditions is satisfied, the common control command instructs the payout control means that the ball lending is not possible.

  Furthermore, when a game ball can be paid out, it is possible to lend the ball to the payout control means by a common payout enable state designation command even if the ball lending is stopped by any payout stop condition. Order that Accordingly, the load relating to information transmission from the game control means to the payout control means is reduced, and the program capacity in the game control means is reduced and the program capacity that can be used for game control is increased. In addition, the number of commands transmitted from the main board 31 to the payout control board 37 can be reduced.

  In the above embodiment, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are possible according to the payable state designation command. Although the state has been returned to the state, the payout stop instruction for the winning ball and the payout stop instruction for the ball lending may be separate commands, and the payout stop canceling instruction for the prize ball and the payout stop canceling instruction regarding the ball lending may be separate commands. Even in such a case, a common command is sent from the game control means to the payout control means even if the conditions for stopping and releasing the winning ball are different, and common even if the conditions for stopping and releasing the ball rental are different. This command can be sent from the game control means to the payout control means.

  However, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and when the payout available state designation command is received, both the ball lending and the prize ball payout are enabled. That is, the ball lending and the prize ball payout are stopped with one command, and if the stop state is canceled, the payout control means from the game control means as compared with the case where the stop instruction command and the stop release instruction command for each are used. The load related to the transmission of information is further reduced.

  In the above embodiment, the payout means is configured to execute both ball lending and prize ball payout. However, the present invention can be applied even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent. Can be applied. In that case, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent, if the payout control means is configured to control both mechanisms, 1 as in the above embodiment. One command can be configured to instruct stop / release of both ball lending and prize ball payout.

  In this embodiment, the payout control means detects that the INT signal related to the payout control signal has risen, and starts a 1-byte data take-in process by an interrupt process, for example. Since a receiving ring buffer (in this example, a reception buffer) capable of storing a plurality of payout control commands is provided, the next payout control command is received after the payout control command is received and before the control based on the command is started. Even if the command is received, the command is not received by the payout control means.

  Further, as shown in the flowcharts of FIGS. 28 to 30, the game control means is configured to be able to execute the command set process of step S251 even in the payout stop state (step S201). . Accordingly, even when the payout is stopped, a payout control command indicating the number of payouts is transmitted to the payout control means when a winning is detected.

  In the payout control means, the interruption process is started even when the payout is stopped, so that the payout control means can receive the payout control command even when the payout is stopped. While the payout is stopped, payout processing according to the received payout control command is stopped, but since a reception ring buffer capable of storing a plurality of payout control commands is provided, it is transmitted from the game control means. The payout control command does not disappear in the payout control means.

  In the payout control means, a command reception number counter is used as an address indicating means indicating in which area in the reception ring buffer the transmission command is stored. Therefore, it is easy to determine which area should be used.

  In the above embodiment, the RAM is used as the fluctuation data storage means. However, as the fluctuation data storage means, a storage means other than the RAM may be used as long as it is an electrically rewritable storage means. Good.

  Similarly to the RAM in the game control means and the payout control means, the RAM in the sound control means, the lamp control means, and the display control means may have a portion that is backed up.

  In addition, the pachinko gaming machine 1 according to the above-described embodiment mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display unit 9 based on the start winning is a combination of the predetermined symbols. The first type pachinko gaming machine that can be granted to the player, but if there is a winning in a predetermined area of the electric game that is released based on the start winning, the second type that can be given a predetermined gaming value to the player A third type in which a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when a stop symbol of a symbol that is variably displayed based on a start winning prize becomes a combination of a predetermined pattern The present invention may be applied to a pachinko gaming machine or a video game machine.

  Further, the present invention is not limited to pachinko gaming machines in which the game medium is a game ball, and the present invention can be applied to slot machines and the like. For example, in the slot machine, the present invention can be applied when at least an effect control board and a payout control board are provided in addition to the main board.

  FIG. 55 is a front view of the front door of an example of the slot machine as seen from the front. As shown in FIG. 55, in the slot machine 500, a game panel 501 is detachably attached near the center. Further, a variable display area 502 in which a plurality of types of symbols are variably displayed is provided near the center of the game panel 501. On the left side of the variable display area 502, a one-bet lamp 503, a two-bet lamp 504, and a three-bet lamp 505 are provided. On the right side of the variable display area 502, a game over lamp 506, a replay lamp 507, a weight lamp 508, a start lamp 509, and a medal insertion instruction lamp 510 are provided.

  Below the variable display area 502, a 7-segment LED credit display 511, a 7-segment LED game number display 512, and a 7-segment LED payout display 513 are provided. In this embodiment, the variable display area 502 has three symbol display areas of “left”, “middle”, and “right”, and the symbol display reels 514a, 514b, and 514c correspond to the symbol display areas, respectively. Is provided.

  An operation table 520 in which various input switches and the like for the player to perform various operations is provided at the bottom of the game panel 501. On the back side of the operation table 520, a BET switch 521 for betting (betting) coins one by one, a MAXBET switch 522 for betting coins by the maximum number (for example, three) that can bet in one game, A settlement switch 523 and a coin insertion slot 524 are provided. Coins inserted into the coin insertion slot 524 are detected by an inserted coin sensor (not shown). In this example, every time a coin is inserted from the coin insertion slot 524, the numerical value displayed on the credit indicator 511 is increased by one, with the upper limit being 50, for example. Then, each time the BET switch 521 is pressed and one coin is bet, the numerical value displayed on the credit indicator 511 is decreased by one. Further, every time the MAXBET switch 522 is pressed and three coins are bet, the numerical value displayed on the credit display 511 is reduced by three.

  On the front side of the operation table 520, a start switch 525, a left reel stop switch 526a, a middle reel stop switch 526b, a right reel stop switch 526c, and a coin jam elimination switch 527 are provided. Lamps 528a and 528b are provided on the left and right sides of the operation table 520, respectively. A title panel 530 that is detachably attached is provided below the operation table 520. On the title panel 530, the model name of the slot machine is drawn. Below the title panel 530, a speaker 531 for outputting sound effects and the like is provided. In addition, a coin storage tray 532 that stores coins exceeding the quantity that can be stored internally (for example, 50) is provided at the bottom of the title panel 530.

  At the upper part of the game panel 501, a panel 540 that is detachably attached is provided. In the vicinity of the center of the panel 540, an LCD (Liquid Crystal Display) 541 for notifying the player of a game method and a game state is provided. For example, when a winning occurs, an image in which the character performs a predetermined action is displayed on the LCD 541 to notify the player that a winning flag described later is set. On the upper part of the panel 540, lamps 542, 543, and 544 for notifying various information are provided. Two speakers 545a and 545b that emit sound effects are provided on the left and right sides of the panel 540. Further, game effect lamps 550, 551, 552, and 553 are provided around the outside of the game panel 501.

  In such a slot machine, a main board, an effect control board, and a payout control board are provided, and the present invention can be applied to a control command transmitted from the main board.

  As described above, when the prohibition condition is released and none of the prohibition conditions are satisfied, the game control means determines which of the plurality of prohibition conditions is satisfied. Regardless, it may be configured to perform a process of transmitting a common payout permission state designation command indicating permission of payout of game media from the payout means to the payout control means. With such a configuration, a load related to information transmission from the game control means to the payout control means is further reduced.

  It is preferable that the game control means uses a common module to control creation of a command to be transmitted to each electric component control means. Such a configuration simplifies a program related to command creation to the electrical component control means in the game control means, and prevents an increase in program capacity.

  The game control means preferably controls output of a command transmitted to each electric component control means using a common module. With such a configuration, a program relating to command output to the electrical component control means in the game control means is simplified, and an increase in program capacity is prevented.

  When the game control means transmits a command to the electrical component control means, the game control means may be configured to output the command only once so that it can be received. With such a configuration, control for command transmission in the game control means is simplified.

  The form of the command sent from the game control means to the electrical component control means may be shared by at least the same data amount of the command outputted at one time. With such a configuration, it is only necessary to always handle a command having the same data amount when transmitting the command, so that control efficiency can be improved.

  The command includes command data and a capture signal instructing capture of the command data, and the electrical component control means is configured to capture the command data in response to the capture signal output from the game control means. May be. With such a configuration, the electrical component control means that receives a command can reliably receive the command.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is a disassembled perspective view which shows the structural example of a ball dispensing apparatus. It is a block diagram which shows the circuit structure of a game control board (main board). It is a block diagram which shows the signal transmission part of the display control command in a main board | substrate, and the circuit structure in a symbol control board | substrate. It is a block diagram which shows the signal transmission part of the sound control command in a main board | substrate, and the structural example of a sound control board. It is a block diagram which shows the signal transmission / reception part in a main board | substrate and a lamp control board. It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a power supply board. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a normal symbol process process. It is explanatory drawing which shows an example of the command form of a control command. FIG. 5 is a timing chart showing a relationship between an 8-bit control signal (command data) constituting an control command and an INT signal. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows an example of the content of a lamp control command. It is explanatory drawing which shows an example of the content of a sound control command. It is explanatory drawing which shows an example of the content of the payout control command. It is explanatory drawing which shows the example of formation of the switch timer in RAM. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows switch-on check processing. It is explanatory drawing which shows the structural example of an input determination value table. It is explanatory drawing which shows one structural examples, such as a command transmission table. It is a flowchart which shows the process example of a command set process. It is a flowchart which shows a command transmission process routine. It is a flowchart which shows the main process which CPU for display control in a display control means performs. It is a flowchart which shows the 2ms timer interruption process of a display control means. It is explanatory drawing which shows the example of 1 structure of the reception command buffer in a display control means. It is a flowchart which shows the example of the command reception process which CPU for display control performs. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a payout control board performs. It is a flowchart which shows the 2ms timer interruption process of the payout control means. It is explanatory drawing which shows the example of 1 structure of RAM in the payout control means. It is explanatory drawing which shows one structural example of the reception command buffer in the payout control means. It is a flowchart which shows the example of the command reception process which CPU for payout control performs. It is a flowchart which shows the example of a switch process. It is a flowchart which shows the example of a payout stop state setting process. It is a flowchart which shows the example of a command analysis execution process. It is a flowchart which shows the example of a prepaid card unit control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a prize ball control process. It is a flowchart which shows the example of a prize ball control process. It is the front view which looked at the slot machine from the front.

Explanation of symbols

1 Pachinko machine 31 Main board 35 Lamp control board 37 Discharge control board 53 Basic circuit 56 CPU
70 Sound control board 80 Symbol control board 101 Display control CPU
371 CPU for payout control

Claims (2)

A gaming machine in which a player can play a predetermined game,
A game control microcomputer for controlling the progress of the game, having a game control change data storage means for storing change data generated when the control is performed ;
Storage content holding means capable of holding the storage content of the game control variation data storage means for a predetermined period even when power supply to the gaming machine is stopped;
Power supply monitoring means for detecting a voltage drop of a predetermined power supply voltage higher than the voltage supplied to the game medium detection means for detecting a game medium, and outputting a detection signal when the occurrence of power interruption is detected;
An initialization operation means for outputting an operation signal according to the operation,
The game control microcomputer is:
A process for setting a backup flag in the game control variation data storage means in response to the input of the detection signal, and a check data creation process for use in determining whether or not the storage contents of the game control variation data storage means are normal Execute processing for stopping power supply for game control including
When power supply is started, determine whether the operation signal is input from the initialization operation means,
If the operation signal is input from the initialization operation means, the game control variation data storage is performed without determining whether or not the backup flag is set in the game control variation data storage means. Initialize the stored contents of the means,
When it is determined that the operation signal is not input from the initialization operation means, it is determined whether or not the backup flag is set in the game control variation data storage means,
When it is determined that the backup flag is not set in the game control variation data storage means, it is possible to determine whether or not the stored contents of the game control variation data storage means are normal based on the check data. , Initializing the storage contents of the game control variation data storage means,
When it is determined that the backup flag is set in the game control variation data storage means, it is determined whether or not the stored contents of the game control variation data storage means are normal based on the check data. And
When it is determined that the storage content of the game control variation data storage means is not normal, the storage content of the game control variation data storage means is initialized,
On the condition that the storage contents of the game control variation data storage means are determined to be normal, the control state is changed to the game control power based on the storage contents stored in the game control variation data storage means. Execute the game control state return control to restore the state when the supply stop processing was started,
It is determined whether or not the operation signal from the initialization operation means is input in a request detection determination period shorter than a game medium detection determination period in which a signal output from the game medium detection means is determined to be valid. A gaming machine characterized by that. A gaming machine in which a player can play a predetermined game,
A payout control microcomputer for controlling payout of game media, comprising payout control variable data storage means for storing fluctuation data generated when performing control;
Storage content holding means capable of holding the storage content of the payout control variation data storage means for a predetermined period even when power supply to the gaming machine is stopped;
Power supply monitoring means for detecting a voltage drop of a predetermined power supply voltage higher than the voltage supplied to the game medium detection means for detecting a game medium, and outputting a detection signal when the occurrence of power interruption is detected;
An initialization operation means for outputting an operation signal according to the operation,
The dispensing control microcomputer is:
Processing for setting a backup flag in the payout control variation data storage means in response to the input of the detection signal, and creation of check data used for determining whether or not the storage content of the payout control variation data storage means is normal Execute processing at the time of power supply stop for payout control including
When power supply is started, determine whether the operation signal is input from the initialization operation means,
If the operation signal is input from the initialization operation means, the payout control variable data storage is performed without executing the determination as to whether or not the backup flag is set in the payout control variable data storage means. Initialize the stored contents of the means,
When it is determined that the operation signal is not input from the initialization operation means, it is determined whether or not the backup flag is set in the payout control variation data storage means,
When it is determined that the backup flag is not set in the payout control variable data storage means, it is not determined whether or not the storage content of the payout control variable data storage means is normal based on the check data. , Initializing the storage contents of the payout control variation data storage means,
When it is determined that the backup flag is set in the payout control variable data storage means, a determination is made as to whether or not the storage content of the payout control variable data storage means is normal based on the check data. And
When it is determined that the storage content of the payout control variation data storage means is not normal, the storage content of the payout control variation data storage means is initialized,
On the condition that the storage content of the payout control variation data storage means is determined to be normal, the control state is controlled based on the storage content stored in the payout control variation data storage means. Executes state return control for payout control that restores the state when the supply stop process was started,
It is determined whether or not the operation signal from the initialization operation means is input in a request detection determination period shorter than a game medium detection determination period in which a signal output from the game medium detection means is determined to be valid.
A gaming machine characterized by that.

Images