JP4219939B2 - Signal processing circuit in image input device - Google Patents

Description

  The present invention relates to a signal processing circuit in an image input apparatus that converts a signal in units of two-dimensionally arranged pixels that are imaged by an image sensor in an image input apparatus such as a digital still camera.

  Conventionally, image processing such as rotation, mirroring, and color array conversion has been performed on an image captured by a digital camera. At that time, the captured image data is read into a CPU provided therein, and the image processing is performed by software.

  By the way, when the CPU has a 32-bit register and image data expressed in units of 1 byte (8 bits) by one pixel is to be processed by software, the CPU processing unit (32 (Bit) and the unit of pixel (8 bits) do not match. Therefore, after the image data is once decomposed into a plurality of registers in the CPU and rotated, 32-bit data (hereinafter, “ The word data) is reconstructed, ie, an extra 24 bits of dummy bits are added to the 8-bit image data, and then stored in a memory or recording medium. The 32-bit image data thus obtained Are read into the CPU and processed, and after the processing is completed, the image data is stored again by returning to 8-bit data. Therefore, in this process, there are many data conversion processes between word data and 1-byte data, and the processing time is increased.

  The present invention is intended to overcome the above-described problems in the prior art, and provides a signal processing circuit in an image input apparatus capable of performing processing such as image rotation, mirroring, and color array conversion at high speed. Objective.

In order to achieve the above object, the invention of claim 1 is provided with a plurality of storage areas having the same number of bits as unit image signals of predetermined units arranged in a two-dimensional array imaged by an image sensor in an image input device. And the unit image signal is one of a plurality of components forming a predetermined unit color array, and the unit color array has one luminance component and a frequency of arrangement in the horizontal or vertical direction. 2 color components that are 1/2 of the components, and further, the unit image signal array stored in each storage area of the storage means is rotated 90 ° to the right while maintaining the unit color array The storage areas of the storage means are connected to each other so as to be stored in the storage areas of the storage means.

  According to a second aspect of the present invention, in the signal processing circuit of the image input device according to the first aspect, the unit color arrangement is one luminance component and the frequency of arrangement in the horizontal or vertical direction is ½ of the luminance component. And a register group as the storage means, the register group includes first and second registers, and the first and second registers include the luminance component and the 0th to 3rd storage areas for storing each of the two color components are provided, and the unit image signal of the 0th storage area of the first register is sent to the 0th storage area of the second register by a predetermined connection line. The unit image signal of the second storage area of the first register is directly connected to the 0th storage area of the first register by a predetermined connection line, and the second register The unit image signal of the zeroth storage area of the register is directly connected to the second storage area of the second register by a predetermined connection line, and the unit image signal of the first storage area of the second register is connected to the first register by the predetermined connection line Are directly connected to the first storage area of the second register and the first storage area of the second register, the unit image signal of the second storage area of the second register is directly connected to the second storage area of the first register, The unit image signals in the three storage areas are directly connected to the third storage area of the first register and the third storage area of the second register by a predetermined connection line.

Further, the invention of claim 3 includes a storage unit including a plurality of storage areas having the same number of bits as unit image signals of a predetermined unit arranged in a two-dimensional manner imaged by an image sensor in the image input device, and the unit The image signal is one component of a plurality of components forming a predetermined unit color array, and the unit color array has one luminance component and a frequency of arrangement in the horizontal or vertical direction being ½ of the luminance component. The unit image signal array stored in each storage area of the storage unit is rotated 90 ° to the left while maintaining the unit color array, and the storage unit Each storage area of the storage means is connected to each other so as to be stored in each storage area.

  According to a fourth aspect of the present invention, in the signal processing circuit of the image input device according to the third aspect, the unit color arrangement is one luminance component and the frequency of arrangement in the horizontal or vertical direction is 1/2 of the luminance component. And a register group as the storage means, the register group includes first and second registers, and the first and second registers include the luminance component and the Second to third storage areas for storing each of the two color components, wherein the unit image signal of the zeroth storage area of the first register is connected to the second storage area of the first register by a predetermined connection line The unit image signal of the second storage area of the first register is directly connected to the second storage area of the second register by a predetermined connection line, and the second register The unit image signal of the zeroth storage area of the register is directly connected to the zeroth storage area of the first register by a predetermined connection line, and the unit image signal of the first storage area of the second register is connected to the first register by the predetermined connection line. The first storage area and the first storage area of the second register, and the unit image signal of the second storage area of the second register is directly connected to the 0th storage area of the second register by a predetermined connection line, A unit image signal in the third storage area of the second register is directly connected to the third storage area of the first register and the third storage area of the second register by a predetermined connection line.

  According to the first and second aspects of the present invention, the storage unit includes a plurality of storage areas having the same number of bits as the unit image signal that is one of the plurality of components, and is stored in each storage area of the storage means. The storage areas of the storage means are connected to each other so that the arrangement of the unit image signals is rotated 90 ° to the right while maintaining the unit color arrangement and stored in the storage areas of the storage means. Since conversion of the data length of the image signal is unnecessary, the right 90 ° rotation process can be performed at high speed and low power consumption. Further, since the image signal of the storage means is rotated 90 ° to the right and returned to the storage means again, there is no need to provide a plurality of storage means, and an inexpensive circuit can be obtained.

  According to the third and fourth aspects of the present invention, the storage unit includes a plurality of storage areas having the same number of bits as the unit image signal, and the arrangement of the unit image signals stored in each storage area of the storage unit is determined. Since the storage areas of the storage means are connected to each other so that they are rotated 90 ° to the left and stored in the storage areas of the storage means while maintaining the unit color arrangement, the data length of the unit image signal can be converted. Since it is unnecessary, the left 90 ° rotation process can be performed at high speed and low power consumption. Further, since the image signal of the storage means is rotated 90 ° to the left and returned to the storage means again, it is not necessary to provide a plurality of storage means, and an inexpensive circuit can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<1. First Embodiment>
FIG. 1 is a diagram showing a digital still camera according to an embodiment of the present invention. As shown in FIG. 1, the digital still camera captures an image captured by a CCD (imaging device) 21 by an analog signal processing circuit 22 and performs A / D conversion, and performs pixel interpolation, color conversion, and the like on the digitized image. Predetermined general image processing such as edge enhancement processing, filtering and thinning processing is executed at high speed in real time processing (real time processing) by the real time processing unit (RPU) 23, and rotation, mirroring, color array conversion, JPEG compression Exceptional image processing including processing and the like is executed by a CPU (central control unit) 24 and a coprocessor 25 corresponding to the signal processing circuit of the present invention, and then a predetermined processing device (personal computer) through an external interface (I / F) 26. In addition, the image is displayed on the finder through the display drive circuit 27a. It is displayed on the LCD27 as, also adapted to store in the common main memory 29 such as a DRAM or SDRAM. At this time, for the image supply to the finder (LCD 27), after performing predetermined processing such as a slight reduction in resolution in the real-time processing unit 23, the images are displayed one after another by outputting images one after another. However, when an imaging button (not shown) in the operation unit 28 is pressed by the operator, a detailed image in the main memory 29 is stored at once in a recording device (Storage Media) such as the memory card 30. .

  When an image given through the analog signal processing circuit 22 is processed in real time, the pixel arrangement data in the middle is not stored in the main memory 29 but directly processed by the RPU 23, while the real time processing is not performed. According to various image processing commands (including a right rotation command and a left rotation command, which will be described later) through the operator's operation unit 28, the CPU 24 and the CPU 24 perform processing such as rotation, mirroring, color arrangement conversion, and JPEG compression processing. It is applied by the processor 25 and once stored as pixel array data in a CCD data buffer (CCD Data Buffer) (not shown) of the main memory 29, and the pixel array data is again input to the real-time processing unit 23 by direct memory access (DMA). Therefore, processing is performed at high speed. Here, the CPU 24 has a 32-bit register inside, and performs data processing in units of 32 bits (1 word). Among the processing not performed in real time, rotation, reflection, The color array conversion process is not performed by software in the CPU 24, but is performed at high speed and with low power consumption by the coprocessor 25 including circuits dedicated to these processes, which will be described in detail later.

  The real-time processing unit 23, the CPU 24, the external interface 26, and the like are bus-connected to the main bus MB together with the main memory 29, the memory card 30, and the JPEG processing unit 31, and the load on the CPU 24 is reduced when these data are exchanged. Therefore, data is transferred between the elements through the main bus MB based on the control of the direct memory access (DMA) controller 32 without using the CPU 24.

  1, reference numeral 30a denotes an optical mechanism having a lens with an autofocus function, an aperture mechanism, etc., reference numeral 30b denotes a strobe, reference numeral 30c denotes a CCD driving circuit for driving the CCD 21, and reference numeral 30d denotes a real-time processing unit 23 and CCD driving. A timing generator (TG) for regulating the operation timing of the circuit 30c and the like, and reference numeral 30e indicate a PLL transmission circuit.

  Next, the coprocessor 25 which is a main part of the present invention will be described. FIG. 2 is a diagram showing register groups of the coprocessor 25 and connections between the registers in the coprocessor 25 according to the first embodiment. As shown, the coprocessor 25 includes register groups RG1 to RG3 corresponding to the storage means of the present invention. Each register group includes registers corresponding to four storage elements. That is, the register groups RG1 to RG3 include registers R1 to R4, respectively. Further, each of the registers R1 to R4 is a register of 32 bits, that is, one word (4 bytes).

  In this digital camera, the pixel unit image data is a monochrome gradation signal represented by 8 bits (1 byte), and each register has 8 bits (1 byte) in the 0th to 3rd bytes B3. That is, when each bit in the register is referred to as the 0th to 31st bits, the 0th to 7th bits, the 8th to 15th bits, the 16th to 23rd bits, and the 24th to 31st bits are set to 0th, respectively. Called byte B0, first byte B1, second byte B2, and third byte B3, image data (corresponding to the unit image signal of the present invention) is read in each byte. That is, in each register R1 to R4 of each register group RG1 to RG3, the image data of each pixel is stored in an area having the same number of bits as the image data of one pixel as a unit.

  Each register R1 to R4 of each register group RG1 to RG3 is electrically connected directly to the CPU 24 in order to read image data from the CPU 24 or output it to the CPU 24. As a result, the bytes B0 to B3 of the registers R1 to R4 of the register group RG1 to RG3 are indirectly connected to the main memory 29 via the CPU 24.

  The 0th to 3rd bytes B3 of the registers R1 to R4 of the register groups RG1 and RG2 and RG2 and RG3 are electrically connected directly to each other through a predetermined connection line as shown below. That is, the 0th byte B0 of all the registers of the register group RG1 is connected to the 0th byte B0 to the 3rd byte B3 of the register R4 of the register group RG2, and the first byte B1 of all the registers of the register group RG1 is the register group. The 0th byte B0 to the 3rd byte B3 of the register R3 of the RG2 are connected, and the 2nd byte B2 of all the registers of the register group RG1 are connected to the 0th byte B0 to the 3rd byte B3 of the register R2 of the register group RG2. The third byte B3 of all the registers of the register group RG1 is connected to the 0th byte B0 to the third byte B3 of the register R1 of the register group RG2. The 0th byte B0 to the 3rd byte B3 of the register R1 of the register group RG2 are connected to the 3rd byte B3 to the 0th byte B0 of the register R1 of the register group RG3, respectively, and the 0th byte of the register R2 of the register group RG2 B0 to the third byte B3 are connected to the third byte B3 to the 0th byte B0 of the register R2 of the register group RG3, respectively, and the 0th byte B0 to the third byte B3 of the register R3 of the register group RG2 are respectively connected to the register group RG3. The third byte B3 to the 0th byte B0 of the register R3 are connected, and the 0th byte B0 to the third byte B3 of the register R4 of the register group RG2 are respectively changed from the third byte B3 to the 0th byte B0 of the register R4 of the register group RG3. It is connected to the.

  Since each register group is connected in this way, as shown below, by transferring image data between each register group, the image is rotated 90 ° to the right, 90 ° to the left, and horizontally to the image. Image processing such as mirroring in the (horizontal direction) is performed at high speed.

  FIG. 3 is a diagram for explaining the rotation processing by the coprocessor 25 in the first embodiment, and FIGS. 3A to 3C are diagrams showing a state of 90 ° rotation to the right, and FIG. FIG. 3 (f) is a diagram showing a state of 90 ° rotation to the left. First, 4-word image data stored in the main memory 29 as shown in FIG. 3A is read into the register group RG2 via the CPU 24 as shown in FIG. 3B. That is, although not shown, the bytes B0 to B3 of the registers R1 to R4 of the register group RG2 are connected to the main memory via the CPU 24 so that the image data is reflected in the vertical direction (vertical direction). Then, the image data of the register group RG2 is transferred to the register group RG1 as shown in FIG. Comparing FIGS. 3A and 3C, it can be seen that the image of 4 words is rotated 90 ° to the right. When the image data is output from the register group RG1, image data rotated 90 ° to the right is obtained.

  Similarly, 4-word image data stored in the main memory 29 as shown in FIG. 3 (d) is read into the register group RG3 via the CPU 24 as shown in FIG. 3 (e), and is registered via the register group RG2. The data is transferred to the group RG1, and the arrangement is as shown in FIG. Comparing FIGS. 3 (e) and 3 (f), it can be seen that the image of 4 words is rotated 90 ° to the left. When the image data is output from the register group RG1, image data rotated 90 ° to the left is obtained.

  FIG. 4 is a diagram for explaining the mirroring process by the coprocessor 25 in the first embodiment. First, 4-word image data stored in the main memory as shown in FIG. 4A is read into the register group RG3 as shown in FIG. 4B and transferred to the register group RG2 as shown in FIG. 4C. Is done. 4 (a) and 4 (c) are compared, an image of 4 words is mirrored in the horizontal direction about the vertical center line CL (line passing through the first byte B1 and the second byte B2 of each register). You can see that it is reflected. When the image data is output from the register group RG2, an image mirrored in the left-right direction is obtained.

  As can be seen from FIG. 1, one connection line is provided from each byte of each register of each register group. In other words, each byte of one register of one register group is connected to the connection line, thereby corresponding to one register of another register group, and has a one-to-one correspondence. Thereby, transfer of image data between any two register groups of the register groups RG1 to RG3 is reversible. Therefore, transfer from the register group RG2 to the register group RG1, transfer from the register group RG3 to the register group RG2, and transfer from the register group RG3 to the register group RG1 via the register group RG2 are also possible. It can be carried out. As a result, the above-described conversion is reversed, that is, 90 ° to the left by the transfer from the register group RG2 to the register group RG1, and the center line CL as the axis by the transfer from the register group RG2 to the register group RG3. The mirror can be rotated 90 ° right by transfer from register group RG3 to register group RG1 via register group RG2.

  Further, when mirroring in the vertical direction, that is, mirroring with the horizontal straight line in the image between the registers R2 and R3 of each register group RG as the axis of symmetry, it is speedy compared with the case where it is realized by the circuit configuration. Therefore, the CPU 24 is realized by software. Note that such vertical mirroring can be easily realized by electrically connecting two register groups with a predetermined connection line and transferring image data between the register groups.

  Further, in this coprocessor 25, image data having a plurality of components constituting a color grouped in units of pixels is converted into image data obtained by merging image data of a plurality of pixels in units of components. The data can be separated into pixel-unit image data having a plurality of components.

  FIG. 5 is a diagram for explaining how color data is merged and separated according to the first embodiment. The merge and separation of color data for converting the data format between the composite pixel data in which two pixels are represented by 32 bits and the 32-bit image data for each component in the unit color array described later of the composite pixel data are shown. Yes. The composite pixel data handled here is 32-bit color image data representing two pixels as a unit, and has a unit color array that is an array of a plurality of components of a group representing a color, The unit color arrangement is composed of one luminance component (Y component) and two color components in which the arrangement frequency in the horizontal or vertical direction is 1/2 of the luminance component (the number of data is half). In the first embodiment, unit pixel data in a format in which each component is arranged in the horizontal direction is used, and the Y component consisting of 8 bits is 2 pixels as image data representing 2 pixels, and these 2 pixels. The 8-bit Cy component (color difference signal obtained by subtracting the luminance component from the blue component) and the Cb component (color difference signal obtained by subtracting the luminance component from the red component) are combined into 32-bit composite pixel data. Then, such composite pixel data is converted into 32-bit image data that is grouped for each component.

  In the process of merging and separating the components constituting this color, the composite pixel data is stored in the registers R1 to R4 of the register groups RG2 and RG1, respectively. That is, in each register R1 to R4 of each register group RG1 and RG2, the same bit as the image data of one component (in this example, Y, Cb, or Cr component) that is a unit corresponding to the unit image signal of the present invention. Each component data is stored in a number of storage areas (0th to 3rd bytes).

  As shown in FIG. 5A, the image data of each component of Y, Cb, Y, and Cr is read into the registers R1 to R4 of the register group RG2, and transferred to the register group RG1, thereby register R1 of the register group RG1. Image data merged in units of pixels in .about.R4 is generated. Conversely, the image data in units of two pixels having the respective components Y, Cb, Y, and Cr are read into the registers R1 to R4 of the register group RG2, and transferred to the register group RG1, whereby the registers R1 to R4 of the register group RG1. Then, image data separated into Y, Cb, Y, and Cr components for 4 pixels is generated. This indicates that the color data can be merged and separated by using the functions of 90 ° rotation to the right and 90 ° to the left.

  Since the conversion process of the coprocessor 25 is reversible as described above, the color of the image data is configured even when the image data as described above is read into the register group RG1 and transferred to the register group RG2. Separation and merger of the components to be performed can be performed.

  As described above, according to the first embodiment, in the register groups RG1 to RG3, the storage area having the same number of bits (1 byte) as the unit image data, that is, each byte of each register R1 to R4 is stored. Since they are directly connected to each other as described above, the image data is transferred between the register groups RG1 to RG3, rotated 90 ° to the right, rotated 90 ° to the left, mirrored in the horizontal direction with respect to the center line, and color image data. The components can be merged and separated. Therefore, when the CPU 24 performs these processes by software, it is necessary to convert the unit image data from 8 bits to 32 bits, whereas in the first embodiment, the unit image data data. It is not necessary to convert the length, the data length conversion step and the data movement for that are not necessary, and the above processing can be performed at high speed and with low power consumption.

<2. Second Embodiment>
In the second embodiment, the apparatus configuration of the first embodiment shown in FIG. 1 is the same as that of the first embodiment except for the coprocessor 25. The coprocessor 25 receives image data provided from the CPU 24. Is rotated 90 ° to the right. Hereinafter, the structure and processing of the coprocessor 25 will be described.

  FIG. 6 is a diagram showing register groups of the coprocessor 25 and connections between the registers in the coprocessor 25 according to the second embodiment. The coprocessor 25 in the second embodiment includes register groups RG4 and RG5 each including four 32-bit registers similar to the register groups RG1 to RG3 in the first embodiment. However, in the second embodiment, the registers R1 and R2 and the registers R3 and R4 have exactly the same connection relationship in the register groups RG4 and RG5, so only the registers R1 and R2 are representatively illustrated.

  In the second embodiment, composite pixel data (video data) in which two pixels are expressed by 32 bits (for example, each component is 8 bits in a YCbYCr color arrangement) is registered in each register R1 of each register group RG4, RG5. It is to be stored in ~ R4. The composite pixel data handled here is the same as the composite pixel data in the first embodiment. In each of the registers R1 to R4 of each of the register groups RG4 and RG5, the same as one component image data (in the above example, Y, Cb, or Cr component) as a unit corresponding to the unit image signal of the present invention. Each component data is stored in a bit number storage area (0th to 3rd bytes).

  Further, the bytes of the registers R1 and R2 (R3 and R4) of the register groups RG4 and RG5 are electrically connected directly to each other through a predetermined connection line as shown below. That is, the 0th byte B0 of the register R1 of the register group RG4 and the 0th byte B0 of the register R2 of the register group RG5 are the second byte B2 of the register R1 of the register group RG4 and the 0th byte of the register R1 of the register group RG5. B0 is the 0th byte B0 of the register R2 of the register group RG4 and the second byte B2 of the register R2 of the register group RG5 is the first byte B1 of the register R2 of the register group RG4 and the first byte B1 of the register R1 of the register group RG5. 1 byte B1 and 1st byte B1 of register R2 of register group RG5, 2nd byte B2 of register R2 of register group RG4, 2nd byte B2 of register R1 of register group RG5, register R2 of register group RG4 The first A third byte B3 of the register R2 of the third byte B3 and the register group RG5 byte B3 and the register R1 in the register group RG5 are connected respectively.

  FIG. 7 is a diagram for explaining a right rotation process by the coprocessor 25 in the second embodiment. As described above, the registers R1 and R2 and the registers R3 and R4 have the same connection because the rotation of 90 ° to the right with respect to 8 pixels is performed with respect to 2 registers, that is, 4 pixels represented by 16-bit video data. It means that we are going in parallel. Therefore, the rotation in the registers R3 and R4 will be described below as a representative. Note that symbols in each byte of each register in FIG. 7 represent the above-described components (Y, Cb, Y, Cr components), and the numbers after them are 8 pixels (0th to 7th pixels). It represents which of these.

  First, paying attention to only the 0th byte B0 and the 2nd byte B2 in which the Y component is stored in the registers R3 and R4, Y0 to Y3 are rotated by the data transfer from the register group RG4 to RG5. Y0 is moved to the original Y1, Y1 is moved to the original Y3 position, Y2 is moved to the original Y0 position, and Y3 is moved to the original Y2 position. For the Cb component and Cr component, the Cb component must be located in the first byte B1 and the Cr component must be located in the third byte B3 in order not to destroy the arrangement of the Y, Cb, Y, and Cr components. First, Cb0 and Cr1 stored in the first byte B1 and the third byte B3 of the register R4 are copied to the register R3 as they are. From the above, it can be seen that the composite pixel data is rotated 90 ° to the right by this conversion. The same applies to the registers R1 and R2.

  As described above, according to the second embodiment, in the register groups RG4 and RG5, a storage area having the same number of bits (1 byte) as one component data as a unit, that is, each of the registers R1 to R4 Since the bytes are directly connected to each other in the connection relationship as described above, the video data can be rotated 90 ° to the right by transferring the image data between the register groups RG4 and RG5. Compared to the case of processing, it is not necessary to convert the data length of each component data constituting the unit color, the data length conversion step and the data movement for that are unnecessary, and the above processing is performed at high speed and with low power consumption. It can be performed.

<3. Third Embodiment>
Also in the third embodiment, the configuration is the same as that of the first embodiment shown in FIG. 1 except for the coprocessor 25, and the coprocessor 25 has image data supplied from the CPU 24. Is rotated 90 ° to the left. Hereinafter, the structure and processing of the coprocessor 25 will be described.

  FIG. 8 is a diagram showing register groups of the coprocessor 25 and connections between the registers in the coprocessor 25 according to the third embodiment. The coprocessor 25 in the third embodiment includes register groups RG6 and RG7 having the same configuration as the register groups RG4 and RG5 in the second embodiment. Similarly to the second embodiment, the registers R1 and R2 and the registers R3 and R4 have the same connection relationship in the register groups RG6 and RG7, so that only the registers R1 and R2 are representatively illustrated. ing.

  In the third embodiment, composite pixel data (video data) in which 2 pixels are expressed by 32 bits (for example, each component is 8 bits in a YCbYCr color arrangement) is stored in each register R1 of each register group RG6, RG7. It is to be stored in ~ R4. The composite pixel data handled here is the same as the composite pixel data in the first embodiment. In each of the registers R1 to R4 of each of the register groups RG6 and RG7, the same as one component image data (in the above example, Y, Cb, or Cr component) as a unit corresponding to the unit image signal of the present invention. Each component data is stored in a bit number storage area (0th to 3rd bytes).

  In addition, each byte of each register of the register groups RG6 and RG7 is electrically directly connected to each other by a predetermined connection line as shown below. That is, the 0th byte B0 of the register R1 of the register group RG6 and the second byte B2 of the register R1 of the register group RG7 are the second byte B2 of the register R1 of the register group RG6 and the second byte of the register R2 of the register group RG7. B2 is the 0th byte B0 of the register R2 of the register group RG6 and the 0th byte B0 of the register R1 of the register group RG7 is the first byte B1 of the register R2 of the register group RG6 and the first byte B1 of the register R1 of the register group RG7. 1 byte B1 and 1st byte B1 of register R2 of register group RG7, 2nd byte B2 of register R2 of register group RG6, 0th byte B0 of register R2 of register group RG7, register R2 of register group RG6 The first A third byte B3 of the register R2 of the third byte B3 and the register group RG7 byte B3 and the register R1 in the register group RG7 is connected.

  FIG. 9 is a diagram for explaining the left rotation processing by the coprocessor 25 in the third embodiment. In the third embodiment, the same composite pixel data (video data) as in the second embodiment is rotated 90 ° to the left. As in the second embodiment, when attention is paid only to the 0th byte B0 and the 2nd byte B2 in which the Y component is stored in the registers R3 and R4, the data transfer from the register group RG6 to RG7 Obviously, it is rotated 90 ° to the left. The Cb component and the Cr component are the same as in the second embodiment. The same applies to the registers R1 and R2.

  As described above, according to the third embodiment, in the register groups RG6 and RG7, a storage area having the same number of bits (1 byte) as one component data as a unit, that is, each of the registers R1 to R4 Since the bytes are directly connected to each other in the connection relationship as described above, video data can be rotated 90 ° to the left by transferring image data between the register groups RG4 and RG5. Compared with the case where processing is performed, it is not necessary to convert the data length of each component data as a unit, the data length conversion step and the data movement therefor are unnecessary, and the above processing can be performed at high speed and with low power consumption. it can.

<4. Fourth Embodiment>
Also in the fourth embodiment, the configuration is the same as that of the first embodiment shown in FIG. 1 except for the coprocessor 25, and the coprocessor 25 receives image data given from the CPU 24. Is rotated 90 ° right in the same manner as in the second embodiment in accordance with the input of a predetermined right rotation command. Hereinafter, the structure and processing of the coprocessor 25 will be described.

  FIG. 10 is a diagram schematically showing the register group of the coprocessor 25 and the connection relationship between the registers in the coprocessor 25 according to the fourth embodiment. The coprocessor 25 in the fourth embodiment includes a register group RG8 including registers R1 to R4 similar to the register groups RG4 and RG5 in the second embodiment. That is, only one register group is provided. In FIG. 10, two register groups RG8 are originally shown side by side for explanation.

  Also in the fourth embodiment, composite pixel data (video data) in which two pixels are represented by 32 bits (for example, each component is 8 bits in a YCbYCr color arrangement) is stored in each of the registers R1 to R4 of the register group RG8. It is supposed to be. The composite pixel data handled here is the same as the composite pixel data in the first embodiment. In each of the registers R1 to R4, a storage area (0th bit) having the same number of bits as the image data of one component (in the above example, Y, Cb, or Cr component) that is a unit corresponding to the unit image signal of the present invention. Each component data is stored in (.about.3rd byte).

  The bytes of the registers R1 and R2 of the register group RG8 are electrically directly connected to each other by a predetermined connection line (corresponding to the right rotation means of the present invention) as shown below. Similarly to the configuration of, the registers R1 and R2 and the registers R3 and R4 have exactly the same connection relationship. That is, the 0th byte B0 of the register R1 is the 0th byte B0 of the register R2, the 2nd byte B2 of the register R1 is the 0th byte B0 of the register R1, and the 0th byte B0 of the register R2 is the 2nd byte of the register R2. B2, the first byte B1 of the register R2 is the first byte B1 of the register R1 and the first byte B1 of the register R2, the second byte B2 of the register R2 is the second byte B2 of the register R1, and the third byte of the register R2 Byte B3 is connected to the third byte B3 of register R1 and the third byte B3 of register R2.

  Further, the bytes of the registers R1 to R4 of the register group RG8 can be switched between image data input from the CPU 24 and image data input from the register group RG8 by a selector (not shown).

  Since the registers R1 and R2 (as well as R3 and R4) are connected as described above, when image data is read from the CPU 24 and the operator inputs a right rotation command through the operation unit, the signal is sent to the selector. As a result, the input of the register group RG8 is switched to the input of the registers R1 to R4, and the image data is transferred. Specifically, it is transferred as follows. That is, the 0th byte B0 of the register R1 to the 0th byte B0 of the register R2, the 2nd byte B2 of the register R1 to the 0th byte B0 of the register R1, and the 0th byte B0 of the register R2 to the 2nd byte of the register R2. B2, from the first byte B1 of the register R2 to the first byte B1 of the register R1 and the first byte B1 of the register R2, from the second byte B2 of the register R2 to the second byte B2 of the register R1, and from the third byte of the register R2 The data is transferred and stored from the byte B3 to the third byte B3 of the register R1 and the third byte B3 of the register R2.

  FIG. 11 is a diagram for explaining the right rotation process by the coprocessor 25 in the fourth embodiment. As shown in the figure, composite pixel data (video data) in which two pixels are expressed by 32 bits (one unit of Y component, Cb component, Y component, and Cr component) is transferred to the second by transfer between the registers as described above. It can be seen that the data is rotated 90 degrees to the right as in the embodiment. As can be seen from this result, in the fourth embodiment, the composite pixel data rotated 90 ° to the right is returned to the same register group RG8 and stored.

  As described above, according to the fourth embodiment, in the register group RG8, a storage area having the same number of bits (1 byte) as one component data as a unit, that is, each byte of each register R1 to R4 is stored. Since they are directly connected to each other as described above, in response to the input of the right rotation command, the video data is rotated 90 ° to the right by transfer between each byte in each register R1, R2 or R3, R4. Compared with the case where the CPU 24 performs these processes by software, it is not necessary to convert the data length of each component data as a unit, and the data length conversion step and the data movement therefor are not necessary. The above processing can be performed at high speed and with low power consumption.

<5. Fifth embodiment>
In the fifth embodiment as well, the configuration of the apparatus of the first embodiment shown in FIG. 1 is the same as that of the first embodiment except for the coprocessor 25, and the coprocessor 25 has image data provided from the CPU 24. Is rotated 90 ° to the left in the same manner as in the third embodiment in accordance with the input of a predetermined left rotation command. Hereinafter, the structure and processing of the coprocessor 25 will be described.

  FIG. 12 is a diagram schematically illustrating the register group of the coprocessor 25 and the connection relationship between the registers in the coprocessor 25 according to the fifth embodiment. The coprocessor 25 in the fifth embodiment includes only one register group RG9 including registers R1 to R4 similar to the register group RG8 in the fourth embodiment. In FIG. 12, two register groups RG9 are originally shown side by side for explanation.

  Also in the fifth embodiment, composite pixel data (video data) in which two pixels are represented by 32 bits (for example, each component is 8 bits in a YCbYCr color arrangement) is stored in each of the registers R1 to R4 of the register group RG9. It is supposed to be. The composite pixel data handled here is the same as the composite pixel data in the first embodiment. In each of the registers R1 to R4, a storage area (0th bit) having the same number of bits as the image data of one component (in the above example, Y, Cb, or Cr component) that is a unit corresponding to the unit image signal of the present invention. Each component data is stored in (.about.3rd byte).

  The bytes of the registers R1 and R2 of the register group RG9 are electrically connected directly to each other through a predetermined connection line (corresponding to the right rotation means of the present invention) as shown below. Similarly to the configuration of, the registers R1 and R2 and the registers R3 and R4 have exactly the same connection relationship. That is, the 0th byte B0 of the register R1 is the second byte B2 of the register R1, the second byte B2 of the register R1 is the second byte B2 of the register R2, and the 0th byte B0 of the register R2 is the 0th byte of the register R1. In B0, the first byte B1 of the register R2 is the first byte B1 of the register R1 and the first byte B1 of the register R2, the second byte B2 of the register R2 is the 0th byte B0 of the register R2, and the third byte of the register R2 Byte B3 is connected to the third byte B3 of register R1 and the third byte B3 of register R2. Further, although not shown, a selector similar to that of the fourth embodiment is provided.

  Since the registers R1 and R2 (as well as R3 and R4) are connected as described above, when image data is read from the CPU 24 and an operator inputs a left rotation command through the operation switch, the signal is As a result, the input of the register group RG9 is switched to the input of the registers R1 to R4, and the image data is transferred. Specifically, it is transferred as follows. That is, the 0th byte B0 of the register R1 to the 2nd byte B2 of the register R1, the 2nd byte B2 of the register R1 to the 2nd byte B2 of the register R2, and the 0th byte B0 of the register R2 to the 0th byte of the register R1. B0, the first byte B1 of the register R2, the first byte B1 of the register R1 and the first byte B1 of the register R2, the second byte B2 of the register R2 to the 0th byte B0 of the register R2, the third of the register R2 The data is transferred and stored from the byte B3 to the third byte B3 of the register R1 and the third byte B3 of the register R2.

  FIG. 13 is a diagram for explaining the left rotation processing by the coprocessor 25 in the fifth embodiment. As shown in the figure, it can be seen that the composite pixel data (video data) is stored by being rotated 90 ° to the left by the transfer between the registers as described above, as in the third embodiment. Further, as can be seen from this result, in the fifth embodiment, the composite pixel data rotated 90 ° to the left is returned to and stored in the same register group RG9.

  As described above, according to the fifth embodiment, in the register group RG9, a storage area having the same number of bits (1 byte) as one component data as a unit, that is, each byte of each register R1 to R4 is stored. Since they are directly connected to each other as described above, in response to the input of the left rotation command, the video data is rotated 90 ° to the left by transfer between the bytes in each register R1, R2 or R3, R4. Compared with the case where the CPU 24 performs these processes by software, it is not necessary to convert the data length of each component data as a unit, and the data length conversion step and the data movement therefor are not necessary. The above processing can be performed at high speed and with low power consumption.

<6. Sixth Embodiment>
Also in the sixth embodiment, the apparatus configuration of the first embodiment shown in FIG. 1 is the same as that of the first embodiment except for the coprocessor 25. The coprocessor 25 has image data provided from the CPU 24. Is rotated 90 degrees right in the same manner as in the third embodiment in accordance with the input of a predetermined right rotation command. Hereinafter, the structure and processing of the coprocessor 25 will be described.

  FIG. 14 is a diagram showing registers of the coprocessor 25 and connections between the registers in the sixth embodiment. The coprocessor 25 in the sixth embodiment includes 32-bit registers R1 and R2 similar to the registers in the first to fifth embodiments.

  Also in the sixth embodiment, composite pixel data (video data) in which two pixels are expressed by 32 bits (for example, each component is 8 bits in a color arrangement of YCrYCb or YYCrCb) is stored in each register R1 and R2. It has become. The composite pixel data handled here is the same as the composite pixel data in the first embodiment. In each of the registers R1 and R2, a storage area (0th bit) having the same number of bits as the image data of one component (in the above example, Y, Cb, or Cr component) that is a unit corresponding to the unit image signal of the present invention. Each component data is stored in (.about.3rd byte).

  The bytes of the registers R1 and R2 are electrically connected directly to each other through a predetermined connection line as shown below. That is, the 0th byte B0 of the register R1 and the 0th byte B0 of the register R2, the 1st byte B1 of the register R1 and the 2nd byte B2 of the register R2, the 2nd byte B2 of the register R1 and the 2nd byte of the register R2 One byte B1 is connected to the third byte B3 of the register R1 and the third byte B3 of the register R2.

  With such a configuration, the coprocessor 25 converts the composite pixel data of the first color arrangement in which two pixels are represented by 32 bits into the composite pixel data of the second color arrangement in which two pixels are represented by 32 bits. can do. For example, composite pixel data (video data) in a format represented by YYCrCb as the first color array can be converted into composite pixel data (video data) in a format represented by YCrYCb as the second color array. Can be easily understood from FIG.

  In FIG. 14, since the bytes of the registers R1 and R2 are connected in a one-to-one correspondence, the above color array conversion is reversible. In the above video data example, the composite color pixel data in the YCrYCb format that is the second color array is input to the register R2 and transferred to the register R1, so that the register R1 has the YYCrCb format that is the first color array. It can be extracted as composite pixel data.

  As described above, according to the sixth embodiment, in the registers R1 and R2, a storage area having the same number of bits (1 byte) as that of one component data as a unit, that is, each byte of each register R1 and R2 Are directly connected to each other in the connection relationship as described above, so that the color arrangement format of the video data can be converted by transfer between each byte of both registers R1 and R2, so that the CPU 24 can perform the conversion by software. Compared with the case where processing is performed, it is not necessary to convert the data length of each component data as a unit, the data length conversion step and the data movement therefor are unnecessary, and the above processing can be performed at high speed and with low power consumption. it can.

<7. Modification>
In the first to sixth embodiments, examples of the coprocessor in the digital still camera and image processing using the coprocessor have been described. However, the present invention is not limited to this.

  For example, in the first to sixth embodiments, the digital camera is shown as the image input device. However, other image input devices such as a digital video camera are the same as those in the first to sixth embodiments. A coprocessor can be used as a signal processing circuit.

  In the first to sixth embodiments, the storage means in the present invention is a register or a register group. However, the present invention can also be used for other storage media such as a memory such as SRAM and DRAM.

  In the first to sixth embodiments, the data length of image data in units of 8 bits is used and each register in the coprocessor 25 is a 32-bit register. For example, an image in units of 16 bits is used. The data length of the data is processed by a 16-bit register in the coprocessor 25, and an integer multiple of 2 or more of the data length of the image data as a unit may be used as the processing unit of the register.

  Furthermore, in the sixth embodiment, the color array is converted by transferring the composite pixel data between the registers R1 and R2. However, after the conversion as in the fourth and fifth embodiments, The composite pixel data may be stored in the same register. That is, in the register R1, the 0th byte B0 and the 0th byte B0, the 1st byte B1 and the 2nd byte B2, the 2nd byte B2 and the 1st byte B1, the 3rd byte B3 and the 3rd byte B3 Are connected to each other and further include a selector for switching between input of image data from the CPU 24 and transfer in the register R1. Thereby, the capacity of the register can be reduced.

It is a figure which shows the digital still camera which concerns on one embodiment of this invention. It is a figure which shows the register group of the coprocessor in 1st Embodiment, and the connection between the registers in them. It is a figure for demonstrating the rotation process by the coprocessor in 1st Embodiment. It is a figure for demonstrating the mirroring process by the coprocessor in 1st Embodiment. It is a figure for demonstrating the mode of merge of color data by 1st Embodiment, and isolation | separation. It is a figure which shows the register group of the coprocessor in 2nd Embodiment, and the connection between the registers in them. It is a figure for demonstrating the right rotation process by the coprocessor in 2nd Embodiment. It is a figure which shows the register group of the coprocessor in 3rd Embodiment, and the connection between the registers in them. It is a figure for demonstrating the left rotation process by the coprocessor in 3rd Embodiment. It is a figure which shows typically the connection relationship between the register group of the coprocessor in 4th Embodiment, and those registers. It is a figure for demonstrating the right rotation process by the coprocessor in 4th Embodiment. It is a figure which shows typically the connection relation between the register group of the coprocessor in 5th Embodiment, and those registers. It is a figure for demonstrating the left rotation process by the coprocessor in 5th Embodiment. It is a figure which shows the register of the coprocessor in 6th Embodiment, and the connection between those registers.

Explanation of symbols

24 CPU
25 coprocessor (signal processing circuit)
29 Main memory B0 to B3 0th to 3rd bytes (storage area)
R1-R4 registers (first and second storage means)
RG1 to RG9 register groups (storage means, first to third storage means)

Claims (4)

A storage unit including a plurality of storage areas having the same number of bits as unit image signals of a predetermined unit that are two-dimensionally arrayed imaged by the image sensor in the image input device;
The unit image signal is one component of a plurality of components forming a predetermined unit color array, and the unit color array has one luminance component and a frequency of arrangement in the horizontal or vertical direction that is 1 / of the luminance component. 2 color components that are two , and
The unit image signals stored in each storage area of the storage unit are rotated 90 ° to the right while maintaining the unit color array and stored in each storage area of the storage unit. A signal processing circuit in an image input device, wherein storage areas are connected to each other. 2. The signal processing circuit according to claim 1, wherein the unit color array includes one luminance component and two color components whose arrangement frequency in the horizontal or vertical direction is ½ of the luminance component. Is,
A register group is provided as the storage means, and the register group includes first and second registers, and the first and second registers store the luminance component and the two color components, respectively. Each with three storage areas,
A unit image signal in the 0th storage area of the first register is directly connected to the 0th storage area of the second register by a predetermined connection line;
The unit image signal in the second storage area of the first register is directly connected to the 0th storage area of the first register by a predetermined connection line,
A unit image signal in the 0th storage area of the second register is directly connected to the second storage area of the second register by a predetermined connection line;
A unit image signal in the first storage area of the second register is directly connected to the first storage area of the first register and the first storage area of the second register by a predetermined connection line;
The unit image signal of the second storage area of the second register is directly connected to the second storage area of the first register;
Image input characterized in that unit image signals in the third storage area of the second register are directly connected to the third storage area of the first register and the third storage area of the second register by a predetermined connection line A signal processing circuit in the apparatus. A storage unit including a plurality of storage areas having the same number of bits as unit image signals of a predetermined unit that are two-dimensionally arrayed imaged by the image sensor in the image input device;
The unit image signal is one component of a plurality of components forming a predetermined unit color array, and the unit color array has one luminance component and a frequency of arrangement in the horizontal or vertical direction that is 1 / of the luminance component. 2 color components that are two , and
Each of the storage means is arranged such that the arrangement of unit image signals stored in each storage area of the storage means is rotated 90 ° to the left while the unit color arrangement is maintained and stored in each storage area of the storage means. A signal processing circuit in an image input device, wherein storage areas are connected to each other. 4. The signal processing circuit according to claim 3, wherein the unit color array includes one luminance component and two color components whose arrangement frequency in the horizontal or vertical direction is ½ of the luminance component. Is,
A register group is provided as the storage means, and the register group includes first and second registers, and the first and second registers store the luminance component and the two color components, respectively. Each with three storage areas,
The unit image signal in the 0th storage area of the first register is directly connected to the second storage area of the first register by a predetermined connection line,
A unit image signal in the second storage area of the first register is directly connected to the second storage area of the second register by a predetermined connection line;
The unit image signal of the 0th storage area of the second register is directly connected to the 0th storage area of the first register by a predetermined connection line,
A unit image signal in the first storage area of the second register is directly connected to the first storage area of the first register and the first storage area of the second register by a predetermined connection line;
The unit image signal in the second storage area of the second register is directly connected to the 0th storage area of the second register by a predetermined connection line,
Image input characterized in that unit image signals in the third storage area of the second register are directly connected to the third storage area of the first register and the third storage area of the second register by a predetermined connection line A signal processing circuit in the apparatus.

Images