JP4217593B2 - Display device - Google Patents

Description

  The present invention relates to a display device having a dot matrix display element in which display pixels are arranged in a predetermined cycle, such as a liquid crystal display device, a plasma display, an electrochromic element, a field emission display, and a digital micromirror device.

  FIG. 29 is a diagram illustrating an example in which an input image signal corresponds to the luminance (display state) of a display pixel in an image device in which a number of display pixels whose luminance can be controlled by an input control signal are arranged in a matrix. It is. In FIG. 29, R1, G1, and B1 indicate arbitrary portions of display pixels in the display device. SR, SG, and SB are video signals input to the liquid crystal display device, and are signals applied to red, green, and blue display pixels, respectively. Each color display pixel of red, green, and blue is called a dot, and red, green, and blue may be called a pixel (pixel) as a set. Here, each color display pixel is one pixel (pixel). And

  Conventionally, when a display pixel R1 is obtained with a signal value r1, a display pixel G1 with a signal value g1, and a display pixel B1 with a signal value b1, the signal value is obtained at a sampling period 3T from the video signal and displayed. Signal distortion is conspicuous. In order to prevent this luminance signal aliasing, the display pixel R1 has a signal value r1 at time t1, the display pixel G1 has a signal value g2 at time t2, and the display pixel B1 has a signal value b3 at time t3. In addition, a method is used in which display is performed by sampling each video signal with a period T. That is, the sampling is performed by matching the horizontal position of the display pixel with the horizontal position of the image.

  When this display method is used, the influence of aliasing distortion of the luminance signal is reduced, but color moiré occurs on the display screen due to a change of the period T or less included in the input video signal. In order to eliminate this, a technique of applying a low pass filter to the input video signal is used.

  However, in the above method, if a low-pass filter is applied to the video signal for the purpose of removing color moire, the signal near the sampling period included in the original video signal is removed by the filter. There is a problem that the resolution is lowered.

  A block diagram of the liquid crystal display device is shown in FIG. In FIG. 30, 401 is an input terminal for a video signal, 402 is a signal processing circuit, 403 is a sync separation circuit, 404 is a controller, 405 is an X driver, 406 is a Y driver, and 407 is an XY matrix type liquid crystal display (hereinafter referred to as LCD). ). The video signal input from the input terminal 401 is subjected to predetermined processing such as γ correction and inversion processing by the signal processing circuit 402 so that it can be displayed on the LCD 407, input to the X driver 405 and simultaneously input to the synchronization separation circuit 403. The synchronization signal is separated, and the separated synchronization signal is input to the controller 404. Based on this, the controller 404 supplies a predetermined drive pulse for driving the LCD 407 synchronized with the video signal to the X driver 405 and the Y driver 406. The LCD 407 displays the video signal and drive pulse supplied from the X driver 405 and the input video signal driven by the drive pulse supplied from the Y driver 406.

  FIG. 31 shows a configuration diagram of the LCD 407 in FIG. In FIG. 31, 461 is a switching element made of FET, 462 is a liquid crystal cell, 463 is a holding capacitor for holding signal charges, 464R, 464G, 464B are primary colors (R, G, B) supplied from the X driver 405. Signal input terminals, 465R, 465G, and 465B are switching elements made of FETs, 466 is a common electrode of the liquid crystal cell 462, 467R, 467G, and 467B are input terminals for drive pulses supplied from the X driver 405, and 468 is a Y driver 406. This is an input terminal for a drive pulse supplied from.

  The LCD of FIG. 31 has an array of pixels of each color corresponding to the array of R, G, B striped color filters as shown in FIG.

  33A is a configuration diagram of the X driver 405 in FIG. 30, and FIG. 33B is a configuration diagram of the Y driver 406. As shown in FIG. 33, the X driver 405 and the Y driver 406 are shift registers. In FIG. 33, 421 is an input terminal for a start pulse of a shift register, 422 is an input terminal for a drive pulse of a shift register, 423 is a D flip-flop, 424 is an output terminal of an LCD drive pulse output from an X driver, and 431 is a shift. A register start pulse input terminal, 432 is a shift register drive pulse input terminal, 433 is a D flip-flop, and 434 is an LCD drive pulse output terminal output from a Y driver.

  The operation of the conventional LCD will be described with reference to FIGS. When a start pulse is input from the input terminal 421 at the beginning of the horizontal scanning period and a clock of m / 3 times the horizontal frequency (m is the number of pixels in the horizontal direction of the liquid crystal display device) is input from the input terminal 422, this driving is performed. The m / 3-stage shift register of FIG. 33A is driven by the pulse, and an output pulse of this shift register is output to the output terminal 424. At this time, one output terminal 424 is commonly connected to three input terminals 467R, 467G, and 467B, and the same drive pulse output from the X driver 405 is simultaneously applied to the gates of the three switching elements 465R, 465G, and 465B. The video signals input from the input terminals 464R, 464G, and 464B are simultaneously sampled and supplied to the vertical signal line by turning on the switches and turning on the switches simultaneously. One end of the switching element 461 is connected to the vertical signal line, and the other end is connected to the liquid crystal cell 462 and the storage capacitor 463. Accordingly, signals are simultaneously written for each of the three vertical scanning lines, and scanning is performed in the horizontal direction by sequentially outputting drive pulses from the shift register of the X driver 405. Further, when a start pulse is input from the input terminal 431 at the beginning of the vertical scanning period and a clock having a horizontal frequency is input from the input terminal 432, the n pulses (n is a liquid crystal display device) of FIG. (The number of vertical pixels) is driven, and an output pulse of this shift register is output to the output terminal 434. The output terminal 434 is connected to the input terminal 468, and the drive pulse output from the Y driver 406 is supplied to the gate of the switching element 461 through a predetermined horizontal gate line, and each switch is turned on, whereby the liquid crystal cell 462 is turned on. The storage capacitor 463 holds electric charge corresponding to the potential difference between the signal supplied to the input terminals 464R, 464G, and 464B and the voltage supplied to the common electrode 466. At this time, a predetermined voltage is supplied to the common electrode 466. By repeating this operation, an image for one screen can be displayed on the LCD of FIG.

  However, when the number of pixels of the LCD is sufficient, it is possible to obtain a sufficient resolution with the configuration as in the conventional example. For example, in a small LCD having a diagonal of 10 cm or less, a large LCD having a diagonal of 20 cm or more is used. If the number of pixels is increased, the area per pixel becomes smaller, the aperture ratio becomes smaller, and sufficient brightness cannot be obtained, so that the number of pixels cannot be increased too much. Therefore, in order to obtain an apparent resolution with an LCD with a small number of pixels, an X driver as shown in FIG. 34 is used instead of the X driver in FIG. In the figure, the same reference numerals as those in FIG. 33 denote the same components as those in FIG. The X driver shown in FIG. 34 is an m-stage shift register. When a start pulse is input from the input terminal 421 at the beginning of the horizontal scanning period and a clock of m times the horizontal frequency is input from the input terminal 422, The m-stage shift register in FIG. 34 is driven by the drive pulse, and the output pulse of this shift register is output to the output terminal 424. One output terminal 424 is separately connected to three input terminals 467R, 467G, and 467B, and drive pulses output from the X driver are sequentially applied to the gates of the switching elements 465R, 465G, and 465B. When the switches are sequentially turned on, the video signals input from the input terminals 464R, 464G, and 464B are sampled at different timings and supplied to the vertical signal lines. The operation relating to the scanning in the vertical direction is the same as that of the conventional example, and thus an image for one screen is displayed on the LCD of FIG. By doing so, the resolution is enhanced by the LCD having a small number of pixels by increasing the sampling frequency of the video signal in the horizontal direction.

  However, in the conventional example shown in FIG. 33, since the three pixels R, G, and B are sampled at the same phase, a sufficient resolution cannot be obtained when the number of pixels of the LCD is not sufficient. In order to further improve the problem, if the three pixels R, G, and B are sampled at different phases as shown in the example of FIG. 34, when displaying a fine image, particularly characters, etc. In addition, there is a problem that aliasing distortion or color moire caused by sampling becomes conspicuous.

  An object of the present invention is to provide a display device capable of displaying both character information and non-character information with good image quality even when an inexpensive display element having a relatively small number of images is used.

In order to achieve the above object, a display device according to the present invention is a display device that displays red, green, and blue pixels arranged in a matrix by sampling an input video signal at a predetermined cycle. First to third red signal values (rn1, rn2, and rn3) and first to third green signal values (gn1, gn2, and gn3) are sampled in time series from red, green, and blue signals in the signal. , And sampling means for obtaining first to third blue signal values (bn1, bn2 and bn3), and selection means for selecting three signal values from these signal values, wherein the selection means comprises the first and second The difference | rn1-rn2 | between the red signal values rn1 and rn2 is compared with the threshold value Th, and when | rn1-rn2 |> Th is satisfied, or the second and third red signal values n2 and the difference between rn3 | rn2-rn3 |, said compared with a threshold value Th | that when> Th is satisfied, in which selectively switches the signal value the selected | RN2-RN3 Features.

Furthermore, in a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, the red, green, and blue signals in the input video signals are time-sequentially displayed. To the first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, sampling means for obtaining bn2 and bn3), and a selection means for selecting three signal values from these signal values, the selection means comprising a difference | gn1-gn2 | between the first and second green signal values gn1 and gn2 Is compared with the threshold value Th, and when | gn1-gn2 |> Th holds, or the difference | gn2-gn3 | between the second and third green signal values gn2 and gn3 is Serial comparison with the threshold value Th, | gn2-gn3 |> When Th is satisfied, and characterized in that the selectively switching the signal value the selected.

Furthermore, in a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, the red, green, and blue signals in the input video signals are time-sequentially displayed. To the first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, sampling means for obtaining bn2 and bn3), and a selection means for selecting three signal values from these signal values. The selection means obtains the difference | bn1-bn2 | between the first and second green signal values bn1 and bn2. When | bn1−bn2 |> Th holds, or the difference | bn2−bn3 | between the second and third green signal values bn2 and bn3 is compared with the threshold Th. Serial comparison with the threshold value Th, | bn2-bn3 |> When Th is satisfied, and characterized in that the selectively switching the signal value the selected.

Furthermore, in a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, the red, green, and blue signals in the input video signals are time-sequentially displayed. To the first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, sampling means for obtaining bn2 and bn3), and a selection means for selecting three signal values from these signal values, wherein the selection means is a difference between the first red signal value rn1 and the second green signal value gn2. rn1−gn2 | is compared with the threshold value Th, and when | rn1−gn2 |> Th is satisfied, or the difference | gn between the second green signal value gn2 and the third blue signal bn3 -Bn3 | is compared with the threshold value Th, | gn2-bn3 |> When Th is satisfied, and characterized in that the selectively switching the signal value the selected.

  ADVANTAGE OF THE INVENTION According to this invention, in the display apparatus which displays the input image containing character information, while reducing the color moire of an input video signal, it can display using the information of an input video signal effectively. That is, it is possible to enhance the sense of resolution in the area where the image is displayed and to prevent aliasing distortion when displaying characters.

A preferred embodiment of the present invention will be described. The specific configuration will be described in detail with reference to FIGS. 1 to 28, but before that, the basic configuration will be described.
FIG. 35 shows the sampling timing in the display device of the present invention. In the present invention, in a mode for displaying character information such as alphabets, Greek letters, Roman numerals, numbers, kana characters, and kanji, the color signal r1 at the phase t1 is the red pixel R1, and the color signal g1 is the green pixel G1. In addition, the color signal b1 is supplied to the pixel B1. Similarly, the color signals r4, g4, and b4 at the phase t4 are supplied to the color pixels R2, G2, and B2, respectively.

  On the other hand, for example, in the case of another mode for displaying non-character information such as a landscape and a human image captured by a video camera, the signal r1 at the phase t1 is the pixel R1, the signal g2 at the phase t2 is the pixel G1, The signal b3 at the phase t3 is supplied to the pixel B1. Similarly, in each phase t4, t5, t6, signals r4, g5, b6 are supplied to the pixels R2, G2, B2, respectively.

Of course, each color signal may be supplied to the pixel as it is, or may be amplified or shaped into a signal having a different waveform and then supplied to the pixel. Which is selected is appropriately determined according to the characteristics of the display element, the configuration of the XY driver, and the like.
FIG. 36 is a block diagram showing a configuration in which character information is detected and the above-described two modes are switched according to the detection result in the display device of the present invention. A detection circuit detects the presence / absence of character information, and a distribution method of the sampled color signal to pixels is determined according to the result. The mode switching timing may be after the end of one frame, but is preferably after the end of one horizontal scanning period.
In this way, video information in which characters are written in a landscape image can be appropriately displayed, which is suitable as a multimedia compatible device.

Hereinafter, the present invention will be described with reference to examples and reference examples.
[Example 1]
FIG. 9 is a block diagram showing the configuration of the display device according to the first embodiment of the present invention, and FIG. 10 is a block diagram showing a liquid crystal display panel portion connected to the device of FIG. In FIG. 9, 301R, 301G and 301B are input video terminals to which video signals SR, SG and SB for controlling the luminance of display pixels of red, green and blue, respectively, 302A, 302B and 302C are input video signals SR, This is an A / D converter that samples and holds SG and SB and converts them into digital signal values. Each output signal value is held until the next signal is input. Sampling is performed in synchronization with a signal φ1 supplied from a timing generator (described later). Reference numerals 303A, 303B, and 303C denote shift registers that sequentially store three output signal values of the A / D converters 302A, 302B, and 302C at predetermined time intervals and output them simultaneously from the three output terminals. Sampling values of the input video signal sampled at different times from this output terminal can be obtained. The shift operation is performed in synchronization with the signal φ2 supplied from the timing generator. 304A, 304B, 304C, 304D, and 304E are flip-flops that hold an input signal in synchronization with the signal φ3 supplied from the timing generator, 305A and 305B are memories that store a predetermined signal value L0, and 306A and 306B are memories 305A , 305B and flip-flops 304B, 304C are compared in magnitude, and the comparison result is a comparator that outputs a signal of “1” or “0”. 307A, 307B are flip-flops 304B and 304C, and 304C and 304D. Differentiators that calculate and output an absolute difference of input signals, 308A and 308B are memories that store a predetermined signal value D0, 309A and 309B are magnitudes of signal values output from the memories 308A and 308B and the differentiators 307A and 307B Compare comparator 310A, 310B calculates the logical product of the signal values output from the comparators 306A and 309A, and 306B and 309B, and outputs a logical product operator 311A, 311B, whichever of the two input signals depends on the given control signal. A signal switcher that selects and outputs one, 312A, 312B and 312C are flip-flops that hold an input signal in synchronization with the signal φ4 supplied from the timing generator, 313 is a clock generator that supplies a signal to the timing generator, A timing generator 314 generates a timing clock to be sent to each part of the apparatus from a signal supplied from the clock generator 313. A timing generator 315 outputs 1 from three input signals a, b, and c by a control signal supplied from the timing generator 314. A signal switching device which selects and outputs. Input a is selected at the rise of the waveform of the control signal φ5, input b is selected at the rise of the waveform of the control signal φ6, and input c is selected and output at the rise of the waveform of the control signal φ7. FIG. 11 shows the waveforms of the control signals φ5, φ6, and φ7. Reference numeral 316 denotes a FIFO memory that sequentially stores input signal values in the memory in synchronization with the control signal φ8 supplied from the timing generator 314, and outputs the signal values in order of signals stored in the memory in synchronization with the control signal φ9. . The contents of the memory are reset by the control signal φ5. 317A is an output terminal of the FIFO memory 316, and 317B is an output terminal of the clock generator 313. These are the same as the terminals 317A and 317B in FIG.

  In FIG. 10, a timing generator 318 generates a timing clock from a clock supplied from a clock generator 313 through a terminal 317B, and a D / A converter 319 decodes an output signal of the FIFO memory 316 into an analog signal. The decoded signal is applied to the column electrode drive circuit 321 of the liquid crystal panel. Reference numeral 320 denotes a liquid crystal display panel portion including a timing generator 318 and a D / A converter 319.

  The timing chart of FIG. 11 shows the time change of the control signals φ1 to φ9 sent from the timing generator 314 in FIG.
  First, at time ta, A / D converters 302A, 302B, and 302C sample and hold signals input to terminals 301R, 301G, and 301B, respectively, using signal φ1 supplied from timing generator 314. These sampled and held signals correspond to the signal values r1, g1, and b1 in FIG.

  At time tb, shift registers 303A, 303B, and 303C store and shift the output signals of A / D converters 302A, 302B, and 302C, respectively, using signal φ2 supplied from timing generator 314.

  From time td to tf and from tg to ti, A / D converters 302A, 302B, 302C and 303A, 303B, 303C operate in the same manner as described above. By these operations, the signal values rn1, rn2 and rn3 from the shift register 303A, the signal values of gn1, gn2 and gn3 from 303B, and the signal values of bn1, bn2 and bn3 from 303C are output to the flip-flops 304A, 304B, 304C, 304D and 304E, respectively. Is done.

  At time ti, flip-flops 304A, 304B, 304C, 304D, and 304E hold and output signal values output from shift registers 303A, 303B, and 303C in synchronization with signal φ3 supplied from timing generator 314. . Here, the flip-flop 304A holds the signal value rn1, 304B holds the signal value gn1, 304C holds the signal value gn2, 304D holds the signal value gn3, and 304E holds the signal value bn3. The comparator 306A compares the output signal value gn1 of the flip-flop 304B with the signal value L0 of the memory 305A and outputs the result. The comparator 306A outputs a signal “1” if the output signal value gn1 <L0 of the flip-flop 304B is satisfied, and outputs a signal “0” if this condition is not satisfied. The comparator 306B compares the output signal value gn2 of the flip-flop 304C with the signal value L0 of the memory 305B and outputs the result. The comparator 306B outputs a signal “1” if the output signal value gn2 <L0 of the flip-flop 304C is satisfied, and outputs a signal “0” if this condition is not satisfied. The differencer 307A calculates and outputs the absolute difference between the output signal value gn1 of the flip-flop 304B and the output signal value gn2 of 304C. The differencer 307B calculates and outputs an absolute difference between the output signal value gn2 of the flip-flop 304C and the output signal value gn3 of 304D. The comparator 309A outputs a signal “1” if the output signal value | gn1-gn2 |> D0 of the differencer 307A is satisfied, and a signal “0” if this condition is not satisfied. The comparator 309B compares the output signal value | gn2-gn3 | of the differentiator 307B with the signal value D0 of the memory 308B and outputs the result. The comparator 309B outputs a signal “1” if the output signal value | gn2−gn3 |> D0 of the differencer 307B is satisfied, and a signal “0” if this condition is not satisfied. The logical operator 310A calculates the logical product of the output of the comparator 306A and the output of the comparator 309A and outputs a signal of “1” or “0”. The logical operator 310B calculates a logical product of the output of the comparator 306B and the output of the comparator 309B and outputs a signal of “1” or “0”. The signal switch 311A selects and outputs the output signal values rn1 and gn2 of the flip-flop 304A based on the output of the logic unit 310A. The signal switch 311B selects and outputs the output signal values bn3 and 304C of the flip-flop 304E based on the output of the logic unit 310B.

  At time tj, flip-flops 312A, 312B and 312C hold the input signal in synchronization with signal φ4 supplied from timing generator 314. The flip-flop 312A holds the output of the signal switch 311A, 312B holds the output of the flip-flop 304C, and 312C holds the output of the signal switch 311B.

  At time tk, the signal switch 315 outputs the signal value input from the flip-flop 312A to the FIFO memory 316 in synchronization with the signal φ5 supplied from the timing generator 314. At the same time, at time tk, the FIFO memory 316 performs a reset operation in synchronization with the signal φ5 supplied from the timing generator 314.

  At time tl, the FIFO memory 316 stores the output of the signal switcher 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of flip-flop 312A is stored.

  At time tm, the signal switch 315 outputs the signal value input from the flip-flop 312B to the FIFO memory 316 in synchronization with the signal φ6 supplied from the timing generator 314. At the same time, at time tm, the FIFO memory 316 outputs the memory contents stored at time tl in synchronization with the signal φ9 supplied from the timing generator 314.

  At time tn, the FIFO memory 316 stores the output of the signal switcher 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of the flip-flop 312B is stored.

  At time to, the signal switch 315 outputs the signal value input from the flip-flop 312C to the FIFO memory 316 in synchronization with the signal φ7 supplied from the timing generator 314.

  At time tp, the FIFO memory 316 stores the output of the signal switch 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of the flip-flop 312C is stored. At the same time, at time tp, the FIFO memory 316 outputs the memory contents stored at time tn in synchronization with the signal φ9 supplied from the timing generator 314.

  At time tq, the FIFO memory 316 outputs the memory contents stored at time tp in synchronization with the signal φ9 supplied from the timing generator 314. The output of the FIFO memory 316 is displayed on the liquid crystal panel 320 through the terminal 317A.

  Thereafter, the above operation is repeated. The period for repeating the operation is PT. The relationship PT = 3T is established between PT and time T in FIG.

[Example 2]
FIG. 12 is a block diagram showing the configuration of the display device according to the second example of the present invention. FIG. 13 is a diagram illustrating an example of input / output characteristics of a signal processor (described later) in FIG. The same reference numerals in FIG. 12 as those in FIG. 9 indicate the same elements. The operation timing is also the same as in FIG. In FIG. 12, reference numerals 321A and 321B denote signal processors having a relationship of Y = f (X) as shown in FIG. The input signal X is an integer from 0 to Xm, and the output signal Y is also an integer from 0 to Ym.

  First, at time ta, A / D converters 302A, 302B, and 302C sample and hold signals input to terminals 301R, 301G, and 301B, respectively, using signal φ1 supplied from the timing generator. These sampled and held signals correspond to the signal values rn1, gn1, and bn1.

  At time tb, shift registers 303A, 303B, and 303C store and shift the output signals of A / D converters 302A, 302B, and 302C, respectively, using signal φ2 supplied from timing generator 314.

  From time td to tf and from tg to ti, A / D converters 302A, 302B, 302C and shift registers 303A, 303B, 303C operate in the same manner as described above. With these operations, the signal values rn1, rn2 and rn3 from the shift register 303A, the signal values gn1, gn2 and gn3 from 303B, and the signal values bn1, bn2 and bn3 from 303C are output.

  At time ti, flip-flops 304A, 304B, 304C, 304D, and 304E hold and output signal values output from shift registers 303A, 303B, and 303C in synchronization with signal φ3 supplied from timing generator 314. . Here, flip-flop 304A holds and outputs signal value rn1, 304B, signal value gn1, 304C holds signal value gn2, 304D holds signal value gn3, and 304E holds signal value bn3. The differencer 307A calculates and outputs the absolute difference between the output signal value gn1 of the flip-flop 304B and the output signal value gn2 of 304C. The differencer 307B calculates and outputs an absolute difference between the output signal value gn2 of the flip-flop 304C and the output signal value gn3 of 304D. The signal processor 321A receives the output signal value gn1 of the flip-flop 304B, and outputs the signal value f (gn1). The signal processor 321B receives the output signal value gn2 of the flip-flop 304C, and outputs a signal value f (gn2). The comparator 309A compares the output signal value | gn1-gn2 | of the differentiator 307A with the signal value f (gn1) of the signal processor 321A. Here, the comparator 309A outputs a signal “1” when the condition | gn1-gn2 |> f (gn1) is satisfied, and outputs a signal “0” when the condition is not satisfied. The comparator 309B compares the output signal value | gn2-gn3 | of the differentiator 307B with the signal value f (gn2) of the signal processor 321B. Here, the comparator 309B outputs a signal “1” when the condition | gn2-gn3 |> f (gn2) is satisfied, and outputs a signal “0” when the condition is not satisfied. The signal switch 311A selects and outputs one of the output signal values rn1 and gn2 of the flip-flop 304A based on the output of the comparator 309A. The signal switch 311B selects and outputs one of the output signal values bn3 and 304C of the flip-flop 304E based on the output of the comparator 309B.

  At time tj, flip-flops 312A, 312B and 312C hold the input signal in synchronization with signal φ4 supplied from timing generator 314. The flip-flop 312A holds the output of the signal switch 311A, 312B holds the output of the flip-flop 304C, and 312C holds the output of the signal switch 311B.

  At time tk, the signal switch 315 outputs the signal value input from the flip-flop 312A to the FIFO memory 316 in synchronization with the signal φ5 supplied from the timing generator 314. At the same time, at time tk, the FIFO memory 316 performs a reset operation in synchronization with the signal φ5 supplied from the timing generator 314.

  At time tl, the FIFO memory 316 stores the output of the signal switcher 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of flip-flop 312A is stored.

  At time tm, the signal switch 315 outputs the signal value input from the flip-flop 312B to the FIFO memory 316 in synchronization with the signal φ6 supplied from the timing generator 314. At the same time, at time tm, the FIFO memory 316 outputs the memory contents stored at time tl in synchronization with the signal φ9 supplied from the timing generator 314.

  At time tn, the FIFO memory 316 stores the output of the signal switcher 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of the flip-flop 312B is stored.

  At time to, the signal switch 315 outputs the signal value input from the flip-flop 312C to the FIFO memory 316 in synchronization with the signal φ7 supplied from the timing generator 314.

  At time tp, the FIFO memory 316 stores the output of the signal switch 315 in the memory in synchronization with the signal φ8 supplied from the timing generator 314. Here, the output signal value of the flip-flop 312C is stored. At the same time, at time tp, the FIFO memory 316 outputs the memory contents stored at time tn in synchronization with the signal φ9 supplied from the timing generator 314. At time tq, the FIFO memory 316 outputs the memory contents stored at time tp in synchronization with the signal φ9 supplied from the timing generator 314. The output of the FIFO memory 316 is displayed on the liquid crystal panel 320 through the terminal 317A.

  Thereafter, the above operation is repeated. The period for repeating the operation is PT. The relationship of PT = 3T is established between the times T and PT in FIG.

  As described above, the display devices according to the first and second embodiments of the present invention include the detection unit that detects the change amount | A−B | between the continuous signal values A and B obtained by sampling, and the signal value A. Based on the comparison result by the first comparison means for comparing the amount of change | A−B | with the predetermined value D0, and the first and second comparison means. Replacement means to replace the signal value given to a pixel of a certain color with a signal value of another color, so that the moire of the input video signal is reduced and the information of the input video signal is used effectively. can do.

[ Reference Example 1 ]
FIG. 6 is a block diagram of a TFT liquid crystal panel display device according to the first reference example of the present invention. In the figure, 201R, 201G and 201B are input terminals for video signals SR, SG and SB, 202 is a clock generator for supplying a signal to a timing generator described later, and 203 is a timing generator for supplying an operation clock to each part. 204R, 204G and 204B are A / D converters which sample and hold the video signals SR, SG and SB and convert them into digital signal values. Each output signal value is held until the next signal is output. Sampling is performed in synchronization with the signal φ 1 supplied from the timing generator 203. 205R, 205G, and 205B are shift registers that sequentially store three output signal values of the A / D converters 204R, 204G, and 204B at predetermined time intervals and simultaneously output them from the three output terminals. Sampling values of input signals sampled at different times from this output terminal can be obtained. The shift operation is performed in synchronization with the signal φ2 supplied from the timing generator 203. 206R, 206G, and 206B are signal switchers that select and output any two signals (possible duplication) from the three input signals, and 207A, 207B, 207C, 207D, 207E, and 207F timing the data of those output signals. A flip-flop 208 is held in synchronization with the rise of the signal φ3 supplied from the generator 203, and three signals 208 are input from the flip-flops 207A, 207B, and 207C in synchronization with the signals φ4 and φ5 supplied from the timing generator 203. A signal switcher that selects and outputs two signals, 209 is a differencer that calculates a difference absolute value of the two input signals, 210 is a ROM that stores a preset threshold value Th, and 211 is a differencer. 209 and the magnitude of the two input signals from ROM 210 And, the magnitude comparator outputs the comparison result, 212 is a timing generator which supplies a signal to the signal switching device 213 and the FIFO memory 214 (described later). Reference numeral 213 denotes a signal switcher including three signal switchers a, b and c for selecting and outputting one signal from two input signals. The signal switcher 213 has a counter inside, and switches input signals in the order of the signal switchers a, b, and c. Switching is controlled by the output signal of the magnitude comparator 211. The signal switching in the signal switcher 213 is synchronized with the signal φ6 supplied from the timing generator 212. The internal counter is reset by a signal φ9 supplied from the timing generator 212. A FIFO memory 214 stores the input signal in synchronization with the signal φ7 supplied from the timing generator 212, and outputs the stored signal in synchronization with the signal φ8 supplied from the timing generator 212. 215 is a signal terminal, 216 is a timing generator that supplies a synchronizing signal to the row electrode driving circuit and the column electrode driving circuit of the liquid crystal panel, and 217 is a liquid crystal panel portion including the timing generator 216, and is an area surrounded by a broken line in the figure It is.

FIG. 7 is a timing chart of the signals φ1 to φ9 output from the timing generators 203 and 212. Each part of the display device performs signal processing in synchronization with this waveform.
  First, at time ta, A / D converters 204R, 204G, and 204B sample and hold the signals input to terminals 201R, 201G, and 201B, respectively, with signal φ1 supplied from timing generator 203. These sampled and held signals correspond to the signal values rn1, gn1, and bn1.

At time tb, shift registers 205R, 205G, and 205B store and shift the output signals of A / D converters 204R, 204G, and 204B, respectively, using signal φ2 supplied from timing generator 203.

At times tc, td and te, tf, A / D converters 204R, 204G, 204B and 205R, 205G, 205B operate in the same manner as described above. By these operations, the signal values rn1, rn2 and rn3 from the shift register 205R, the signal values gn1, gn2 and gn3 from 205G, and the signal values bn1, bn2 and bn3 from 205B are output to the signal switches 206R, 206G and 206B, respectively. The signal switchers 206R, 206G, and 206B select two predetermined signals (possible duplication) among the three signal values input to each. Here, it is assumed that the signal switch 206R is set to output the signal value rn1, 206G, the signal value gn2, and 206B to output the signal value bn3.

At time tg, flip-flops 207A, 207B, 207C, 207D, 207E and 207F hold the signal values output from signal switchers 206R, 206G and 206B in synchronization with signal φ3 supplied from timing generator 203. ,Output. Here, based on the above assumption, flip-flop 207A holds signal value rn1, 207B holds signal value gn2, 207C holds signal value bn3, 207D holds signal value rn1, 207E holds signal value gn2, and 207F holds signal value bn3. And output to the signal switch 208.

At time th, the signal switch 208 selects and outputs two predetermined signals from the output signals of the flip-flops 207A, 207B and 207C by the signal φ4 supplied from the timing generator 203. Here, it is assumed that signal switcher 208 is set in advance so that output signal value rn1 of flip-flop 207A and output signal value gn2 of 207B are selected by signal φ4. The differencer 209 calculates and outputs the difference absolute value of the two signals rn1 and gn2 selected by the signal switcher 208. The comparator 211 compares the output of the differentiator 209 with the threshold value Th of the ROM 210 and outputs the result. The comparator 211 determines “true” or “false” whether the output> Th of the subtractor 209 is satisfied, and outputs the result as a binary signal. When this condition is satisfied, a “true” signal is output.

At time ti, the signal switch 213 selects the input terminal a2 of the signal switch 213 if the signal received from the comparator 211 is “true”, and selects a1 if it is “false”, and outputs it to the output terminal O. This selection is performed in synchronization with the signal φ6 supplied from the timing generator 212. If the output of the comparator 211 is “false”, the signal value rn 1 is input to the input terminal a 1 of the signal switch 213, the signal value gn 2 is input to the a 2, and rn 1 is output to the output terminal O. Here, it is assumed that rn1 is output from the output terminal O.

At time tj, the FIFO memory 214 stores the signal value rn1 output from the signal switch 213 by the signal φ7 supplied from the timing generator 212.

At time tk, the signal switch 213 outputs the signal value of the input terminal b2 of the signal switch 213 to the output terminal O. At this time, the output of the comparator 211 is not used. Here, the signal value gn2 is selected. At the same time, at time tk, the FIFO memory 214 outputs the signal value rn1 stored at time tj and holds the output signal value until time to. The signal value output from the FIFO memory 214 passes through the terminal 215 and is displayed on the liquid crystal panel 217.

  At time tl, the signal switcher 208 selects and outputs two signals from the output signals 207A, 207B, and 207C at time t1 by the signal φ5 supplied from the timing generator 203. Here, it is assumed that the signal switch 208 is set so that the output signals 207B and 207C are selected in advance by the signal φ5. Therefore, signal values gn2 and bn3 are output from the signal switch 208. At the same time, at time tl, the FIFO memory 214 stores the signal value gn2 selected by the signal switcher 213 by the signal φ7 supplied from the timing generator 212.

At time tm, the signal switch 213 selects either the signal value of the input terminal c1 or c2 of the signal switch 213 according to “true” or “false” of the signal received from the comparator 211, and outputs it to the output terminal O. Output. This selection is performed in synchronization with the signal φ6 supplied from the timing generator 12. Here, it is assumed that the signal value gn2 is input to the input terminal c1 of the signal switcher 213, the signal value bn3 is input to the c2, and the gn2 is output to the output terminal O.

At time tn, the FIFO memory 214 stores the output signal value (value selected at time tm) gn2 of the signal switch 213 by the signal φ7 supplied from the timing generator 212.

At time to, the FIFO memory 214 outputs the signal value gn2 stored at time t1, and holds the output signal value until time tp. The output signal value is displayed on the liquid crystal panel 217.
  At time tp, the FIFO memory 214 outputs the signal value gn2 stored at time tn. The output signal value is displayed on the liquid crystal panel 217.
  Thereafter, the above operation is repeated. The period for repeating the operation is PT. The relationship of PT = 3T is established between the times T and PT.

[ Reference Example 2 ]
FIG. 8 is a block diagram illustrating a configuration of the display device according to the second reference example. Hereinafter, description will be made with reference to FIGS. In FIG. 8, the same reference numerals as those in FIG. 6 denote the same elements. In FIG. 8, 218R, 218G, and 218B are signal filters, and apply predetermined filters to signals input from the signal input terminals 201R, 201G, and 201B. 219R, 219G, and 219B are A / D converters that sample and hold the signals output from the signal filters 218R, 218G, and 218B, respectively, and convert them into digital signal values. Each output signal value outputs the following signal. Is held until. Sampling is performed in synchronization with the signal φ 1 supplied from the timing generator 203. 220R, 220G, and 220B are shift registers that function in the same manner as the shift registers 205R, 205G, and 205B. 221R, 221G, and 221B are signal switchers that select and output one preset from three input signal values. 222A, 222B, and 222C are flip-flops that have two inputs and two outputs and hold data in synchronization with the rise of the signal φ3 supplied from the timing generator 203, and are respectively signal switchers 206R, 206G, and 206B. And the outputs of the signal switchers 221R, 221G and 221B.

Next, the operation of the apparatus will be described with reference to FIGS.
  First, at time ta, the A / D converters 204R, 204G, and 204B sample and hold the signals input to the input terminals 201R, 201G, and 201B by the signal φ1 supplied from the timing generator 203, respectively. At the same time, the A / D converters 219R, 219G, and 219B sample and hold the outputs of the signal filters 218R, 218G, and 218B, respectively.

At time tb, shift registers 205R, 205G, and 205B store and shift output signals of A / D converters 204R, 204G, and 204B, respectively, in synchronization with signal φ2 supplied from timing generator 203. At the same time, shift registers 220R, 220G, and 220B store and shift the output signal values of A / D converters 219R, 219G, and 219B, respectively.

From time tc to td and from te to tf, the A / D converters 204R, 204G, 204B, 219R, 219G, 219B and the shift registers 205R, 205G, 205B, 220R, 220G, 220B operate in the same manner as described above. Through the above operation, signal values rn1, rn2, and rn3 are output from the shift register 205R, 205n to gn1, gn2, and gn3, and 205B to bn1, bn2, and bn3. The shift register 220R outputs signal values Frn1, Frn2, and Frn3, 220G outputs Fgn1, Fgn2, and Fgn3, and 220B outputs signal values Fbn1, Fbn2, and Fbn3. The signal switchers 206R, 206G, and 206B select two (possible duplication) of the three input signal values. The signal switchers 221R, 221G, and 221B select one of the three input signal values. Here, it is assumed that the signal value Frn1, 221G is Fgn2, and 221B is Fbn3.

Flip-flops 207A, 207B, and 207C hold the signal values output from signal switchers 206R, 206G, and 206B from time tg and output in synchronization with signal φ3 supplied from timing generator 203. Here, it is assumed that the flip-flop 207A holds the signal value rn1, 207B holds the signal value gn2, and 207C holds and outputs the signal value bn3. The flip-flops 222A, 222B, and 222C synchronize with the signal φ3, and output the signal values output from the signal switchers 206R, 206G, and 206B and the signal values output from the signal switchers 221R, 221G, and 221B in time. Hold from tg and output. Here, based on the above assumption, the flip-flop 222A holds the signal values rn1 and Frn1, 222B and the signal values gn2 and Fgn2, and 222C holds and outputs the signal values bn3 and Fbn3, respectively. The differencer 209A calculates and outputs an absolute difference | rn1−gn2 | of the output signal values of the flip-flops 207A and 207B. The differencer 209B calculates and outputs an absolute difference | gn2-bn3 | between the output signal values of the flip-flops 207B and 207C. The comparator 211A compares the output of the differentiator 209A with the threshold value Th of the ROM 210, and outputs the result as a binary signal of “true” or “false”. When the output signal value of the differentiator 209A> the threshold value Th, a “true” signal is output. Otherwise, a “false” signal is output. Similarly, the comparator 211B compares the output of the differentiator 209B with the threshold value Th of the ROM 210, binarizes the result with “true” or “false”, and outputs the result. The logical operator 223 calculates and outputs a logical sum of the output signals of the comparators 211A and 211B. If either is “true”, the output of the logical operator 223 is “true”.

At time th, the output of the logical operator 223 is held in the flip-flop 207G and output in synchronization with the control signal φ4.

At the time ti, tk, tm, the signal switch 213 receives the input terminals a1, b1, c1 or a2, b2, c2 of the signal switch 213 according to “true” or “false” of the signal received from the output of the flip-flop 207G. Is selected and the signal value is output to the output terminal O. That is, if the output of the flip-flop 207G is “true”, the signal switch 213 selects the input terminals a2, b2, and c2, and sequentially outputs signal values in synchronization with the signal φ6 supplied from the timing generator 212. . If the output of the flip-flop 207G is “false”, the signal switch 213 selects the input terminals a1, b1, and c1, and sequentially outputs signal values in synchronization with the signal φ6 supplied from the timing generator 212. Here, it is assumed that the output of the flip-flop 207G is “true”, the signal value rn1 is input to the input terminal a1 of the signal switch 213, and the signal value Frn1 is input to a2. It is assumed that signal value> threshold value Th is satisfied. Then, at time ti, the signal value Frn1 input to the input terminal a2 of the signal switch 213 is output to the output terminal O.

At time tj, the FIFO memory 214 stores the signal value rn1 output from the signal switch 213 by the signal φ7 supplied from the timing generator 212.

At time tk, the signal switch 213 selects b2 among the input terminals b1 and b2 of the signal switch 213 in synchronization with the signal φ6. Since the signal value Fgn2 is input to the input terminal b2, the signal switch 213 outputs the signal value Fgn2 to the output terminal O. Similarly to the above, at time tk, the FIFO memory 214 outputs the signal value Frn1 stored at time tj and holds the output signal value until time to. The output signal value passes through the terminal 215 and is displayed on the liquid crystal panel 217.

At time tl, the FIFO memory 214 stores the signal value Fgn2 output from the signal switcher 213 at time t1 by the signal φ7 supplied from the timing generator 212.

At time tm, the signal switch 213 selects the signal value of c2 among the input terminals c1 and c2 of the signal switch 213 in synchronization with the signal φ6. Since the signal value Fbn3 is input to the input terminal c2, the signal switch 213 outputs the signal value Fbn3 to the output terminal O.

At time tn, the FIFO memory 214 stores the output signal value (value selected at time tm) Fbn3 of the signal switch 213 by the signal φ7 supplied from the timing generator 212.

At time to, the FIFO memory 214 outputs the signal value gn2 stored at time t1, and holds the output signal value until time tp. The output signal value is displayed on the liquid crystal panel 217.

At time tp, the FIFO memory 214 outputs the signal value gn2 stored at time tn. The output signal value is displayed on the liquid crystal panel 217.

Thereafter, the above operation is repeated. The period for repeating the operation is PT. A relationship of PT = 3T is established between this PT and time T in FIG.

In this reference example, when the input video signal changes greatly per unit time and the amount of change exceeds a predetermined threshold, the video signal output to the liquid crystal panel 217 is partially switched. For example, if the signal filters 218R, 218G, and 218B are low-pass filters, it is possible to selectively perform a filtering process on an area where moire is likely to occur in the input image. Therefore, it is possible to selectively perform moire reduction processing while retaining information of the input image.

As described above, the display devices according to Reference Examples 1 and 2 of the present invention sequentially sample from the signals that control the red, green, and blue display pixels at certain times t1, t2, and t3 (t1 <t2 <t3). The signal values are selected from the three signal values rn1, rn2 and rn3, gn1, gn2 and gn3, bn1, bn2 and bn3 obtained in the above, and given to three consecutively arranged red, green and blue pixel arrays When the difference between rn1 and rn2, the difference between gn1 and gn2, or the difference between bn1 and bn2 is greater than a predetermined threshold value Th, and the respective differences> Th are satisfied, or rn2 and rn3 And the difference between gn2 and gn3 or the difference between bn2 and bn3 are compared to a value greater than a predetermined threshold Th, When the difference> Th is established, by providing means for selectively switching the signal value applied to the display pixel, the color moire of the input video signal is reduced, and information of the input video signal is effectively utilized for display. Can do.

In addition, the signal value given to the pixel array of the display device is selectively switched according to the change in the amplitude of the input video signal. At this time, by selectively switching the signal value when the input video signal is passed through a predetermined signal filter and the signal value when the input video signal is not passed, the input video signal is selectively selected only in a region where color moiré is likely to occur. A signal filter can be applied, and information of the input video signal can be used effectively.

[ Reference Example 3 ]
FIG. 1 is a block diagram of a TFT liquid crystal panel display device according to a third reference example of the present invention. In the figure, 1 is an input terminal for video signals SY, SR, SG, SB, and 2 is an A / D converter that samples and holds the video signal and converts it into a digital signal value. This output signal value is held until the next signal is output.

3 is a signal switch for selecting one of three input signal values, and 10 is a signal switch for selecting one of two input signal values. This output signal is held until the next signal is output. Selection timing is supplied by an external timing generator 4 (described later). Reference numerals 4 and 14 denote timing generators for generating a plurality of different timing signals from a given periodic signal. Reference numerals 5 and 6 denote memories for storing one input signal value. This is because when the next signal value is input, the previously stored signal value is lost. Reference numeral 7 denotes an arithmetic unit for obtaining an absolute value of a difference between two given signal values. Reference numeral 8 denotes a memory for storing a preset threshold value. Reference numeral 9 denotes a comparator that compares the output signal value of the arithmetic unit 7 with the threshold value stored in the memory 8. The timing for comparison is supplied by the timing generator 4. 11 is an output terminal of the switch 10, 12 is a clock generator for supplying a periodic signal to the entire display device, 13 is an output signal terminal of the clock generator 12, and 15 has an input buffer for storing three signal values. This is a D / A converter that converts the signal value in the buffer into an analog signal at the timing supplied from the generator 14. This output signal is held until the next signal is output. Reference numeral 18 denotes a liquid crystal panel, 16 denotes a column electrode drive circuit of the liquid crystal panel 18, 17 denotes a row electrode drive circuit of the liquid crystal panel 18, and 19 denotes a block configuration inside a broken line.

  FIG. 2 is a diagram showing an operation timing chart in each part. The waveform in the figure is output to each part by the timing generator 4. Each part of the display device performs signal processing in synchronization with this waveform. Ck1, 2, 3,... Indicate timings based on the number of clock pulses. The operation will be described below with reference to FIGS.

At the clock (Ck) 1, the signal is sampled from the video input terminal 1 and converted into digital data by the A / D converter 2 to obtain signal values yn 1, rn 1, gn 1, bn 1 of each signal. In Ck4, the switch 3 selects and outputs the signal value rn1 of the signal SR. At Ck5, the signal value yn1 of the signal SY is stored in M5, and the signal value rn1 of the SR signal is stored in M6. At Ck6, a signal is sampled from the video input terminal 1 and converted into digital data, and signal values yn2, rn2, gn2, and bn2 of each signal are obtained. At Ck7, the switch 3 selects and outputs the signal value gn2 of the signal SG. The arithmetic unit 7 calculates and outputs the absolute difference between the signal value yn1 stored in M5 and the signal value yn2 output from the A / D converter 1. In Ck8, the comparator 9 compares the output of the arithmetic unit 7 with the threshold value th written in the RM8 in advance. In Ck9, using the output of the comparator 9, the switch 10 selects the signal value rn1 stored in M6 or the signal value gn2 output by the switch 3, and outputs it to the signal output terminal 11. The output signal value is stored in the input buffer of the D / A converter 15. At Ck10, the signal value yn2 of the signal SY is stored in M5, and the signal value gn2 of the SG signal is stored in M6. At Ck11, a signal is sampled from the video input terminal 1 and converted into digital data, and signal values yn3, rn3, gn3, and bn3 of each signal are obtained. The switch 10 outputs the signal value gn2 of the SG signal to the signal output terminal 11. The output signal value is stored in the input buffer of the D / A converter 15. At Ck12, the switch 3 selects and outputs the signal value bn3 of the SB signal. The computing unit 7 calculates and outputs the absolute difference between the signal value yn2 stored in M5 and the signal value yn3 output from the A / D converter 1. In Ck13, the comparator 9 compares the output of the arithmetic unit 7 with the threshold value th written in the RM 8 in advance. In Ck 14, the switch 10 selects the signal value gn 2 stored in M 6 or the signal value bn 3 output from the switch 3 based on the output of the comparator 9, and outputs it to the signal output terminal 11. The output signal value is stored in the input buffer of the D / A converter 15. The signal output from the signal output terminal 11 is processed by the D / A converter 15.

FIG. 3 shows an output signal of the D / A converter 15. The output signal of the switch 10 is stored in the input buffer in the D / A converter 15 at the Ck 9, 11 and 14, and is output from the D / A converter 15 between Ck 16 and 30 as shown in FIG. The signal levels on1, on2, and on3 at this time are values obtained by converting the digital signal output from the switch 10 at Ck9, 11 and 14 into an analog signal by the D / A converter 15. Corresponding to the signal values on1, on2, on3, the display pixels R, G, B are respectively lit.
  Thereafter, the operations of Ck1 to 30 are repeated.

FIG. 4 is a diagram illustrating a specific comparison / selection signal processing example. In the figure, th is a threshold value. Hereinafter, FIG. 4 will be described.

  In the example of the process 1, since | yn1-yn2 | <th, a red display pixel is displayed with the signal value rn1. Since | yn2-yn3 |> th, a blue display pixel is displayed with a signal value of gn2 instead of bn3.
  In the example of the process 2, since | yn1-yn2 | <th, a red display pixel is displayed with the signal value rn1. Since | yn2-yn3 |> th, a blue display pixel is displayed with a signal value of gn2 instead of bn3.
  In the example of the processing 3, since | yn1-yn2 |> th, a red display pixel is displayed with a signal value of gn2 instead of rn1. Since | yn2-yn3 | <th, a blue display pixel is displayed with the signal value bn3.
  In the example of the process 4, since | yn1-yn2 |> th, a red display pixel is displayed with a signal value of gn2 instead of rn1. Since | yn2-yn3 | <th, a blue display pixel is displayed with the signal value bn3.

[ Reference Example 4 ]
FIG. 5 is a block diagram of a portion corresponding to 19 in FIG. 1 of a TFT liquid crystal panel display device according to a fourth reference example of the present invention. The other structure is the same as that of FIG. In the figure, 20 is a signal input terminal for each signal SR, SG, SB, and 21 is an A / D converter that samples and holds a video signal and converts it into a digital signal value. In the reference example 3, the signal SY is used for the input of the comparison means, but in this reference example, the signal SG is used instead of the signal SY. Thus, the configuration can be simplified as compared with the reference example 3.

The operation of the apparatus shown in FIG. 5 will be described below.
  The waveform output by the timing generator 4 of this reference example is the same as that shown in FIG. Each part of the display device performs signal processing in synchronization with this waveform.

At Ck1, a signal is sampled from the signal input terminal 20 and converted into digital data, and signal values rn1, gn1, and bn1 of each signal are obtained. In Ck4, the switch 3 selects and outputs the signal value rn1 of the signal SR. At Ck5, the signal value gn1 of the signal SG is stored in the memory 5 and the signal value rn1 of the signal SR is stored in the memory 6. At Ck6, the signal is sampled from the signal input terminal 20 and converted into digital data, and signal values rn2, gn2, and bn2 of each signal are obtained. At Ck7, the switch 3 selects and outputs the signal value gn2 of the signal SG. The computing unit 7 calculates and outputs the absolute difference between the signal value gn1 stored in the memory 5 and the signal value gn2 output from the A / D converter 21. In Ck8, the comparator 9 compares the output of the arithmetic unit 7 with the threshold value th written in the memory 8 in advance. In Ck 9, using the output of the comparator 9, the switch 10 selects the signal value rn 1 stored in the memory 6 or the signal value gn 2 output from the switch 3 and outputs it to the signal output terminal 11. The output signal value is stored in the input buffer of the D / A converter 15. At Ck10, the signal value gn2 of the signal SG is stored in the memory 5 and the memory 6 simultaneously. At Ck11, the signal is sampled from the signal input terminal 20 and converted into digital data, and signal values rn3, gn3, and bn3 of each signal are obtained. The switch 10 outputs the signal value gn2 of the signal SG to the signal output terminal 11. At Ck12, the switch 3 selects and outputs the signal value bn3 of the signal SB. The arithmetic unit 7 calculates and outputs the absolute difference between the signal value gn2 stored in the memory 5 and the signal value gn3 output from the A / D converter 21. The output signal value is stored in the input buffer of the D / A converter 15. In Ck 13, the comparator 9 compares the output of the arithmetic unit 7 with the threshold value th written in the memory 8 in advance. In Ck 14, based on the output of the comparator 9, the switch 10 selects the signal value gn 2 stored in the memory 6 or the signal value bn 3 output from the switch 3 and outputs it to the signal output terminal 11. The output signal value is stored in the input buffer of the D / A converter 15. The signal output from the signal output terminal 11 is processed by the D / A converter 15. FIG. 3 shows an output signal of the D / A converter 15. The output signal of the switch 10 is stored in the buffer in the D / A converter 15 at the Ck 9, 11 and 14, and is output from the D / A converter 15 between Ck 16 and 30 as shown in FIG. The signal levels on1, on2, and on3 at this time are values obtained by converting the digital signals output by the switch 10 at Ck9, 11, and 14 into analog signals. Corresponding to the signal values on1, on2, on3, the display pixels R, G, B are respectively lit.
  Thereafter, the operations of Ck1 to 30 are repeated.

As described above, the display device according to the reference examples 3 and 4 of the present invention includes a means for comparing a difference between two signal values selected from signal values obtained by sampling and a predetermined threshold value, and a comparison. By means of selectively switching signal values given to display pixels in accordance with the output of the means, color moiré of the input video signal is reduced, and information of the input video signal is effectively utilized for display. Can do.

[Reference Example 5 ]
FIG. 14 is a block diagram of a liquid crystal display device according to a fifth reference example of the invention. In the figure, 401 is an input terminal for a video signal, 402 is a signal processing circuit, 403 is a sync separation circuit, 404 is a controller, 405 is an X driver, 406 is a Y driver, 407 is an LCD, and 408 is for displaying character information. A control signal input terminal 409, a character generation circuit for generating character information to be displayed based on the control signal input from the input terminal 408, and a synthesis circuit 410 for combining the video signal and the character information. The LCD 407 has a configuration as shown in FIG. Further, the X driver 405 has a shift register configured as shown in FIG. In FIG. 15, 421 is a start pulse input terminal, 422 is a drive pulse input terminal, 423 is a D flip-flop, 424 is a drive pulse output terminal, 425 is a mode switching signal input terminal, and 426 is a switch circuit.

The operation of the liquid crystal display device according to the fifth reference example of the present invention will be described with reference to FIGS. The video signal input from the input terminal 401 is subjected to predetermined processing such as γ correction and inversion processing in the signal processing circuit 402 so that it can be displayed on the LCD 407 and input to the synthesizing circuit 410 and simultaneously to the synchronization separation circuit 403. The synchronization signal is inputted and separated, and the separated synchronization signal is inputted to the controller 404. Based on this, the controller 404 supplies a predetermined drive pulse for driving the LCD 407 synchronized with the video signal to the X driver 405 and the Y driver 406. Further, a control signal for displaying character information on the LCD 409 together with an image is input from the input terminal 408 and supplied to the character generation circuit 409. The character generation circuit 409 is also supplied with the synchronization signal separated by the synchronization separation circuit 403, and the character generation circuit 409 generates characters to be displayed on the LCD 407 in synchronization with the video signal. The output video signal of the signal processing circuit 402 and the output of the character generation circuit 409 are combined by the combining circuit 410 and supplied to the X driver 405. The LCD 407 is driven by a video signal supplied from the X driver 405, a signal obtained by combining character information, a drive pulse, and a drive pulse supplied from the Y driver 406, and displays character information on the screen simultaneously with the image.

  Further, the character generation circuit 409 supplies a mode switching signal for switching the driving mode to the input terminal of the X driver 405. That is, the character generation circuit 409 performs control so that the switch circuit 426 is connected to the a side in a region where characters are displayed on the screen, and is controlled so as to connect the switch circuit 426 to the b side in regions where no characters are displayed. To do. At this time, the m output terminals 424 are respectively connected to the switching elements 465R, 465G, and 465B via the m input terminals 467R, 467G, and 467B of the LCD of FIG. Further, when a start pulse is input from the input terminal 421 at the beginning of the horizontal scanning period and a clock of m times the horizontal frequency is input from the input terminal 422, the m-stage shift register in FIG. Is done. At this time, since the switch circuit 426 is connected to the a side by the control signal from the character generation circuit 409 in the area for displaying characters, the same drive pulse is output to the output terminal 424 for each of the three output terminals. This is supplied to the gates of the switching elements 465R, 465G, and 465B via the input terminals 467R, 467G, and 467B, and the switches are simultaneously turned on. As a result, the video signals input from 464R, 464G, and 464B are simultaneously sampled and supplied to the vertical signal line. In the area where no character is displayed, since the switch circuit 426 is connected to the b side by the control signal from the character generation circuit 409, different drive pulses are output to the output terminal 424, and each switching element 465R. 460G and 465B are sequentially supplied to the respective gates, and the respective switches are sequentially turned on. As a result, the video signals input from the input terminals 464R, 464G, and 464B are sampled at different timings and supplied to the vertical signal lines.

  The subsequent operations are common to the above two modes. In the Y driver in FIG. 33B, a start pulse is input from the input terminal 431 at the beginning of the vertical scanning period, and a clock having a horizontal frequency is input from the input terminal 432. Then, the n-stage shift register is driven by this drive pulse, and the output pulse of this shift register is output to the output terminal 434. The output terminal 434 is connected to the input terminal 468. The drive pulse output from the Y driver 406 is supplied to the gate of the switching element 461 through a predetermined horizontal gate line, and each switch is turned on, whereby the liquid crystal cell 462 is turned on. The storage capacitor 463 holds a charge corresponding to the potential difference between the signal supplied to the input terminal 464 and the voltage supplied to the common electrode 466. At this time, a predetermined voltage is supplied to the common electrode 466. By repeating this operation, an image for one screen can be displayed on the LCD.

  In this way, in a liquid crystal display device having a function of adding character information to an input image and displaying it, in a region where characters are not displayed, a video signal is applied to R, G, and B pixels of the liquid crystal display device. Correspondingly, sampling is performed at different phases, and in the area where characters are displayed, the three pixels R, G, and B are sampled at the same phase, thereby enhancing the resolution in the area where images are displayed. Furthermore, it is possible to prevent aliasing from occurring when displaying characters.

[Reference Example 6 ]
FIG. 16 is a block diagram of a liquid crystal display device according to a sixth reference example of the present invention. In the figure, reference numeral 411 denotes a video signal delay circuit, the X driver 405 is as shown in FIG. 33A, and the other components having the same numbers as those in FIG. 14 are the same as in FIG. It is. FIG. 17 shows an example of the delay circuit 411 in FIG. 16, wherein 441R, 441G, 441B are video signal input terminals, 442R, 442G are switch circuits, 443 is a delay circuit, 444R, 444G is a switch circuit, Reference numeral 445 denotes a mode switching signal input terminal, and 446R, 446G, and 446B denote video signal output terminals.

The operation of the liquid crystal display device according to the sixth reference example of the present invention will be described with reference to FIGS. The video signal input from the input terminal 401 is subjected to predetermined processing in the signal processing circuit 402, input to the synthesizing circuit 410 and simultaneously input to the synchronization separation circuit 403 to separate the synchronization signal, and the separated synchronization The signal is input to the controller 404. Based on this, the controller 404 supplies a predetermined drive pulse for driving the LCD synchronized with the video signal to the X driver 405 and the Y driver 406. Further, a control signal for displaying character information on the LCD together with an image is input from the input terminal 408 and supplied to the character generation circuit 409. The character generation circuit 409 is also supplied with the synchronization signal separated by the synchronization separation circuit 403. Based on this, the character generation circuit 409 generates characters to be displayed on the LCD 407 in synchronization with the video signal. The output video signal of the signal processing circuit 402 and the output of the character generation circuit 409 are combined by the combining circuit 410 and supplied to the X driver 405 via the delay circuit 411. The LCD 407 is driven by a video signal supplied from the X driver 405, a signal obtained by combining character information, a drive pulse, and a drive pulse supplied from the Y driver 406, and displays character information on the screen simultaneously with the image.

  Further, the character generation circuit 409 supplies a mode switching signal for switching the display mode to the delay circuit 411 via the controller 404. That is, the character generation circuit 409 controls the switch circuits 442R, 442G, 444R, and 444G to be connected to the a side in an area that does not display characters on the screen, and the switch circuits 442R, 442G, and 444R in an area that displays characters. 444G is controlled to be connected to the b side. The delay amount of the delay circuit 443 is a delay amount for one pixel of the LCD 407. Therefore, when the switch circuits 442R, 442G, 444R, and 444G are connected to the a side, the video signals ROUT, GOUT, and BOUT output from the output terminals 446R, 444G, and 444B are the same as the signal BOUT. The signal ROUT is delayed by one pixel, and the signal ROUT is delayed by two pixels. When the switch circuits 442R, 442G, 444R, 444G are connected to the b side, the signals input from the input terminals 441R, 441G, 441B are output as they are to the output terminals 446R, 446G, 446B.

In this reference example, since the X driver 405 is as shown in FIG. 33A, the LCD 407 samples three pixels of R, G, and B with the same phase, but by passing through the delay circuit 411, Since the video signal is delayed in the area where characters are not displayed, the same effect as when the three pixels R, G, and B are sampled at different phases can be obtained. In the area where characters are displayed, a delay circuit is provided. Since no delay processing is performed at 411, the three pixels R, G, and B are sampled with the same phase. Subsequent operations are the same as in the case of the fifth reference example, and a description thereof will be omitted.

In this way, in a liquid crystal display device having a function of adding character information to an input image for display, the conventionally used X driver is used as it is, as in the fifth reference example. In the area where characters are not displayed, the video signal is sampled at different phases corresponding to the R, G and B pixels of the liquid crystal display device, and in the area where characters are displayed, the same three pixels R, G and B are used. By sampling at the phase, it is possible to enhance the resolution in the area where the image is displayed, and to prevent aliasing distortion when displaying characters.

  Further, in this reference example, the delay circuit 411 in FIG. 16 may be configured as shown in FIG. In the figure, 451R, 451G, and 451B are video signal input terminals, 452 is a sample hold circuit, and 453R, 453G, and 453B are video signal output terminals. A sample hold pulse as shown in FIG. 19A is supplied from the controller 404 to the delay circuit in an area where characters are not displayed. At this time, the phase of each pulse is shifted by one pixel of the LCD. Accordingly, in the case of the delay circuit of FIG. 17, the video signals output from the output terminals 453R, 453G, and 453B are delayed by one pixel with respect to the signal BOUT, and the signal ROUT is delayed by two pixels. Is done. Further, in the area for displaying characters, a pulse as shown in FIG. 19B is supplied and each sample and hold circuit 452 is set to the through state so that the video signals input from the input terminals 451R, 451G and 451B are output. The data is output as it is to the terminals 453R, 453G, and 453B.

  By doing so, the same effect as in the case of the delay circuit of FIG. 17 can be obtained, and it is possible to easily cope with a change in the number of pixels of the LCD by configuring the delay circuit with a sample hold circuit. The effect of becoming is also obtained.

[Reference Example 7 ]
The block diagram of the liquid crystal display device according to the seventh reference example of the present invention is the same as that of FIG. 16, and the difference from the sixth reference example is that the X driver 405 is as shown in FIG. The delay circuit 411 shown in FIG. 20 is different in its control, and the other operations are the same, so that the description thereof is omitted. In FIG. 20, the same reference numerals as those in FIG. 17 denote the same components. The switch circuits 442B, 442G, 444B, and 444G in FIG. 20 are controlled so as to be connected to the a side in a region that displays a character and to the b side in a region that does not display a character by a control signal from the character generation circuit 409. Is done. Further, since the X driver 405 is as shown in FIG. 34, the LCD 407 samples three pixels of R, G, and B at different timings, but the video signal is not subjected to delay processing in an area where characters are not displayed. , R, G, and B are sampled at different phases, and the video signal is delayed by passing through the delay circuit 411 in the character display area. The same effect as that obtained by sampling at the above phase can be obtained.
By doing so, it is possible to obtain the same effect as that of the sixth reference example.

Further, as in the sixth reference example, it is needless to say that the delay circuit 411 is as shown in FIG. 21, and a sample hold pulse as shown in FIG. 22 may be supplied. In FIG. 21, the same reference numerals as those in FIG. 18 denote the same components. Furthermore, the sample hold pulse shown in FIG. 22A may be supplied in a region where characters are not displayed, and the pulse shown in FIG. 22B may be supplied in a region where characters are displayed.

[Reference Example 8 ]
FIG. 23 is a block diagram of a liquid crystal display device according to an eighth reference example of the present invention. In the figure, reference numeral 412 denotes a character area discriminating circuit for discriminating a character area of an input video signal. Other components having the same numbers as those in FIG. 14 are the same components.

The operation of the liquid crystal display device according to the eighth reference example of the present invention will be described with reference to FIG. The video signal input from the input terminal 401 is input to the signal processing circuit 402, the synchronization separation circuit 403, and the character area determination circuit 412. The signal processing circuit 402 performs predetermined processing so that it can be displayed on the LCD 407, and the video signal output therefrom is supplied to the X driver 405. The synchronization separation circuit 403 separates the synchronization signal, and the separated synchronization signal is input to the controller 404. Based on this, the controller 404 supplies a predetermined drive pulse for driving the LCD 407 synchronized with the video signal to the X driver 405 and the Y driver 406. Further, the character area discriminating circuit 412 discriminates an area including characters and an area not including characters from the input video signal, and supplies a drive mode switching control signal to the X driver 405. The LC 4D 7 is driven by the video signal and drive pulse supplied from the X driver 405 and the drive pulse supplied from the Y driver 406, and displays character information on the screen simultaneously with the image.

In this reference example, the X driver 405 is the same as that shown in FIG. 15. When the character area determination circuit 412 determines that the area includes a character as in the fifth reference example, the character area determination circuit 412. The switch circuit 426 is connected to the a side by the control signal output from the control circuit 426. When it is determined that the area does not include a character, the switch circuit 426 is controlled to be connected to the b side. Therefore, as in the fifth reference example, when the input video signal is displayed on the LCD 407, the R, G, and B pixels are sampled at different phases in the area not including characters, and the characters are included. In the region, three pixels of R, G, and B are sampled with the same phase. Since the following operation is the same as that of the fifth reference example, description thereof is omitted.

  In this manner, in a liquid crystal display device that displays an input image including character information, in a region where no character is displayed, video signals are separated from each other in correspondence with R, G, and B pixels of the liquid crystal display device. In the area where characters are displayed, the three pixels R, G, and B are sampled in the same phase in the area where characters are displayed, thereby improving the sense of resolution and displaying characters in the area where images are displayed. It is possible to prevent the aliasing distortion from occurring during the process.

[Reference Example 9 ]
FIG. 24 is a block diagram of a liquid crystal display device according to a ninth reference example of the present invention. In this reference example, the X driver 405 is as shown in FIG. 33, and the delay circuit 411 is as shown in FIG. 17 or FIG. In this reference example, the delay circuit 411 is controlled by the control signal from the character area discrimination circuit 412 via the controller 404 to control the delay amount of the video signal. The control method is the same as in the sixth reference example, in which a delay process is performed in an area where characters are not displayed and a delay process is not performed in an area where characters are displayed.
By doing so, it is possible to obtain the same effect as the eighth reference example while diverting the conventional X driver.

[Reference Example 10 ]
A block diagram of a liquid crystal display device according to a tenth reference example of the present invention is shown in FIG. 24 as in the ninth reference example. In this reference example, the X driver 405 is as shown in FIG. 34, and the delay circuit 411 is as shown in FIG. 20 or FIG. In this reference example, the delay circuit 411 is controlled by the control signal from the character area discrimination circuit 412 via the controller 404 to control the delay amount of the video signal. The control method is the same as in the seventh reference example, and the delay process is not performed in the area where characters are not displayed, and the delay process is performed in the area where characters are displayed.
By doing so, it is possible to obtain the same effect as the ninth reference example.

As described above, according to Reference Examples 5 to 10 of the present invention, in a liquid crystal display device having a function of adding character information to an input video signal and displaying it, the video signal is displayed on the liquid crystal in a region where no character is displayed. Sampling is performed at different phases corresponding to, for example, R, G, and B pixels of the display device, and by sampling three pixels of R, G, and B at the same phase in a region where characters are displayed, In the area where the image is displayed, it is possible to enhance the resolution and further prevent aliasing distortion when displaying characters.
Further, when the delay means is provided, a conventionally used X driver can be used as it is in a liquid crystal display device having a function of adding character information to an input video signal for display.

[Reference Example 11 ]
The block diagram of the liquid crystal display device in the eleventh reference example of the present invention is the same as that shown in FIG. In FIG. 23, 401 is a video signal input terminal, 402 is a signal processing circuit, 403 is a sync separation circuit, 404 is a controller, 405 is an X driver, 406 is a Y driver, 607 is an LCD, and 412 is a character of the input video signal. It is a character area discriminating circuit for discriminating an area. The LCD 407 has a configuration as shown in FIG. 31 as in the conventional example. Further, the X driver 405 is a shift register configured as shown in FIG. 15. 421 is a start pulse input terminal, 422 is a drive pulse input terminal, 423 is a D flip-flop, and 424 is a drive pulse output. Terminals 425 are input terminals for mode switching signals, and 426 is a switch circuit. The Y driver 406 is the same as that in the conventional example, as shown in FIG.

The operation of the liquid crystal display device according to the eleventh reference example of the present invention will be described with reference to FIGS. A video signal input from an input terminal 401 is input to a signal processing circuit 402, a synchronization separation circuit 403, and a character area determination circuit 412. The signal processing circuit 402 performs predetermined processing such as gamma correction and inversion processing so that it can be displayed on the LCD 407 and is supplied to the X driver 405. In the synchronization separation circuit 403, the synchronization signal is separated, and the separated synchronization signal is input to the controller 404, and a predetermined drive pulse for driving the LCD synchronized with the video signal is supplied to the X driver 405 and the Y driver 406. To supply. Further, a character area discriminating circuit 408 discriminates an area including characters from an input video signal, and supplies a drive mode switching control signal to the X driver 405. The LCD 407 is driven by the video signal and drive pulse supplied from the X driver 405 and the drive pulse supplied from the Y driver 406 and displays character information on the screen simultaneously with the image.

  Here, the character area discriminating circuit 412 performs control so that the switch circuit 426 is connected to the a side in the area where characters are displayed on the screen, and the switch circuit 426 is set to the b side in areas where no characters are displayed. Control to connect to. At this time, the m output terminals 424 are connected to the respective switching elements via the m input terminals of the LCD. Therefore, when a start pulse is input from the input terminal of 421 at the beginning of the horizontal scanning period and a clock of m times the horizontal frequency is input from the input terminal of 422, the m-stage shift register of FIG. Driven. At this time, in the area where characters are displayed, the switch circuit 426 is connected to the a side by the control signal from the character area discriminating circuit 412, so that the same drive pulse is applied to the output terminals of 424 every three output terminals. The video signals input from 464R, 464G, and 464B are supplied to the gates of the switching elements of 465R, 465G, and 465B via the input terminals of 467R, 467G, and 467B. At the same time, it is sampled and supplied to the vertical signal line. Further, in the area where no character is displayed, the switch circuit 426 is connected to the b side by the control signal from the character area discrimination circuit 412, so that different drive pulses are output to the output terminals 424, 465R, The video signals input from 464R, 464G, and 464B are sequentially supplied to the vertical signal lines by being sequentially supplied to the gates of the switching elements of 465G and 465B. .

  The following operations are common to the above two modes. When a start pulse is input from the input terminal 431 at the beginning of the vertical scanning period and a clock having a horizontal frequency is input from the input terminal 432, the drive pulse The n-stage cyst register of the Y driver is driven, and an output pulse of this cyst register is output to the output terminal 434. The output terminal of 434 is connected to the input terminal of 468, and the drive pulse output from the Y driver of 406 is supplied to the gate of the switching element of 461 through a predetermined horizontal gate line, and each switch is turned on. , 462 holds the charge corresponding to the potential difference between the signal supplied to the input terminal 464 and the voltage supplied to the common electrode 466. At this time, a predetermined voltage is supplied to the common electrode 466. By repeating this operation, an image for one screen can be displayed on the LCD.

FIG. 25 shows a specific configuration of the character area discriminating circuit 412 in FIG. 23 in the eleventh reference example of the present invention. In the figure, reference numeral 511 denotes a video signal input terminal, 512 denotes a luminance signal forming circuit for forming a luminance signal from the inputted video signal, 513 denotes a color signal forming circuit for forming a color signal from the inputted video signal, and 514 denotes a luminance. A signal level detection circuit, 515 is a color signal level detection circuit, 516 is a discrimination circuit for discriminating whether a character display region or a character non-display region, and 517 is an output terminal for a mode switching signal.

  The operation of the character area discrimination circuit in this reference example will be described with reference to FIG. The video signal supplied to the input terminal 401 in FIG. 23, that is, the signal supplied to the LCD 407 through the signal processing circuit 402 is supplied to the input terminal 511, and is input from the input terminal 511. The received video signal is supplied to a luminance signal forming circuit 512 and simultaneously supplied to a color signal forming circuit 513. A luminance signal forming circuit 512 forms a luminance signal from the input video signal. That is, when the input video signal is a composite video signal, the luminance signal is formed by performing Y / C separation, and when the input video signal is an RGB signal, the luminance is determined by a predetermined calculation (Y = 0.3R + 0.59G + 0.11B). Form a signal. The color signal forming circuit 513 forms a color signal from the input video signal. When the input video signal is a composite video signal, the color signal generated here may be a chroma signal subjected to Y / C separation or a color difference signal obtained by demodulating the chroma signal. If the input signal is an RGB signal, a color signal is formed by a predetermined calculation. The luminance signal generated by the luminance signal forming circuit 512 and the color signal generated by the color signal forming circuit 513 are input to the luminance signal level detection circuit 514 and the color signal level detection circuit 515, respectively. The signal level is detected and input to the discrimination circuit 516. The determination circuit 516 determines whether or not the input signal is a character, and outputs the result to the output terminal 517 as a mode switching signal. The mode switching signal output from the output terminal 517 is supplied to the X driver 405 and controls the X driver as described above. That is, control is performed so that the 426 switch circuit is connected to the a side in the area where characters are displayed on the screen, and the 426 switch circuit is connected to the b side in areas where no characters are displayed. A control signal is output from the determination circuit 516.

  Next, a specific determination method in the determination circuit 516 in this reference example will be described. When the luminance signal level detection circuit 514 detects that the luminance signal level is greater than a predetermined value from the input video signal, and no color signal is detected by the 515 color signal level detection circuit at that time, that is, input If the input image is a black and white image, or if the color signal level detection circuit 515 detects that the color signal level is smaller than a predetermined value, that is, if the input image is very close to the black and white image. The determination circuit 516 determines that the currently input display image area is an area for displaying characters, and outputs a corresponding mode switching signal. In other areas, it is determined that the area does not display characters, and a corresponding mode switching signal is output. As described above, in the discrimination circuit of this reference example, in the display image, an area where the color signal level is lower than the predetermined value is an area where characters are displayed, and an area where the color signal level is higher than the predetermined value is text. It is determined that the area is not displayed, and a switching signal is output so as to control the sampling phase when displaying on the LCD in accordance with the determination result.

  In this manner, in a liquid crystal display device that displays an input image including character information, in a region where no character is displayed, video signals are separated from each other in correspondence with R, G, and B pixels of the liquid crystal display device. In the area where characters are displayed, the three pixels R, G, and B are sampled in the same phase in the area where characters are displayed, thereby improving the sense of resolution and displaying characters in the area where images are displayed. It is possible to prevent the aliasing distortion from occurring during the process.

[Reference Example 12 ]
FIG. 26 shows a configuration of a character area discrimination circuit used in the liquid crystal display device according to the twelfth reference example of the present invention. The configuration and the like of the entire liquid crystal display device are the same as those in the eleventh reference example and are shown in FIG. In FIG. 26, reference numeral 514b denotes a luminance signal level change detection circuit, 515b denotes a color signal level change detection circuit, and 516b denotes a determination circuit that determines whether a character display area or a character display area.

  The operation and discrimination method of the character area discrimination circuit of this reference example will be described with reference to FIG. In the figure, a video signal input from an input terminal 511 is input to a luminance signal forming circuit 512 and a color signal forming circuit 513, and a luminance signal and a color signal are obtained as output signals, respectively. This is supplied to the level change detection circuit and the color signal level change detection circuit 515b. The luminance signal level change detection circuit 514b detects a change in the level of the input luminance signal and supplies the detection result to the discrimination circuit 516b. Similarly, the color signal level change detection circuit 515b detects a change in the level of the input color signal and supplies the detection result to the discrimination circuit 516b. FIG. 27 shows an example of a specific configuration of the luminance signal level change detection circuit 514b and the color signal level change detection circuit 515b. As shown in FIG. 27, the luminance signal or the color signal supplied from the input terminal 5141 is supplied to the subtracting circuit 5143 together with the signal delayed by the delay circuit 5142 for a predetermined time, and the calculation result in the subtracting circuit 5143 is obtained. 5144 is output from the output terminal 5144. That is, the difference between the signal levels of the input luminance signal and color signal at predetermined time intervals is output as a detection result. Further, in the discrimination circuit 516b, it is discriminated from the supplied detection signals whether it is a region for displaying characters or a region for not displaying characters, and the discrimination result is output to the output terminal 517. At this time, when the level difference of the luminance signal supplied from the luminance signal level change detection circuit 514b is larger than a predetermined value and the level difference of the color signal supplied from the color signal level change detection circuit 515b is smaller than the predetermined value. It is determined that the portion is a region for displaying characters, a corresponding mode switching signal is output to the output terminal of 517, otherwise it is determined that the region is not displaying characters, and the corresponding mode switching is performed. The signal is output to the output terminal 517. As described above, in the discrimination circuit of the present reference example, an area in which the change in the level of the luminance signal is larger than the predetermined value and the level change in the color signal is smaller than the predetermined value in the display image is an area where characters are displayed. The other areas are determined to be areas where characters are not displayed, and a switching signal is output to control the sampling phase when displaying on the LCD in accordance with the determination result.

  Further, in this reference example, instead of detecting the change in the signal level of the luminance signal and the color signal, the frequency components of the luminance signal and the color signal may be detected as shown in FIG. That is, the frequency component of the luminance signal generated by the luminance signal forming circuit 512 is detected by the luminance signal frequency detecting circuit 514c, and the color signal generated by the color signal forming circuit 513 is similarly detected by the color signal frequency detecting circuit 515c. The frequency components of the signal are detected and the respective detection results are supplied to the discrimination circuit 516c. In the discrimination circuit 516c, when the frequency of the luminance signal supplied from the luminance signal frequency detection circuit 514c is larger than a predetermined value and the frequency of the color signal supplied from the color signal frequency detection circuit 515c is smaller than the predetermined value. It is determined that the portion is a region for displaying characters, a corresponding mode switching signal is output to the output terminal of 517, otherwise it is determined that the region is not displaying characters, and the corresponding mode switching is performed. The signal is output to the output terminal 517. As described above, in the discrimination circuit of the present reference example, the area where the frequency of the luminance signal is higher than the predetermined value and the frequency of the color signal is lower than the predetermined value in the display image is an area where characters are displayed. This area is determined to be an area where characters are not displayed, and a switching signal is output so as to control the sampling phase when displaying on the LCD in accordance with the determination result.

In this manner, in a liquid crystal display device that displays an input image including character information, in a region where no character is displayed, video signals are separated from each other in correspondence with R, G, and B pixels of the liquid crystal display device. In the area where characters are displayed, the three pixels R, G, and B are sampled in the same phase in the area where characters are displayed, thereby improving the sense of resolution and displaying characters in the area where images are displayed. It is possible to prevent the aliasing distortion from occurring during the process.
Further, the discrimination circuits shown in the eleventh reference example and the twelfth reference example are combined, and the display mode is switched according to the level change and the frequency change from the discrimination results of the plurality of discrimination circuits. good.

[Reference Example 13 ]
The block diagram of the liquid crystal display device in the thirteenth reference example of the present invention is the same as that shown in FIG. In FIG. 24, reference numeral 411 denotes a video signal delay circuit, the X driver 405 is the same as that shown in FIG. 33A, and the configuration of the character area discrimination circuit 412 is the eleventh or twelfth reference example. Therefore, the description is omitted here. The delay circuit 411 in FIG. 24 is the same as that shown in FIG. 17, 441 is a video signal input terminal, 442 is a switch circuit, 443 is a delay circuit, 444 is a switch circuit, 445 is a mode switching signal input terminal, Reference numeral 446 denotes a video signal output terminal.

The operation of the liquid crystal display device of the thirteenth reference example of the present invention will be described with reference to FIGS. The video signal input from the input terminal 401 is subjected to predetermined processing by the signal processing circuit 402, and simultaneously input to the synchronization separation circuit 403 to separate the synchronization signal. The separated synchronization signal is input to the controller 404, and the video signal A predetermined drive pulse for driving the LCD synchronized with the signal is supplied to the X driver 405 and the Y driver 406. The video signal output from the signal processing circuit 402 is supplied to the X driver 405 via the delay circuit 411. The LCD 407 is driven by the video signal and drive pulse supplied from the X driver 405 and the drive pulse supplied from the Y driver 406 to display an image on the screen.

  Further, the character area discriminating circuit 412 discriminates an area including characters and an area not including characters from the input video signal and supplies a display mode switching control signal to the delay circuit 411. That is, the character area discriminating circuit 412 performs control so that the switch circuits 442 and 444 are connected to the a side in the area where no character is displayed on the screen, and the switch circuits 442 and 444 are set to the b side in the area where the character is displayed. Control to connect. The delay amount of the delay circuit 443 is a delay amount for one pixel of the LCD 407. Therefore, when the switch circuits 442 and 444 are connected to the a side, the video signal output from the output terminal 446 is delayed by one pixel with respect to the B signal, and the R signal is A signal delayed by two pixels is output. When the switch circuits 442 and 444 are connected to the b side, the signal input from the signal 441 is output to the output terminal 446 as it is.

In this reference example, since the X driver 405 is as shown in FIG. 33A, the LCD 407 samples three pixels of R, G, and B with the same phase, but by passing through the delay circuit 411, Since the video signal is delayed in the area where characters are not displayed, the same effect is obtained as when three pixels of R, G, and B are sampled at different phases. In the area where characters are displayed, 411 Since no delay processing is performed in the delay circuit, three pixels are sampled with the same phase. Since the following operation is the same as that of the eleventh reference example, description thereof is omitted.

In this manner, as in the eleventh and twelfth reference examples, in the liquid crystal display device that displays the input image including the character information, the conventionally used X driver is used as it is. The video signal is sampled at different phases corresponding to the R, G, and B pixels of the liquid crystal display device in the area where no character is displayed, and the three pixels R, G, and B have the same phase in the area where the character is displayed. Sampling in (3) makes it possible to enhance the resolution in the image display area and to prevent aliasing distortion when characters are displayed.

  Further, in this reference example, the delay circuit 411 in FIG. 24 may be configured as shown in FIG. In the figure, reference numeral 451 denotes a video signal input terminal, 452 denotes a sample hold circuit, and 453 denotes a video signal output terminal. In an area where no character is displayed on the delay circuit, a sample hold pulse as shown in FIG. At this time, the phase of each pulse is shifted by one pixel of the LCD. Therefore, in the same manner as in the above-described reference example, the video signal output from the output terminal 453 is a signal in which the G signal is delayed by one pixel and the R signal is delayed by two pixels with respect to the B signal. Further, in the area for displaying characters, a pulse as shown in FIG. 19B is supplied and each sample and hold circuit is set to the through state so that the video signal inputted from the input terminal 451 is directly applied to the output terminal 453. Is output.

  By configuring the delay circuit with a sample-and-hold circuit, it is possible to easily cope with a change in the number of pixels of the LCD.

[Reference Example 14 ]
The block diagram of the liquid crystal display device in the fourteenth reference example of the present invention is the same as that in FIG. 24. The difference from the thirteenth reference example is that the X driver 405 is the one shown in FIG. Is the same as that shown in FIG. 20, except that the control is different, and the other operations are the same, and the description thereof will be omitted. In FIG. 20, the same reference numerals as those in FIG. 17 denote the same components. The switch circuits 442 and 444 in FIG. 20 are controlled by a control signal from the character area discriminating circuit 412 so as to be connected to the a side in an area where no character is displayed and to the b side in an area where no character is displayed. Further, since the X driver 405 is as shown in FIG. 34, the LCD 407 samples three pixels of R, G, and B at different timings, but the video signal is not subjected to delay processing in an area where characters are not displayed. , R, G, and B are sampled at different phases, and the video signal is delayed by passing through the delay circuit 411 in the character display area. The same effect as that obtained by sampling at the above phase can be obtained.

By doing so, it is possible to obtain the same effect as the thirteenth reference example. Further, in this reference example, as in the thirteenth reference example, it is needless to say that the delay circuit shown in FIG. 21 may be supplied with a sample hold pulse as shown in FIG. Furthermore, in FIG. 22, the sample hold pulse of (a) may be supplied in a region where characters are not displayed, and the pulse of (b) may be supplied in a region where characters are displayed.

According to the above-described embodiments and reference examples, in a display device that displays an input image including character information, in an area where characters are not displayed, video signals are displayed on each color pixel of the display device, for example, R, G, and B pixels. Sampling is performed at different phases corresponding to each other, and in the area where characters are displayed, the three pixels R, G, and B are sampled at the same phase, so that the resolution is improved in the area where images are displayed. Further, it is possible to prevent aliasing distortion when displaying characters.
Further, in a display device that displays an input image including character information, a conventionally used X driver can be used as it is.

It is a block diagram of the display apparatus by the 3rd reference example of this invention. It is a figure which shows the drive control timing of the display apparatus of FIG. It is a figure which shows the output of a D / A converter. It is a figure for demonstrating the mode of the signal processing in the display apparatus of FIG. It is a control system block diagram of the display apparatus by the 4th reference example of this invention. It is a control system block diagram of the display apparatus by the 1st reference example of this invention. It is a figure which shows the output of a timing generator. It is a control system block diagram of the display apparatus by the 6th reference example of this invention. 1 is a block diagram of a control system of a display device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the display element which concerns on this invention. It is a figure which shows the output of a timing generator. A control system block diagram of a display device according to a second embodiment of the present invention. It is a figure which shows the input output characteristic of a signal processing circuit. It is a control system block diagram of the display apparatus by the 5th reference example of this invention. It is a circuit block diagram of the driver of the display element which concerns on this invention. It is a control system block diagram of the display apparatus by the 6th reference example of this invention. It is a figure which shows the structure of the delay circuit based on this invention. It is a figure which shows another structure of the delay circuit based on this invention. It is a figure which shows the sample hold pulse of the delay circuit of FIG. It is a figure which shows the structure of the delay circuit based on the 7th reference example of this invention. It is a figure which shows another structure of the delay circuit based on this invention. It is a figure which shows the sample hold pulse of the delay circuit of FIG. It is a control system block diagram of the display apparatus by the 8th reference example of this invention. It is a control system block diagram of the display apparatus by the 9th reference example of this invention. It is a circuit block diagram of the character area discrimination circuit based on the 11th reference example of this invention. It is a circuit block diagram of the character area discrimination circuit based on the 12th reference example of this invention. FIG. 3 is a circuit configuration diagram of a color signal level change detection circuit according to the present invention. It is a circuit block diagram of the frequency detection circuit which concerns on this invention. It is a schematic diagram for demonstrating the relationship between the sampling timing of an input video signal, and a display pixel. It is a block diagram of a display apparatus. It is a circuit block diagram of a liquid crystal display element. It is a top view which shows the arrangement | sequence of the color pixel used for a display element. It is a figure which shows the circuit structure of an example of the driver of a display element. It is a figure which shows the circuit structure of the other example of the driver of a display element. It is a schematic diagram for demonstrating the relationship between the sampling timing of an input video signal and a display pixel in the display apparatus which concerns on this invention. It is a control system block diagram of the display apparatus which concerns on this invention.

Explanation of symbols

201R, 201G, 201B Input video terminals 202A, 202B, 202C A / D converters 203A, 203B, 203C Shift registers 204A, 204B, 204C, 204D, 204E Flip-flops 205A, 205B Memory 206A, 206B storing predetermined signal value L0 Comparator 207A, 207B Differentiator 208A, 208B Memory 209A, 209B Comparator 210A, 210B AND operator 211A, 211B Signal switcher 212A, 212B, 212C Flip-flop 213 Clock generator 214 Timing generator 215 Signal switch 216 FIFO memory 217A FIFO memory output terminal 217B Clock generator output terminal 218 Generator 219 D / A converter 220 TFT liquid crystal panel 221A, 221B Signal processor

Claims (5)

In a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, sampling the red, green, and blue signals in the input video signals in time series The first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, bn2 and sampling means for obtaining bn3), and selection means for selecting three signal values from these signal values, the selection means obtaining the difference | rn1−rn2 | between the first and second red signal values rn1 and rn2 Compared with the threshold value Th, when | rn1−rn2 |> Th holds, or the difference | rn2−rn3 | between the second and third red signal values rn2 and rn3 is Compared to have value Th | rn2-rn3 |> when Th is established, the display device which is characterized in that those selectively switching the signal value the selected. In a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, sampling the red, green, and blue signals in the input video signals in time series The first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, bn2 and sampling means for obtaining bn3) and selection means for selecting three signal values from these signal values, the selection means obtaining the difference | gn1-gn2 | between the first and second green signal values gn1 and gn2 Compared with the threshold value Th, when | gn1-gn2 |> Th holds, or the difference | gn2-gn3 | between the second and third green signal values gn2 and gn3 Compared with the values Th, | gn2-gn3 |> When Th is established, the display device which is characterized in that those selectively switching the signal value the selected. In a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, sampling the red, green, and blue signals in the input video signals in time series The first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, bn2 and a sampling means for obtaining bn3), and a selecting means for selecting three signal values from these signal values, wherein the selecting means determines the difference | bn1-bn2 | between the first and second green signal values bn1 and bn2. When | bn1−bn2 |> Th is established, or the difference | bn2−bn3 | between the second and third green signal values bn2 and bn3 is compared with the threshold value Th. Compared with the values Th, | bn2-bn3 |> When Th is established, the display device which is characterized in that those selectively switching the signal value the selected. In a display device that samples input video signals at a predetermined cycle and displays red, green, and blue pixels arranged in a matrix, sampling the red, green, and blue signals in the input video signals in time series The first to third red signal values (rn1, rn2 and rn3), the first to third green signal values (gn1, gn2 and gn3), and the first to third blue signal values (bn1, bn2 and sampling means for obtaining bn3) and selection means for selecting three signal values from these signal values, the selection means being the difference | rn1− between the first red signal value rn1 and the second green signal value gn2. gn2 | is compared with the threshold value Th, and when | rn1-gn2 |> Th is satisfied, or the difference between the second green signal value gn2 and the third blue signal bn3 | gn2-bn | Is compared with the threshold value Th, | GN2-BN3 |> When Th is established, the display device which is characterized in that those selectively switching the signal value the selected. The selection means switches the first red signal value rn1 and the third blue signal value bn3 to a signal value of gn1, gn2, or gn3 according to the comparison result. Item 4. The display device according to Item 1 .

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