JP4214767B2 - Manufacturing method of multilayer chip component - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer chip component, particularly a multilayer coil component.
[0002]
[Prior art]
Multilayer chip components having a multilayer structure of ceramic layers and internal conductor layers are manufactured for various uses such as multilayer inductors and multilayer filters. In the production of these multilayer chip components, it is necessary that each layer be accurately formed at a predetermined position in the main surface direction.
[0003]
As a method for positioning each of the layers, for example, there is a method for manufacturing a ceramic inductor as disclosed in JP-A-5-55066. This is to produce a laminate in which ceramic green sheets with through-holes connecting between conductor layers and conductor patterns comprising spiral coils are alternately stacked by connecting through the through-holes. A method of manufacturing a multilayer ceramic inductor by firing the laminated body after pressure bonding and forming external electrodes, and when forming a conductor pattern on a ceramic green sheet in which a through hole is formed, The conductor pattern for alignment having a certain positional relationship between the conductor pattern is disposed at a predetermined position in the alignment through hole formed in advance in the ceramic green sheet, and the conductor pattern is aligned, A conductor pattern is formed together with the positioning conductor pattern A.
[0004]
According to this manufacturing method, the alignment of the conductor pattern can be performed easily and accurately, the variation in the inductance value of the obtained multilayer inductor is reduced, and the quality is improved.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-55066
[Problems to be solved by the invention]
However, in the above method, when the conductor pattern is formed on the ceramic green sheet, the alignment conductor pattern formed together with the conductor pattern and the alignment formed immediately below the through hole of the ceramic green sheet. Since alignment is performed between the conductor patterns for use, there is a possibility that the amount of positional deviation increases as a large number of layers are stacked. For this reason, when designing a multilayer chip component, it is necessary to provide a large margin from the end face of the chip, and there is a problem that it becomes an obstacle to downsizing and high performance of the product.
[0007]
The present invention provides a method for manufacturing a laminated chip component in which an insulator layer and a conductor layer are sequentially formed on an insulator substrate, wherein the insulator layer and the conductor layer are accurately formed at predetermined positions in the main surface direction. It is an object of the present invention to reduce the amount of misalignment and reduce the size and performance of multilayer chip components.
[0008]
In order to solve the above-described problem, the multilayer chip component manufacturing method according to the present invention includes a conductor layer (hereinafter referred to as the conductor layer closest to the insulator substrate) on the insulator substrate or the insulator layer formed on the insulator substrate. An alignment layer made of the same material as that of the first conductor layer is formed and fired at the same time, and an insulator layer and a conductor layer are formed on the first conductor layer. A multilayer chip component manufacturing method comprising a step of sequentially forming a plurality of layers configured and firing for each layer , wherein the alignment mark has a linear shape or a combination of lines. The entire circumference or a part of the circumference is surrounded by a part constituting the first conductor layer, and the closest distance between the alignment mark and the part constituting the first conductor layer is the line. Width of The insulating layer and the conductor layer that are sequentially formed on the first conductor layer are formed at positions determined with reference to the alignment mark. To do.
[0010]
In the method for manufacturing a laminated chip component, all the conductor layers including the first conductor layer are formed by a photolithography process or a printing process.
[0011]
By using the above-described method for manufacturing a multilayer chip component, all of the insulator layers and conductor layers sequentially formed on the first conductor layer are positioned with reference to the same alignment mark, so that each layer is sequentially formed. As a result, it is possible to prevent the positional deviation from increasing. Further, all or part of the periphery of the alignment mark is disposed so as to be surrounded by the first conductor layer, and the closest distance between the alignment mark and the first conductor layer is determined by the alignment mark. Since the width of the line constituting the mark is 0.2 times or more and 1 time or less, as the insulator layer and the conductor layer are baked for each layer, the component of the alignment mark is volatilized. Deformation due to disappearance is prevented. For this reason, all the layers from the first conductor layer to the uppermost layer are positioned with high accuracy.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a method for manufacturing a multilayer chip component according to the present invention will be described in detail with reference to the drawings.
[0013]
FIG. 1 is a manufacturing process diagram of a multilayer chip component according to an embodiment of the present invention. As shown in step (a), a photosensitive conductive paste is screen-printed on the insulator substrate 1 to form a conductive paste layer 2. The conductive paste layer 2 is formed with a predetermined pattern shape (not shown) by a photolithography process, and an alignment mark having a predetermined shape (described later) is formed at a predetermined position. In the photolithography process, an exposure mask is set on the conductive paste layer 2, and development is performed after exposure. Thereafter, firing is performed to form the first conductor layer 3 and the alignment mark 4 (step (b)). The first conductor layer 3 formed in this way is the conductor layer closest to the insulator substrate 1 and has at least a portion that becomes a conductor pattern of the multilayer chip component as a component and a portion that surrounds the periphery of the alignment mark 4 ( Included below).
[0014]
Next, a photosensitive insulating paste is screen-printed on the first conductor layer 3 to form an insulating paste layer 5 (step (c)). The insulating paste layer 5 has through holes (not shown) formed at predetermined positions by a photolithography process. In the photolithography process, an exposure mask is set at a position determined on the basis of the alignment mark 4 on the insulating paste 5, and development is performed after exposure. Thereafter, it is baked to form the insulator layer 6 (step (d)).
[0015]
Next, the photosensitive conductive paste is screen-printed on the insulator layer 6 to form the conductive paste layer 2 (step (e)). A pattern (not shown) having a predetermined shape is formed on the conductive paste layer 2 by a photolithography process. In the photolithography process, an exposure mask is set at a position determined on the basis of the alignment mark 4 on the conductive paste layer 2, and is developed after exposure. Thereafter, firing is performed to form the conductor layer 7 (step (f)).
[0016]
Further, steps (c) to (f) are repeated as necessary, and a laminate having a predetermined number of layers is formed on the insulating substrate 1.
[0017]
The obtained laminate is cut into a predetermined size together with the insulating substrate, and then subjected to a process such as barrel polishing as necessary. Thereafter, an external electrode is formed on the outer surface of the obtained laminate so as to be connected to the lead portion of the conductor layer, and then a plating film is formed on the external electrode portion to obtain a laminated chip component.
[0018]
In the manufacturing method described above, the first conductor layer 3 and the alignment mark 4 are formed simultaneously. Then, in the photolithography process of the insulator layer 5 and the conductor layer 2 formed on the first conductor layer 3, the exposure mask is aligned based on the alignment mark 4. That is, all the insulating layers and conductor layers formed on the first conductor layer 3 are positioned with reference to the same alignment mark 4. Therefore, the positioning of the insulating layer or the conductor layer can be performed with higher accuracy than the case where the alignment mark that differs for each layer is used as a reference, and the increase in the amount of misalignment due to the increase in the number of layers can be suppressed.
[0019]
Further, as the shape of the alignment mark 4, for example, the shapes shown in FIGS. 2A to 2C are preferably used. In this way, alignment can be easily performed by using a linear shape or a combined shape. The alignment mark 4 is formed so as to be surrounded by a part of the first conductor layer 3 made of the same material. In addition to the shape in which the entire periphery of the alignment mark 4 is surrounded by the first conductor layer 3 as shown in FIGS. 2A to 2C, a part of the periphery of the alignment mark, for example, 1/2 cycle Alternatively, a shape in which the 3/4 circumference is surrounded by the conductor layer may be used.
[0020]
Since the periphery of the alignment mark 4 is surrounded by the first conductor layer 3, the atmosphere of the alignment mark and the metal component of the conductor layer can be increased in the vicinity of the alignment mark when firing each layer. For this reason, a part of the alignment mark disappears due to volatilization during baking and the shape is prevented from changing, so that the insulating layer and the conductor layer can be accurately positioned from the lowermost layer to the uppermost layer. Therefore, there is an effect that the multilayer chip component can be reduced in size and performance.
[0021]
In the shape in which the alignment mark is surrounded by the conductor layer, the closest distance between the conductor layer and the alignment mark is preferably 0.2 to 1 times the line width of the alignment mark. When the closest distance is shorter than 0.2 times the line width, it is difficult to recognize the shape of the alignment mark when performing automatic alignment using a mechanical device. Further, if the closest distance is longer than one time the line width, the effect of preventing the disappearance or shrinkage of the alignment mark described above is reduced.
[0022]
In the multilayer chip component manufacturing method of the present invention, as the material of the insulator substrate, various insulating inorganic materials such as alumina are used. As the material for the insulator layer, various inorganic materials having insulation properties such as glass are used. As the material for the conductor layer, various metals or alloys containing components that volatilize during firing, such as an alloy of Ag, Ag and Pd, are used.
[0023]
As a method for forming the insulator layer and the conductor layer in the multilayer chip component of the present invention, a method in which a photolithography process is performed after screen printing of the photosensitive paste as described above is preferably used. However, the present invention is not limited to the above method, and all the insulator layers and the conductor layers on the first conductor layer are positioned with reference to the same alignment mark, and the periphery of the alignment mark is the same. Any other method may be used as long as it is satisfied to be formed so as to be surrounded by a conductor layer made of a material. For example, after an insulating paste or a conductive paste is screen-printed, the pattern shape may be formed by a method such as chemical etching. Further, an insulating paste layer or a conductive paste layer having a desired pattern shape may be directly formed by screen printing. Different formation methods may be used for each layer.
[0024]
【Example】
3A to 3F are manufacturing process diagrams of the laminated coil component according to the embodiment of the present invention as viewed from above. FIGS. 4A to 4F are cross-sectional views taken along the cut surface A of FIGS. 3A to 3F.
[0025]
As shown in FIG. 3 and FIG. 4A, a photosensitive conductive paste made of Ag powder, photosensitive resin, solvent, etc. is screen-printed on an insulating substrate 11 mainly composed of alumina, and a conductive paste layer is formed. 12 was formed.
[0026]
An exposure mask is placed on the conductive paste layer 12, and after the exposure, development processing is performed, and further, baking is performed at a predetermined temperature, and the first conductor layer 13 and the alignment mark (not shown) having the shape shown in FIG. ) Was formed. The alignment mark is formed so that the periphery thereof is surrounded by a part constituting the first conductor layer 13, and the shape of the alignment mark and the first conductor layer 13 surrounding the periphery is as shown in FIG. It was. The closest distance between the alignment mark and the first conductor layer 13 was 0.75 times the line width of the alignment mark.
[0027]
Next, an insulating paste made of glass powder, photosensitive resin, solvent or the like was screen-printed on the first conductor layer 13 to form an insulating paste layer 15 shown in (c).
[0028]
An exposure mask was placed on the insulating paste layer 15 with the alignment mark as a reference, and exposure was performed. Thereafter, development processing was performed, and baking was performed at a predetermined temperature to form an insulator layer 16 having through holes 18 shown in (d).
[0029]
Next, the photosensitive conductive paste was screen-printed on the insulator layer 16 to form the conductive paste layer 12 shown in FIG. An exposure mask was placed on the conductive paste layer 12 with the alignment mark as a reference, and exposure was performed. Thereafter, development processing was performed, and baking was performed at a predetermined temperature to form a conductor layer 17 having a shape shown in (f). Thus, the conductor layer 17 was connected to the first conductor layer 13 through the through hole 18 to form a helical coil.
[0030]
After the obtained laminate was cut along the cut line 19, barrel polishing was performed. Thereafter, an Ag paste was applied and baked so as to be connected to lead portions to the surface of the laminated body at both ends of the coil to form external electrodes (not shown). A plating film was formed on the external electrode portion by electrolytic plating to obtain a laminated coil component.
[0031]
Even after the above baking process, the alignment mark did not change its shape due to disappearance. Therefore, the alignment of the exposure mask when forming the insulator layer 16 or the conductor layer 17 can be performed with high accuracy.
[0032]
As described above, in the multilayer chip component manufacturing method of the present invention, all of the insulator layer and the conductor layer sequentially formed on the first conductor layer are positioned with reference to the same alignment mark. It is possible to prevent the positional deviation from increasing as each layer is sequentially formed. Further, all or part of the periphery of the alignment mark is disposed so as to be surrounded by the first conductor layer, and the closest distance between the alignment mark and the first conductor layer is determined by the alignment mark. When the width of the line constituting the mark is 0.2 times or more and 1 time or less, the alignment mark component does not volatilize in the sequential firing of the insulator layer and the conductor layer, and the deformation due to the disappearance of the alignment mark Is prevented. For this reason, all the layers from the first conductor layer to the uppermost layer are positioned with high accuracy.
[0033]
Therefore, the positional deviation amount of the multilayer chip component is reduced, and there is an effect that the size and performance can be further reduced.
[Brief description of the drawings]
FIG. 1 is a process diagram illustrating a method for manufacturing a multilayer chip component according to an embodiment of the present invention.
FIG. 2 is a diagram showing a shape of an alignment mark and a surrounding conductor layer in a method for manufacturing a laminated chip component according to an embodiment of the present invention.
FIG. 3 is a process diagram illustrating a method for manufacturing a laminated coil component according to an embodiment of the present invention.
4 (a) to 3 (f) are cross-sectional views taken along a cut surface A in each drawing.
[Explanation of symbols]
1, 11 Insulator substrate 2, 12 Conductive paste layer 3, 13 First conductor layer 4, 14 Alignment mark 5, 15 Insulation paste layer 6, 16 Insulator layer 7, 17 Conductor layer 8, 18 Through hole 19 Cut line

Claims (3)

On the insulator substrate or on the insulator layer formed on the insulator substrate, the conductor layer closest to the insulator substrate (hereinafter referred to as the first conductor layer) and the same material as the first conductor layer with alignment mark composed are formed simultaneously, the steps to be fired, the first conductor layer, a plurality of layers are sequentially formed composed of the insulating layer and the conductive layer is fired for each layer A method of manufacturing a laminated chip component, wherein the alignment mark has a shape of a line or a combination of lines, and all or part of the periphery of the alignment mark is a part of the first conductor layer. The first conductor layer is disposed so as to be surrounded, and a closest distance between a part of the alignment mark and the first conductor layer is not less than 0.2 times and not more than one time the width of the line. Sequentially formed on All edges layer and the conductive layer, characterized in that it is formed in the position determined the positioning mark as a reference, the manufacturing method of the laminated chip component. The method for manufacturing a multilayer chip component according to claim 1, wherein all conductor layers including the first conductor layer are formed by a photolithography process. The method for manufacturing a multilayer chip component according to claim 1, wherein all the conductor layers including the first conductor layer are formed by a printing process.

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