JP4214248B2 - Field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor, and more particularly to a field effect transistor configured to obtain a high gain in a high frequency band.
[0002]
[Prior art]
In recent years, with the rapid spread of communication infrastructure such as the Internet, the demand for larger capacity and higher speed of information communication has increased, and research on practical application of millimeter wave band communication systems has been actively conducted.
For this reason, field effect transistors such as a field effect transistor (MESFET) and a high electron mobility transistor (HEMT) having a Schottky gate electrode made of a compound semiconductor based on GaAs or InP are used as switching elements used in communication circuits. There is a strong demand for higher frequencies.
[0003]
Evaluation of high speed in such a field effect transistor is performed based on the cutoff frequency. This cutoff frequency is defined as a frequency at which the current gain becomes 1, and the higher the frequency, the better the high frequency characteristics.
By the way, the cutoff frequency is given by the reciprocal of the travel time from the source electrode to the drain electrode of the electrons, and the longest time among the travel times is the travel time in the intrinsic region which is a channel directly under the gate electrode.
[0004]
For this reason, attempts have been made to obtain high frequency characteristics, particularly high gain at high frequencies, by shortening the gate electrode as much as possible and shortening the length of the intrinsic region as much as possible to increase the cutoff frequency.
[0005]
However, due to the shortening of the gate length as described above, the method for obtaining a high cut-off frequency is limited to shortening to about 20 nm, for example, about 0.05 μm or less due to the limitation of the pattern miniaturization technique. It is substantially difficult to achieve a higher cutoff frequency (see Non-Patent Document 1).
[0006]
Furthermore, in order to shorten the movement time of electrons in the intrinsic region, attention has been paid to the use of a material that can move electrons faster, for example, In _y Ga _1-y As than the material of GaAs.
In this way, at present, an intrinsic region that becomes a channel of a field effect transistor is formed of In _0.7 Ga _0.3 As, for example, as In _y Ga _1-y As (where 0 <y <1), and the gate length A field effect transistor having a cutoff frequency of 562 GHz has been reported by shortening the length to 25 nm (see Non-Patent Document 2).
[0007]
On the other hand, by applying a magnetic field along the direction in which electrons flow to the channel layer in a region immediately below the source electrode and the drain electrode, magnetic field energy is added to the electrons flowing through the channel layer, and electrons flow through the channel layer. There is known a field effect transistor that accelerates (see Patent Document 1). In Patent Document 1, a magnetic mirror is formed in a channel layer immediately below a source electrode and a drain electrode by applying a magnetic field in parallel along the traveling direction of electrons, and electrons flowing through the channel layer are transferred by this magnetic mirror. Receives magnetic field energy. This discloses that electrons are accelerated by converting this magnetic field energy into kinetic energy.
[0008]
[Non-Patent Document 1]
Loi D. Nguyen, April S. Brown, Mark A. Thompson, and Linda M. Jelloian, "50nm Self-Aligned-Gate Psudomorfic AlInAs / GaInAs High Electron Mobility Transistors", September 1992, IEEE Transaction on Electron Devices, Vol. 39 , No.9, pp. 2007-2014
[Non-Patent Document 2]
Yoshimi Yamashita, Atsushi Endo, Keisuke Shinohara, Yasutoshi Hikosaka, Toshiaki Matsui, Satoshi Cold Water, Takashi Mimura, “Ultra High Speed f _T = 562 GHz InP-HEMT”, March 28, 2002, 49th Association of Applied Physics Lecture Proceedings, 30a-YK-5, p. 1240
[Patent Document 1]
JP 2001-284602 A (page 2-3, FIG. 1)
[0009]
[Problems to be solved by the invention]
In the techniques of Non-Patent Documents 1 and 2, the frequency is increased by selecting a material having a high mobility and a high electron saturation rate and shortening the channel size, but it is not possible to suppress scattering accompanied by energy dissipation of electrons. There is a problem.
[0010]
In the technique of Patent Document 1, even if conversion from magnetic field energy to kinetic energy can be efficiently performed, electrons having high energy immediately lose energy by a scattering process accompanied by energy dissipation such as optical phonon scattering in the crystal. Therefore, there is a problem that the speed of electrons cannot be improved efficiently.
As described above, a field effect transistor that can suppress scattering accompanied by energy dissipation of electrons is not known at present.
[0011]
In view of the above problems, an object of the present invention is to provide a field effect transistor capable of obtaining a higher cutoff frequency and higher gain at a high frequency.
[0012]
[Means for Solving the Problems]
In order to achieve the above object , the present invention provides a field effect transistor comprising a gate and a channel layer formed of two-dimensional electrons, wherein the gate electrode formed on the gate is formed of a ferromagnetic material. And the magnetic field of the ferromagnetic gate layer is applied in a direction perpendicular to the channel layer by two-dimensional electrons .
In particular, the gate is preferably a Schottky gate or a MOS gate . In particular, a channel layer based on two-dimensional electrons is formed by a heterojunction of compound semiconductors. In particular, the ferromagnetic material contains at least one of Nd (neodymium), Sm ( samarium ), and Ce (cerium).
[0014]
According to the above configuration , in a field effect transistor including a gate and a channel layer formed of two-dimensional electrons, a magnetic field is applied in a direction perpendicular to the moving direction of the electrons, so that the electrons move in the moving direction and the direction of the magnetic field. In response to the Lorentz force in a direction perpendicular to the direction, the material moves in this direction, producing a so-called quantum Hall effect.
[0015]
This significantly reduces the resistivity with respect to the direction of movement of the electrons, resulting in conduction without electron dissipation. This is because energy dissipation due to optical phonons occurs when a magnetic field is not applied, but energy dissipation due to such optical phonons does not occur when a magnetic field is applied, and electrons can move at a very high speed. is there.
[0016]
Therefore, the electrons flowing through the channel layer between the source electrode and the drain electrode become a current that does not involve energy dissipation due to optical phonons, so the time for the electrons to travel through the channel layer directly under the gate electrode is greatly reduced. The cut-off frequency is significantly increased. As a result, high-frequency characteristics, particularly gain at high frequencies, can be significantly improved without reducing the gate length.
[0017]
When a magnetic field is applied to the region immediately below the gate electrode of the channel layer, electrons moving through the channel layer are quantum based on the application of the magnetic field in the region immediately below the gate electrode where speeding up the electrons is most important. The Hall effect accelerates more effectively, and the time for traveling in the channel layer below the gate is further shortened.
[0018]
When the gate electrode is formed of at least a ferromagnetic material, preferably a magnet such as a neodymium magnet, the magnetic field generated by the gate electrode itself is applied to electrons moving in a region immediately below the gate electrode of the channel layer. Applied in the vertical direction.
[0019]
Thus, according to the present invention, in a field effect transistor having a gate and a channel layer formed of two-dimensional electrons, a magnetic field is applied in a direction perpendicular to the direction of movement of electrons, so-called quantum Hall effect. Electrons are effectively accelerated, and the time for traveling in the channel layer region directly under the gate electrode is greatly reduced. Therefore, since the cutoff frequency can be significantly increased without reducing the gate length, the high-frequency characteristics of the field effect transistor are greatly improved, and a high gain can be obtained particularly at a high frequency.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on the embodiments shown in the drawings.
1 and 2 show the configuration of a first embodiment of a field effect transistor according to the present invention.
In FIG. 1, a field effect transistor 10 has the same configuration as a so-called high electron mobility transistor (HEMT) fabricated on a normal InP substrate, and In _x Al _{1− serving as a} buffer layer on the InP substrate 11. _x As layer 12, undoped In _y Ga _1-y As layer 13, undoped In _x Al _1-x As layer 14, n-type In _x Al _1-x As layer 15, undoped In _x Al _1-x As layer 16, The n ⁺ -type In _y Ga _{1 -y} As layer 17 has a stacked structure.
[0021]
A source electrode 19 and a drain electrode 20 are provided on the n ⁺ -type In _y Ga _{1 -y} As layer 17. The top layer of n ⁺ -type In _y Ga _1-y As layer 17 is a so-called gate recess exposing regions where the Schottky junction is formed undoped In _x Al _1-x As layer 16 is formed, an undoped an In _x Al _A gate electrode 21 is formed on the _1-x As layer 16.
[0022]
On the uppermost n ⁺ -type In _y Ga _{1 -y} As layer 17, a SiO ₂ layer 18 serving as a protective film is deposited, and only the electrode portion is opened. The gate electrode 21 has a structure of a T-type gate electrode so as to reduce the gate resistance as much as possible.
[0023]
Here, the channel 22 of the field effect transistor 10 includes an undoped In _y Ga _{1 -y} As layer 13, an undoped In _x Al _{1 -x} As layer 14, and an n-type In _x Al _{1 -x} As layer 15. _A two-dimensional electron gas is formed at the heterojunction interface with the undoped In _x Al _1-x As layer 14 in the _y Ga _1-y As layer 13 to form a two-dimensional electron channel layer 23.
[0024]
As the heterojunction, the In _y Ga _1-y As layer 13 may be In _0.53 Ga _0.43 As, the In _x Al _1-x As layer 14 may be In _0.52 Al _0.48 As, or the like. The composition of the heterojunction is not limited to the above composition. A laminated structure such as In _0.53 Ga _0.43 As / InAs / In _0.53 Ga _0.43 As may be used.
Depending on the channel structure, the formed two-dimensional electron gas is also called a quasi-two-dimensional electron gas. In the present invention, including such a structure, it will be called a two-dimensional electron channel layer.
Although the gate has been described as a Schottky junction, it may be a pn junction gate, a MIS gate, or a MOS gate.
[0025]
Here, such a field effect transistor 10 is manufactured as follows. That is, first, in the same manner as a so-called high electron mobility transistor (HEMT) fabricated on a normal InP substrate, an MBE (molecular beam epitaxy) apparatus is used on a semi-insulating InP substrate 11 at a substrate temperature of 450 ° C. In addition, an undoped In _0.52 Al _0.48 As layer 12 (thickness 300 nm), an undoped In _0.53 Ga _0.47 As layer 13 (thickness 20 nm), an undoped In _0.70 Al _0.31 As layer 14 (thickness 2 nm), and an n-type buffer layer In _0.53 Al _0.47 As layer 15 (doping concentration 5 × 10 ¹⁸ cm ³ , thickness 12 nm), undoped In _0.52 Al _0.48 As layer 16 (thickness 10 nm), n ⁺ -type In _0.53 Ga _0.47 As layer 17 (doping concentration 3 × 10 ¹⁹ cm ³ , thickness 50 nm) are epitaxially grown sequentially.
[0026]
Next, after so-called element isolation is performed by mesa etching, an SiO ₂ layer 18 (thickness 400 nm) is formed by CVD. Then, by ordinary photolithography, the opening pattern is formed in the region of the source electrode and the drain electrode of the SiO ₂ layer 18, a hole by dry etching and wet etching of the SiO ₂ layer 18 at this region.
Then, Au (thickness 200 nm) / Ti (thickness 50 nm) is deposited on the entire surface from the top of the SiO ₂ layer 18, and the source electrode 19 and the drain electrode 20 are formed by lift-off.
[0027]
Thereafter, an opening pattern is formed in the region of the gate electrode of the SiO ₂ layer 18 between the source electrode 19 and the drain electrode 20 by using an electron beam drawing apparatus, and dry etching of the SiO ₂ layer 18 is performed in this region. And a hole is formed by wet etching. In this hole, the n ⁺ -type In _0.53 Ga _0.47 As layer 17 is wet etched with a citric acid-based etchant to expose the undoped In _0.52 Al _0.48 As layer 16.
Finally, Ti (thickness 20 nm) and Al (thickness 500 nm) are sequentially deposited thereon, and the gate electrode 21 is formed by lift-off.
In this way, the field effect transistor 10 is completed.
[0028]
The field effect transistor 10 according to the present invention is configured as described above and operates as follows. That is, a voltage is applied between the source electrode 19 and the drain electrode 20, and the electron movement direction in the undoped In _y Ga _{1 -y} As layer 13 in which the two-dimensional electron channel layer 23 is formed in the region of the gate electrode 21. A magnetic field B that is perpendicular to the direction, i.e., downward in FIG.
Here, the magnetic field B is an external magnetic field of the field effect transistor 10 and may be applied by a magnet or the like provided in the package of the field effect transistor.
[0029]
When a voltage is applied to the gate electrode 21, the n ⁺ -type In _y Ga _{1 -y} As layer 17 and the undoped In _x Al _{1 -x} As layer are formed from the source electrode 19 based on the gate voltage applied to the gate electrode 21. 16 through the undoped In _y Ga _{1 -y} As layer 13 and further through the undoped In _x Al _{1 -x} As layer 16 and the n ⁺ -type In _y Ga _{1 -y} As layer 17 to the drain electrode 20. Electrons will flow toward you. Here, since the sum of the thicknesses of the n ⁺ -type In _y Ga _{1 -y} As layer 17 and the undoped In _x Al _{1 -x} As layer 16 is sufficiently shorter than the channel, the channel is a two-dimensional electron channel. The length of the undoped In _y Ga _{1 -y} As layer 13 in which the layer 23 is formed may be used.
[0030]
FIG. 2 is a diagram schematically showing changes in resistivity in the x and y directions due to the quantum Hall effect. In FIG. 2, the horizontal axis represents the two-dimensionally distributed electron density Ns, and the vertical axis represents the resistivity ρxx, ρxy in the x and y directions. Here, the xy plane is a surface on which the two-dimensional electron channel layer 23 is formed, and the direction from the source electrode 19 to the drain electrode 20 is the x direction.
As shown in the figure, it can be seen that the resistivity ρxy in the y direction changes stepwise due to the quantum Hall effect. This corresponds to the discrete value of the electric field Ey described above. On the other hand, the resistivity ρxx in the x direction is zero in a certain region, and in this region, conduction without energy dissipation due to optical phonons occurs.
In the absence of the magnetic field B, due to energy dissipation due to optical phonons, the speed of the electrons is at most about 2 × 10 ⁷ cm / s, for example.
When the magnetic field B is applied and conduction without energy dissipation occurs due to the optical phonon as in the present invention, the electron has a saturation speed (about 2 × 10 ⁷ cm / s) for conduction without dissipation. Beyond, it continues to be accelerated by the electric field due to the drain voltage. As a result, it is possible to move at a speed exceeding the saturation speed of electrons, which has been limited so far, and to follow a higher-frequency input signal.
[0031]
Therefore, electrons flowing through the undoped In _y Ga _1-y As layer 13 in which the two-dimensional electron channel layer 23 is formed between the source electrode 19 and the drain electrode 20 become a current without energy dissipation due to optical phonons. Since the time for electrons to travel through the undoped In _y Ga _1-y As layer 13 in which the two-dimensional electron channel layer 23 directly under the gate is formed, the cutoff frequency is significantly increased. In this way, a field effect transistor with excellent high-frequency characteristics can be obtained by significantly improving the gain of high-frequency characteristics, particularly at high frequencies, without reducing the gate length.
[0032]
Next, a second embodiment of the field effect transistor according to the present invention will be described. FIG. 3 is a sectional view showing the configuration of the second embodiment of the field effect transistor according to the present invention.
The field effect transistor 30 of the second embodiment is different from the field effect transistor 10 shown in FIG. 1 in that a ferromagnetic gate layer 31 made of a ferromagnetic material is disposed on the gate electrode 21. is there. Here, in order to reduce electrode resistance and protect the upper portion of the ferromagnetic gate layer 31, a metal layer may be further provided to form a multilayer gate electrode structure.
As the ferromagnetic material of the ferromagnetic gate layer 31, a neodymium magnet (Nd—Fe—B), a samarium magnet (Sm—Co), a cerium magnet (Ce), a ferrite magnet, or the like can be used.
According to the field effect transistor 30, the ferromagnetic gate layer 31 made of a ferromagnetic material is disposed on the gate electrode 21, and the magnetic field B is applied to the channel 22 as illustrated. The operation is the same except that the externally applied magnetic field is not required.
[0033]
FIG. 4 is a cross-sectional view showing the configuration of a modification of the second embodiment of the field effect transistor according to the present invention.
The field effect transistor 35 of the second embodiment is different from the field effect transistor 30 shown in FIG. 3 in that a ferromagnetic layer 32 for applying a magnetic field to the channel 22 is used as a substrate instead of the ferromagnetic gate layer 31. 11 is arranged at the lower part of 11.
According to the field effect transistor 35, the magnetic layer B is applied to the channel 22 as shown in the figure by disposing the ferromagnetic layer 32 made of a ferromagnetic material below the substrate 11. The operation is the same except that the externally applied magnetic field is not required.
[0034]
Here, simulation experiments of the field effect transistor 10 of the first embodiment and the field effect transistor 30 of the second embodiment described above are shown.
The field effect transistor 10 of the first embodiment shown in FIG. 1 is used as sample A, and similarly, as shown in FIG. 3, a neodymium magnet (Nd—Fe), which is a ferromagnetic material, is further formed on the gate electrode 21. A field effect transistor 30 (sample B) according to the second embodiment in which the ferromagnetic gate layer 31 formed in (B) is disposed is manufactured.
[0035]
Each of these samples A and B was simulated.
FIG. 5 is a diagram showing a simulation result of the cutoff frequency with respect to the gate length by the field effect transistor of FIGS. 1 and 3.
As can be seen from FIG. 5, the change in the cut-off frequency with respect to the gate length (μm) shows that the sample A is cut off as the gate length is shortened in the state where no external magnetic field is applied, as shown by the white square. Although the frequency is high, the cutoff frequency is at most 0.2 THz at the gate length of 0.15 μm. Therefore, in the case where the external magnetic field is not applied, the sample A has almost the same cutoff frequency as that of the conventional HEMT indicated by the black square in FIG.
[0036]
On the other hand, in the sample B indicated by white circles in FIG. 5, by forming the gate electrode 21 from a neodymium magnet, a magnetic field is applied by the gate electrode 21 as indicated by an arrow in FIG. Since the speed increases, it can be seen that a very high cutoff frequency of 1.08 THz can be obtained at a gate length of 0.15 μm.
For sample A, a cut-off frequency of 1.0 THz was obtained at a gate length of 0.15 μm when an external magnetic field of 1.0 T (Tesla) was applied.
Therefore, compared with the case where an external magnetic field is not applied, it can be confirmed that the cut-off frequency is greatly improved by the effect of the magnetic field application according to the present invention.
[0037]
In the embodiment described above, the thickness of each of the layers 12 to 18 epitaxially grown on the InP substrate 11 is fixed. However, the thickness is not limited to this and may be changed to other thicknesses.
In the above-described embodiments, the case where the present invention is applied to a so-called HEMT has been described as a field effect transistor. However, the present invention is not limited to this, and other configurations such as a MOSFET and a Schottky gate type field effect transistor are used. It is clear that the present invention can be applied to a field effect transistor using two-dimensional electrons or pseudo two-dimensional electrons.
[0038]
【The invention's effect】
As described above, according to the present invention, in a field effect transistor including a gate and a channel layer formed of two-dimensional electrons, a so-called quantum Hall effect is obtained by applying a magnetic field in a direction perpendicular to the direction of electron movement. As a result, electrons are effectively accelerated, and the time for traveling through the channel layer directly under the gate electrode is greatly reduced. Therefore, since the cutoff frequency can be significantly increased without reducing the gate length, the high-frequency characteristics of the field effect transistor are greatly improved, and a high gain can be obtained particularly at a high frequency.
As described above, according to the present invention, an extremely excellent field effect transistor having a higher cutoff frequency and capable of obtaining a high gain at a high frequency is provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of an embodiment of a field effect transistor according to the present invention.
FIG. 2 is a diagram showing changes in resistivity in the x direction and the y direction due to the quantum Hall effect.
FIG. 3 is a cross-sectional view showing a configuration of a second embodiment of a field effect transistor according to the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a modification of the second embodiment of the field effect transistor according to the present invention.
5 is a diagram showing a simulation result of a cutoff frequency with respect to a gate length by the field effect transistor of FIGS. 1 and 3. FIG.
[Explanation of symbols]
10, 30, 35 Field effect transistor 11 InP substrate 12 Undoped In _x Al _{1 -x} As layer 13 Undoped In _y Ga _{1 -y} As layer 14 Undoped In _x Al _{1 -x} As layer 15 n-type In _x Al _{1 -x} As layer 16 Undoped In _x Al _{1 -x} As layer 17 n ⁺ type In _y Ga _{1 -y} As layer 18 SiO ₂ layer 19 Source electrode 20 Drain electrode 21 Gate electrode 22 Channel 23 Two-dimensional electron channel layer 31 Ferromagnetic gate layer 32 Ferromagnetic layer

Claims (5)

A field effect transistor comprising a gate and a channel layer formed by two-dimensional electrons,
The gate electrode formed on the gate includes a ferromagnetic gate layer formed of a ferromagnetic material,
A field effect transistor, wherein the magnetic field of the ferromagnetic gate layer is applied in a direction perpendicular to the channel layer by two-dimensional electrons .   The field effect transistor according to claim 1, wherein the gate is a Schottky gate.   The field effect transistor according to claim 1, wherein the gate is a MOS gate. 2. The field effect transistor according to claim 1, wherein the channel layer by the two-dimensional electrons is formed by a heterojunction of a compound semiconductor. The field effect transistor according to claim 1, wherein the ferromagnetic material contains at least one of Nd (neodymium), Sm ( samarium ), and Ce (cerium).

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