JP4200912B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a non-volatile semiconductor memory device using a non-volatile semiconductor memory cell having a two-layer gate structure having a floating gate and a control gate, and more particularly to a read voltage margin even if the threshold voltage of the memory cell changes in temperature. The present invention relates to a nonvolatile semiconductor memory device in which a large change is not caused.

  Nonvolatile semiconductor memory cells that can electrically write, erase, and read information are known as EEPROM (Electrically Erasable Programmable Read Only Memory). Typical examples include flash memory and conventional EEPROM. These memories use a MOS transistor having a two-layer gate structure having a floating gate and a control gate as a memory cell.

Information is written depending on whether or not new charges are accumulated by some means in the floating gate that has been erased to remove charges. For example, if the state in which electrons are accumulated is data “1”, the erased state in which no electrons are accumulated is data “0”.
Data is read using the fact that the threshold voltage changes with reference to the control gate depending on whether electrons are accumulated in the floating gate. Usually, a voltage of about 1 V is applied to the drain of the memory and a voltage of several volts is applied to the control gate, and data “0” or “1” is determined depending on whether the memory is turned on. That is, if the read voltage (voltage applied to the control gate at the time of reading) is higher than the threshold voltage of the memory, the memory is turned on, and this is detected to determine data “0”. On the other hand, if the read voltage is lower than the threshold voltage of the memory, the memory is turned off, and therefore data “1” is determined.

  In order to make such a determination accurately, it is important that the threshold voltage of the memory is high or low with a sufficient margin relative to the read voltage, that is, the read voltage margin is large. However, as shown in FIG. 4, the threshold voltage has a temperature dependency such that it is smaller as the temperature is higher and is larger as the temperature is lower. Therefore, for example, if the read voltage is fixed to the average value Vr of the erase state threshold voltage and the write state threshold voltage at the reference temperature T1, the read voltage margin decreases at the temperature T2 and an erroneous determination occurs. There is a problem that it is easy.

  In order to solve such a problem, it is only necessary to make the read voltage have the same temperature dependence as the temperature change of the threshold voltage. As a method of generating such a read voltage, for example, there is a method disclosed in Patent Document 1. In this method, a MOS transistor having a temperature fluctuation amount approximately equal to the temperature fluctuation amount of the threshold voltage of the memory is prepared, and the voltage generated and a constant voltage having a small temperature fluctuation amount are added to obtain a read voltage. Is.

However, this method has to prepare a MOS transistor having a temperature fluctuation amount approximately equal to the temperature fluctuation amount of the threshold voltage of the memory. In addition, the circuit becomes complicated by requiring a reference voltage generating circuit with a small amount of temperature fluctuation to be added and an adding circuit for two voltages.
Japanese Patent Laid-Open No. 10-320983

  The present invention has been made to solve such problems of the prior art, and the problem is that the voltage is approximately equal to the average value of the erase state threshold voltage and the write state threshold voltage which change with temperature. Is generated with a simple circuit configuration, and the voltage is used as a read voltage to provide a nonvolatile semiconductor memory device in which the temperature change of the read voltage margin is reduced.

  The invention according to claim 1 for solving the above-mentioned problem is that a nonvolatile semiconductor memory device (1) using a MOS transistor having a two-layer gate of a floating gate and a control gate as a memory cell forms the memory cell. Between the potential reference line (4) having the same potential as the source potential of the transistor and the reference voltage supply line (6) for supplying a reference voltage (Vs) having a small temperature change with reference to the potential of the potential reference line, the reference Three resistors (R1, R2, and R3) having different first, second, and third resistance temperature coefficients are connected in series from the voltage supply line side, and an interconnection point of the second and third resistors ( 7) is a threshold voltage in a state where electrons are accumulated in the floating gate of the transistor at the same reference temperature at the first reference temperature (T1) and the second reference temperature (T2). Accumulated The values of the first, second, and third resistors and the reference voltage are determined so as to be equal to the average value of the threshold voltage of the current state, and the voltage is read to the control gate of the transistor. A nonvolatile semiconductor memory device is characterized by being applied.

  According to the nonvolatile semiconductor memory device having such a configuration, the values of the read voltage are the threshold voltage in the erase state and the write state in the write state at the first reference temperature T1 and the second reference temperature T2. It matches the average value with the threshold voltage, and a sufficient read voltage margin is ensured at these reference temperatures. In addition, since a read voltage close to the average value of the threshold voltages is output even in the intermediate temperature range, there is an effect that a sufficient read voltage margin is ensured between the reference temperatures T1 and T2.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the voltage (Vr) at the interconnection point (7) is equal to the first reference temperature (T1) and the second reference temperature (T1). At each reference temperature (T2) , the threshold voltage of the state in which electrons are accumulated in the floating gate of the transistor at the same reference temperature after performing the write and erase operations a predetermined number of times and the state in which the electrons are not accumulated. The threshold voltage is estimated, and the values of the first, second, and third resistors and the reference voltage are determined so as to be equal to the average value thereof .
According to such a configuration, it is possible to set a read voltage in anticipation of a change in threshold voltage due to repeated writing and erasing operations, and a read voltage margin can be secured even if the threshold voltage changes. As a result, it is possible to set various read voltages.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, a resistor having an equal resistance temperature coefficient is used as the second and third resistors. To do.
According to such a configuration, the resistance values of the first, second, and third resistors and the reference voltage Vs can be easily determined, and the same effect as in the first aspect of the invention can be achieved. .

According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to third aspects, resistors having the same resistance value are used as the second and third resistors. To do.
According to such a configuration, the resistance values of the first, second, and third resistors and the reference voltage Vs can be easily determined, and the same effect as in the first aspect of the invention can be achieved. .

According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the channel resistance of a PMOS transistor is used as the first resistance, and the second and third resistances are used. It is characterized by using a polysilicon resistor.
If such a resistor is used, the first, second, and third resistors required in the inventions of claims 1 to 3 can be easily realized, and the effects of the invention described in each claim can be achieved. Play.

  Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a circuit configuration of the nonvolatile semiconductor memory device 1. This circuit shows a circuit configuration at the time of reading from a memory array 2 having a configuration of 2 rows × 2 columns composed of four memory cells M11, M12, M21, and M22. This circuit is configured to perform parallel reading in units of rows. In order to simplify the description, the memory device has a 2-bit × 2-bit configuration, but can be easily expanded to a large-capacity nonvolatile semiconductor memory device by increasing the number of rows and columns. Circuits necessary for writing and erasing are omitted because they are irrelevant to the read voltage generation circuit 3 which is the point of the present invention.

  The four memory cells M11, M12, M21, and M22 are N-channel MOS transistors having a two-layer gate of a floating gate and a control gate. The sources of the memory cells (hereinafter also referred to as memory transistors) M11, M12, M21, and M22 are connected to the potential reference line 4 and grounded. The gates of the memory transistors M11 and M12 in the first row are connected in common and receive a read voltage Vr that is an output voltage of the read voltage generation circuit 3 via the analog switch S10. Similarly, the gates of the memory transistors M21 and M22 in the second row are also connected in common and receive the read voltage Vr via the analog switch S20.

The drains of the memory transistors M11 and M21 in the first column are connected to the resistor R10 via analog switches S11 and S12, respectively. A power supply voltage Vdd is supplied to the other end of the resistor R10. Similarly, the drains of the memory transistors M21 and M22 in the second column are also connected to the resistor R20 via the analog switches S21 and S22, respectively. The power supply voltage Vdd is also supplied to the other end of the resistor R20. A common connection point between the resistor R10 and the analog switch S11 is connected to the inverting input terminal of the sense amplifier Q1. Similarly, the common connection point between the resistor R20 and the analog switch S21 is connected to the inverting input terminal of the sense amplifier Q2. A reference voltage Vref is input to the non-inverting input terminals of the sense amplifiers Q1 and Q2. The value of the reference voltage Vref is set to about ½ of the power supply voltage Vdd . Both the power supply voltage V dd and the reference voltage Vref are given with the potential of the potential reference line 4 as a reference.

When reading the data stored in the first row of the memory transistors M11, M 12 is are both ON state analog switches S10 and S11, S21. At this time, the drain of the memory transistor M11, M 12, the power supply voltage V dd is applied respectively through a resistor R10, R20. At the same time, a read voltage Vr is commonly applied to the gates. When the value of the read voltage Vr is larger than the respective threshold voltages of the memory transistors M11 and M12, the memory transistor is turned on, and when it is smaller, it is turned off.

  Since the drain voltage of the memory transistor in the ON state is reduced to near the potential of the potential reference line 4, the output of the corresponding sense amplifier becomes “High” level. On the other hand, the output of the sense amplifier corresponding to the memory transistor in the OFF state becomes “Low” level. In this way, the data stored in the memory transistors M11 and M12 are read in parallel according to the voltage levels of the outputs OUT1 and OUT2 of the sense amplifiers Q1 and Q2. Data stored in the memory transistors M21 and M22 in the second row is read in the same manner.

  Incidentally, the problem here is the value of the read voltage Vr. In order to increase the read voltage margin, it is preferable to set the read voltage Vr to an intermediate value between the threshold voltage in the erased state and the threshold voltage in the written state, that is, an average value. However, as described in the “Background Art” section, the threshold voltage decreases as the temperature increases. Therefore, in order to ensure a sufficient read voltage margin, the value of the read voltage Vr needs to be lowered with the same temperature dependence as the temperature rises.

  In order to have such temperature dependence, in this embodiment, the read voltage Vr is generated using the read voltage generation circuit 3 as shown in FIG. The read voltage generation circuit 3 includes a reference voltage generation circuit 5, a first resistor R1, a second resistor R2, and a third resistor R3. The reference voltage generation circuit 5 receives the supply of the power supply voltage Vdd and generates a reference voltage Vs having a small temperature dependency with the potential reference line 4. Between the output line (reference voltage supply line) 6 of the reference voltage generation circuit 5 and the potential reference line 4, resistors R1, R2, and R3 are connected in series in this order from the reference voltage generation circuit 5 side, and read as an output. The voltage Vr is taken from the interconnection point 7 between the resistors R2 and R3.

  Next, how to determine a circuit constant that changes the read voltage Vr almost following the temperature change of the threshold voltage of the memory transistor under the read voltage generation circuit 3 having such a configuration will be described. The erase state threshold voltage and the write state threshold voltage of the memory transistors used in the memory array 2 change as shown by curves 10 and 11 in FIG. Therefore, the average threshold voltage, which is the average value of the two threshold voltages, decreases as the temperature rises as shown by the curve 12 in FIG.

The point on the average threshold voltage curve 12 at temperature (first reference temperature) T1 is A1, the point at temperature (second reference temperature) T2 is A2, and the voltage at points A1 and A2 (average threshold) Voltage) is V1 and V2, respectively. The temperature T2 is higher than the temperature T1 by a temperature difference t ° C.
The average threshold value between the points A1 and A2 changes while drawing a curve as shown by an average threshold voltage curve 12 in FIG. Ideally, the read voltage Vr changes in accordance with the average threshold voltage curve 12. However, since it is difficult to completely match the curve, in this embodiment, the circuit constant is determined so that the value of the read voltage Vr becomes V1 at the temperature T1 and V2 at the temperature T2. That is, the circuit constant is determined so that the read voltage curve 13 representing the temperature change of the read voltage Vr passes through the points A1 and A2. If the circuit constant is determined in this way, the read voltage Vr changes between the temperature T1 and the temperature T2 while drawing a curve that almost matches the average threshold voltage curve 12, and the read voltage Vr and the average threshold are changed. This is because the difference from the voltage is a small value.

The average temperature coefficient of the average threshold voltage between the temperatures T1 and T2 is m [/ ° C.]. The resistance values of the resistors R1, R2, and R3 at the temperature T1 are R1, R2, and R3, respectively, and the average temperature coefficients of the resistance values between the temperatures T1 and T2 are a1, a2, and a3 [/ ° C.], respectively. If defined in this way, the values of the average threshold voltage V2 and the resistors R1, R2, and R3 at the temperature T2 are expressed as follows.

Average threshold voltage V2 at temperature T2 = (1 + m · t) · V1
Value of resistance R1 at temperature T2 = (1 + a1 · t) · R1
Value of resistance R2 at temperature T2 = (1 + a2 · t) · R2
Value of resistance R3 at temperature T2 = (1 + a3 · t) · R3
Conditions for the value of the read voltage Vr to coincide with the average threshold voltage V2 at the temperatures T1 and T2 are expressed by the following two expressions.

V1 = Vs · R3 / (R1 + R2 + R3) (1) Formula (1 + m · t) · V1 = Vs · (1 + a3 · t) · R3 / ((1 + a1 · t) · R1
+ (1 + a2 · t) · R2 + (1 + a3 · t) · R3)
The following conditions are derived from these two equations.
m. (a1.R1 + a2.R2 + a3.R3) .t-a3. (R1 + R2 + R3)
+ (M + a1) .R1 + (m + a2) .R2 + (m + a3) .R3 = 0 (2) That is, the resistance materials and the resistance values of the resistors R1, R2, and R3 are determined so that the equation (2) is satisfied. Thus, the value of the read voltage Vr becomes equal to the average threshold voltages V1 and V2 at the temperatures T1 and T2, respectively.

Since the equation (2) is too general and it is not easy to determine the values of the resistors R1, R2, and R3 from this equation, a constraint is added to determine the values of the resistors R1, R2, and R3.
As a constraint, the same resistance material is used for the resistors R2 and R3. That is,
a2 = a3
Also,
R2 + R3 = 2R
Then, the following relationship is derived from the equation (2).

R1 / 2R = −m · (1 + a3 · t) / (m · (1 + a1 · t) + a1−a3)
(3) Expression Since the left side of this expression must be a positive number, the right side must also be a positive number. Accordingly, it is a necessary condition for the temperature coefficients m, a1, a2, a3 and the temperature difference t to have a relationship in which the right side of the equation (3) is positive.

here,
R1 / 2R = 1 / β If the equation (4) is set, the resistors R2 and R3 are calculated as follows from the equations (1) and (4).
R2 = R1 · (β− (1 + β) · V1 / Vs) (5) Equation R3 = R1 · (1 + β) · V1 / Vs (6) Equation In these Equations (5) and (6), the value of β is the temperature If the values of the coefficients m, a1, a2, a3 and the temperature difference t are determined, they are constants that can be calculated using the equations (3) and (4). V1 is an average value of two threshold voltages of the memory transistor at the temperature T1, and is known. Therefore, if the resistance value of the resistor R1 and the value of the reference voltage Vs are determined, the resistance values of the resistors R2 and R3 are determined by the equations (5) and (6), respectively. Here are some numerical examples.
[Numerical example 1]
m = −0.002 [/ ° C.]
a1 = 0.05 [/ ° C]
a2 = a3 = 0.0005 [/ ° C.]
t = 100 [° C]
V1 = 1 [V]
Vs = 3 [V]
R1 = 5 [kΩ]
In this case, from equations (5) and (6)
R2 = 58 [kΩ]
R3 = 31 [kΩ]
It becomes.

In addition, when the values of the resistors R2 and R3 obtained by previously determining the value of the resistor R1 and the value of the reference voltage Vs are difficult to realize, the value of the resistor R1 or the reference voltage Vs The value is adjusted so as to obtain a feasible resistance value.
Further, when the method of determining the value of the reference voltage Vs first and determining the values of the resistors R2 and R3 based on the value is adopted, the power supply voltage Vdd in FIG. The voltage applied to the memory cell when reading the stored data of the memory cell may be used as it is. If the power supply voltage Vdd is used as the reference voltage Vs as described above, it is not necessary to provide the reference voltage generation circuit 5.

  In addition, as described above, the value of the resistor R1 and the value of the reference voltage Vs may be determined first, and instead of the method of determining the values of the resistors R2 and R3 based on the values, the values may be determined as follows. Instead of determining the value of the reference voltage Vs first, a constraint condition of R2 = R3 is given instead to determine the values of the resistors R2, R3 and the value of the reference voltage Vs. In this case, the values of the resistors R2 and R3 and the value of the reference voltage Vs are calculated by the following equations.

R2 = R3 = 0.5 · β · R1 (7) Equation Vs = 2 · (1 + 1 / β) · V1 (8) Equation [Numerical Example 2]
m = −0.002 [/ ° C.]
a1 = 0.05 [/ ° C]
a2 = a3 = 0.0005 [/ ° C.]
t = 100 [° C]
V1 = 1 [V]
R1 = 5 [kΩ]
R2 = R3
In this case, from equations (7) and (8)
R2 = R3 = 45 [kΩ]
Vs = 2.1 [V]
It becomes.

Also in this case, if the values of the resistors R2 and R3 or the value of the reference voltage Vs are difficult to realize, adjustment is performed so that the value of the resistor R1 is changed to be a realizable value .

The resistance having the temperature coefficient of 0.0005 [/ ° C.] taken up in Numerical Examples 1 and 2 can be realized by, for example, a polysilicon resistance. This is because the resistance value and temperature coefficient of polysilicon can be arbitrarily adjusted to some extent by changing the impurity concentration. Further, a resistance having a temperature coefficient of 0.05 [/ ° C.] can be realized by a channel resistance of a PMOS transistor. This is because the channel resistance and temperature coefficient of the PMOS transistor can be adjusted arbitrarily by changing the channel width, channel length, channel region impurity concentration, gate bias voltage, and the like.
FIG. 3 shows a configuration example of the read voltage generation circuit 3 when a PMOS transistor and a polysilicon resistor are used. The reference voltage generation circuit 5 having a small temperature dependency in the figure can be realized by a band gap reference voltage generation circuit, for example.

  As described above, in the nonvolatile semiconductor memory device 1 according to the present embodiment, the value of the read voltage Vr is the threshold voltage in the erase state of the memory transistor and the write state at the first reference temperature T1 and the second reference temperature T2. The read voltage generation circuit 3 was configured to match the average value with the threshold voltage at. Therefore, not only a sufficient read voltage margin is ensured at these reference temperatures, but also a read voltage close to the ideal read voltage is output in the intermediate temperature range. Thereby, there is an effect that a sufficient read voltage margin is secured between the reference temperatures T1 and T2. Further, in the case of the present embodiment, there is an advantage that it is not necessary to prepare a MOS transistor having a temperature fluctuation amount approximately equal to the temperature fluctuation amount of the threshold voltage of the memory transistor as in the conventional technique described in “Background Art”. There is.

(Modified embodiment)
In the embodiment described above, the value of the read voltage Vr matches the average threshold voltage at the temperature (first reference temperature) T1, and the value at the temperature (second reference temperature) T2. The circuit constants of the read generation circuit 3 have been set so as to match the average threshold voltage at temperature.

However, it is not always best to set the read voltage Vr to match the average threshold voltage in this way. For example, the threshold voltage changes with repeated writing and erasing operations. The degree of change of the write state threshold voltage and the erase state threshold voltage due to the repeated operation is not the same.
In this case, if the value of the read voltage Vr is set to the average value of the threshold voltage immediately after the manufacture of the memory cell, the read voltage margin may be reduced due to a change in the threshold voltage. In consideration of these points, the threshold voltage after the predetermined number of times of writing and erasing operations is predicted, and the value of the read voltage Vr is set in advance so that the read voltage margin at the time of executing the predetermined number of times is optimal. It can be said that setting is preferable. In this case, the value of the read voltage Vr is slightly different from the average value of the threshold voltages immediately after the memory cell is manufactured.

  To do this, the first reference temperature T1 is equal to a predetermined first set voltage in consideration of the above points, and the second reference temperature T2 is equal to a predetermined second set value. Determine circuit constants.

1 is a circuit configuration example of a nonvolatile semiconductor memory device according to the present invention. It is explanatory drawing of the idea of approximating a read voltage to the average value of threshold voltage. 3 is a configuration example of a read voltage generation circuit. It is a figure explaining the temperature change of the threshold voltage of a memory transistor.

Explanation of symbols

  In the drawings, 1 is a nonvolatile semiconductor memory device, 2 is a memory array, 3 is a read voltage generation circuit, 4 is a potential reference line, 5 is a reference voltage generation circuit, 6 is a reference voltage supply line, 7 is an interconnection point, M11 , M12, M21, M22 are memory cells (memory transistors, N-channel MOS transistors), R1 is a first resistor, R2 is a second resistor, R3 is a third resistor, T1 is a first reference temperature, T2 Is a second reference temperature, Vr is a read voltage, and Vs is a reference voltage.

Claims (5)

  In a nonvolatile semiconductor memory device (1) using a MOS transistor having a two-layer gate of a floating gate and a control gate as a memory cell, a potential reference line (4) having the same potential as the source potential of the transistor constituting the memory cell, First, second, and third resistors in order from the reference voltage supply line side to the reference voltage supply line (6) that supplies a reference voltage (Vs) with a small temperature change based on the potential of the potential reference line. Three resistors (R1, R2, R3) having different temperature coefficients are connected in series, and the voltage (Vr) at the interconnection point (7) of the second and third resistors is the first reference temperature (T1). And the second reference temperature (T2) equal to the average value of the threshold voltage when electrons are accumulated in the floating gate of the transistor and the threshold voltage when no electrons are accumulated at the same reference temperature. To be Said first, second, third resistor value with the reference voltage and the determined non-volatile semiconductor memory device and applying a read voltage to the voltage to the control gate of the transistor. The voltage (Vr) at the interconnection point (7) at the same reference temperature after the write and erase operations are executed a predetermined number of times at each of the first reference temperature (T1) and the second reference temperature (T2) . The threshold voltage in a state where electrons are accumulated in the floating gate of the transistor and the threshold voltage in a state where electrons are not accumulated are predicted so as to be equal to the average value thereof . The nonvolatile semiconductor memory device according to claim 1, wherein a value of a third resistor and the reference voltage are determined.   3. The nonvolatile semiconductor memory device according to claim 1, wherein resistors having the same temperature coefficient of resistance value are used as the second and third resistors.   4. The nonvolatile semiconductor memory device according to claim 1, wherein resistors having the same resistance value are used as the second and third resistors. 5. The nonvolatile semiconductor memory device according to claim 1, wherein a channel resistance of a PMOS transistor is used as the first resistance, and a polysilicon resistance is used as the second and third resistances.

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